MAX98355A, MAX98355B 数字脉冲编码调制(PCM)输入的D类功率放大器 - 概述 Page 1 of 2 Login 产品 方案 设计 销售联络 支持中心 公司简介 Register 简体中文 (cn) 我的Maxim Maxim > 产品 > 音频 > MAX98355A, MAX98355B MAX98355A, MAX98355B 数字脉冲编码调制(PCM)输入的D类功率放大器 9焊球、I²S输入、无噪声D类音频放大器 概述 设计资源 定购信息 相关产品 所有内容 状况 数据资料 型号 状况 MAX98355A 状况：生产中。 MAX98355B 状况：生产中。 英文 下载 Rev. 1 (PDF, 1.7MB) Email 概述 MAX98355A/MAX98355B为数字脉冲编码调制(PCM)输入的D类功率放大器，具有AB类放大器的音频性能和D类放 大器的效率。IC通过一个增益选择输入(GAIN)引脚提供五种可选择的增益设置(3dB、6dB、9dB、12dB和15dB)。 数字音频接口具有高度设计灵活性，MAX98355A支持I²S数据，MAX98355B支持左对齐数据。两款IC均支持时分 复用(TDM)数据；数字音频接口可支持8kHz至96kHz采样速率和所有数据格式。可配置IC从立体声输入数据产生左 声道、右声道或(左声道 + 右声道)/2输出。IC采用16/24/32位I²S和左对齐模式工作；工作在TDM模式时，采用16 位数据、多达4个时隙。IC无需外部提供MCLK信号(常见于PCM通信)。从而降低了EMI和电路板耦合噪声，并且缩 小系统尺寸、减少IC引脚数量。 IC还具有非常宽的BCLK和LRCLK抖动容限(12ns典型值)，确保可靠工作。 有源辐射抑制、边沿斜率限制和过冲控制电路有效降低EMI。无需滤波的扩频调制技术省去了传统D类放大器中的 输出滤波器，大大减小方案元件数量。 IC提供9引脚WLP封装(1.345mm x 1.435mm x 0.64mm)，工作在-40°C至+85°C温度范围。 MAX98355/56产品视频(修订版) 现备有评估板：MAX98355EVKIT 关键特性 单电源供电(2.5V至5.5V) 5V供电时，为4Ω负载提供3.2W输出功率 2.2mA静态电流 92%效率(RL = 8Ω，POUT = 900mW，VDD = 3.7V) 25µVRMS输出噪声(AV = 15dB) 0.013%超低THD+N，1kHz 无需MCLK 8kHz至96kHz采样速率 支持左声道、右声道或(左声道 + 右声道)/2输出 边沿斜率控制技术支持无滤波D类放大器设计 77dB PSRR，217Hz 较高的RF抑制，有效抑制GSM无线设备的TDMA噪声 完备的喀嗒声抑制电路 可靠的短路保护和热保护 应用/使用 蜂窝电话 笔记本电脑 便携式媒体播放器 平板电脑 http://china.maximintegrated.com/datasheet/index.mvp/id/7502 2013-11-10 MAX98355A, MAX98355B 数字脉冲编码调制(PCM)输入的D类功率放大器 - 概述 Page 2 of 2 提供节省空间的封装: 1.345mm x 1.435mm WLP (0.4mm间 距) 关键特性: Speaker Amplifiers Part Number MAX98355A MAX98355B Class D Spkr. Amp. VCC (V) Spkr. Amp. VCC (V) Spkr. Amp. ICC (mA) POUT into 4Ω @ 1% THD+N (W) POUT into 4Ω @ 10% THD+N (W) POUT into 8Ω @ 1% THD+N (W) POUT into 8Ω @ 10% THD+N (W) min max typ min min min min 2.5 5.5 2.5 2.5 3.2 1.4 1.8 Spkr. Amp. Half Pwr. THD+N (%) 0.013 SNR (dB) PSRR (dB) AWeighted min 105 77 No | 关注我们 Spkr. Amp. Ext. Gain Spkr. Amp. Fxd. Gain (V/V) min 1.5 查看所有Speaker Amplifiers (36) Pricing Notes: This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor. 图表 Simplified Block Diagram 更多信息 顶标 顶标 新品发布 MAX98355A MAX98355B [ 2012-09-25 ] 没有找到你需要的产品吗？ 应用工程师帮助选型，下个工作日回复 参数搜索 应用帮助 信息索引 概述 设计资源 定购信息 相关产品 概述 关键特性 应用/使用 关键指标 图表 注释、注解 数据资料 技术文档 评估板 可靠性报告 软件/模型 价格与供货 样品 在线订购 封装信息 无铅信息 类似功能器件 类似应用器件 评估板 类似型号器件 配合该器件使用的产品 参考文献： 19-6278 Rev. 1; 2013-11-01 本页最后一次更新: 2013-11-01 © 2013 Maxim Integrated版权所有 联络我们' | 工作机会 | 隐私权政策 | http://china.maximintegrated.com/datasheet/index.mvp/id/7502 法律声明 | 代理商网站入口 2013-11-10 EVALUATION KIT AVAILABLE MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers General Description The MAX98355A/MAX98355B are digital pulse-code modulation (PCM) input Class D power amplifiers that provide Class AB audio performance with Class D efficiency. These ICs offer five selectable gain settings (3dB, 6dB, 9dB, 12dB, and 15dB) set by a single gainselect input (GAIN). The digital audio interface is highly flexible with the MAX98355A supporting I2S data and the MAX98355B supporting left-justified data. Both ICs support time division multiplexed (TDM) data. The digital audio interface accepts sample rates ranging from 8kHz to 96kHz for all supported data formats. The ICs can be configured to produce a left channel, right channel, or left/2 + right/2 output from the stereo input data. The ICs operate using 16/24/32-bit data for I2S and left justified modes as well as 16-bit data with up to four slots when using TDM mode. The ICs eliminate the need for the external MCLK signal that is typically used for PCM communication. This reduces EMI and possible board coupling issues in addition to reducing the size and pin count of the ICs. The ICs also feature a very high wideband jitter tolerance (12ns typ) on BCLK and LRCLK to provide robust operation. Active emissions-limiting, edge-rate limiting, and overshoot control circuitry greatly reduce EMI. A filterless spread-spectrum modulation scheme eliminates the need for output filtering found in traditional Class D devices and reduces the component count of the solution. Features SSingle-Supply Operation (2.5V to 5.5V) S3.2W Output Power into 4I at 5V S2.4mA Quiescent Current S92% Efficiency (RL = 8I, POUT = 900mW, VDD = 3.7V) S25µVRMS Output Noise (AV = 15dB) SLow 0.013% THD+N at 1kHz SNo MCLK Required SSample Rates of 8kHz to 96kHz SSupports Left, Right, or Left/2 + Right/2 Outputs SSophisticated Edge Rate Control Enables Filterless Class D Outputs S77dB PSRR at 217Hz SLow RF Susceptibility Rejects TDMA Noise from GSM Radios SExtensive Click-and-Pop Reduction Circuitry SRobust Short-Circuit and Thermal Protection SAvailable in Space-Saving Package: 1.345mm x 1.435mm WLP (0.4mm Pitch) The ICs are available in a 9-pin WLP package (1.345mm x 1.435mm x 0.64mm) and are specified over the -40NC to +85NC temperature range. Simplified Block Diagram Applications Cellular Phones SHUTDOWN AND CHANNEL SELECT Tablets Portable Media Players Notebook Computers Ordering Information appears at end of data sheet. Functional Diagram appears at end of data sheet. PCM INPUT DIGITAL AUDIO INTERFACE MAX98355A MAX98355B GAIN CONTROL DAC CLASS D OUTPUT STAGE For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX98355A.related. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. 19-6278; Rev 1; 8/13 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Digital Audio Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MCLK Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 BCLK Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 LRCLK Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PCM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DAC Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SD_MODE and Shutdown Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Class D Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ultra-Low EMI Filterless Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Speaker Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Gain Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Click-and-Pop Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power-Supply Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Layout and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Maxim Integrated 2 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers LIST OF FIGURES Figure 1. I2S Audio Interface Timing Diagram (MAX98355A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Left-Justified Audio Interface Timing Diagram (MAX98355B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. TDM Audio Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. MAX98355A I2S Digital Audio Interface Timing, 16-Bit Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. MAX98355A I2S Digital Audio Interface Timing, 24-Bit Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. MAX98355B Left-Justified Digital Audio Interface Timing, 16-Bit Resolution . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. MAX98355B Left-Justified Digital Audio Interface Timing, 24-Bit Resolution . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. MAX98355A TDM Digital Audio Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9. MAX98355B TDM Digital Audio Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10. MAX98355A TDM Digital Audio Interface Timing, Example of Four 16-Bit Slots . . . . . . . . . . . . . . . . . . . . 24 Figure 11. MAX98355B TDM Digital Audio Interface Timing, Example of Four 16-Bit Slots . . . . . . . . . . . . . . . . . . . . 25 Figure 12. SD_MODE Resistor Connection Using Open-Drain Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. SD_MODE Resistor Connection Using Pullup/Down Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 14. EMI with 12in of Speaker Cable and No Output Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 15. Left-Channel PCM Operation with 6dB Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16. Left-Channel PCM Operation with 12dB Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17. Right-Channel PCM Operation with 6dB Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 18. Stereo PCM Operation Using Two ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 19. Left/2 + Right/2 PCM Operation with 6dB Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 20. MAX98355A/MAX98355B WLP Ball Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LIST OF TABLES Table 1. RMS Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2. BCLK Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3. LRCLK Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Digital Filter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 5. SD_MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 6. Examples of SD_MODE Pullup Resistor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7. Gain Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Maxim Integrated 3 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers ABSOLUTE MAXIMUM RATINGS VDD, LRCLK, BCLK, and DIN to GND.....................-0.3V to +6V All Other Pins to GND............................... -0.3V to (VDD + 0.3V) Continuous Current In/Out of VDD/GND/OUT_.................. Q1.6A Continuous Input Current (all other pins)......................... Q20mA Duration of OUT_ Short Circuit to GND or VDD…......Continuous Duration of OUTP Short to OUTN..............................Continuous Continuous Power Dissipation (TA = +70NC) WLP (derate 13.7mW/NC above +70NC)....................1096mW Junction Temperature......................................................+150NC Operating Temperature Range........................... -40NC to +85NC Storage Temperature Range............................. -65NC to +150NC Soldering Temperature (reflow).......................................+230NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) WLP Junction-to-Ambient Thermal Resistance (qJA)...........73°C/W Junction-to-Case Thermal Resistance (qJC)................50°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL Supply Voltage Range VDD Undervoltage Lockout UVLO Quiescent Current Shutdown Current Standby Current IDD ISHDN ISTNDBY CONDITIONS MAX UNITS 5.5 V 1.8 2.3 V TA = +25NC 2.75 3.35 TA = +25NC, VDD = 3.7V SD_MODE = 0V, TA = +25NC 2.4 2.7 0.6 2 FA SD_MODE = 1.8V, no BCLK, TA = +25NC Time from receipt of first clock cycle to full operation, including 6ms fade-in volume ramp 300 400 FA 7 7.5 ms Q0.3 Q1.5 mV Guaranteed by PSSR test tON Output Offset Voltage VOS TA = +25NC, gain = 15dB KCP Peak voltage, TA = Into shutdown +25NC, A-weighted, 32 samples per Out of shutdown second (Note 3) Power-Supply Rejection Ratio Maxim Integrated PSRR VDD = 2.5V to 5.5V, TA = +25NC f = 217Hz, 200mVP-P ripple TA = +25NC (Notes 3, 4) f = 10kHz, 200mVP-P ripple TYP 2.5 1.4 Turn-On Time Click-and-Pop Level MIN mA -66 dBV -72 60 75 77 dB 60 4 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS THD+N = 10%, gain = 12dB Output Power (Note 3) POUT THD+N = 1%, gain = 12dB Total Harmonic Distortion + Noise THD+N MIN TYP ZSPK = 4I + 33FH 3.2 ZSPK = 8I + 68FH 1.8 ZSPK = 8I + 68FH, VDD = 3.7V 0.93 ZSPK = 4I + 33FH 2.5 ZSPK = 8I + 68FH 1.4 ZSPK = 8I + 68FH, VDD = 3.7V 0.77 f = 1kHz, POUT = 1W, TA = +25NC, ZSPK = 4I + 33FH 0.02 f = 1kHz, POUT = 0.5W, TA = +25NC, ZSPK = 8I + 68FH 0.013 MAX UNITS W 0.06 % Dynamic Range DR A-weighted, all gain settings, VRMS = 4.55V (clipping), 24- or 32-bit data 105 dB Output Noise VN A-weighted, all gain settings, 24- or 32-bit data (Note 4) 25 FVRMS Gain (Relative to a 2.1dBV Reference Level) Current Limit Efficiency AV GAIN = GND through 100kI 14.4 15 15.6 GAIN = GND 11.4 12 12.6 GAIN = unconnected 8.4 9 9.6 GAIN = VDD 5.4 6 6.6 GAIN = VDD through 100kI 2.4 3 3.6 ILIM h ZSPK = 8I + 68FH, THD+N = 10%, f = 1kHz, gain = 12dB DAC Gain Error 2.8 A 92 % 1 Frequency Response -0.2 dB % +0.2 dB DAC DIGITAL FILTERS VOICE MODE IIR LOWPASS FILTER (LRCLK < 30kHz) Passband Cutoff Stopband Cutoff Stopband Attenuation Maxim Integrated Ripple limit cutoff 0.443 x fS -3dB cutoff 0.446 x fS fPLP Hz 0.464 x fS fSLP f > fSLP 75 Hz dB 5 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AUDIO MODE FIR LOWPASS FILTER (30kHz < LRCLK < 50kHz) Passband Cutoff Stopband Cutoff fPLP Ripple limit cutoff 0.43 x fS -3dB cutoff 0.47 x fS -6.02dB cutoff 0.5 x fS 0.58 x fS fSLP Stopband Attenuation f > fSLP AUDIO MODE FIR LOWPASS FILTER (LRCLK > 50kHz) Passband Cutoff Stopband Cutoff Hz 60 Ripple limit cutoff 0.24 x fS -3dB cutoff 0.31 x fS fPLP dB Hz 0.477 x fS fSLP Stopband Attenuation f < fSLP Hz 60 Hz dB DIGITAL AUDIO INTERFACE I2S/left justified mode Resolution BCLK Frequency Range 16/24/32 TDM mode fBCLK BCLK must be 32, 48, or 64X of LRCLK Bits 16 0.2432 6.4512 MHz BCLK High Time tBCLKH 40 ns BCLK Low Time tBCLKL 40 ns Maximum Low Frequency BCLK and LRCLK Jitter RMS jitter below 40kHz Maximum High Frequency BCLK and LRCLK Jitter RMS jitter above 40kHz ns Input High Voltage VIH Digital audio inputs Input Low Voltage VIL Digital audio inputs Maxim Integrated 0.5 12 1.3 V 0.6 V 6 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER Input Leakage Current Input Capacitance DIN to BCLK Setup Time LRCLK to BCLK Setup Time DIN to BCLK Hold Time LRCLK to BCLK Hold Time SYMBOL IIH, IIL CONDITIONS VIN = 0V, VDD = 5.5V, TA = +25NC MIN TYP -1 CIN MAX UNITS +1 FA 3 tSETUP 10 tSYNCSET 10 tHOLD 10 tSYNCHOLD 10 pF ns SD_MODE COMPARATOR TRIP POINTS B0 See SD_MODE and shutdown operation for details B1 B2 SD_MODE Pulldown Resistor RPD 0.08 0.16 0.355 0.65 0.77 0.825 1.245 1.4 1.5 92 100 108 V kI GAIN COMPARATOR TRIP POINTS VGAIN AV = 3dB gain 0.65 x VDD 0.85 x VDD AV = 6dB gain 0.9 x VDD VDD AV = 9dB gain 0.4 x VDD 0.6 x VDD AV = 12dB gain 0 0.1 x VDD AV = 15dB gain 0.15 x VDD 0.35 x VDD V Note 2: 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design. Note 3: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For RL = 8I, LL = 68FH. For RL = 4I, LL = 33FH. Note 4: Digital silence used for input signal. Maxim Integrated 7 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers tBCLK tBCLKH tBCLKL BCLK (INPUT) tSYNCSET tSYNCHOLD LRCLK (INPUT) tSETUP tHOLD DIN (INPUT) LSB MSB LSB MSB Figure 1. I2S Audio Interface Timing Diagram (MAX98355A) tBCLK tBCLKH tBCLKL BCLK (INPUT) tSYNCSET tSYNCHOLD LRCLK (INPUT) tSETUP tHOLD DIN (INPUT) LSB MSB LSB MSB Figure 2. Left-Justified Audio Interface Timing Diagram (MAX98355B) tBCLK tBCLK tBCLKH tBCLKL tBCLKL BCLK (INPUT) tSYNCSET tSYNCSET tSYNCHOLD LRCLK (INPUT) tSYNCHOLD LRCLK (INPUT) tSETUP tHOLD DIN (INPUT) tBCLKH BCLK (INPUT) LSB MSB MAX98355A tSETUP tHOLD DIN (INPUT) LSB MSB MAX98355B Figure 3. TDM Audio Interface Timing Diagram Maxim Integrated 8 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) General SHUTDOWN CURRENT vs. SUPPLY VOLTAGE QUIESCENT CURRENT vs. SUPPLY VOLTAGE MAX98355A/B toc02 3.0 0.6 SHUTDOWN CURRENT (µA) 3.5 QUIESCENT CURRENT (mA) 0.7 MAX98355A/B toc01 4.0 2.5 2.0 1.5 1.0 0.5 0.4 0.3 0.2 0.1 0.5 0 0 2.5 3.0 3.5 4.0 4.5 5.0 2.5 5.5 3.0 SUPPLY VOLTAGE (V) 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) Speaker Amplifier TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER -40 -50 f = 6kHz -60 f = 1kHz -70 -80 -30 -40 -50 f = 6kHz -60 -70 f = 1kHz -80 f = 100Hz 0.001 0.01 0.1 OUTPUT POWER (W) Maxim Integrated 1 10 -100 0 -10 -20 VDD = 5V GAIN = 12dB ZSPK = 8I + 68µH -30 -40 -50 f = 6kHz -60 -70 f = 1kHz -80 f = 100Hz -90 -90 -100 -20 VDD = 4.2V GAIN = 12dB ZSPK = 8I + 68µH THD+N RATIO (dB) -30 -10 MAX98355A/B toc04 VDD = 3.7V GAIN = 12dB ZSPK = 8I + 68µH THD+N RATIO (dB) THD+N RATIO (dB) -20 0 MAX98355A/B toc03 0 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX98355A/B toc05 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 0.001 0.01 0.1 OUTPUT POWER (W) f = 100Hz -90 1 10 -100 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 9 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) f = 6kHz -60 f = 1kHz -70 -80 f = 100Hz 0.01 0.1 1 -50 f = 6kHz -60 -70 f = 1kHz 1 -100 10 100 0.001 0.01 0.1 1 THD+N RATIO (dB) -30 -40 -50 -60 POUT = 100mW -70 1k 10k 100k -100 VDD = 5V GAIN = 12dB ZSPK = 8I + 68µH -20 10 MAX98355A/B toc11 -20 0 -10 THD+N RATIO (dB) MAX98355A/B toc09 VDD = 4.2V GAIN = 12dB ZSPK = 8I + 68µH -30 -40 -50 -60 POUT = 150mW -70 -80 POUT = 500mW -90 FREQUENCY (Hz) Maxim Integrated 0 -10 -80 POUT = 350mW 10 f = 100Hz -90 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY POUT = 75mW -90 f = 1kHz TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY -50 -80 0.1 -70 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY -40 -70 0.01 f = 6kHz -60 OUTPUT POWER (W) -30 -60 0.001 -50 OUTPUT POWER (W) VDD = 3.7V GAIN = 12dB ZSPK = 8I + 68µH -20 -100 10 -40 -80 f = 100Hz -90 -30 OUTPUT POWER (W) 0 THD+N RATIO (dB) -40 VDD = 5V GAIN = 12dB ZSPK = 4I + 33µH -20 MAX98355A/B toc10 0.001 -10 -100 -30 -80 -90 -100 0 -10 THD+N RATIO (dB) -40 -50 -20 THD+N RATIO (dB) THD+N RATIO (dB) -30 VDD = 4.2V GAIN = 12dB ZSPK = 4I + 33µH -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX98355A/B toc07 VDD = 3.7V GAIN = 12dB ZSPK = 4I + 33µH -20 0 MAX98355A/B toc06 0 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX98355A/B toc08 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER 10 100 POUT = 850mW -90 1k FREQUENCY (Hz) 10k 100k -100 10 100 1k 10k 100k FREQUENCY (Hz) 10 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY -50 -60 POUT = 150mW -80 -40 -50 -60 -70 POUT = 250mW POUT = 600mW 1k 10k -100 100k 10 1.5 THD+N = 10% 1.0 0.5 THD+N = 1% 1k 10k LOAD (I) Maxim Integrated POUT = 350mW 10 100 100 1k 10k 100k OUTPUT POWER vs. LOAD RESISTANCE 2.0 THD+N = 10% 1.5 MAX98355A/B toc14 POUT = 1.5W FREQUENCY (Hz) 1.0 4.5 VDD = 5V GAIN = 12dB ZSPK = RLOAD I + 68µH 4.0 3.5 3.0 2.5 THD+N = 10% 2.0 1.5 1.0 THD+N = 1% THD+N = 1% 0.5 0 10 -70 -100 100k VDD = 4.2V GAIN = 12dB ZSPK = RLOAD I + 68µH 2.5 0.5 0 1 -60 OUTPUT POWER vs. LOAD RESISTANCE OUTPUT POWER (W) 2.0 100 3.0 MAX98355A/B toc15 VDD = 3.7V GAIN = 12dB ZSPK = RLOAD I + 68µH -50 FREQUENCY (Hz) OUTPUT POWER vs. LOAD RESISTANCE 2.5 -40 -90 OUTPUT POWER (W) 100 POUT = 850mW -90 MAX98355A/B toc16 10 -30 -80 FREQUENCY (Hz) OUTPUT POWER (W) -20 -80 -90 -100 -30 VDD = 5V GAIN = 12dB ZSPK = 4I + 33µH -10 THD+N RATIO (dB) -40 -70 -20 THD+N RATIO (dB) THD+N RATIO (dB) -30 VDD = 4.2V GAIN = 12dB ZSPK = 4I + 33µH -10 0 MAX98355A/B toc13 VDD = 3.7V GAIN = 12dB ZSPK = 4I + 33µH -20 0 MAX98355A/B toc12 0 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX98355A/B toc17 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY 0 1 10 LOAD (I) 100 1 10 100 LOAD (I) 11 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) OUTPUT POWER vs. SUPPLY VOLTAGE THD+N = 10% 1.0 THD+N = 1% 0.5 0 THD+N = 10% 2.5 2.0 1.5 THD+N = 1% 1.0 3.0 3.5 4.0 4.5 5.0 3.0 4.0 4.5 5.0 50 40 30 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT POWER PER CHANNEL (W) Maxim Integrated 1k 10k 100k EFFICIENCY vs. OUTPUT POWER 100 MAX98355A/B toc22 90 80 70 60 50 40 90 80 70 60 50 40 30 30 VDD = 3.7V GAIN = 12dB ZSPK = 8I + 68µH 100 FREQUENCY (Hz) EFFICIENCY (%) 60 20 10 5.5 EFFICIENCY vs. OUTPUT POWER EFFICIENCY (%) 70 3.5 100 MAX98355A/B toc21 80 -1 SUPPLY VOLTAGE (V) EFFICIENCY vs. OUTPUT POWER 90 0 -3 2.5 SUPPLY VOLTAGE (V) 100 1 -2 0.5 5.5 MAX98355A-B toc20 3.0 ZSPK = 8I + 68µH 2 0 2.5 EFFICIENCY (%) MAX98355A/B toc19 GAIN = 12dB ZSPK = 4I + 33µH 3.5 NORMALIZED GAIN vs. FREQUENCY 3 MAX98355A/B toc23 1.5 OUTPUT POWER PER CHANNEL (W) 2.0 OUTPUT POWER (W) MAX98355A/B toc18 GAIN = 12dB ZSPK = 8I + 68µH 4.0 NORMALIZED GAIN (dB) OUTPUT POWER vs. SUPPLY VOLTAGE 2.5 20 20 VDD = 4.2V GAIN = 12dB ZSPK = 8I + 68µH 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT POWER PER CHANNEL (W) VDD = 5V GAIN = 12dB ZSPK = 8I + 68µH 10 0 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT POWER PER CHANNEL (W) 12 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) EFFICIENCY vs. OUTPUT POWER 50 40 30 80 60 50 40 30 20 0 0 0 2.0 MAX98355A-B toc27 100 PSRR (dB) 60 40 20 20 f = 1kHz ZSPK = 8I + 68µH 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) Maxim Integrated 5.0 5.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT POWER PER CHANNEL (W) INBAND OUTPUT SPECTRUM 40 30 VDD = 5V GAIN = 12dB ZSPK = 4I + 33µH 0 50 30 40 2.5 20 BCLK = 6.144MHz LRCLK = 96kHz ZSPK = 8I + 68µH 0 -20 AMPLITUDE (dBV) 80 60 50 VDD = 5V ZSPK = 8I + 68µH 90 70 50 10 MAX98355A-B toc28 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY 70 2.5 1.5 POWER-SUPPLY REJECTION RATIO vs. SUPPLY VOLTAGE 80 0 1.0 OUTPUT POWER PER CHANNEL (W) 90 10 0.5 OUTPUT POWER PER CHANNEL (W) 100 60 20 VDD = 4.2V GAIN = 12dB ZSPK = 4I + 33µH 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 70 30 20 VDD = 3.7V GAIN = 12dB ZSPK = 4I + 33µH 10 PSRR (dB) 90 MAX98355A/B toc29 60 70 MAX98355A/B toc26 80 EFFICIENCY (%) 70 90 EFFICIENCY (%) 80 EFFICIENCY vs. OUTPUT POWER 100 MAX98355A/B toc25 90 EFFICIENCY (%) EFFICIENCY vs. OUTPUT POWER 100 MAX98355A/B toc24 100 -40 -60 -80 -100 10 -120 0 -140 10 100 1k FREQUENCY (Hz) 10k 100k 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) 13 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) -80 -20 -40 -60 -80 -40 -60 -80 -100 -100 -100 -120 -120 -120 -140 -140 2 4 6 8 10 12 14 16 18 20 -140 0 2 FREQUENCY (kHz) 4 6 8 10 12 14 16 18 20 -20 -40 -60 -80 8 10 12 14 16 18 20 -40 -60 -80 -100 -100 -120 -120 -140 -140 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 FREQUENCY (kHz) -40 -60 -80 -20 -40 -60 -80 -100 -100 -120 -120 -140 BCLK = 2.8224MHz LRCLK = 44.1kHz ZSPK = 8I + 68µH 0 AMPLITUDE (dBV) -20 10 12 14 16 18 20 INBAND OUTPUT SPECTRUM 20 MAX98355A/B toc35 BCLK = 2.8224MHz LRCLK = 44.1kHz ZSPK = 8I + 68µH 0 8 FREQUENCY (kHz) INBAND OUTPUT SPECTRUM 20 AMPLITUDE (dBV) 6 BCLK = 3.072MHz LRCLK = 48kHz ZSPK = 8I + 68µH 0 AMPLITUDE (dBV) -20 4 INBAND OUTPUT SPECTRUM 20 MAX98355A/B toc33 BCLK = 3.072MHz LRCLK = 48kHz ZSPK = 8I + 68µH 0 -140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) Maxim Integrated 2 FREQUENCY (kHz) INBAND OUTPUT SPECTRUM 20 AMPLITUDE (dBV) 0 FREQUENCY (kHz) MAX98355A/B toc36 0 MAX98355A/B toc34 -60 BCLK = 5.6448MHz LRCLK = 88.2kHz ZSPK = 8I + 68µH 0 MAX98355A/B toc32 -20 20 AMPLITUDE (dBV) -40 INBAND OUTPUT SPECTRUM BCLK = 5.6448MHz LRCLK = 88.2kHz ZSPK = 8I + 68µH 0 AMPLITUDE (dBV) -20 MAX98355A/B toc30 BCLK = 6.144MHz LRCLK = 96kHz ZSPK = 8I + 68µH 0 AMPLITUDE (dBV) INBAND OUTPUT SPECTRUM 20 MAX98355A/B toc31 INBAND OUTPUT SPECTRUM 20 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) 14 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) INBAND OUTPUT SPECTRUM -20 AMPLITUDE (dBV) -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 -140 -140 2 4 6 8 10 12 14 16 18 20 0 2 4 6 FREQUENCY (kHz) INBAND OUTPUT SPECTRUM BCLK = 1.024MHz LRCLK = 16kHz ZSPK = 8I + 68µH 0 -40 -60 -80 BCLK = 1.024MHz LRCLK = 16kHz ZSPK = 8I + 68µH 0 -20 AMPLITUDE (dBV) AMPLITUDE (dBV) -20 -40 -60 -80 -100 -100 -120 -120 -140 -140 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 FREQUENCY (kHz) -40 -60 -80 -20 -40 -60 -80 -100 -100 -120 -120 -140 BCLK = 512kHz LRCLK = 8kHz ZSPK = 8I + 68µH 0 AMPLITUDE (dBV) AMPLITUDE (dBV) -20 10 12 14 16 18 20 INBAND OUTPUT SPECTRUM 20 MAX98355A-B toc41 BCLK = 512kHz LRCLK = 8kHz ZSPK = 8I + 68µH 0 8 FREQUENCY (kHz) INBAND OUTPUT SPECTRUM 20 -140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) Maxim Integrated 10 12 14 16 18 20 INBAND OUTPUT SPECTRUM 20 MAX98355A-B toc39 20 8 FREQUENCY (kHz) MAX98355A-B toc40 0 MAX98355A-B toc42 AMPLITUDE (dBV) -20 BCLK = 2.048MHz LRCLK = 32kHz ZSPK = 8I + 68µH 0 MAX98355A/B toc38 BCLK = 2.048MHz LRCLK = 32kHz ZSPK = 8I + 68µH 0 INBAND OUTPUT SPECTRUM 20 MAX98355A/B toc37 20 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) 15 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Pin Configuration TOP VIEW BUMP SIDE DOWN + MAX98355A MAX98355B SD_MODE VDD OUTP A1 A2 A3 DIN GAIN OUTN B1 B2 B3 BCLK GND LRCLK C1 C2 C3 WLP Pin Description PIN NAME A1 SD_MODE A2 VDD A3 OUTP B1 DIN FUNCTION Shutdown and Channel Select. Determines left, right, or left/2 + right/2 mix and also used for shutdown. See Table 5. Power-Supply Input Positive Speaker Amplifier Output Digital Input Signal Amplifier Gain B2 GAIN Gain Connections Gain (dB) GND through 100kI resistor 15 GND 12 Unconnected 9 VDD 6 VDD through 100kI resistor 3 B3 OUTN Negative Speaker Amplifier Output C1 BCLK Bit Clock Input Signal. BCLK must be 32, 48, or 64 x LRCLK. Valid frequency range: 256kHz–6.144MHz. C2 GND Ground C3 LRCLK Maxim Integrated Left/Right Word Clock Input. Valid frequency range: 8kHz–96kHz. 16 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Detailed Description The MAX98355A/MAX98355B are digital PCM input Class D power amplifiers. The MAX98355A accepts standard I2S data through DIN, BCLK, and LRCLK while the MAX98355B accepts left justified data through the same inputs. Both versions can accept 16-bit TDM data with up to four slots. These devices eliminate the need for an external MCLK signal that is typically required for PCM data transmission. SD_MODE selects which data word is output by the amplifier and is used to put the IC into shutdown. The GAIN pin offers five gain settings and allows the output of the amplifier to be tuned to the appropriate level. The output stage features low-quiescent current, comprehensive click-and-pop suppression, and excellent RF immunity. The ICs offer Class AB audio performance with Class D efficiency in a minimal board-space solution. The Class D amplifier features spread-spectrum modulation with edge-rate and overshoot control circuitry that offers significant improvements in switch-mode amplifier radiated emissions. The amplifier features click-and-pop suppression that reduces audible transients on startup and shutdown. The amplifier includes thermal-overload and short-circuit protection. Digital Audio Interface Modes The input stage of the digital audio interface is highly flexible, supporting 8kHz, 16kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz sampling rates with 16/24/32bit resolution for I2S/left justified data as well as up to a 4-slot, 16-bit time division multiplexed (TDM) format (only the first two slots can be selected by the ICs). When LRCLK has a 50% duty cycle, the data format is determined by the part number selection (MAX98355A/MAX98355B). When a frame sync pulse is used for the LRCLK the data format is automatically configured to TDM mode. The frame sync pulse indicates the beginning of the first time slot. MCLK Elimination The ICs eliminate the need for the external MCLK signal that is typically used for PCM communication. This reduces EMI and possible board coupling issues in addition to reducing the size and pin-count of the ICs. Maxim Integrated Jitter Tolerance The ICs feature a very high BCLK and LRCLK jitter tolerance of 0.5ns for RMS jitter below 40kHz and 12ns for wideband RMS jitter while maintaining a dynamic range greater than 98dB (Table 1). BCLK Polarity When operating in I2S/left justified mode, incoming serial data is always clocked-in on the rising edge of BCLK. In TDM mode, the MAX98355A clocks-in serial data on the rising edge of BCLK while the MAX98355B clocks in serial data on the falling edge of BCLK (Table 2). LRCLK Polarity LRCLK specifies whether left-channel data or right-channel data is currently being read by the digital audio interface. The MAX98355A indicates the left channel word when LRCLK is low, and the MAX98355B indicates the left channel word when LRCLK is high (Table 3). LRCLK supports 8kHz, 16kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz frequency clocks (±5% at each rate). Table 1. RMS Jitter Tolerance FREQUENCY RMS JITTER TOLERANCE (ns) < 40kHz 0.5 40kHz–BCLK 12 Table 2. BCLK Polarity MODE PART NUMBER BCLK POLARITY I2S MAX98355A Rising edge Left Justified MAX98355B Rising edge TDM MAX98355A Rising edge MAX98355B Falling edge Table 3. LRCLK Polarity PART NUMBER LRCLK POLARITY (LEFT CHANNEL) MAX98355A Low MAX98355B High 17 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers PCM Timing Characteristics The MAX98355A follows standard I2S timing by setting a delay of one BCLK cycle after the LRCLK transition before the beginning of a new data word (Figure 4 and Figure 5). The MAX98355B follows the left justified timing specification by aligning the LRCLK transitions with the beginning of a new data word (Figure 6 and Figure 7). Figure 8 and Figure 9 show TDM operation, in which a frame-sync pulse is used for LRCLK. In TDM mode, there must be 32, 48, or 64 BCLK cycles per LRCLK. In TDM mode, the IC only accepts 16-bit formatted data and only the first two TDM slots can be selected. However, if the first 16 bits are selected (SD_MODE = logic-high), then the bit-depth or number of channels has no effect as long as there are 32, 48, or 64 BCLK cycles per LRCLK. All extra bits in the frame are ignored (Figure 10 and Figure 11). If the second 16 bits are selected (SD_MODE = logichigh through RSMALL), then the TDM data must be 16-bit data and cannot include more than 4 channels (64 BCLK cycles). TDM operation is available in both ICs. I2S: 16-BIT DATA, 16 BITS/CHANNEL, SD_MODE = LOGIC-HIGH RIGHT LRLCK LEFT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 IGNORED I2S: 16-BIT DATA, 16 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RSMALL LRLCK RIGHT LEFT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 IGNORED IGNORED I2S: 16-BIT DATA, 16 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RLARGE LRLCK RIGHT LEFT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 LEFT AND RIGHT AVERAGED Figure 4. MAX98355A I2S Digital Audio Interface Timing, 16-Bit Resolution Maxim Integrated 18 Maxim Integrated DIN BCLK LRLCK LEFT D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT IGNORED D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I2S: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RLARGE DIN BCLK LRLCK LEFT D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I2S: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RSMALL DIN BCLK LRLCK I2S: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = LOGIC-HIGH LEFT AND RIGHT AVERAGED D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RIGHT D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RIGHT IGNORED D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RIGHT D23 D22 IGNORED D23 D22 D23 D22 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Figure 5. MAX98355A I2S Digital Audio Interface Timing, 24-Bit Resolution 19 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers LEFT JUSTIFIED: 16-BIT DATA, SD_MODE = LOGIC-HIGH LRCLK RIGHT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D6 D5 D4 D3 D2 D1 D0 D15 D14 IGNORED LEFT JUSTIFIED: 16-BIT DATA, SD_MODE = PULLUP THROUGH RSMALL LRCLK RIGHT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 IGNORED IGNORED LEFT JUSTIFIED: 16-BIT DATA, SD_MODE = PULLUP THROUGH RLARGE LRCLK RIGHT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 LEFT AND RIGHT AVERAGED Figure 6. MAX98355B Left-Justified Digital Audio Interface Timing, 16-Bit Resolution Maxim Integrated 20 Maxim Integrated D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT IGNORED D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT DIN BCLK LRCLK D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT LEFT JUSTIFIED: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RLARGE DIN BCLK LRCLK LEFT JUSTIFIED: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RSMALL DIN BCLK LRCLK LEFT JUSTIFIED: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = LOGIC-HIGH D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RIGHT D7 D6 D5 D4 D3 D2 D1 D0 RIGHT D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 LEFT AND RIGHT AVERAGED D7 D6 D5 D4 D3 D2 D1 D0 IGNORED D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 RIGHT D22 D23 LEFT IGNORED D23 D22 LEFT D31 D30 D29 LEFT MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Figure 7. MAX98355B Left-Justified Digital Audio Interface Timing, 24-Bit Resolution 21 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = LOGIC-HIGH R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 IGNORED R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 IGNORED TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 IGNORED IGNORED TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 LEFT AND RIGHT AVERAGED Figure 8. MAX98355A TDM Digital Audio Interface Timing Maxim Integrated 22 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = LOGIC-HIGH R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 IGNORED R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 IGNORED TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 IGNORED IGNORED TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 LEFT AND RIGHT AVERAGED Figure 9. MAX98355B TDM Digital Audio Interface Timing Maxim Integrated 23 Maxim Integrated Y0 L15 L14 L13 L12 L11 L10 L9 IGNORED Y1 L8 L7 L6 L5 L4 L3 L2 Y1 L8 IGNORED Y0 L15 L14 L13 L12 L11 L10 L9 L7 L6 L5 L4 L3 L2 DIN BCLK LRCLK Y0 L15 L14 L13 L12 L11 L10 L9 IGNORED Y1 L8 L7 L6 L5 L3 L2 L1 L1 L1 L0 R15 R14 R13 R12 R11 R10 R9 L0 R15 R14 R13 R12 R11 R10 R9 L0 R15 R14 R13 R12 R11 R10 R9 LEFT AND RIGHT AVERAGED L4 TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE DIN BCLK LRCLK TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL DIN BCLK LRCLK TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = LOGIC-HIGH R8 R8 R8 R7 R7 R7 R6 R6 R6 R5 R5 R5 R4 R4 R4 R3 R3 R3 R2 R2 R2 R1 R1 R1 R0 X15 X14 X13 X12 X11 X10 X9 R0 X15 X14 X13 X12 X11 X10 X9 R0 X15 X14 X13 X12 X11 X10 X9 X7 X8 X8 X7 X7 IGNORED X8 X6 X6 X6 X5 X5 X5 X4 X4 X4 X3 X3 X3 X2 X2 X2 X1 X1 X1 IGNORED X0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 IGNORED X0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 X0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y8 Y8 Y7 Y7 Y7 Y6 Y6 Y6 Y5 Y5 Y5 Y4 Y4 Y4 Y3 Y3 Y3 Y2 Y2 Y2 Y1 Y1 Y1 Y0 L15 L14 Y0 L15 L14 Y0 L15 L14 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Figure 10. MAX98355A TDM Digital Audio Interface Timing, Example of Four 16-Bit Slots 24 Maxim Integrated Y1 Y0 L15 L14 L13 L12 L11 L10 L9 IGNORED L8 L7 L6 L5 L4 L3 L2 L1 Y1 L8 IGNORED Y0 L15 L14 L13 L12 L11 L10 L9 L7 L6 L5 L4 L3 L2 L1 DIN BCLK LRCLK Y0 L15 L14 L13 L12 L11 L10 L9 IGNORED Y1 L8 L7 L6 L5 L4 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 L0 R15 R14 R13 R12 R11 R10 R9 L0 R15 R14 R13 R12 R11 R10 R9 LEFT AND RIGHT AVERAGED L3 TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE DIN BCLK LRCLK TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL DIN BCLK LRCLK TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = LOGIC-HIGH R8 R8 R8 R7 R7 R7 R6 R6 R6 R5 R5 R5 R4 R4 R4 R3 R3 R3 R2 R2 R2 R1 R0 X15 X14 X13 X12 X11 X10 X9 R1 R0 X15 X14 X13 X12 X11 X10 X9 R1 R0 X15 X14 X13 X12 X11 X10 X9 X8 X7 X8 X8 X7 X7 IGNORED X6 X6 X6 X5 X5 X5 X4 X3 X4 X3 X4 X3 X2 X2 X2 X0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 X0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 X1 IGNORED X0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 IGNORED X1 X1 Y8 Y8 Y8 Y7 Y7 Y7 Y6 Y6 Y6 Y5 Y5 Y5 Y4 Y4 Y4 Y3 Y3 Y3 Y2 Y2 Y2 Y1 Y1 Y1 Y0 L15 L14 Y0 L15 L14 Y0 L15 L14 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Figure 11. MAX98355B TDM Digital Audio Interface Timing, Example of Four 16-Bit Slots 25 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers SD_MODE and Shutdown Operation Standby Mode If BCLK stops toggling, the ICs automatically enter standby mode. In standby mode, the Class D speaker is turned off and the outputs go into a high-impedance state, ensuring that unwanted current is not transferred to the load during this condition. Standby mode should not be used in place of the shutdown mode, as the shutdown mode provides the lowest power consumption and the best power-on/off click-and-pop performance. The ICs feature a low-power shutdown mode, drawing less than 0.6FA (typ) of supply current. During shutdown, all internal blocks are turned off, including setting the output stage to a high-impedance state. Drive SD_MODE low to put the ICs into shutdown. The state of SD_MODE determines the audio channel that is sent to the amplifier output (Table 5). Drive SD_MODE high to select the left word of the stereo input data. Drive SD_MODE high through a sufficiently small resistor to select the right word of the stereo input data. Drive SD_MODE high through a sufficiently large resistor to select both the left and right words of the stereo input data ((left + right)/2). RLARGE and RSMALL are determined by the VDDIO voltage (logic voltage from control interface) that is driving SD_MODE according to the following two equations: DAC Digital Filters The DAC features a digital lowpass filter that is automatically configured for voice playback or music playback based on the sample rate that is used. This filter eliminates the effect of aliasing and any other high-frequency noise that might otherwise be present. Table 4 shows the digital filter settings that are automatically selected. RSMALL (kI) = 98.5 x VDDIO - 100 RLARGE (kI) = 222.2 x VDDIO - 100 Table 4. Digital Filter Settings LRCLK FREQUENCY -3dB CUTOFF FREQUENCY RIPPLE LIMIT CUTOFF FREQUENCY STOPBAND CUTOFF FREQUENCY STOPBAND ATTENUATION (dB) fLRCLK < 30kHz 0.446 x fLRCLK 0.443 x fLRCLK 0.464 x fLRCLK 75 30kHz < fLRCLK < 50kHz 0.47 x fLRCLK 0.43 x fLRCLK 0.58 x fLRCLK 60 fLRCLK > 50kHz 0.31 x fLRCLK 0.24 x fLRCLK 0.477 x fLRCLK 60 Table 5. SD_MODE Control SELECTED CHANNEL SD_MODE STATUS High VSD_MODE > B2 trip point (1.4V typ) Left Pullup through RSMALL B2 trip point (1.4V typ) > VSD_MODE > B1 trip point (0.77V typ) Right Pullup through RLARGE B1 trip point (0.77 typ) > VSD_MODE > B0 trip point (0.16V typ) Left/2 + Right/2 Low B0 trip point (0.16V typ) > VSD_MODE Shutdown Table 6. Examples of SD_MODE Pullup Resistor Values LOGIC VOLTAGE LEVEL (VDDIO) (V) RSMALL (kI, 1% TOLERANCE) RLARGE (kI, 1% TOLERANCE) 1.8 76.8 300 3.3 226 634 Maxim Integrated 26 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers When the devices are configured in left-channel mode (SD_MODE is directly driven to logic-high by the control interface), take care to avoid violating the Absolute Maximum Ratings limits for SD_MODE. Ensuring that VDD is always greater than VDDIO is one way to prevent SD_MODE from violating the Absolute Maximum Ratings limits. If this is not possible in the application (e.g., if VDD < 3.0V and VDDIO = 3.3V, then it is necessary to add a small resistance (~2kI) in series with SD_MODE to limit the current into the SD_MODE pin. This is not a concern when using the right channel or (left + right)/2 modes. Figure 12 and Figure 13 show how to connect an external resistor to SD_MODE when using an open-drain driver or a pullup/down driver. PROCESSOR VDDIO R Ultra-Low EMI Filterless Output Stage Traditional Class D amplifiers require the use of external LC filters, or shielding, to meet EN55022B electromagnetic-interference (EMI) regulation standards. Maxim’s active emissions-limiting edge-rate control circuitry and spread-spectrum modulation reduces EMI emissions while maintaining up to 92% efficiency. LEFT MODE MAX98355A MAX98355B VSD_MODE GPIO Class D Speaker Amplifier The filterless Class D amplifier offers much higher efficiency than Class AB amplifiers. The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET on-resistance and quiescent current overhead. B2 (1.4V typ) RIGHT MODE 100kI ±8% B1 (0.77V typ) (LEFT + RIGHT)/2 MODE B0 (0.16V typ) Figure 12. SD_MODE Resistor Connection Using Open-Drain Driver PROCESSOR MAX98355A MAX98355B VDDIO GPIO R VSD_MODE LEFT MODE B2 (1.4V typ) RIGHT MODE 100kI ±8% B1 (0.77V typ) (LEFT + RIGHT/2 MODE B0 (0.16V typ) Figure 13. SD_MODE Resistor Connection Using Pullup/Down Driver Maxim Integrated 27 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Maxim’s spread-spectrum modulation mode flattens wideband spectral components while proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency. The ICs’ spread-spectrum modulator randomly varies the switching frequency by Q10kHz around the center frequency (300kHz). Above 10MHz, the wideband spectrum looks like noise for EMI purposes (Figure 14). Speaker Current Limit If the output current of the speaker amplifier exceeds the current limit (2.8A typ), the IC disables the outputs for approximately 100Fs. At the end of the 100Fs, the outputs are re-enabled. If the fault condition still exists, the IC continues to disable and re-enable the outputs until the fault condition is removed. Gain Selection The ICs offer five programmable gain selections through a single gain input (GAIN). Gain is referenced to the Output signal level (dBV) = input signal level (dBFS) + 2.1dB + selected amplifier gain (dB) where 0dBFS is referenced to 0dBV. Click-and-Pop Suppression The IC speaker amplifier features Maxim’s comprehensive click-and-pop suppression. During startup, the clickand-pop suppression circuitry reduces audible transient sources internal to the device by ramping the input signal from mute to 0dB. When entering shutdown, the differential speaker outputs immediately go into a high-impedance state without creating audible click-and-pop noise. Table 7. Gain Selection 90 EMISSIONS LEVEL (dBµV/m) full-scale output of the DAC, which is 2.1dBV (Table 7). Assuming that the desired output swing is not limited by the supply voltage rail, the IC’s output level can be calculated based on the digital input signal level and selected amplifier gain according to the following equation: 70 50 30 10 GAIN GAIN (dB) Connect to GND through 100kI Q5% resistor 15 Connect to GND 12 Unconnected 9 Connect to VDD 6 Connect to VDD through 100kI Q5% resistor 3 -10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) Figure 14. EMI with 12in of Speaker Cable and No Output Filtering Maxim Integrated 28 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Applications Information 2.5V TO 5.5V 2.5V TO 5.5V 10µF 0.1µF SD_MODE GAIN B2 CODEC GPIO* BCLK BIT CLOCK FRAME CLOCK LRCLK DIN DATA OUT A1 C3 B1 0.1µF SD_MODE GAIN B2 CODEC VDD A2 A3 C1 10µF MAX98355A MAX98355B GPIO* OUTP BCLK BIT CLOCK B3 OUTN FRAME CLOCK LRCLK DIN DATA OUT C2 GND A1 VDD A2 A3 C1 C3 B1 MAX98355A MAX98355B B3 OUTP OUTN C2 GND *RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH. THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW. *RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH. THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW. Figure 15. Left-Channel PCM Operation with 6dB Gain Figure 16. Left-Channel PCM Operation with 12dB Gain 2.5V TO 5.5V 10µF CODEC GPIO* BIT CLOCK FRAME CLOCK DATA OUT RSMALL (76.8kI)** 0.1µF VDD GAIN SD_MODE BCLK LRCLK DIN A1 B2 A2 A3 C1 C3 B1 MAX98355A MAX98355B B3 OUTP OUTN C2 GND *RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH. **76.8kI ASSUMES VGPIO = 1.8V. THE MAX98355A/MAX98355B ARE SHUTDOWN WHEN GPIO IS LOW. Figure 17. Right-Channel PCM Operation with 6dB Gain Maxim Integrated 29 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers 2.5V TO 5.5V 10µF 0.1µF VDD GAIN SD_MODE BCLK LRCLK DIN A1 B2 A2 A3 C1 OUTP MAX98355A MAX98355B C3 B3 B1 OUTN C2 GND CODEC *RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH. THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW. GPIO* BIT CLOCK 2.5V TO 5.5V FRAME CLOCK 10µF DATA OUT RSMALL (76.8kI)** 0.1µF VDD GAIN SD_MODE BCLK LRCLK DIN A1 C1 C3 B1 B2 A2 A3 OUTP MAX98355A MAX98355B B3 OUTN C2 GND *RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH. **76.8kI ASSUMES VGPIO = 1.8V. THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW. Figure 18. Stereo PCM Operation Using Two ICs Maxim Integrated 30 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier’s output. The filter adds cost, size, and decreases efficiency and THD+N performance. The ICs’ filterless modulation scheme does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Because the switching frequency of the ICs is well beyond the bandwidth of most speakers, voice coil movement due to the switching frequency is very small. Use a speaker with a series inductance > 10FH. Typical 8I speakers exhibit series inductances in the 20FH to 100FH range. Power-Supply Input VDD, which ranges from 2.5V to 5.5V, powers the IC, including the speaker amplifier. Bypass VDD with a 0.1FF and 10FF capacitor to GND. Some applications might require only the 10FF bypass capacitor, making it possible to operate with a single external component. Apply additional bulk capacitance at the ICs if long input traces between VDD and the power source are used. 2.5V TO 5.5V 10µF Layout and Grounding Proper layout and grounding are essential for optimum performance. Good grounding improves audio performance and prevents switching noise from coupling into the audio signal. Use wide, low-resistance output traces. As load impedance decreases, the current drawn from the device outputs increases. At higher current, the resistance of the output traces decreases the power delivered to the load. For example, if 2W is delivered from the speaker output to a 4I load through 100mI of total speaker trace, 1.904W is being delivered to the speaker. If power is delivered through 10mI of total speaker trace, 1.951W is being delivered to the speaker. Wide output, supply, and ground traces also improve the power dissipation of the ICs. The ICs are inherently designed for excellent RF immunity. For best performance, add ground fills around all signal traces on top or bottom PCB planes. WLP Applications Information For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: Wafer-Level Packaging (WLP) and Its Applications. Figure 20 shows the dimensions of the WLP balls used on the ICs. 0.1µF 0.24mm CODEC RLARGE (300kI)** GPIO* SD_MODE BCLK BIT CLOCK LRCLK FRAME CLOCK DIN DATA OUT A1 VDD GAIN B2 A2 C1 MAX98355A C3 B1 A3 OUTP MAX98355B B3 OUTN C2 GND *LEFT AND RIGHT CHANNELS SUMMED WHEN GPIO IS HIGH. **300kI ASSUMES VGPIO = 1.8V. THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW. Figure 19. Left/2 + Right/2 PCM Operation with 6dB Gain Maxim Integrated 0.21mm Figure 20. MAX98355A/MAX98355B WLP Ball Dimensions 31 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Functional Diagram 2.5V TO 5.5V 10µF 0.1µF VDD GAIN A2 MAX98355A MAX98355B LRCLK C3 BCLK C1 DIN B1 SD_MODE A1 DIGITAL AUDIO INTERFACE B2 INTERPOLATOR DAC CLASS D OUTPUT STAGE A3 OUTP B3 OUTN C2 GND Ordering Information PART MAX98355AEWL+ MAX98355BEWL+ TEMP RANGE PIN-PACKAGE -40NC to +85NC -40NC to +85NC 9 WLP 9 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. Maxim Integrated 32 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 9 WLP W91F1+1 21-0459 Refer to Application Note 1891 E PIN 1 INDICATOR MARKING 1 COMMON DIMENSIONS A3 A A1 AAAA D A2 A 0.05 S S See Note 7 SIDE VIEW TOP VIEW E1 A 0.64 0.05 A1 0.19 0.03 A2 A3 0.45 REF 0.025 BASIC b 0.27 0.03 D1 0.80 BASIC E1 0.80 BASIC e 0.40 BASIC SD 0.00 BASIC SE 0.00 BASIC SE e B C SD B D1 A 1 2 3 A b 0.05 M S DEPOPULATED BUMPS PKG. CODE E D W91B1+7 1.260 0.040 1.260 0.040 NONE W91C1+1 1.595 0.035 1.415 0.035 NONE W91F1+1 1.435 0.015 1.345 0.015 NONE W91G1+1 1.465 0.015 1.455 0.015 NONE W91J1+1 1.238 0.015 1.238 0.015 NONE AB BOTTOM VIEW NOTES: 1. Terminal pitch is defined by terminal center to center value. 2. Outer dimension is defined by center lines between scribe lines. 3. All dimensions in millimeter. 4. Marking shown is for package orientation reference only. 5. Tolerance is ± 0.02 unless specified otherwise. 6. All dimensions apply to PbFree (+) package codes only. 7. Front - side finish can be either Black or Clear. - DRAWING NOT TO SCALE - Maxim Integrated maxim integrated TITLE APPROVAL TM PACKAGE OUTLINE 9 BUMPS, WLP PKG. 0.4mm PITCH DOCUMENT CONTROL NO. 21-0459 REV. G 1 1 33 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Revision History REVISION NUMBER REVISION DATE 0 5/12 Initial release 1 8/13 Updated Electrical Characteristics table with lower tolerances; updated Typical Operating Characteristics; updated style throughout DESCRIPTION PAGES CHANGED — 1, 3–7, 9–18, 26, 31, 33 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated Products, Inc. 34 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.