TTL
MEMORIES
SERIES 54/74. 54S/74S
PROGRAMMABLE READ-ONLY MEMORIES
BULLETIN NO. DL-S 7512258 , MAY 1975
•
Titanium-Tungsten (Ti-W) Fuse Li nks for
Fast , Low-Voltage , Reliable Programming
•
•
AII Schottky-Clamped PROM's Offer:
Fast Chip Se lect to Simplify System Decode
Choice of Three-State or Open-Collector Outputs
P-N-P Inputs for Reduced Loading on
System Buffers/Drivers
TYPE NUMBER (PACKAGES)
0
一55 C
回
to 1250 C
CS 1 6ql
ADE 9c1 1
GND$113|
NC 12
BIT SIZE
SN54188A(J , W)
SN54S188(J , W)
SN54S288(J , W)
SN54S287(J , W)
SN54S387(J , W)
SN54S470(J)
SN54S47 1(J)
SN54S472(J)
SN54S473(J)
SN74188A(J , N)
SN74S188(J , N)
SN74S288(J , N)
SN74S287(J , N)
SN74S387(J , N)
SN74S470(J , N)
SN74S47 1( J , N)
SN74S472(J , N)
SN74S473(J , N)
|rvcc
23 GND 2
22 口口 1
21 DO 2
20 D03
IP19 D04
18 DO 5
17
1
口 06
Applications Include:
Microprogramming/Firmware Loaders
Code Converters/Character Generators
Translators/Emulators
Address Mapping/Look-Up Tables
OUTPUT
512 bits
(64W x 8 B)
SN74186(J , N)
U
Full Decoding and Chip Select Simplify
System Design
to 700 C (ORGANIZATION) CONFIGURA Tl ON
SN54186(J , W)
512 BITS
(64 WORDS BY 8 BITS)
'186
M11|
ADNCAZ3
。，OC
•
256 bits
(32W x 8 B)
1024 bits
(256 W x 4 B)
2048 bits
(256 W x 8 B)
4096 bits
(512Wx8B)
256 BITS
(32 WORDS BY 8 BITS)
'188A , 'S188 , 'S288
DO 2 2(1 1
DO 3 3( 11
口 o 4 4r1 1
口 o 5 5( 11
口 066(11
口 o 7 7( 11
GND 8(]1
11) 15
11 )14
11J 13
11 )12
lI ìll
11 ìl0
ID9
cs
AD E
AD D
AD C
ADB
AD A
DO 8
TYPICAL ACCESS TIME (n5)
FROM
ADDRESS
open-collector
50
55
open-collector
open-collector
three-state
three.state
open-collector
open.collector
three-state
three'5tate
open-collector
30
25
25
42
42
50
50
55
55
34
12
12
15
15
20
20
20
20
2048 BITS
1024 BITS
(256 WORDS BY 4 BITS) (256 WORDS BY 8 BITS)
'S470 , 'S471
'S287 , 'S387
ADF 2( 11
AD E 3(11
AD D 4(1 1
ADA 5r1 1
ADB 6(11
AD C 7(11
GND 8(11
11)15 A 口 H
11)14 CS2
11J 13 CS 1
1I ~12
口 01
lI ìll
D02
11)1 口口 03
11) 9 DO 4
F:, 16 DO 7
15 DO 8
|BM TOT
13 GND 2
NC-No mternal connection
troisused for testingpurposes
The logic at TO is undefined
FROM
CHIP SELECT
Pin assignments for
all 口 f
20 VCC
19 AD H
18 AD G
17 AD F
16 CS 2
15 CS 1
14 DO B
13 DO 7
12 D06
11 DO 5
4096 BITS
(512 WORDS BY 8 BITS)
'S472 , 'S473
川
FEmvcc
ADB
11 - 11)19 ADI
2(
AD C 3
AD E
DO 1
口 02
DO 3
DO 4
GND 1
16 AD F
15 CS
14 DO 8
13
口 07
12 D06
11 DO 5
these memories are the same for all packages.
description
These monolithic TTL programmable read-only memories (PROM's) feature titanium-tungsten (Ti-W) fuse links with
each link designed to program in one millisecond or less. The Schottky-clamped versions of these PROM's offer
considerable flexibility for upgrading existing designs or improving new designs as they feature full Schottky clamping
for improved performance , low-current MOS-compatible p-n-p inputs , choice of bus-driving three-state or
open-collector outputs , and improved chip-select access times.
The high-complexity 2048- and 4096-bit PROM's can be used to significantly improve system
memories as all are offered in the 20-pin dual-in-line package having pin-row spacings of 0.300 inch.
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575
SERIES 54/74, 54S/74S
PROGRAMMABLE READ-ONLY MEMORIES
description (continued)
Data can be electronicallγprogrammed ， as desired , at any bit location in accordance with the programming procedure
specified. A 川 PROM's ， except the 'S287 and 'S387 , are supplied with a low.logic-Ievel output condition stored at each
bit location. The programming procedure open-circuits Ti-W metal links , which reverses the stored logic level at selected
locations. 丁 he procedure is irreversible; once altered , the output for that bit location is permanently programmed.
Outputs never having been altered may later be programmed to supply the opposite output leve l. Operation of the unit
within the recommended operating conditions will not alter the memory content.
A low level at the chip-select input(s) enables each PROM except the '186 , which is enabled by a high level at both
chip-select inputs. The opposite level at any chip-select input causes the outputs to be off.
The three-state output offers the convenience of an open-collector output with the speed of a totem-pole output; it can
be bus-connected to other similar outputsγet it retains the fast rise time characteristic of the TTL totem-pole output.
The open-collector output offers the capability of direct interface with a data line having a passive pull-up.
schematics of inputs and outputs
'186, '188A
下白
'186 , '188A
EOUIVALENT OF
EACHINPUT
N
…。一
V
P
CU
CT
TYPICAL OF
ALL OUTPUTS
-1.
M
~OU TeUT
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Programming circuit not shown
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EOUIVALENT OF
EACHINPUT
EM『'-明 ra-
SAUT-UEEL
唱
'S188, 'S287 , 'S288, 'S387
'S470 , 'S471 , 'S472 , 'S473
3s-TL
m-mb-AT
,
'S287 , 'S288
'S471 , 'S472
TYPICAL OF
ALL OUTPUTS
Vcc
U T P' U T
JNPUT
OUTPUT
Programming circuit not shown
Programming circuit not shown
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
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Supply voltage (see Note 1)
Input voltage
Off-state output voltage
Operating free-air temperature range: SN54' , SN54S' Circuits
SN74' , SN74S' Circuits
Storage temperature range
NOTE1: Voltage vaJues are with respect to network ground terminal (GND 2 of '186) ,. For '186 GND 1 and both GND 2 terminaJs are all
connected to system ground except during programming. The supply-voJtage rating d 口 es n 口 t appJy during programming of the '188 ,
'188A , or the 5451745 PROM's.
575
TEXAS JNCORPORATED
INSTRUMENTS
183
TVPES SN54186. SN74186
PROGRAMMA8LE READ-ONLY MEMORIES
recommended conditions for programming
Vcc
GND 1
Supply voltages (see Note 2)
MIN
4.75
High level
Input conditions (see Note 3 and 4)
Low level
Output voltage
Output current , output being programmed
Duration of programming pulse (see Note 5)
Programming duty cycle
Free-air temperature
•
NOM MAX UNITI
5 5.25
V I
-6 t
一5
Open circuit
or equivalent
-6 t V
一5
一 6.5 t 丰 V
95
mA
一 120 -130
1
20 ms
25
35 %
o
55 。 C
t Absolute ma 川 mum ratings.
丰 Clamp to ensure output does not exceed 一 0.5 V with respect to G ND 1.
NOTES: 2. Voltage values are with respect to the GND 2 terminals.
3. The high.level (of f) output of a Series 54 /7 4 or 54S /7 4S open-collector gate with no pull-up resistor meets the requirements for
a high-Ievel input condition.
4. The low-Ievel input voltage must be within :t 0.5 v 口 Its of the applied voltage at GND 1
5. Programming is guaranteed if the pulse is applied to the output for 10 ms. Typically , programming occurs in less than 1 ms.
step-by-step programming procedure
Programming the SN54186 or SN74186 is performed individually for each of the 512 bit locations and consists
basicallγof applying a current pulse to each output terminal where a low logic level is to be changed to a high (oft)
leve l. The power supply and ground connections described below are designed to ensure that alteration of the
memory content occurs during the programming procedure only.
回
1.
Connect the memory as shown in Figure 1. To address a particular word in the memory , set the input switches
to the binary equivalent of that word where a low logic level is as specified under "recommended conditions
for programming" and a high logic level is either an open circuit or connection to an open-collector TTL gate
with no pull-up resistor.
2.
Applγa
3.
Repeat Step 2 for each high-Ievel output desired in the word addressed (program only one bit at a time). Anγbit
that is to remain at a low level should have its respective output open-circuited during the entire programming
cycle for the addressed word.
programming current pulse as specified to the pin associated with the first bit to be changed from a
low-Ievel to a high-Ievel output.
4.
Set the next input address and repeat steps 2 and 3 at a programming duty cycle of 35% maximum. This
procedure is repeated for each input address for which a specific output word pattern is desired. A low logic
level can always be changed to a high logic level simply by repeating Steps 1 and 2. Once programmed to
provide a high logic level , the output cannot be changed to supply a low logic leve l.
NOTE: When verification indicates that a bit did not program , repeat steps 2 through 4. If the bit did n 口 t program after the second application
of a 1-millisecond programming pulse , repeat steps 2 through 4 using programming pulse time of 10 to 20 millisec 口 nds. Regardless of
the programming pulse duration , its total average pulse time should be no more than 35% of the programming cycle.
nγ
•N
P
L
℃
tJ1
。
OPENCOLLECTOR OUTPUT
INO PULL.UP RESISTORI
007
CS1
CS2
GNO 1
008
-5 V tu -6 V
FIGURE 1-PROGRAMMING CONNECTIONS
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575
TYPES SN54188A, SN74188A, AND SERIES 54S/74S
PROGRAMMABLE READ-ONLY MEMORIES
recommended conditions for programming
Supply voltage. VCC (see Note 6)
Steady state
Progra 口1 pulse
Input voltage
High level. VIH
Low level. VIL
'188A
SN54S'. SN74S'
NOM MAX MIN NOM MAX
5
5.75 4.75
5 5.75
11 t
10 10.5
11 t
10.5
5
5
2.4
。
0.5
。
0.5
See load circuit
See load circuit
(Figure 2)
(Figure 2)
MIN
4.75
10
2 .4
Termination of all outputs except the one to be programmed
Voltage applied to output to be programmed. VO(p r) (see Note 7)
0.25
+0.3
-0.8
20
35
55
o
0.25
0.3
V
I
Duration of VCC programming pulse Y (see Figure 3 and Note 8)
1
20
ms
Programming duty cycle
25
25
35
% I
。c
Free-air temperature
。
。
55
r Absolute maximum ratings.
NOTES: 6. Voltage values are with respect to the GND 2 terminals.
7. The '188A , 'S 188 , 'S288 , 'S470 , 'S471 , 'S472 , and 'S473 are supplied with all bit locations containing a low logic level , and
programming a bit changes the output of the bit to high logic leve l. The 'S287 and 'S387 are supplied with all bit outputs at a
high logic level , and programming a bit changes it to a low logic leve l.
8. Programming is guaranteed if the pulse applied is 10 ms long. Typically , programming occurs in 1 ms
step-by-step programming procedure
1. Apply steady-state supply voltage (VCC
=5
V) and address the word to be programmed.
回
2. Verify that the bit location needs to be programmed. If not. proceed to the next bit.
3. If the bit requires programming. disable the outputs by applying a high-Iogic-Ievel voltage to the chip-select
input{s).
4. Only one bit location is programmed at a time. Connect each output not being programmed to 5 V through 3.9 k S1
and apply the voltage specified in the table to the output to be programmed. Maximum current out of the
programming output supply during programming is 150 mA.
5. Step VCC to 10.5 V nomina l. Maximum supply current required during programming is 750 mA.
6.
Applγa low-Iogic-Ievel voltage to the chip-select input{s). This should occur between 10μ5 and 1 ms after VCC has
reached its 10.5-V leve l. See programming sequence of Figure 3.
7. After the X pulse time (1 ms) is reached. a high logic level is applied to the chip-select inputs to disable the
outputs.
10μ5 to 1 ms after the chip-select input{s) reach a high logic level , VCC should be stepped down to 5 V at
which level verification can be accomplished.
8. Within
9. The chip-select input{s) may be taken to a low logic level (to permit program verification) 10μs or more after V CC
reaches its steady-state value of 5 V.
10. At a Y pulse duty cycle of 35% or less. repeat steps 1 through 8 for each output where it is desired to program a
bit.
NOTES: A) vcc should be removed between program pulses to reduce dissipation and chip temperatures. See Figure 3.
B) When verificat 旧 n indicates that a bit did not program , repeat steps 3 through 9. If the bit did not program after the
second application of a 1.ms X pulse , repeat steps 3 through 9 using an X pulse time of 10 to 20 ms. Regardless of the x
duration , the total average pulse time of Y should be no more than 35% of the programming cycle
5V
~
3.9 k l!
OUTPUT ---..,)
LOAD CIRCUIT FO I'{ EACH OUTPUT
NOT BEING PROGRAMMED OR FOR
PROGRAM VERIFICATION
FIGURE 2
V'L
APPlY
REMOVE
VO(prl
VO(p叫
FIGURE 3-VOLTAGE WAVEFORMS FOR PROGRAMMING
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185
TVPES SN54186. SN54188A. SN74186. SN74188A
PROGRAMMABLE READ-ONLY MEMORIES
recommended operating conditions
MIN
Supply voltage , VCC
SN54186
SN74186
SN54188A
SN74188A
NOM
405
5
MAX
MIN
505
4075
NOM
UNIT
MAX
5
5025
V
Higholevel output voltage , VOH
505
505
V
Lo w- Ieve1 output current , IOL
12
12
mA
70
。c
Operating free-air temperature , T A
一 55
125
o
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
'186
TEST CONDITIONSt
MIN
VIH
Higholevel inputvoltage
VIL
Low-Ievel input voltage
VIK
Input clamp voltage
IOH
Higholevel output current
VOL
Low-Ievel output voltage
回
'188A
MAX
2
VCC = MIN ,
11 = -12 mA
Vcc = MIN ,
VIH = 2 V.
VIL = 008 V
Input current at maximum
Vcc = MIN ,
VIH = 2V ,
VIL = 008 V ,
IOL = 12 mA
Vcc = MAX ,
VI = 505 V
IIH
High-Ievel input current
Vcc = MAX ,
VI = 2 .4 V
IIL
Low-Ievel input current
Vcc = MAX ,
VI = 0 .4 V
ICC
Supply current
Vcc = MAX ,
See Note 9
ICCH
Supplycurrent , alloutputshigh
ICCL
Supply current , all outputslow
Co
Off-state output capacitance
11
TYP 丰
input voltage
VO = 2 V ,
TYP 丰
MAX
UNIT
V
2
008
008
一1. 5
一1. 5
VOH = 2 .4 V
100
VOH=505V
200
100
0 .4
0 .4 5
V
V
μA
V
1 1 mA
40
40
μA
mA
80th CS at 0 V
47
95
80th CS at 405 V
80
120
Vcc = MAX
VCC = 5 V ,
MIN
mA
See Note 10
50
80
See Note 11
82
110
f = 1 MHz
605
mA
pF
605
tF口 r conditions shown as MIN or MAX , use the appropriate value specified under recommended operating conditions o
0
+AII typical values are at VCC = 5 V , T A = 25 Co
NOTES: 90 ICC of '186 is measured with all outputs open and the address inputs at 405 Vo Typical values are for 50% of the bits programmedo
100 ICCH of '188A is measured with all inputs at 405 V , all outputs openo
110 ICCL of '188A is measured with the chip-select input grounded , all other inputs at 405 V , and all outputs openo The typical value
shown is for the worst-case condition of all eight outputs low at one timeo This condition may not be possible after the device has
been programmed
switching characteristics, VCC = 5 V, TA = 25 C
0
TYPE
TEST CONDITIONS
tpLH (n51
ta(adl (n51
ta(CS!CSI (n51
Access time from
Access time from
chip select (enable time)
address
Propagation delay
tin、 e ，
low-to-h igh-Ievel output
from chip select (disable time)
'186
同百7
CL = 30 pF ,
RL2 = 600
n,
RL 1 = 400
n,
See Figure 4
TYP
MAX
TYP
MAX
TYP
50
75
55
75
40
75
30
50
34
50
23
50
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575
SERIES 54S/74S
PROGRAMMABLE READ-ONLY MEMORIES WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
'S387 ,
'S188
Supply voltage , VCC
MIN
NOM
Series 54S
4.5
5
Series 74S
4.75
5
UNIT
'S470 , 'S473
MAX
MIN
NOM
MAX
5.5
4.5
5
5.5
5.25
4.75
5
5.25
V
High-Ievel output voltage , VOH
5.5
5.5
V
Low-Ievel output current , IOL
20
16
mA
Ope r<l ting free-air temperature , T A
-55
125
-55
。
70
o
Series 74S
125.
。c
70
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
「
PARAMETER
VIH
High-Ievel input voltage
VIL
Low-Ievel input voltage
VIK
Input clamp voltage
TEST CONDITIONSt
MIN
TYP 丰
11 =一 18mA
Vcc = MIN ,
High-Ievel output current
Low-Ievel output voltage
V
一1. 2
V
μA
VIH=2V ,
100
Vcc = MIN ,
VIH = 2 V ,
VIL = 0.8 V ,
IOL = MAX
11
Input current at maximum input voltage
Vcc = MAX ,
VI = 5.5 V
IIH
High-Ievel input current
Vcc = MAX ,
VI = 2.7 V
IIL
Low-Ievel input current
Vcc = MAX ,
VI=0.5V
Vcc = MAX ,
ICC
0.8
50
VIL = 0.8 V
VOL
Supply current
UNIT
V
Vcc = MIN ,
IOH
MAX
2
'S188
0.5
25
μAI
一 250
μAI
80
110
Chip select(s) at 0 V ,
'S387
100
135
Outputs open ,
'S4 70
110
155
See Note 12
'S473
120
回
V
switching characteristics over recommended ranges of T A and VCC (unless otherwise noted)
TYPE
TEST CONDITIONS
tpLH (ns)
Propagation delay time ,
ta(ad) (ns)
ta( Cs) (ns)
Access time from
Access time from
address
chip select (enable time)
low-to.high-Ieveloutput
from chip select (disable time)
TYP 丰
MAX
TYP 丰
MAX
TYP 丰
MAX
SN54S188
25
50
12
30
12
30
SN74S188
25
40
12
25
12
25
SN54S387
CL=30pF ,
42
75
15
401'
15
401'
SN74S387
RL1 =300 .11,
42
65
15
35
15
35
SN54S470
RL2 = 600 .11,
50
80
20
40
15
35
SN74S470
See Figure 4
50
70
20
35
15
30
SN54S473
55
20
15
SN74S473
55
20
15
t For conditions shown as M 1N 口 r MAX , use the appropriate value specified under recommended operating conditions.
0
丰 AII typical values are at VCC = 5 V , T A = 25 C.
0
• An SN54S387 in the W p~~kage operating at free-air temperatures above 108 C requires a heat sink that provides a thermal resistance from
case to free air , ReCA' 口 f not more than 42 oC/W.
PTentative specí ~ications.
NOTE 12: The typical values of ICC shown are with all outputs low.
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575
SERIES 54S/74S
PROGRAMMABLE READ-ONLY MEMORIES WITH 3-STATE OUTPUTS
recornrnended operating conditions
'S287
'S288
'S471 , 'S472
Supply voltage , VCC
High-Ievel output current , 10H
MIN
NOM
Series 54S
4.5
5
Series 74S
4.75
5
MAX
UNIT
MIN
NOM
MAX
5.5
4.5
5
5.5
5.25
4.75
5
5.25
Series 54S
一2
-2
Series 74S
-6.5
一 6.5
Low-Ievel output current , 10L
16
Operating free-air temperature , T A
20
Series 54S
一 55
125
一 55
Series 74S
o
70
o
125.
V
mA
mA
。C
70
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
回
VIH
High-Ievel input voltage
VIL
Low-Ievel input voltage
VIK
Input clamp voltage
VOH
High-Ievel output voltage
TEST CONDITIONSt
Vcc = MIN ,
11 = -18 mA
Vcc = MIN ,
VIH = 2 V ,
VIL = 0.8 V ,
10H = MAX
Vcc = MIN ,
VIH = 2 V ,
Low-Ievel output voltage
VIL = 0.8 V ,
10L = MAX
l
Off-state output current ,
high-Ievel voltage applied
Vcc = MAX ,
VIH=2V ,
Off-state output current ,
Vcc = MAX ,
low-Ievel voltage applied
VO = 0.5 V
10ZL
Input current at maximum
11
input voltage
TYP 丰
SN74S'
MAX
MIN
2 .4
VIH = 2 V ,
VI = 5.5V
MAX
UNIT
V
0.8
0.8
V
一 1.2
一1. 2
V
3 .4
VO=2 .4 V
Vcc = MAX ,
TYP 丰
2
2
VOL
OZH
SN54S'
MIN
2 .4
V
3.2
0.5
0.5
V
50
50
μA
一50
-50
μA
11 mA
IIH
High-Ievel input current
Vcc = MAX ,
VI = 2.7 V
25
25
μA
IIL
Low-Ievel input current
Vcc = MAX ,
VI = 0.5 V
一250
一 250
μA
10S
Short-circuit output current S
一 100
mA
ICC
Supply current
一30
Vcc = MAX
Vcc= MAX ,
'S287
Chip select(s) at 0 V ,
Outputs open ,
See Note 12
一 100
100
135
'S288
80
'S471
110
'S472
120
-30
100
135
110
80
110
155
110
155
I
I
mA
120
switching characteristics over recommended ranges of T A and VCC (unless otherwise noted)
TYPE
TEST CONDITIONS
ta(ad) (ns)
ta(CS) (ns)
tpxz (n5)
Access time
Access time from
Disable time from
from address
chip select (enable time)
MAX
TYP 丰
MAX
TYP 丰
42
75p
15
40p
12
SN54S287
SN74S287
SN54S288
SN74S288
SN54S471
SN74S471
SN54S472
high or low level
TYP 丰
CL = 30 pF for
ta(ad) and ta(CS) ,
5 pF for tpxz;
RL = 300 S1;
See Figure 5
SN74S472
MAX
42
65
15
35
12
25
50
12
30
8
25
40
12
25
8
20
50
80
20
40
15
35
50
70
20
35
15
30
55
20
15
55
20
15
30
t For conditi 口 ns shown as MIN or MAX , use the appropriate value specified under rec 口 mmended operati 吨 conditions.
0
iAIlt川 al values are 川 cc = 5 V , T A = 25 C
Not more than one output sh 口 uld be shorted at a time and duration of the short-circuit should not exceed one second.
o
.An SN54S287 in the W package operating at free-air temperatures above 10S C requires a heat sink that provides a thermal resistance from
0
case-to-free-air , ReCA' 口f not more than 42 C/W.
NOTE 12: The typl;;I.values of ICC shown are with all outputs low.
pTentative specifications
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SERIES 54/74 , 54S/74S
PROGRAMMABLE READ-ONLY MEMORIES
PARAMETER MEASUREMENT INFORMATION
Vcc
CHIP
CS
3V
SELECT
INPUT(S)
FROM OUTPUT
UNDER TEST
RL2
= 600 n
VOLTAGE WAVEFORM5
LOAD CIRCUIT
NOTES:
A. The input pulse generat口 r has the following characteristics: Zout "" 50 n and PRR';; 1 MHz. For Series 54 /7 4 , t r ';; 7 ns ,
tf .;; 7 ns. For Series 54S /7 4S , tr .;; 2.5 ns , tf';; 2.5 ns.
B. CL includes pr口 be and jig capacitance.
C. The pulse generator is connected to the input under test. The other inputs, memory content permitting , are connected so that the
input will switch the output under test.
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FIGURE 4-SWITCHING TIMES OF '186 , '188A , '5188, 'S470 , 'S387 , AND 'S473
Vcc
ADDRES5
INPUT5
(5ee N 口 te A)
TEST
POINT
OUTPUT
(51 and 52 closed)
FROM OUTPUT
uNDER TEST
ACCESS TIME FROM ADDRESS INPUTS
VOL TAGE WAVEFORMS
CHIP5ELECT
INPUT5
(See Note B)
3V
1.5 V
'→-一一一
OV
!唾钟 tpLZ
__""4.5V
i←一→←ta( Cs)
WAVEFORM 1
CL includes probe and jig capacitance
AII diodes are 1 N3064
f飞一 --VOL
问一一嗣-ta( Cs)
1.5
Lτ 」二 VOH
V
、、t. 0.5
V
tpHZ 忡..、-坦 OV
tpxz
= tpHZ
or tpLZ
ACCESS (ENABLE) T1 ME AND DISABLE TIME FROM CHIP SELECT
VOLTAGE WAVEFORMS
LOAD CIRCUIT
NOTES:
lμ[0.5 V
See Note C)
WAVEFORM 2
(51 open , 52 closed ,
See Note C)
A. When measuring access times from address inputs , the chip.select input(s) 以 are) low.
B. When measuring access and disable times from chip.select input(s) , the address inputs are steady.state
C. Wavef口 rm 1 is for the output with internal conditions such that the output is low except when disabled. Waveform 2 is for the
output with internal conditions such that the output is high except when disabled.
D. Input waveforms are supplied by pulse generators having the following characteristics: tr .;; 2.5 ns , tf .;; 2.5 ns , PRR .;; 1 MHz ,
and Zout "" 50 n.
FIGURE 5-SWITCHING TIMES OF 'S287 , 'S288 , 'S471 , AND 'S472
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TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE <HANGES AT ANY T1 ME
IN ORDER TO IMPROVE DESIGN AND TO SUPPl Y THE BEST PRODUCT POSSIBlE
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