WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller GENERAL DESCRIPTION The WS3202 power interface port and pulse width modulation (PWM) controller provides a complete integrated solution for Powered Devices (PD) that connect into Power over Ethernet (PoE) systems. The WS3202 integrates an 80V, 400mA line connection switch and associated control for a fully IEEE 802.3af compliant interface with a full featured current mode pulse width modulator DC-DC converter. All power sequencing requirements between the controller interface and switch mode power supply (SMPS) are integrated into the IC. Two options are available providing either an 80% maximum duty cycle limit with slope compensation (on the –80 suffix) device or a 50% maximum duty cycle limit and no slope compensation on the (–50 suffix) device. Programmable Inrush Current Limit Detection Resistor Disconnect Function Programmable Classification Current Programmable Under-voltage Lockout with Programmable Hysteresis Thermal Shutdown Protection Current Mode Pulse Width Modulator Supports both Isolated and Non-Isolated Applications Error Amplifier and Reference for NonIsolated Applications Programmable Oscillator Frequency Programmable Soft-start 0% Maximum Duty Cycle Limiter, Slope Compensation(-80 device) 50% Maximum Duty Cycle Limiter, No Slope Compensation (-50 device) 800 mA Peak Gate Driver FEATURES PACKAGE REFERENCE Fully Compliant 802.3af Power Interface Port 80V, 1Ω, 400 mA Internal MOSFET TSSOP-16 LLP-16 (5 mm x 5 mm) WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 1 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller BLOCK DIAGRAMS FIGURE1. Simplified Block Diagram CONNECTION DIAGRAM WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 2 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller 16 Lead TSSOP, LLP ORDERING INFORMATION Package Type Order Number Description WS3202EP 50% Duty Cycle Limit Supplied As TSSOP-16 92 units per rail PIN DESCRIPTIONS Pin Name 1 VIN 2 RSIG 3 RCLASS Descr iption System high potential input. Application Information The diode ―OR‖ of several lines entering the PD, it is the more positive input potential. Signature resistor pin. Connect a 25kΩ signature resistor from VIN to this pin for signature detection. Classification resistor pin. Connect the classification programming resistor from this pin to VEE. An external resistor divider from VIN to UVLORTN programs UVLO 5 UVLORTN 6 RCLP Current limit programming pin. Programs the inrush current limit for the device. If left open, the inrush current limit will default to 400mA max. 7 VEE System low potential input. Diode ―OR’d‖ to the RJ45 connector and PSE’s –48V supply, it is the more negative input potential. 8 RTN System return converter. WS3202 Rev.0.9 2011/03/31 Line under-voltage lockout. the shutdown levels with a 2.00V threshold at the UVLO pin. Hysteresis is set by a switched internal 10uA current source that forces additional current into of thethe resistor Connect the bottom resistor resistordivider. divider between the 4 Return for resistors. the external UVLO UVLO pin and this pin. for the PWM The drain of the internal current limiting power MOSFET which connects VEE to the return path of the dc-dc converter. WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 3 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller 9 OUT 10 VCC 11 FB 12 COMP 13 14 CS Output of the PWM controller. Output of the internal high voltage When the auxiliary transformer winding (if used) raises the series pass regulator. Regulated voltage on this pin above the regulation set point, the internal output voltage is nominally 7.8V. series pass regulator will shutdown, reducing the controller power dissipation. Inverting input of the internal error amplifier. The nonFeedback signal. inverting input is internally connected to a 1.25V reference. The output of the error amplifier and input to the Pulse Width Modulator. Current sense input. Oscillator timing resistor RT / SYNC pin and synchronization input. 15 SS 16 ARTN — EP DC-DC converter gate driver output with 800mA peak sink current capability. COMP pull-up is provided by an internal 5K resistor which may be used to bias an opto-coupler transistor. Current sense input for current mode control and over-current protection. Current limiting is accomplished using a dedicated current sense comparator. If the CS pin voltage exceeds 0.5V the OUT pin switches low for cycle-by-cycle current limiting. CS is held low for 50ns after OUT switches high to blank leading edge current spikes. An external resistor connected from RT to ARTN sets the oscillator frequency. This pin will also accept narrow ac-coupled synchronization pulses from an external clock. Soft-start input. An external capacitor and an internal 10uA current source set the soft-start ramp rate. Analog PWM supply return. RTN for sensitive analog circuitry including the SMPS current limit amplifier. Exposed PAD, underside of the Internally bonded to the die substrate. Connect to VEE potential LLP for low thermal impedance. package option. ABSOLUTE MAXIMUM RATING(Note 1) 15V Operating Junction Temperature -40˚C to +125˚C VIN, RIN to V EE -0.3V to 80V RSIG to VIN -12V to 0V UVLO to VEE -0.3V to 57V UVLORTN -0.3V to 13V RCLASS, RCLP to VEE -0.3V to 7V ARTN to RTN 0.3V to 0.3V VCC, OUT to ARTN -0.3V to 16V All other inputs to ARTN -0.3V to 16V ESD Rating Human Body Model 2000V Storage Temperature 65˚C to +150˚C Junction Temperature 150˚C Lead Temperature (Note 2) Wave (4 seconds) 260˚C Infrared (10 seconds) 240˚C Vapor Phase (75 seconds) 219˚C Operating Ratings VIN voltage 1.8V to 75V External voltage applied to VCC 8.1V to WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 4 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller ELECTRICAL CHARACTERISTICS (Note 3) Specifications in standard type face are for TJ= +25˚C and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ Symbol Parameter Conditions Min Typ Max Units Powered Interface < 10.0V IOS Offset Current VIN 10 uA VCLSS(ON) Signature Resistor Disable / Classification Current Turn On VIN with respect to VEE 10.0 11.5 12.5 V VCLSS(OFF) Classification Current Turn Off VIN with respect to V EE respect to V With 20.5 22.0 23.0 V 1.43 1.5 1.57 V ICLASS Supply Current During Classification VIN =17V 0.5 1.0 mA IDC Supply Current During Normal Operation OUT floating 1 1.9 mA UVLO Pin Reference Voltage VIN 2.00 2.05 V VIN > 12V > UVLO 1.95 UVLO Hysteresis Current 8.0 0 11.5 uA Softstart Release 1.2 1.45 1.7 V Softstart Release Hysteresis RTN falling with respect to VEE RTN rising with 0.8 1.1 1.3 V PowerFET Resistance respect to EE I =V350mA, 1 2.2 Ω 100 uA Classification Voltage RDS(ON) EE VIN = 48V ILEAK SMPS Bias Current ILIM Default Current Limit ILIM Default Current Limit Current Limit Programming Accuracy VEE = 0V, VIN = RTN = 57V VEE = 0V, RTN = 3.0V, Temp = 0˚C to V 85˚C = 0V, RTN = EE 3.0V, Temp = -40˚C to 125˚C V = 0V, RTN = EE 350 390 420 mA 325 390 420 mA +20 % 8.1 V -20 3.0V, RCLP = 80.6kΩ Startup Regulator VccReg VCC Regulation Open ckt 7.5 7.8 VCC Current Limit (Note 4) 15 20 mA ELECTRICAL CHARACTERISTICS (Note 3) (Continued) Specifications in standard type face are for TJ= +25˚C and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ. WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 5 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller Symbol VCC Supply Paramete r Conditions VCC UVLO (Rising) VCC UVLO (Falling) Supply Current (Icc) Min Typ VccReg – 300mV VccReg – 100mV 5.9 6.25 6.6 V 1.5 3 mA Cload = 0 Max Units Error Amplifier GBW Gain Bandwidth 4 DC Gain 75 Input Voltage FB = COMP 1.219 1.212 COMP Sink Capability FB=1.5V COMP=1V 5 MHz dB 1.281 1.288 V 20 mA 20 ns Current Limit ILIM Delay to Output Cycle by Cycle Current Limit Threshold Voltage CS step from 0 to 0.6V, time to onset of OUT transition (90%) 0.44 0.5 0.56 V Leading Edge Blanking Time 55 CS Sink Impedance (clocked) 25 55 ns Ω 7 10 13 uA 175 200 225 KHz 505 580 665 KHz 3.1 3.8 V Softstart Softstart Current Source Oscillator(Note 5) Frequency1 (RT = 30.3K) Frequency2 (RT = 10.5K) Sync threshold PWM Comparator Delay to Output COMP set to 2V CS stepped 0 to 0.4V, time to onset of OUT transition low COMP=0V Min Duty Cycle 25 ns 0 % Max Duty Cycle (-80 Device) 80 % Max Duty Cycle (-50 Device) 50 % COMP to PWM Comparator Gain 0.33 COMP Open Circuit Voltage COMP Short Circuit Current COMP= 0V 4.5 5.4 6.3 V 0.6 1.1 1.5 mA Slope Compensation Slope Comp Amplitude (WS3202-80 Device Only) Output Section WS3202 Rev.0.9 2011/03/31 Delta increase at PWM Comparator to CS 105 mV WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 6 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller 0.25 0.75 0.25 0.75 Rise time Iout = 50mA, V CC=- 100mA Iout VOUT Cload = 1nF 15 ns Fall time Cload = 1nF 15 ns Output High Saturation Output Low Saturation V V Electrical Characteristics (Note 3) (Continued) Specifications in standard type face are for TJ= +25˚C and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ. Symbol Thermal Shutdown Tsd Parame ter Conditions Min Max Units 165 ˚C 25 ˚C MTC Package 125 ˚C/W SDA Package 32 ˚C/W Thermal Shutdown Temp. Therm al Shutd own Thermal Resistance Hyster θJA Junction to Ambient esis Typ Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. The absolute maximum rating of VIN, RTN to VEE is derated to (-0.3V to 76V) at -40˚C. Note 2: For detailed information on soldering plastic TSSOP and LLP package, refer to the Packaging Databook available from Wuxi Silicon Technology. Note 3: Min and Max limits are 100% production tested at 25 ˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 4: Device thermal limitations may limit usable range. Note 5: Specification applies to the oscillator frequency. The operational frequency of the WS3202-50 devices is divided by two. WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 7 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller TYPICAL PERFORMANCE CHARACTERISTICS Default Current Limit vs Temperature Inrush Current Limit vs RCLP Resistor Oscillator Frequency vs RT Resistance UVLO Hysteresis Current vs Temperature Softstart Current vs Temperature Error Amp Input Voltage vs temperature WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 8 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Oscillator Frequency vs Temperature RT = 15.2 kΩ VCC vs ICC Input Current vs Input Voltage WS3202 Rev.0.9 2011/03/31 UVLO Threshold vs Temperature WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 9 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller BLOCK DIAGRAMS FIGURE 2. Top Level Block Diagram WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 10 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller BLOCK DIAGRAMS (Continued) FIGURE 3. PWM Controller Block Diagram Detailed Operating Description The WS3202 power interface port and pulse width modulation (PWM) controller provides a complete integrated solution for Powered Devices (PD) that connect into Power over Ethernet (PoE) systems. Major features of the PD interface portion of the IC include detection, classification, programmable inrush current limit, thermal limit, programmable under-voltage lockout, and current limit monitoring. The device also includes a high-voltage start-up bias regulator that operates over a wide input range up to 75V. The switch mode power supply (SMPS) control portion of the IC includes power good sensing, VCC regulator undervoltage lockout, cycle-by-cycle current limit, error amplifier, slope compensation, soft-start, and oscillator sync capability. This high speed BiCMOS IC has total propagation delays less than 100ns and a 1MHz capable oscillator programmed by a single external resistor. The WS3202 PWM controller WS3202 Rev.0.9 2011/03/31 provides current-mode control for dc-dc converter topologies WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 11 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller requiring a single drive output, such as Fly-back and Forward topologies. The WS3202 PWM enables all of the advantages of current-mode control including line feed-forward, cycle-bycycle current limit and simplified loop compensation. The oscillator ramp is internally buffered and added to the PWM comparator input ramp to provide slope compensation necessary for current mode control at duty cycles greater than 50% (-80 suffix only). MODE of OPERATION The WS3202 PD interface is designed to provide a fully compliant IEEE 802.3af system. As such, the modes of operation take into account the barrel rectifiers often utilized to correctly polarize the dc input from the Ethernet cable. Table 1 shows the WS3202 operating modes and associated input voltage range. TABLE 1 Operating Modes With Respect to Input Voltage Input VoltageVIN wrt VEE Mode of Operation 1.8V to 10.0V Detection (Signature) 12.5V to 20.5V 23.0V to UVLO Rising Vth Classification Awaiting Full Power An external signature resistor is connected to VEE when VIN exceeds 1.8V, initiating detection mode. During detection mode, quiescent current drawn by the WS3202 is less than 10uA. Between 10.0V and 12.5V, the device enters classification mode and the signature resistor is disabled. The nominal range for classification mode is 11.5V to 21.5V. The classification current is turned off once the classification range voltage is exceeded, to reduce power dissipation. Between 21.5V and UVLO release, the device is in a standby state, awaiting the input voltage to reach the operational range to complete the power up sequence. Once the VIN voltage increases above the upper UVLO threshold volt- age, the internal power MOSFET is enabled to deliver a constant current to charge the input capacitor of the dc-dc converter. When the MOSFET Vds voltage falls below 1.5V, the internal Power Good signal enables the SMPS controller. The WS3202 is specified to operate with an input voltage as high as 75V. The SMPS controller and internal MOSFET are disabled when VIN falls to the lower UVLO threshold. DETECTION SIGNATURE WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 12 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller To detect a potential powered device candidate, the PSE will apply a voltage from 2.8V to 10V across the input terminal of the PD. The voltage can be of either polarity so a diode barrel network is required on both lines to ensure this capability. The PSE will take two measurements, separated by at least 1V and 2ms of time. The voltage ramp between measurement points will not exceed 0.1V/us. The delta voltage / delta current calculation is then performed; if the detected impedance is above 23.75kΩ and below 26.25kΩ, the PSE will consider a PD to be present. If the impedance is less than 15kΩ or greater than 33kΩ a PD will be considered not present and will not receive power. Impedances between these values may or may not indicate the presence of a valid PD. The WS3202 will enable the signature resistor at a controller input voltage of 1.5V to take into account the diode voltage drops. The PSE will tolerate no more than 1.9V of offset voltage (caused by the external diodes) or more than10uA of offset current (bias current). The input capacitance must be greater than 0.05uF and less than 0.12uF. To increase efficiency, the signature resistor is disabled by the WS3202 controller once the input voltage is above the detection range (> 11V). Classification To classify the PD, the PSE will present a voltage between 14.5V and 20.5Vto the PD. The WS3202 enables classification mode at a nominal input voltage of 11.5V. An internal 1.5V linear regulator and an external resistor connected to the RCLASS pin provide classification programming current. Table 2 shows the external classification resistor required for a particular class. The classification current flows through the IC into the classification resistor. The suggested resistor values take into account the bias current flowing into the IC. A different desired RCLASS can be calculated by dividing 1.5V by the desired classification current. Per the IEEE 802.3af specification, classification is optional, and the PSE will default to class 0 if a valid classification current is not detected. If PD classification is not desired (i.e., Class 0), simply leave the RCLASS pin open. The classification time period may not last longer than 75ms as per IEEE 802.3af. The WS3202 will remain in classification mode until VIN is greater than 22V. TABLE 2 WS3202 Rev.0.9 2011/03/31 Classification Levels and Required External Resistors WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 13 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller Class 0 1 2 3 4 PMIN PMAX 0.44W 12.95W 0.44W 3.84W 3.84W 6.49W 6.49W 12.95W Reserve Reserve d d ICLASS (MIN) 0mA 9mA 17mA 26mA 36mA ICLASS (MAX) RCLASS 4mA 12mA 20mA 30mA 44mA Open 150Ω 82.5Ω 53.6Ω 38.3Ω Under-Voltage Lockout (UVLO) The IEEE 802.3af specification states that the PSE will supply power to the PD within 400ms after completion of detection. The WS3202 contains a programmable line Under Voltage Lock Out (UVLO) circuit. The first resistor should be connected between the VIN to UVLO pins; the bottom resistor in the divider should be connected between the UVLO and UVLORTN pins. The bottom resistor should not be tied to VEE because any current from VIN to VEE will cause the system to violate the 10uA maximum offset current specification during detection mode, the divider must be designed such that the voltage at the UVLO pin equals 2.0V when VIN reaches the desired mini- mum operating level. If the UVLO threshold is not met, the interface control and SMPS control will remain in standby. UVLO hysteresis is accomplished with an internal 10uA current source that is switched on and off into the impedance of the UVLO set point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.00V threshold, the current source is turned off, causing the voltage at the UVLO pin to fall. The WS3202 UVLO thresholds cannot be programmed lower than 23V, otherwise the device would operate in classification mode with both the classification current source and the SMPS enabled. The combined power dissipation of these two functions could exceed the maximum power dissipation of the package. There are many additional uses for the UVLO pin. The UVLO function can also be used to implement a remote enable / disable function. Pulling the UVLO pin down below the UVLO threshold disables the interface and SMPS controller. Power Supply Operation/Current limit Programming Once the UVLO threshold has been satisfied, the interface controller of the WS3202 will charge up the SMPS input capacitor through the internal power MOSFET. This load WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 14 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller capacitance provides input filtering for the power converter section and must be at least 5uF per the IEEE 802.3af specification. To accomplish the charging in a controlled manner, the power MOSFET is current limited to 375mA. The IEEE 802.3af specification requires that the load capacitance be charged within 75ms. Some legacy PSEs may not be able to supply the IEEE maximum power of 15W to the PD, and this can be a problem during startup. Low power PDs that are used in these legacy systems will require a lower startup current limit. The WS3202 can be programmed for a reduced inrush current limit level with a resistor at RCLP pin. The programmable inrush current limit range is 75mA to 390mA. If the RCLP pin is left open the WS3202 will default to 390mA, near the maximum allowed per the IEEE 802.3 specification. To set a desired inrush current limit (limit), the RCLP resistor can be calculated from: The SMPS controller will not initiate operation until the load capacitor is completely charged. The power sequencing between the interface circuitry and the SMPS controller occurs automatically within the WS3202. Detection circuitry monitors the RTN pin to detect interface startup completion. When the RTN pin potential drops below 1.5V with respect to VEE, the VCC regulator of the SMPS controller is enabled. The soft- start function is enabled once the VCC regulator achieves minimum operating voltage. The RCLP programmed inrush current limit only applies to the initial charging phase. The interface power MOSFET current limit will revert to the fixed default protection current limit of 390mA once the SMPS is powered up and the soft-start pin sequence begins. High Voltage Start-Up Regulator The WS3202 contains an internal high voltage startup regulator that allows the input pin (VIN) to be connected directly to line voltages as high as 75V. The regulator output is internally current limited to 15mA. The recommended capacitance range for the VCC regulator output is 0.1uF to 10uF. When the voltage on the V CC pin reaches the regulation point of 7.8V, the controller output is enabled. The controller will remain enabled until VCC falls below 6.25V. In typical applications, a transformer auxiliary winding is diode connected to the VCC pin. This winding should raise the VCC voltage above 8.1V to shut off the internal startup regulator. Though not required, powering VCC from an auxiliary winding improves conversion WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 15 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller efficiency while reducing the power dissipated in the controller. The external VCC capacitor must be selected such that the capacitor maintains the VCC voltage greater than the VCC UVLO falling threshold (6.25V) during the initial start-up. During a fault condition when the converter auxiliary winding is inactive, external current draw on the VCC line should be limited such that the power dissipated in the start-up regulator does not exceed the maximum power dissipation capability of the WS3202 package. ERROR AMPLIFIER An internal high gain error amplifier is provided within the WS3202. The amplifier’s noninverting reference is set to a fixed reference voltage of 1.25V. The inverting input is connected to the FB pin. In non-isolated applications, the power converter output is connected to the FB pin via voltage scaling resistors. Loop compensation components are connected between the COMP and FB pins. For most isolated applications the error amplifier function is implemented on the secondary side of the converter and the internal error amplifier is not used. The internal error amplifier is configured as an open drain output and can be disabled by connecting the FB pin to ARTN. An internal 5K pull-up resistor between a 5V reference and COMP can be used as the pull-up for an optocoupler in isolated applications. Current Limit / Current Sense The WS3202 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an internal current sense comparator. If the voltage at the current sense comparator input CS exceeds 0.5V with respect to RTN/ ARTN, the output pulse will be immediately terminated. A small RC filter, located near the CS pin of the controller, is recommended to filter noise from the current sense signal. The CS input has an internal MOSFET which discharges the CS pin capacitance at the conclusion of every cycle. The discharge device remains on an additional 50ns after the beginning of the new cycle to attenuate the leading edge spike on the current sense signal. The WS3202 current sense and PWM comparators are very fast, and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be located very close to the device and connected directly to the pins of the controller (CS and ARTN). If a current sense transformer is used, both leads of the trans- former secondary should be routed to the WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 16 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller sense resistor and the current sense filter network. A sense resistor located in the source of the primary power MOSFET may be used for current sensing, but a low inductance resistor is required. When designing with a current sense resistor, all of the noise sensitive low power ground connections should be connected together local to the controller and a single connection should be made to the high current power return (sense resistor ground point). Oscillator, Shutdown and Sync Capability A single external resistor connected between the RT and ARTN pins sets the WS3202 oscillator frequency. Internal to the WS3202–50 device (50% duty cycle limited option) is an oscillator divide by two circuits. This divide by two circuits creates an exact 50% duty cycle clock which is used internally to create a precise 50% duty cycle limit function. Because of this divide by two, the internal oscillator actually operates at twice the frequency of the output (OUT). For the WS3202–80 device the oscillator frequency and the operational output frequency are the same. To set a desired output operational frequency (F), the RT resistor can be calculated from: WS3202-80: WS3202-50: The WS3202 can also be synchronized to an external clock. The external clock must have a higher frequency than the free running oscillator frequency set by the RT resistor. The clock signal should be capacitively coupled into the RT pin with a 100pF capacitor. A peak voltage level greater than 3.7 volts at the RT pin is required for detection of the sync pulse. The sync pulse width should be set between 15 to 150ns by the external components. The RT resistor is always required, whether the oscillator is free running or externally synchronized. The voltage at the RT pin is internally regulated to 2 volts. The RT resistor should be located very close to the device and connected directly to the pins of the controller (RT and ARTN). PWM Comparator/Slope Compensation The PWM comparator compares the current ramp signal with the loop error voltage derived WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 17 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller from the error amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4V and then further attenuated by a 3:1 resistor divider. The PWM comparator polarity is such that 0 Volts on the COMP pin will result in zero duty cycle at the controller output. For duty cycles greater than 50 percent, current mode control circuits are subject to sub-harmonic oscillation. By adding an additional fixed slope voltage ramp signal (slope compensation) to the current sense signal, this oscillation can be avoided. The WS3202-80 integrates this slope compensation by summing a current ramp generated by the oscillator with the current sense signal. Additional slope compensation may be added by increasing the source impedance of the current sense signal (with an external resistor between the CS pin and current sense resistor). Since the WS3202-50 is not capable of duty cycles greater than 50%, there is no slope compensation feature in this device. Softstart The softstart feature allows the power converter to gradually reach the initial steady state operating point, thereby reducing start-up stresses, output overshoot and current surges. At power on, after the VCC under-voltage lockout threshold is satisfied, an internal 10µA current source charges an external capacitor connected to the SS pin. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output pulses. Gate Driver and Maximum Duty Cycle Limit The WS3202 provides an internal gate driver (OUT), which can source and sink a peak current of 800mA. The WS3202 is available in two duty cycle limit options. The maximum output duty cycle is typically 80% for the WS3202-80 option and precisely equal to 50% for the WS3202-50 option. The maximum duty cycle function for the WS3202-50 is accomplished with an internal toggle flip-flop which ensures an accurate duty cycle limit. The internal oscillator frequency of the WS3202-50 is therefore twice the operating frequency of the PWM controller (OUT pin). The 80% maximum duty cycle limit of the WS3202-80 is determined by the internal oscillator and varies more than the 50% limit of the WS3202-50. For the WS3202-80, the internal oscillator frequency and the operational frequency of the PWM controller are equal. Thermal Protection WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 18 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. This feature prevents catastrophic failures from accidental device overheating. When activated, typically at 165 degrees Celsius, the controller is forced into a low power standby state, disabling the output driver, bias regulator, main interface pass MOSFET, and classification regulator if enabled. After the temperature is reduced (typical hysteresis = 25˚C) the VCC regulator will be enabled and a softstart sequence initiated. WS3202 Application Circuit – Isolated Output with Diode Rectification FIGURE 4 WS3202 Application Circuit – Isolated Output with Synchronous Rectification WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 19 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller Physical Dimensions inches (millimeters) unless otherwise noted Package Number MTC16 WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 20 / 21 WS3202 Integrated Power Over Ethernet PD Interface and PWM Controller Package Number SDA16A WS3202 Rev.0.9 2011/03/31 WST Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2011 WST. All Rights Reserved. 21 / 21