LM5020 www.ti.com SNVS275F – MAY 2004 – REVISED APRIL 2006 LM5020 100V Current Mode PWM Controller Check for Samples: LM5020 FEATURES PACKAGES • • • • • • • • 1 2 • • • • • • Internal Start-up Bias Regulator Error Amplifier Precision Voltage Reference Programmable Softstart 1A Peak Gate Driver Maximum Duty Cycle Limiting (80% for LM5020-1 or 50% for LM5020-2) Programmable Line Under Voltage Lockout (UVLO) with Adjustable Hysteresis Cycle-by-Cycle Over-Current Protection Slope Compensation (LM5020-1) Programmable Oscillator Frequency with Synchronization Capability Current Sense Leading Edge Blanking Thermal Shutdown Protection DESCRIPTION The LM5020 high voltage pulse-width-modulation (PWM) controller contains all of the features needed to implement single ended primary power converter topologies. Output voltage regulation is based on current-mode control, which eases the design of loop compensation while providing inherent line feedforward. The LM5020 includes a high-voltage start-up regulator that operates over a wide input range up to 100V. The PWM controller is designed for high speed capability including an oscillator frequency range to 1MHz and total propagation delays less than 100ns. Additional features include an error amplifier, precision reference, line under-voltage lockout, cycleby-cycle current limit, slope compensation, softstart, oscillator synchronization capability and thermal shutdown. The controller is available in both VSSOP10 and WSON-10 packages. APPLICATIONS • • • VSSOP-10 WSON-10 (4 mm x 4 mm) Telecommunication Power Converters Industrial Power Converters +42V Automotive Systems Typical Application Circuit VIN VIN VOUT VCC LM5020 UVLO SS OUT CS RT/ SYNC FB GND COMP COMPENSATION Figure 1. Non-Isolated Flyback Converter 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated LM5020 SNVS275F – MAY 2004 – REVISED APRIL 2006 www.ti.com Connection Diagram Top View 1 10 2 9 3 8 4 7 5 6 VIN FB SS RT/SYNC CS COMP UVLO VCC OUT GND Figure 2. 10-Lead VSSOP, WSON PIN DESCRIPTIONS Pin Name Description 1 VIN Source Input Voltage Input to the start-up regulator. Input range is 13V to 100V. Application Information 2 FB Feedback Signal Inverting input of the internal error amplifier. The noninverting input is internally connected to a 1.25V reference. 3 COMP The output of the error amplifier and input to the Pulse Width Modulator COMP pull-up is provided by an internal 5K resistor which may be used to bias an opto-coupler transistor. 4 VCC Output of the internal high voltage series pass regulator. Regulated output voltage is 7.7V If an auxiliary winding raises the voltage on this pin above the regulation set point, the internal series pass regulator will shut down, reducing the internal power dissipation. 5 OUT Output of the PWM controller Gate driver output with a 1A peak current capability. 6 GND Ground return 7 UVLO Line Under-Voltage Shutdown An external resistor divider from the power converter source voltage sets the shutdown levels. The threshold at this pin is 1.25V. Hysteresis is set by a switched internal 20µA current source. 8 CS Current Sense input Current sense input for current mode control and overcurrent protection. Current limiting is accomplished using a dedicated current sense comparator. If the CS pin voltage exceeds 0.5V the OUT pin switches low for cycle-by-cycle current limiting. CS is held low for 50ns after OUT switches high to blank leading edge current spikes. 9 RT / SYNC Oscillator timing resistor pin and synchronization input An external resistor connected from RT to GND sets the oscillator frequency. This pin also accepts synchronization pulses from an external clock. 10 SS Softstart Input An external capacitor and an internal 10µA current source set the soft-start ramp rate. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5020 LM5020 www.ti.com SNVS275F – MAY 2004 – REVISED APRIL 2006 Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 100V VCC to GND -0.3V to 16V RT to GND -0.3V to 5.5V All other pins to GND -0.3V to 7V Power Dissipation Internally Limited ESD Rating (3) Human Body Model 2kV Storage Temperature -65°C to +150°C Junction Temperature 150°C (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor. (2) (3) Operating Ratings VIN Voltage 13V to 90V External Voltage applied to VCC 8V to 15V Operating Junction Temperature -40°C to +125°C Electrical Characteristics Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6kΩ. (1) Symbol Parameter Conditions Min Typ Max Units 7.4 7.7 8.0 V Startup Regulator VCCReg VCC Regulation VCC = Open (2) VCC Current Limit See I-VIN Startup Regulator Leakage VIN = 100V 15 150 22 500 mA µA IIN Shutdown Current VUVLO = 0V, VCC = open 250 350 µA VCC Supply ICC VCC UVLO (Rising) VccReg - 300mV VccReg 100mV VCC UVLO (Falling) 5.3 6.0 6.7 V 2 3 mA Supply Current Cload = 0 V Error Amplifier GBW Gain Bandwidth 4 DC Gain MHz 75 Reference Voltage FB = COMP COMP Sink Capability FB = 1.5V COMP= 1V dB 1.225 1.25 1.275 5 17 V 1.225 1.25 1.275 V 16 20 24 µA mA UVLO Pin Shutdown Threshold Undervoltage Shutdown Hysteresis Current Source Current Limit ILIM Delay to Output CS step from 0 to 0.6V Time to onset of OUT Transition (90%) Cycle by Cycle CS Threshold Voltage 0.45 Leading Edge Blanking Time (1) (2) 30 0.5 ns 0.55 50 V ns Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL). Device thermal limitations may limit usable range. Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5020 3 LM5020 SNVS275F – MAY 2004 – REVISED APRIL 2006 www.ti.com Electrical Characteristics (continued) Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6kΩ.(1) Symbol Parameter Conditions Min CS Sink Impedance (clocked) Typ Max Units 35 55 Ω Soft Start Softstart Current Source 7 10 13 µA Softstart to COMP Offset 0.35 0.55 0.75 V Oscillator Frequency1 (RT = 31.6k) See (3) 175 200 225 kHz Frequency2 (RT = 9.76k) See (3) 560 630 700 kHz 2.4 3.2 3.8 V Sync threshold PWM Comparator Delay to Output COMP set to 2V, CS stepped 0 to 0.4V, Time to onset of OUT transition low Min Duty Cycle COMP=0V Max Duty Cycle (-1 Device) 25 75 Max Duty Cycle (-2 Device) 0 % 85 % 50 COMP to PWM Comparator Gain % 0.33 COMP Open Circuit Voltage COMP Short Circuit Current 80 ns 4.3 5.2 6.1 V COMP=0V 0.6 1.1 1.5 mA Delta increase at PWM Comparator to CS 80 105 130 mV Slope Compensation Slope Comp Amplitude (LM5020-1 Device Only) Output Section Output High Saturation Iout = 50mA, VCC - VOUT 0.25 0.75 V Output Low Saturation IOUT = 100mA, VOUT 0.25 0.75 V Rise Time Cload = 1nF 18 ns Fall Time Cload = 1nF 15 ns Thermal Shutdown Temp. 165 °C Thermal Shutdown Hysteresis 25 °C Thermal Shutdown Tsd (3) 4 Specification applies to the oscillator frequency. The operational frequency of the LM5020-2 devices is divided by two. Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5020 LM5020 www.ti.com SNVS275F – MAY 2004 – REVISED APRIL 2006 Typical Performance Characteristics Unless otherwise specified: TJ = 25°C. VCC and VIN vs VIN 20 VCC vs ICC (VIN = 48V) 9 18 8 16 7 6 12 VCC (V) VCC (V) 14 10 8 5 4 6 3 4 2 2 0 1 0 20 10 0 5 10 VIN (V) 15 20 25 ICC (mA) Figure 3. Figure 4. Oscillator Frequency vs RT Oscillator Frequency vs Temperature RT = 31.6kΩ 210 1.00E+06 FREQUENCY (kHz) 1.00E+05 200 195 190 1.00E+04 1 10 -40 100 RT (k:) 10 o TEMPERATURE ( C) Figure 5. Figure 6. Soft Start Current vs Temperature Error Amp. Gain/Phase Plot 13.0 GAIN (dB) CURRENT (PA) 11.8 10.6 9.4 8.2 50 225 40 180 30 135 20 90 10 45 0 0 -45 -10 -20 -90 -30 -135 -180 -40 7.0 -40 10 110 60 -50 10k 110 60 o TEMPERATURE ( C) PHASE (o) FREQUENCY (Hz) 205 100k 1M -225 10M FREQUENCY (Hz) Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5020 5 LM5020 SNVS275F – MAY 2004 – REVISED APRIL 2006 www.ti.com Block Diagram 7.7V SERIES REGULATOR VCC VIN REFERENCE ENABLE 5V 1.25V UVLO + - LOGIC 1.25V UVLO HYSTERESIS (20 PA) RT/SYNC CLK OSC VCC DRIVER SLOPECOMP RAMP GENERATOR (LM5020-1 Only) OUT 50 PA Max Duty Limit LM5020-1 (80%) LM5020-2 (50%) 0 S Q R Q 5V COMP 5k 2R 1.25V FB GND PWM + - LOGIC 1.4V R SS SS CS 0.5V 2k + - 10 PA SS CLK + LEB 6 Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5020 LM5020 www.ti.com SNVS275F – MAY 2004 – REVISED APRIL 2006 DETAILED OPERATING DESCRIPTION The LM5020 High Voltage PWM controller contains all of the features needed to implement single ended primary power converter topologies. The LM5020 includes a high-voltage startup regulator that operates over a wide input range to 100V. The PWM controller is designed for high speed capability including an oscillator frequency range to 1MHz and total propagation delays less than 100ns. Additional features include an error amplifier, precision reference, line under-voltage lockout, cycle-by-cycle current limit, slope compensation, softstart, oscillator sync capability and thermal shutdown. The functional block diagram of the LM5020 is shown in Figure 1. The LM5020 is designed for current-mode control power converters, which require a single drive output, such as Flyback and Forward topologies. The LM5020 provides all of the advantages of current-mode control including line feed-forward, cycle-by-cycle current limiting and simplified loop compensation . High Voltage Start-Up Regulator The LM5020 contains an internal high voltage startup regulator, that allows the input pin (Vin) to be connected directly to line voltages as high as 100V. The regulator output is internally current limited to 15mA. When power is applied, the regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended capacitance range for the Vcc regulator is 0.1µF to 100µF. When the voltage on the VCC pin reaches the regulation level of 7.7V, the controller output is enabled. The controller will remain enabled until VCC falls below 6V. In typical applications, a transformer auxiliary winding is connected through a diode to the VCC pin. This winding should raise the VCC voltage above 8V to shut off the internal startup regulator. Powering VCC from an auxiliary winding improves conversion efficiency while reducing the power dissipated in the controller. The external VCC capacitor must be selected such that the capacitor maintains the Vcc voltage greater than the VCC UVLO falling threshold (6V) during the initial start-up. During a fault condition when the converter auxiliary winding is inactive, external current draw on the VCC line should be limited such that the power dissipated in the start-up regulator does not exceed the maximum power dissipation capability of the controller. An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the VCC and the Vin pins together and feeding the external bias voltage (8-15V) to the two pins. Line Under Voltage Detector The LM5020 contains a line Under Voltage Lock Out (UVLO) circuit. An external set-point voltage divider from Vin to GND sets the operational range of the converter. The resistor divider must be designed such that the voltage at the UVLO pin is greater than 1.25V when Vin is in the desired operating range. If the under voltage threshold is not met, all functions of the controller are disabled and the controller remains in a low power standby state. UVLO hysteresis is accomplished with an internal 20µA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V threshold the current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable / disable function. If an external transistor pulls the UVLO pin below the 1.25V threshold, the converter is disabled. Error Amplifier An internal high gain error amplifier is provided within the LM5020. The amplifier's non-inverting input is internally set to a fixed reference voltage of 1.25V. The inverting input is connected to the FB pin. In non-isolated applications, the power converter output is connected to the FB pin via voltage scaling resistors. Loop compensation components are connected between the COMP and FB pins. For most isolated applications the error amplifier function is implemented on the secondary side of the converter and the internal error amplifier is not used. The internal error amplifier is configured as an open drain output and can be disabled by connecting the FB pin to ground. An internal 5K pull-up resistor between a 5V reference and COMP can be used as the pullup for an optocoupler in isolated applications. Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5020 7 LM5020 SNVS275F – MAY 2004 – REVISED APRIL 2006 www.ti.com Current Limit/Current Sense The LM5020 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an internal current sense comparator. If the voltage at the current sense comparator input exceeds 0.5V, the output is immediately terminated. A small RC filter, located near the controller, is recommended to filter noise from the current sense signal. The CS input has an internal MOSFET which discharges the CS pin capacitance at the conclusion of every cycle. The discharge device remains on an additional 50ns after the beginning of the new cycle to attenuate the leading edge spike on the current sense signal. The LM5020 current sense and PWM comparators are very fast, and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be located very close to the LM5020 and connected directly to the pins of the controller (CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense resistor and the current sense filter network. A sense resistor located in the source of the primary power MOSFET may be used for current sensing, but a low inductance resistor is required. When designing with a current sense resistor all of the noise sensitive low power ground connections should be connected together local to the controller and a single connection should be made to the high current power ground (sense resistor ground point). Oscillator and Sync Capability A single external resistor connected between the RT and GND pins sets the LM5020 oscillator frequency. Internal to the LM5020-2 device (50% duty cycle limited option) is an oscillator divide by two circuit. This divide by two circuit creates an exact 50% duty cycle pulse which is used internally to create a precise 50% duty cycle limit function. Because of this, the internal oscillator actually operates at twice the frequency of the output (OUT). For the LM5020-1 device the oscillator frequency and the operational output frequency are the same. To set a desired output operational frequency (F), the RT resistor can be calculated from: LM5020-1: 1 RT = F x 158 x 10-12 (1) LM5020-2: RT = 1 F x 316 x 10-12 (2) The LM5020 can also be synchronized to an external clock. The external clock must have a higher frequency than the free running oscillator frequency set by the RT resistor. The clock signal should be capacitively coupled into the RT pin through a 100pF capacitor. A peak voltage level greater than 3.7 Volts at the RT pin is required for detection of the sync pulse. The sync pulse width should be set between 15 to 150ns by the external components. The RT resistor is always required, whether the oscillator is free running or externally synchronized. The voltage at the RT pin is internally regulated at 2 Volts. The RT resistor should be located very close to the device and connected directly to the pins of the controller (RT and GND). PWM Comparator / Slope Compensation The PWM comparator compares the current ramp signal with the loop error voltage derived from the error amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4V and then further attenuated by a 3:1 resistor divider. The PWM comparator polarity is such that 0 Volts on the COMP pin will result in a zero duty cycle at the controller output. For duty cycles greater than 50 percent, current mode control circuits are subject to sub-harmonic oscillation. By adding an additional fixed slope voltage ramp signal (slope compensation) to the current sense signal, this oscillation can be avoided. The LM5020-1 integrates this slope compensation by summing a current ramp generated by the oscillator with the current sense signal. Additional slope compensation may be added by increasing the source impedance of the current sense signal. Since the LM5020-2 is not capable of duty cycles greater than 50%, there is no slope compensation feature in this device. 8 Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5020 LM5020 www.ti.com SNVS275F – MAY 2004 – REVISED APRIL 2006 Soft Start The softstart feature allows the power converter to gradually reach the initial steady state operating point, thereby reducing start-up stresses and current surges. At power on, after the VCC and the line undervoltage lockout thresholds are satisfied, an internal 10µA current source charges an external capacitor connected to the SS pin. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output pulses. Gate Driver and Maximum Duty Cycle Limit The LM5020 provides an internal gate driver (OUT), which can source and sink a peak current of 1 Amp. The LM5020 is available in two duty cycle limit options. The maximum output duty cycle is typically 80% for the LM5020-1 option and precisely equal to 50% for the LM5020-2 option. The maximum duty cycle function for the LM5020-2 is accomplished with an internal toggle flip-flop which ensures an accurate duty cycle limit. The internal oscillator frequency of the LM5020-2 is therefore twice the operating frequency of the PWM controller (OUT pin). The 80% maximum duty cycle limit of the LM5020-1 is determined by the internal oscillator and varies more than the 50% limit of the LM5020-2. For the LM5020-1 the internal oscillator frequency and the operational frequency of the PWM controller are equal. Thermal Protection Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. This feature prevents catastrophic failures from accidental device overheating. When activated, typically at 165 degrees Celsius, the controller is forced into a low power standby state, disabling the output driver and the bias regulator. After the temperature is reduced (typical hysteresis = 25°C) the VCC regulator is enabled and a softstart sequence initiated. Typical Application Circuit: 36V - 75 VIN and 3.3V, 4.5A OUT C9 R10 R13 T1 V+ J1 30-75V IN 1 J2 +3.3V 2 C12 470 pF D2 CMPD2838E 20 0.1 PF 10, 1W 1 C13 100 PF GND D3 MBRD835L 2 GND C4 0.1 PF Shutdown R3 2.87k GND C10 4.7 PF 1 7 GND VIN VCC UVLO OUT C6 220 pF R5 15.0k Z1 1SMB5936B COMP CS FB 9 RT/ 10 SYNC GND SS C8 100 pF R6 12.4k GND Q1 Si7898DP R11 2.43k 4 5 R12 1.47k R7 8 2 100 6 R8 0.47 R9 0.47 GND C11 1000 pF LM5020 C5 0.01 PF C7 3300 pF D1 CMPD2838E GND GND U1 R4 1.00k 3 SYNC Input GND GND GND C3 0.01 PF GND 5 6 7 8 GND C2 2.2 PF R1 10 OUT RTN 4 3 2 1 C1 2.2 PF GND R2 61.9k C15 270 PF GND GND GND C14 100 PF GND GND GND GND Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5020 9 LM5020 SNVS275F – MAY 2004 – REVISED APRIL 2006 www.ti.com Table 1. Bill Of Materials ITEM 10 PART NUMBER DESCRIPTION VALUE C 1 C4532X7R2A225M CAPACITOR, CER, TDK 2.2µF, 100V C 2 C4532X7R2A225M CAPACITOR, CER, TDK 2.2µF, 100V C 3 C2012X7R1H103K CAPACITOR, CER, TDK 0.01µF, 50V C 4 C3216X7R2A104K CAPACITOR, CER, TDK 0.1µF, 100V C 5 C2012X7R1H103K CAPACITOR, CER, TDK 0.01µF, 50V C 6 C2012C0G1H221J CAPACITOR, CER, KEMET 220pF, 50V C 7 C2012C0G1H332J CAPACITOR, CER, TDK 3300pF, 50V C 8 C2012C0G1H101J CAPACITOR, CER, TDK 100pF, 50V C 9 C2012X7R1H104K CAPACITOR, CER, TDK 0.1µF, 50V C 10 C3216X7R1C475K CAPACITOR, CER, TDK 4.7µF, 16V C 11 C2012C0G1H102J CAPACITOR, CER, TDK 1000pF, 50V C 12 C2012C0G1H471J CAPACITOR, CER, TDK 470p, 50V C 13 C4532X7S0G107M CAPACITOR, CER, TDK 100µF, 4V C 14 C4532X7S0G107M CAPACITOR, CER, TDK 100µF, 4V C 15 A700X277M0004AT CAPACITOR, ALUM ORGANIC, KEMET 270µF, 4V D 1 CMPD2838E-NSA DIODE, SIGNAL, CENTRAL D 2 CMPD2838E-NSA DIODE, SIGNAL, CENTRAL D 3 MBRD835L DIODE, RECTIFIER, ON SEMICONDUCTOR J 1 MKDS 1/2-3.81 TERM BLK, MINI, 2 POS, PHOENIX CONTACT J 2 MKDS 1/2-3.81 TERM BLK, MINI, 2 POS, PHOENIX CONTACT Q 1 SI7898DP FET, SILICONIX 150V, 85mΩ R 1 CRCW120610R0F RESISTOR 10 R 2 CRCW12066192F RESISTOR 61.9kΩ R 3 CRCW08052871F RESISTOR 2.87kΩ R 4 CRCW08051001F RESISTOR 1.00kΩ R 5 CRCW08051502F RESISTOR 15.0kΩ R 6 CRCW08051242F RESISTOR 12.4kΩ R 7 CRCW08051000F RESISTOR 100 R 8 CRCW12060R47F RESISTOR 0.47 R 9 CRCW12060R47F RESISTOR 0.47 R 10 CRCW251210R0F RESISTOR 10, 1W R 11 CRCW08052431F RESISTOR 2.43K R 12 CRCW08051471F RESISTOR 1.47K R 13 CRCW080520R0F RESISTOR 20 T 1 B0695-A COILCRAFT TRANSFORMER, FLYBACK, EFD20 CORE T 1 PA0751 PULSE TRANSFORMER, FLYBACK, EFD20 CORE U 1 LM5020-2MM CONTROLLER, SINGLE OUT, PWM, NATIONAL Z 1 1SMB5936B DIODE, ZENER, SMB, 30V Submit Documentation Feedback ALTERNATE Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5020 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM5020MM-1 ACTIVE VSSOP DGS 10 1000 TBD Call TI Call TI -40 to 125 SBLB LM5020MM-1/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SBLB LM5020MM-2 ACTIVE VSSOP DGS 10 1000 TBD Call TI Call TI -40 to 125 SBNB LM5020MM-2/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SBNB LM5020MMX-1 ACTIVE VSSOP DGS 10 3500 TBD Call TI Call TI -40 to 125 SBLB LM5020MMX-1/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SBLB LM5020MMX-2 ACTIVE VSSOP DGS 10 3500 TBD Call TI Call TI -40 to 125 SBNB LM5020MMX-2/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SBNB LM5020SD-1 ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5020-1 LM5020SD-1/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5020-1 LM5020SD-2/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5020-2 LM5020SDX-1 ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5020-1 LM5020SDX-1/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5020-1 LM5020SDX-2 ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5020-2 LM5020SDX-2/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5020-2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5020MM-1 VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5020MM-1/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5020MM-2 VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5020MM-2/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5020MMX-1 VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5020MMX-1/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5020MMX-2 VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5020MMX-2/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5020SD-1 WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5020SD-1/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5020SD-2/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5020SDX-1 WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5020SDX-1/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5020SDX-2 WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5020SDX-2/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5020MM-1 VSSOP DGS 10 1000 203.0 190.0 41.0 LM5020MM-1/NOPB VSSOP DGS 10 1000 203.0 190.0 41.0 LM5020MM-2 VSSOP DGS 10 1000 203.0 190.0 41.0 LM5020MM-2/NOPB VSSOP DGS 10 1000 203.0 190.0 41.0 LM5020MMX-1 VSSOP DGS 10 3500 367.0 367.0 35.0 LM5020MMX-1/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LM5020MMX-2 VSSOP DGS 10 3500 367.0 367.0 35.0 LM5020MMX-2/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LM5020SD-1 WSON DPR 10 1000 203.0 190.0 41.0 LM5020SD-1/NOPB WSON DPR 10 1000 203.0 190.0 41.0 LM5020SD-2/NOPB WSON DPR 10 1000 203.0 190.0 41.0 LM5020SDX-1 WSON DPR 10 4500 367.0 367.0 35.0 LM5020SDX-1/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5020SDX-2 WSON DPR 10 4500 367.0 367.0 35.0 LM5020SDX-2/NOPB WSON DPR 10 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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