ETC DS9194

RT9194
Preliminary
Low-Dropout Linear Regulator Controller
with PGOOD Indication
General Description
Features
The RT9194 is a low-dropout voltage regulator controller
with a specific PGOOD indicating scheme, it acts as a
power supervisor of the power regulated. The part could
drive an external N-Channel MOSFET for various
applications accordingly; especially, the part is operated
with VCC power ranging from 4.5V to 13.5V. With such a
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topology, it's with advantages of flexible and cost-effective.
The part comes to a small footprint package of SOT-23-6.
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Ordering Information
4.5V to 13.5V Operation Voltage
High Accuracy ± 2% 0.8V Voltage Reference
Quick Transient Response
Power Good Indicator with Delay
Enable Control
Compliant with Intel “Grantsdale Chipset Platform
Design Guide” Specification
Small Footprint Package SOT-23-6
RoHS Compliant and 100% Lead (Pb)-Free
Applications
RT9194
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Package Type
E : SOT-23-6
Operating Temperature Range
C : Commercial Standard
P : Pb Free with Commercial Standard
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Note :
Special Designed for Intel ® Grantsdale platform
FSB_VTT power regulation
Processor Power-Up Sequening
Notebook and laptop PC
Other Power regulation with Power Good indication.
Pin Configurations
RichTek Pb-free products are :
−RoHS compliant and compatible with the current require-
(TOP VIEW)
VCC
ments of IPC/JEDEC J-STD-020.
−Suitable for use in SnPb or Pb-free soldering processes.
−100%matte tin (Sn) plating.
DRI PGOOD
6
5
4
1
2
3
EN
GND
FB
Marking Information
For marking information, contact our sales representative
directly or through a RichTek distributor located in your
area, otherwise visit our website for detail.
SOT-23-6
Note : There is no pin1 indicator on top mark for SOT-23-6
type, and pin 1 will be lower left pin when reading top mark
from left to right.
Typical Application Circuit
VCC
Chip Enable
VIN
Ccc
1
2
3
EN
GND
VCC
RT9194
FB
DRI
PGOOD
6
CIN
5
4
Q1
RPGOOD
VOUT
R1
PGOOD
COUT
R2
VOUT
DS9194-05 March 2006
R1+ R2
= 0.8 ×
R2
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RT9194
Preliminary
Test Circuit
VCC
VIN
12V
Ccc
1uF
Chip Enable
EN
GND
CIN
100uF
VCC
RT9194
Q1
PHD3055
DRI
100k
FB
VOUT
PGOOD
RPGOOD
PGOOD
VOUT
COUT
100uF
R1
1k
R1+ R2
= 0.8 ×
R2
R2
2k
Figure 1. Typical Test Circuit
VCC
12V
Ccc
1uF
Chip Enable
5V
EN
GND
VFB
FB
VCC
RT9194
DRI
A
VDRI
PGOOD
CFB
VFB = 1V for current sink at DRI
VFB = 0.6V for current source at DRI
Figure 2. DRI Source/Sink Current Test Circuit
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DS9194-05 March 2006
RT9194
Preliminary
Functional Pin Description
Pin Name
Pin No.
Pin Function
EN
1
Chip Enable (Active High)
GND
2
Ground
FB
3
Output Voltage Feedback
PGOOD
4
Power Good Open Drain Output
DRI
5
Driver Output
VCC
6
Power Supply Input
Function Block Diagram
EN
VCC
Reference 0.8V
Voltage
+
0.7V
-
DRI
Driver
PGOOD
+
-
3ms
Delay
FB
GND
DS9194-05 March 2006
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RT9194
Preliminary
Absolute Maximum Ratings
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(Note 1)
Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 15V
Enable Voltage --------------------------------------------------------------------------------------------------------- 7V
Power Good Output Voltage ---------------------------------------------------------------------------------------- 7V
Power Dissipation, PD @ TA = 25°C
SOT-23-6 ---------------------------------------------------------------------------------------------------------------- 0.4W
Package Thermal Resistance
SOT-23-6, θJA ----------------------------------------------------------------------------------------------------------- 250°C/W
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C
Junction Temperature ------------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
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(Note 3)
Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 4.5V to 13.5V
Enable Voltage --------------------------------------------------------------------------------------------------------- 0V to 5.5V
Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V/12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
VCC Operation Voltage Range
VCC input range
4.5
--
13.5
V
POR Threshold
VCC rising
4.0
4.2
4.5
V
POR Hysteresis
VCC falling
--
0.2
--
V
VCC Supply Current
VCC = 12V
--
0.3
0.8
mA
Driver Source Current
VCC = 12V, VDRI = 6V
5
--
--
mA
Driver Sink Current
VCC = 12V, VDRI = 6V
5
--
--
mA
Reference Voltage (VFB)
VCC = 12V, VDRI = 5V
0.784
0.8
0.816
V
Reference Line Regulation (VFB)
VCC = 4.5V to 15V
--
3
6
mV
Amplifier Voltage Gain
VCC = 12V, no load
--
70
--
dB
PSRR at 100Hz, No Load
VCC = 12V, no load
50
--
--
dB
Rising Threshold
VCC = 12V
--
90
--
%
Hysteresis
VCC = 12V
--
15
--
%
Sink Capability
VCC = 12V @ 1mA
--
0.2
0.4
V
Delay Time
VCC = 12V
1
3
10
ms
Falling Delay
VCC = 12V
--
15
--
us
Power Good
To be Continued
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DS9194-05 March 2006
RT9194
Preliminary
Parameter
Test Conditions
Min
Typ
Max
Units
Chip Enable
EN Rising Threshold
VCC = 12V
--
0.7
--
V
EN Hysteresis
VCC = 12V
--
30
--
mV
Standby Current
VCC = 12V, VEN = 0V
--
--
5
uA
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
DS9194-05 March 2006
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RT9194
Preliminary
Typical Operating Characteristics
Feedback Voltage vs. Temperature
Quiescent Current vs. Temperature
0.48
0.47
0.46
VIN = 1.5V, VCC = 12V, RPGOOD = 100k
CIN = COUT = 100uF, R1 = 1k, R2 = 2k
Feedback Voltage (V)
Refer to Test Circuit Figure 1
0.85
0.8
0.75
VIN = 1.5V, VCC = 12V, RPGOOD = 100k
CIN = COUT = 100uF, R1 = 1k, R2 = 2k
0.7
0.45
-50
-25
0
25
50
75
100
-50
125
-25
0
75
100
125
DRI
Source
Current
Temperature
DRI
Sink Current
vs.vs.
Temperature
DRISource
Sink Current
Temperature
DRI
Current vs.
vs. Temperature
60
50
45
40
Refer to Test Circuit Figure 2
55
DRI Sink Current (mA)
30
Refer to Test Circuit Figure 2
DRI Source Current (mA)
50
Temperature (°C)
Temperature (°C)
27
24
21
18
15
VFB = 1V, VCC = 12V, VDRI = 6V
VFB = 0.6V, VCC = 12V, VDRI = 6V
35
12
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
Temperature (°C)
Sink Current vs. DRI Voltage
PGOOD Delay Time vs. Temperature
4
20
15
10
5
PGOOD Delay Time (ms)
Refer to Test Circuit Figure 2
25
Sink Current (mA)
25
3.5
VIN = 1.5V, VCC = 12V
RPGOOD = 100k
R1 = 1k, R2 = 2k
Refer to Test Circuit Figure 1
Quiescent Current (mA)
0.49
Refer to Test Circuit Figure 1
0.9
0.5
3
2.5
2
TA = 25°C
1.5
0
0
0.5
1
1.5
2
DRI Voltage (V)
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2.5
3
-50
-25
0
25
50
75
100
125
Temperature (°C)
DS9194-05 March 2006
RT9194
Preliminary
PGOOD Delay Time
VCC = 12V, ILOAD = 1A
CIN = COUT = 100uF
Refer to Test Circuit Figure 1
VCC = 12V, CIN = COUT = 100uF, ILOAD = 100mA
VOUT (V)
VPGOOD (V)
VEN (V)
VOUT (V)
ILoad (A)
VPGOOD (V)
VEN (V)
Time (500us/Div)
Time (500us/Div)
PGOOD Off
VEN (V)
Enable Threshold Voltage (V)
VPGOOD (V)
Refer to Test Circuit Figure 1
ILoad (A)
1
VIN = 1.5V, VCC = 12V, RPGOOD = 100kΩ
CIN = COUT = 100uF, R1 = 1k, R2 = 2k
0.95
0.9
Turn on
0.85
0.8
Turn off
0.75
0.7
0.65
Refer to Test Circuit Figure 1
Enable Threshold Voltage vs. Temperature
VCC = 12V
CIN = COUT = 100uF
VOUT (V)
Refer to Test Circuit Figure 1
PGOOD Delay Time
0.6
-50
Time (50us/Div)
-25
0
25
50
75
100
125
Temperature (°C)
-20
5
0
Time (250us/Div)
DS9194-05 March 2006
VIN = 1.5V to 2.5V, ILOAD = 100mA
CIN = 2.2uF, COUT = 100uF
10
0
-10
2.5
1.5
Time (100us/Div)
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Refer to Test Circuit Figure 1
0
FB Voltage
Deviation (mV)
20
Input Voltage
Deviation (V)
VIN = 2.5V, VOUT = 1.2V
CIN = COUT = 100uF
Line Transient Response
Refer to Test Circuit Figure 1
Load
Current(A)
FB Voltage
Deviation (mV)
Load Transient Response
RT9194
Preliminary
Application Information
Capacitors Selection
Careful selection of the external capacitors for RT9194 is
highly recommended in order to remain high stability and
performance.
Regarding the supply voltage capacitor, connecting a
capacitor which is 7 1μF between VCC and ground is a
must. The capacitor improves the supply voltage stability
to provide chip normally operating.
Regarding the input capacitor, connecting a capacitor
which 7 100μF between VIN and ground is recommended
to increase stability. With large value of capacitance could
result in better performance for both PSRR and line
transient response.
the output voltage decay rate. Drive the EN pin high to
turn on the device again.
Under Voltage Protection
RT9194 equips the VOUT under-voltage (UV) protection
function. The UV protection circuits will start monitoring
the power status after the PGOOD pin goes high. If the
output voltage drops to below 75% of its setting value,
the PGOOD and DRI pins will be pulled low and latch
RT9194. The UV latch status will be released only when
VCC or Enable pin goes low and returns high again, which
will also cause RT9194 to re-activate.
MOSFET Selection
When driving external pass element, connecting a
capacitor 7 100μF between V OUT and ground is
recommended for stability. With larger capacitance can
reduce noise and improve load transient response and
PSRR.
The RT9194 are designed to driver external N-Channel
MOSFET pass element. MOSFET selection criteria
include threshold voltage V GS (V TH ), maximum
continuous drain current ID, on-resistance R DS(ON)
,maximum drain-to-source voltage VDS and package
thermal resistance θ(JA).
Output Voltage Setting
The most critical specification is the MOSFET RDS(ON).
Calculate the required RDS(ON) from the following formula:
V − VOUT
NMOSFET RDS(ON) = IN
ILOAD
For example, the MOSFET operate up to 2A when the
input voltage is 1.5V and set the output voltage is 1.2V,
R ON = (1.5V-1.2V) / 2A = 150mΩ, the MOSFET's
RON have to select lower than 150mΩ. A Philip PHD3055E
MOSFET with an RDS(ON) of 120mΩ(typ.) is a close
match.
The RT9194 develop a 0.8V reference voltage; especially
suit for low voltage application. As shown in application
circuit, the output voltage could easy set the output
voltage by R1 & R2 divider resistor.
Power Good Function
The RT9194 has the power good function with delay.
The power good output is an open drain output. Connect
a 100kΩ pull up resistor to VOUT to obtain an output
voltage. When the output voltage arrive 90% of normal
value the power good will output voltage with 3ms delay
time.
When the output voltage falling arrive 75% of normal
value the power good will turn off with less than 1ms
delay time. But, there are two exceptions. One is the
enable pull low the power good will turn off quickly. The
second is the VCC falling arrive POR value (4V typ.) the
power good also will turn off quickly.
Chip Enable Operation
Pull the EN pin low to drive the device into shutdown mode.
During shutdown mode, the standby current drops to
5μA(MAX). The external capacitor and load current determine
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And carry on consider the thermal resistance from
junction to ambient θ(JA) of the MOSFET's package. The
power dissipation calculate by :
PD = (VIN − VOUT) x ILOAD
The thermal resistance from junction to ambient θ(JA)
calculate by :
(T − T )
θ (JA) = J A
PD
In this example, PD = (1.5V − 1.2V) x 2A = 0.6W. The
PHD3055E's θ(JA) is 75°C/W for its D-PAK package, which
translates to a 45°C temperature rise above ambient. The
package provides exposed backsides that directly transfer
heat to the PCB board.
DS9194-05 March 2006
RT9194
Preliminary
PNP Transistor Selection
The RT9194 could driver the PNP transistor to sink output current. PNP transistor selection criteria include DC current
gain hFE, threshold voltage VEB, collector-emitter voltage VCE, maximum continues collector current IC, package thermal
resistance θ(JA).
For example, the PNP transistor operates sink current up to 0.5A when the input voltage is 1.5V and set the output
voltage is 1.2V. As show in Figure 3. A KSB772 PNP transistor, the VCE = 1.2V, VBE = -1V, IC = 0.5A, IB = 0.5/160 7
3.125mA, when the DRI pin voltage is 0.2V could sink 6.8mA(MAX) is a close match.
Sink Current vs. DRI Voltage
25
VIN
VCC
VCC
PGOOD
GND
Chip Enable
EN
Q1
DRI
Ccc
RT9194
20
CIN
RPGOOD
VOUT
FB
R1
Q2
COUT
Sink Current (mA)
PGOOD
15
10
5
R2
TA = 25°C
0
0
Figure 3
0.5
1
1.5
2
2.5
3
DRI Voltage (V)
Figure 4
Layout Considerations
There are three critical layout considerations. One is the divider resistors should be located to RT9194 as possible to
avoid inducing any noise. The second is capacitors place. The CIN and COUT have to put at near the NMOS for improve
performance. The third is the copper area for pass element. We have to consider when the pass element operating
under high power situation that could rise the junction temperature. In addition to the package thermal resistance limit,
we could add the copper area to improve the power dissipation. As show in Figure 5 and Figure 6.
VIN
VIN
PGOOD
CIN
+
VCC
VCC
GND
Chip Enable
EN
Q1
DRI
Ccc
PGOOD
RT9194
FB
GND
RPGOOD
VOUT
PGOOD
VCC
R1
VOUT
+
COUT
FB
EN
+
R2
GND
Figure 5
DS9194-05 March 2006
Figure 6
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RT9194
Preliminary
Outline Dimension
H
D
L
C
B
b
A
A1
e
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.889
1.295
0.031
0.051
A1
0.000
0.152
0.000
0.006
B
1.397
1.803
0.055
0.071
b
0.250
0.560
0.010
0.022
C
2.591
2.997
0.102
0.118
D
2.692
3.099
0.106
0.122
e
0.838
1.041
0.033
0.041
H
0.080
0.254
0.003
0.010
L
0.300
0.610
0.012
0.024
SOT-23-6 Surface Mount Package
RICHTEK TECHNOLOGY CORP.
RICHTEK TECHNOLOGY CORP.
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]
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DS9194-05 March 2006