RT9024 - Richtek

RT9024
Low-Dropout Linear Regulator Controller with PGOOD
Indication
General Description
Features
The RT9024 is a low-dropout voltage regulator controller
with a specific PGOOD indicating scheme. The part could
drive an external N-MOSFET for various applications. The
part is operated with VCC power ranging from 3.8V to
13.5V. With such a topology, it's with advantages of
flexible and cost-effective. The part comes to a small
footprint package of SOT-23-6.
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Ordering Information
Applications
RT9024
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Package Type
E : SOT-23-6
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Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
3.8V to 13.5V Operation Voltage
0.8V ± 2% High Accuracy Voltage Reference
Quick Transient Response
Power Good Indicator with Delay
Enable Control
Small Footprint Package SOT-23-6
RoHS Compliant and 100% Lead (Pb)-Free
DSC
DSLR
Pin Configurations
(TOP VIEW)
Note :
VCC
DRI PGOOD
Richtek products are :
`
6
RoHS compliant and compatible with the current require-
5
4
2
3
GND
FB
ments of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
EN
SOT-23-6
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
Typical Application Circuit
VCC
Chip Enable
VIN
Ccc
1 EN
2
3
GND
FB
VCC
RT9024
DRI
PGOOD
6
CIN
5
4
Q1
RPGOOD
VOUT
R1
COUT
R2
VOUT = 0.8
PGOOD
DS9024-03 April 2011
R1 + R2
R2
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RT9024
Test Circuit
V CC
V IN
12V
V CC
12V
Chip Enable
1 EN
2
GND
Ccc
1uF
VCC 6
C IN
100uF
RT9024 DRI 5
3 FB
V O U T = 0.8
R1 + R2
R2
2
V OUT
R PGOOD
PGOOD
1 EN
5V
Q1
PHD3055
100k
PGOOD 4
R1
1k
Ccc
1uF
Chip Enable
C OUT
100uF
GND
VCC
RT9024
3 FB
V FB
6
DRI 5
PGOOD
A
V DRI
4
C FB
V FB = 1V for current sink at DRI
V FB = 0.6V for current source at DRI
R2
2k
Figure 1. Typical Test Circuit
Figure 2. DRI Source/Sink Current Test Circuit
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
EN
Chip Enable (Active High).
2
GND
Ground.
3
FB
Output Voltage Feedback.
4
PGOOD
Power Good Open Drain Output.
5
DRI
Driver Output.
6
VCC
Power Supply Input.
Function Block Diagram
EN
VCC
Reference 0.8V
Voltage
+
0.7V
-
DRI
Driver
PGOOD
+
-
3ms
Delay
FB
GND
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DS9024-03 April 2011
RT9024
Absolute Maximum Ratings
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(Note 1)
Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 15V
Enable Voltage --------------------------------------------------------------------------------------------------------- 7V
Power Good Output Voltage ---------------------------------------------------------------------------------------- 7V
Power Dissipation, PD @ TA = 25°C
SOT-23-6 ---------------------------------------------------------------------------------------------------------------- 0.4W
Package Thermal Resistance (Note 2)
SOT-23-6, θJA ----------------------------------------------------------------------------------------------------------- 250°C/W
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C
Junction Temperature ------------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
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(Note 4)
Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 3.8V to 13.5V
Enable Voltage --------------------------------------------------------------------------------------------------------- 0V to 5.5V
Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V/12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VCC Operation Voltage Range
VCC Input Range
3.8
--
13.5
V
POR Threshold
VCC Rising
3.15
3.4
3.65
V
POR Hysteresis
VCC Falling
0.1
0.2
0.3
V
VCC Supply Current
VCC = 12V
--
0.3
0.8
mA
Driver Source Current
VCC = 12V, VDRI = 6V
5
--
--
mA
Driver Sink Current
VCC = 12V, VDRI = 6V
5
--
--
mA
Reference Voltage (VFB)
VCC = 12V, VDRI = 5V
0.784
0.8
0.816
V
Reference Line Regulation (VFB)
VCC = 4.5V to 15V
--
3
6
mV
Amplifier Voltage Gain
VCC = 12V, No Load
--
70
--
dB
PSRR at 100Hz, No Load
VCC = 12V, No Load
50
--
--
dB
Rising Threshold
VCC = 12V
85
90
95
%
Hysteresis
VCC = 12V
--
15
--
%
Sink Capability
VCC = 12V @ 1mA
--
0.2
0.4
V
Delay Time
VCC = 12V
1
3
10
ms
Falling Delay
VCC = 12V
--
15
20
us
Power Good
To be Continued
DS9024-03 April 2011
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RT9024
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Chip Enable
EN Rising Threshold
VCC = 12V
--
0.7
1
V
EN Hysteresis
VCC = 12V
--
30
--
mV
Standby Current
VCC = 12V, VEN = 0V
--
--
5
uA
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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DS9024-03 April 2011
RT9024
Typical Operating Characteristics
Feedback Voltage vs. Temperature
Quiescent Current vs. Temperature
0.50
0.43
0.40
0.38
0.35
VIN = 1.5V, VCC = 12V, RPGOOD = 100k
CIN = COUT = 100uF, R1 = 1k, R2 = 2k
0.33
0.85
0.8
0.75
VIN = 1.5V, VCC = 12V, RPGOOD = 100k
CIN = COUT = 100uF, R1 = 1k, R2 = 2k
0.30
0.7
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
50
75
100
125
DRI Sink Current vs. Temperature
DRI Source Current vs. Temperature
50
45
40
Refer to Test Circuit Figure 2
55
DRI Sink Current (mA)
30
Refer to Test Circuit Figure 2
DRI Source Current (mA)
25
Temperature (°C)
60
27
24
21
18
15
VFB = 1V, VCC = 12V, VDRI = 6V
VFB = 0.6V, VCC = 12V, VDRI = 6V
35
12
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
Temperature (°C)
Current
vs.vs.
DRIDRI
Voltage
DRISink
Sink
Current
Voltage
PGOOD Delay Time vs. Temperature
4
20
15
10
5
PGOOD Delay Time (ms)
Refer to Test Circuit Figure 2
25
Sink Current (mA)
Refer to Test Circuit Figure 1
0.45
3.5
VIN = 1.5V, VCC = 12V
RPGOOD = 100k
R1 = 1k, R2 = 2k
Refer to Test Circuit Figure 1
Quiescent Current (mA)
0.48
Feedback Voltage (V)
Refer to Test Circuit Figure 1
0.9
3
2.5
2
TA = 25°C
1.5
0
0
0.5
1
1.5
2
DRI Voltage (V)
DS9024-03 April 2011
2.5
3
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT9024
PGOOD Delay Time
VCC = 12V, ILOAD = 1A
CIN = COUT = 100uF
Refer to Test Circuit Figure 1
VCC = 12V, CIN = COUT = 100uF, ILOAD = 100mA
V OUT
VPGOOD
VEN (V)
V OUT
ILoad (A)
VPGOOD
VEN (V)
Time (500us/Div)
Time (500us/Div)
PGOOD Off
VEN (V)
Enable Threshold Voltage (V)
VPGOOD
Refer to Test Circuit Figure 1
ILoad (A)
1
VIN = 1.5V, VCC = 12V, RPGOOD = 100kΩ
CIN = COUT = 100uF, R1 = 1k, R2 = 2k
0.95
0.9
Turn on
0.85
0.8
Turn off
0.75
0.7
0.65
Refer to Test Circuit Figure 1
Enable Threshold Voltage vs. Temperature
VCC = 12V
CIN = COUT = 100uF
V OUT
Refer to Test Circuit Figure 1
PGOOD Delay Time
0.6
-50
Time (50us/Div)
-25
0
25
50
75
100
125
Temperature (°C)
-20
5
0
Time (250us/Div)
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VIN = 1.5V to 2.5V, ILOAD = 100mA
CIN = 2.2uF, COUT = 100uF
10
0
-10
2.5
1.5
Time (100us/Div)
DS9024-03 April 2011
Refer to Test Circuit Figure 1
0
FB Voltage
Deviation (mV)
20
Input Voltage
Deviation (V)
VIN = 2.5V, VOUT = 1.2V
CIN = COUT = 100uF
Line Transient Response
Refer to Test Circuit Figure 1
Load
Current(A)
FB Voltage
Deviation (mV)
Load Transient Response
RT9024
Application Information
Capacitors Selection
MOSFET Selection
Careful selection of the external capacitors for RT9024 is
highly recommended in order to remain high stability and
performance.
The RT9024 are designed to driver external N-MOSFET
pass element. MOSFET selection criteria include
threshold voltage VGS (VTH), maximum continuous drain
current ID, on-resistance RDS(ON) ,maximum drain-tosource voltage VDS and package thermal resistance θ(JA).
Regarding the supply voltage capacitor, connecting a
capacitor which is ≥ 1μF between VCC and ground is a
must. The capacitor improves the supply voltage stability
for proper operation.
Regarding the input capacitor, connecting a capacitor which
≥ 100μF between VIN and ground is recommended to
increase stability. With large value of capacitance could
result in better performance for both PSRR and line
transient response.
When driving external pass element, connecting a
capacitor ≥ 100μF between V OUT and ground is
recommended for stability. With larger capacitance can
reduce noise and improve load transient response and
PSRR.
Output Voltage Setting
The RT9024 develops a 0.8V reference voltage; especially
suitable for low voltage application. As shown in application
circuit, the output voltage could easy set the output
voltage by R1 & R2 divider resistor.
Power Good Function
The RT9024 has the power good function with delay. The
power good output is an open drain output. Connect a
100kΩ pull up resistor to VOUT to obtain an output voltage.
When the output voltage arrives 90% of normal value.
PGOOD will become active and be pulled high by external
circuits with typically 3ms delay.
Chip Enable Operation
Pull the EN pin low to drive the device into shutdown mode.
During shutdown mode, the standby current drops to
5μA(MAX). The external capacitor and load current determine
the output voltage decay rate. Drive the EN pin high to
turn on the device again.
DS9024-03 April 2011
The most critical specification is the MOSFET RDS(ON).
Calculate the required RDS(ON) from the following formula:
N − MOSFET RDS(ON) =
VIN - VOUT
ILOAD
For example, the MOSFET operate up to 2A when the
input voltage is 1.5V and set the output voltage is 1.2V,
R ON = (1.5V-1.2V) / 2A = 150mΩ, the MOSFET's
RON must be lower than 150mΩ. Philip PHD3055E
MOSFET with an RDS(ON) of 120mΩ(typ.) is a suitable
solution.
The power dissipation is calculate as :
PD = (VIN − VOUT) x ILOAD
The thermal resistance from junction to ambient θ(JA) is :
θ (JA) =
(TJ − TA )
PD
In this example, PD = (1.5V − 1.2V) x 2A = 0.6W. The
PHD3055E's θ(JA) is 75°C/W for its D-PAK package, which
translates to a 45°C temperature rise above ambient. The
package provides exposed backsides that directly transfer
heat to the PCB board.
PNP Transistor Selection
The RT9024 could driver the PNP transistor to sink output
current. PNP transistor selection criteria include DC current
gain hFE, threshold voltage VEB, collector-emitter voltage
VEN, maximum continues collector current IC, package
thermal resistance θ(JA).
For example, the PNP transistor operates sink current up
to 0.5A when the input voltage is 1.5V and set the output
voltage is 1.2V. As show in Figure 3. A KSB772 PNP
transistor, the VEN = 1.2V, VBE = -1V, IC = 0.5A, IB = 0.5/
160 ≥ 3.125mA, when the DRI pin voltage is 0.2V could
sink 6.8mA(MAX) is a close match.
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RT9024
Sink
Current
vs.vs.
DRIDRI
Voltage
DRI
Sink
Current
Voltage
25
VIN
20
PGOOD
VCC
GND
Chip Enable
EN
Q1
DRI
Ccc
PGOOD
RT9024
Sink Current (mA)
VCC
CIN
RPGOOD
VOUT
FB
R1
Q2
COUT
15
10
5
R2
TA = 25°C
0
0
Figure 3
0.5
1
1.5
2
2.5
3
DRI Voltage (V)
Figure 4
Layout Considerations
There are three critical layout considerations. One is the divider resistors should be located to RT9024 as possible to
avoid inducing any noise. The second is capacitors place. The CIN and COUT have to put at near the N-MOSFET for
improve performance. The third is the copper area for pass element. We have to consider when the pass element
operating under high power situation that could rise the junction temperature. In addition to the package thermal resistance
limit, we could add the copper area to improve the power dissipation. As show in Figure 5 and Figure 6.
VIN
VIN
PGOOD
CIN
+
VCC
VCC
GND
Chip Enable
EN
Q1
DRI
Ccc
PGOOD
RT9024
FB
GND
RPGOOD
VOUT
PGOOD
VCC
COUT
VOUT
+
R1
FB
EN
+
R2
GND
Figure 5
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Figure 6
DS9024-03 April 2011
RT9024
Outline Dimension
H
D
L
C
B
b
A
A1
e
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.889
1.295
0.031
0.051
A1
0.000
0.152
0.000
0.006
B
1.397
1.803
0.055
0.071
b
0.250
0.560
0.010
0.022
C
2.591
2.997
0.102
0.118
D
2.692
3.099
0.106
0.122
e
0.838
1.041
0.033
0.041
H
0.080
0.254
0.003
0.010
L
0.300
0.610
0.012
0.024
SOT-23-6 Surface Mount Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS9024-03 April 2011
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