RDA5800C SINGLE-CHIP BROADCAST FM RADIO TUNER 1 Rev.4.1–Oct.2007 General Description The RDA5800C is a single-chip broadcast FM stereo radio tuner with fully integrated synthesizer, IF selectivity and MPX decoder. The tuner uses the CMOS process, support multi-interface and require the least external component. The package size is 4X4mm and is completely adjustment-free. All these make it very suitable for portable devices. The RDA5800C has a powerful low-IF digital audio processor, this make it have optimum sound quality with varying reception conditions. The RDA5800C can be tuned to the worldwide frequency band. Figure 1-1. RDA5800C Top View 1.1 Features z CMOS single-chip fully-integrated FM tuner z Low power consumption ¾ z z z High cut z Programmable de-emphasis (50/75 μs) Total current consumption lower than 16mA at z Receive signal strength indicator (RSSI) 3.3V power supply z Bass boost z Analog and digital volume control z I2S digital output interface z Line-level analog output voltage Support worldwide frequency band ¾ ¾ 76 -108 MHz Digital low-IF tuner ¾ Image-reject down-converter z 32.768 KHz reference clock ¾ High performance A/D converter z 2-wire and 3-wire serial control bus interface ¾ IF selectivity performed internally z Directly support 32Ω resistance loading z Integrated LDO regulator Fully integrated digital frequency synthesizer ¾ Fully integrated on-chip RF and IF VCO ¾ Fully integrated on-chip loop filter z Autonomous search tuning z Support crystal oscillator z Digital auto gain control (AGC) z Digital adaptive noise cancellation ¾ Mono/stereo switch ¾ Soft mute ¾ z 1.2 2.7 to 5.5 V operation voltage 4X4mm 24 pin QFN package Applications z Cellular handsets z MP3, MP4 players z Portable radios z PDAs, Notebook PCs Copyright © RDA Microelectronics Inc. 2006. All rights are reserved. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. RDA Microelectronics, Inc. 2 RDA5800C FM Tuner V4.1 Table of Contents 1 General Description ....................................................................................................................................1 1.1 Features .........................................................................................................................................1 1.2 Applications ..................................................................................................................................1 2 Table of Contents.........................................................................................................................................2 3 Functional Description................................................................................................................................3 3.1 FM Receiver..................................................................................................................................3 3.2 Synthesizer ....................................................................................................................................3 3.3 Power Supply ................................................................................................................................4 3.4 Powerdown and Reset ...................................................................................................................4 3.5 Control Interface ...........................................................................................................................4 3.6 I2S Audio Data Interface ...............................................................................................................5 3.7 GPIO Outputs................................................................................................................................5 4 Electrical Characteristics ...........................................................................................................................6 5 Receiver Characteristics .............................................................................................................................7 6 Serial Interface ............................................................................................................................................8 6.1 Three-wire Interface Timing .........................................................................................................8 6.2 I2C Interface Timing......................................................................................................................9 7 Register Definition ....................................................................................................................................10 8 Pins Description.........................................................................................................................................12 9 Application Diagram.................................................................................................................................13 9.1 Audio Loading Resistance Larger than 32Ω & TCXO Application:...........................................13 9.1.1 Bill of Materials: .........................................................................................................................13 9.2 Audio Loading Resistance Lower than 32Ω & TCXO Application:...........................................14 9.2.1 Bill of Materials: .........................................................................................................................14 9.3 Audio Loading Resistance Larger than 32Ω & DCXO Application: ..........................................15 9.3.1 Bill of Materials: .........................................................................................................................15 9.4 MCU CODEC Application: ........................................................................................................16 9.4.1 Bill of Materials: .........................................................................................................................16 10 Package Physical Dimension ....................................................................................................................17 11 Change List................................................................................................................................................18 12 Notes： .......................................................................................................................................................18 13 Contact Information .................................................................................................................................19 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 2 of 19 RDA Microelectronics, Inc. 3 RDA5800C FM Tuner V4.1 Functional Description I PGA LNAN C1 - Q PGA Limiter 32.768 KHz Q ADC digital filter MPX decoder stereo/mono audio VCO R DAC ROUT GPIO Synthesizer GPIO RST SEN 2.7-5.5 V DVDD AVDD LOUT 0/90 C2 RCLK L DAC Audio DSP Core + LNA LNAP I ADC RSSI LDO Interface Bus SCLK MCU SDIO VIO Figure 3-1. RDA5800C FM Tuner Block Diagram 3.1 FM Receiver The receiver uses a digital low-IF architecture that avoids the difficulties associated with direct conversion while delivering lower solution cost and reduces complexity, and integrates a low noise amplifier (LNA) supporting the FM broadcast band (76 to 108MHz), a quadrature image-reject mixer, a programmable gain control (PGA), a high resolution analog-to-digital converters (ADCs), an audio DSP and a highfidelity digital-to-analog converters (DACs). The LNA has differential input ports (LNAP and LNAN) and supports any input port by set according registers bits (LNA_PORT_SEL[1:0]). The LNA default input resistance is 150 Ohm under single or dual input mode. It default input common mode voltage is GND. The limiter prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. The quadrature mixer down converts the LNA output differential RF signal to low-IF, it also has image-reject function. The PGA amplifies the mixer output IF signal and then digitized with ADCs. The DSP core finishes the channel selection, FM demodulation, stereo MPX decoder and output audio signal. The MPX decoder can autonomous switch from stereo to mono to limit the output noise. The DACs convert digital audio signal to analog and change the volume at same time. The DACs has low-pass feature and -3dB frequency is about 30 KHz. 3.2 Synthesizer The frequency synthesizer generates the local oscillator signal which divide to quadrature, then be used to downconvert the RF input to a constant low intermediate frequency (IF). The synthesizer reference clock is 32.768 KHz. The synthesizer frequency is defined by bits CHAN[9:0] with the range from 76MHz to 108MHz. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 3 of 19 RDA Microelectronics, Inc. 3.3 RDA5800C FM Tuner V4.1 Power Supply Parameter The RDA5800C integrated one LDO which supplies power to the chip. The external supply voltage range is 2.7-5.5 V. 3.4 Powerdown and Reset Test Min Typ Max Unit Condition SEN Input to RST ↑ Setup SEN Input to RST The RDA5800C selects three-wire or I2C control interface in reset process. Setting RST pin low after power up will reset the chip to initial state. Setting RST pin high will bring the chip out of reset. Setting SEN low on the rising edge of RST will select three-wire control interface, and setting SEN high on the rising edge of RST will select I2C control interface. Symbol ↑ Hold tsrst 30 ns thrst 30 ns Table 3-2 I2C Reset Timing Characteristics When need, the RDA5800C could enter into a powerdown mode to reduce power consumption, with software setting the ENABLE bit low. In powerdown mode, analog and digital circuitry are both disabled, while maintaining register configuration and keeping control interface active. The RDA5800C could enter back into normal mode by setting the ENABLE bit high, and resume normal working. Details refer to RDA5800 Programming Guide. 3.5 The RDA5800C supports three-wire and I2C control interface. User could select either of them to program the chip. Figure 3-1. Three-wire Interface Reset Timing Diagram Parameter Symbol Test Min Typ Max Unit Condition SEN Input to RST ↑ Setup SEN Input to RST ↑ Hold tsrst 30 ns thrst 30 ns Table 3-1 SPI Reset Timing Characteristics Figure 3-2. I2C Interface Reset Timing Diagram Control Interface The three-wire interface is a standard SPI interface. It includes three pins: SEN, SCLK and SDIO. Each register write is 25-bit long, including 4-bit high register address, a r/w bit, 4-bit low register address, and 16-bit data (MSB is the first bit). RDA5800C samples command byte and data at posedge of SCLK. Each register read is also 25-bit long, including 4-bit high register address, a r/w bit, 4-bit low register address, and 16-bit data (MSB is the first bit) from RDA5800C. The turn around cycle between command byte from MCU and data from RDA5800C is a half cycle. RDA5800C samples command byte at posedge of SCLK, and output data also at posedge of SCLK. The I2C interface is compliant to I2C Bus Specification 2.1. It includes two pins: SCLK and SDIO. A I2C interface transfer begins with START condition, a command byte and data bytes, each byte has a followed ACK (or NACK) bit, and ends with STOP condition. The command byte includes a 7-bit chip address (0010000b) and a R/W bit. The ACK (or NACK) is always sent out by receiver. When in write transfer, data bytes is written out from MCU, and when in read transfer, data bytes is read out from RDA5800C. There is no visible register address in I2C interface transfers. The I2C The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 4 of 19 RDA Microelectronics, Inc. interface has a fixed start register address (0x02h for write transfer and 0x0Ah for read transfer), and an internal incremental address counter. If register address meets the end of register file, 0x3Ah, register address will wrap back to 0x00h. For write transfer, MCU programs registers from register 0x02h high byte, then register 0x02h low byte, then register 0x03h high byte, till the last register. RDA5800 always gives out ACK after every byte, and MCU gives out STOP condition when register programming is finished. For read transfer, after command byte from MCU, RDA5800 sends out register 0x0Ah high byte, then register 0x0Ah low byte, then register 0x0Bh high byte, till receives NACK from MCU. MCU gives out ACK for data bytes besides last data byte. MCU gives out NACK for last data byte, and then RDA5800 will return the bus to MCU, and MCU will give out STOP condition. Details refer to RDA5800 Programming Guide. 3.6 I2S Audio Data Interface The RDA5800C supports I2S (Inter_IC Sound Bus) RDA5800C FM Tuner V4.1 audio interface. The interface is fully compliant with I2S bus specification. When setting I2SEN bit high, RDA5800C will output SCK, WS, SD signals from GPIO3, GPIO1, GPIO2 as I2S master and transmitter, the sample rate is 42Kbps. 3.7 GPIO Outputs The RDA5800C has three GPIOs. The function of GPIOs could programmed with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0] and I2SEN. If I2SEN is set to low, GPIO pins could be programmed to output low or high or high-Z, or be programmed to output interrupt and stereo indicator with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0]. GPIO2 could be programmed to output a low interrupt (interrupt will be generated only with interrupt enable bit STCIEN is set to high) when seek/tune process completes. GPIO3 could be programmed to output stereo indicator bit ST. Constant low, high or high-Z functionality is available regardless of the state of VA and VD supplies or the ENABLE bit. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 5 of 19 RDA Microelectronics, Inc. 4 RDA5800C FM Tuner V4.1 Electrical Characteristics Table 4-1 SYMBOL DC Electrical Specification (Recommended Operation Conditions): DESCRIPTION MIN TYP MAX UNIT AVDD Analog Supply Voltage 2.7 3.3 5.5 V DVDD Digital Supply Voltage 2.7 3.3 5.5 V VIO Interface Supply Voltage 1.5 - 3.6 V Tamb Ambient Temperature -20 27 +70 ℃ VIL CMOS Low Level Input Voltage 0 0.3*DVDD V VIH CMOS High Level Input Voltage 0.7*VDD DVDD V VTH CMOS Threshold Voltage Table 4-2 SYMBOL 0.5*VDD V DC Electrical Specification (Absolute Maximum Ratings): DESCRIPTION MIN TYP MAX UNIT VIO Interface Supply Voltage -0.5 +4 V Tamb Ambient Temperature IIN -40 +90 °C (1) -10 +10 mA (1) -0.3 VIO+0.3 V -20 dBm Input Current VIN Input Voltage Vlna LNA FM Input Level Notes: 1. For Pin: SCLK, SDIO, SEN, RST. Table 4-3 Power Consumption Specification (VDD = 2.7 to 5.5 V, TA = -25 to 85 ℃, unless otherwise specified) SYMBOL DESCRIPTION CONDITION TYP UNIT IA Analog Supply Current ENABLE=1 13 mA ID Digital Supply Current ENABLE=1 3 mA IVIO Interface Supply Current SCLK and RCLK inactive 1 μA IAPD Analog Powerdown Current ENABLE=0 2 μA IDPD Digital Powerdown Current ENABLE=0 2 μA The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 6 of 19 RDA Microelectronics, Inc. 5 RDA5800C FM Tuner V4.1 Receiver Characteristics Table 5-1 Receiver Characteristics (VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified) SYMBOL PARAMETER CONDITIONS MIN BAND=0 BAND=1 TYP MAX UNIT 87.5 108 MHz 76 91 MHz 1.5 2 μV EMF 130 150 170 Ω 2 4 6 pF - dBμV - dB - dB General specifications Fin FM Input Frequency 1,2,3 Vrf (S+N)/N=26dB Sensitivity Rin LNA Input Resistance Cin 7 LNA Input Capacitance 7 4 IP3in Input IP3 AGCD=1 80 m=0.3 40 ±200KHz 45 1,2 αam AM Suppression S200 Adjacent Channel Selectivity Left and Right Audio VAFL; VAFR Frequency Output Voltage (Pins LOUT and ROUT) (S+N)/N αSCS Volume_dac[3:0] =1111 Maximum Signal Plus Noise 1,2,3,5 to Noise Ratio Stereo Channel Separation 60 75 90 mV 54 60 - dB 35 - - dB 0.3 0.5 % 1 dB - Ω Audio Total Harmonic THD αAOI Volume_dsp[3:0]=1111 - 1,3,6 Distortion Audio Output L/R Imbalance Audio Output Loading RL Resistance Single-ended 32 - Pins LNAN, LNAP, LOUT, ROUT and NC(22,23) Vcom_rfin Pins LNAN and LNAP Input Audio Output Common Vcom Vcom_nc Mode Voltage8 Pins NC (22, 23) Common Mode Voltage V Float Common Mode Voltage 0.9 1 1.1 V 0.45 0.5 0.55 V ! The NC(22, 23) pins SHOULD BE left floating. Notes: 1. Fin=76 to 108MHz; Fmod=1KHz; de-emphasis=75μs; MONO=1; L=R unless noted otherwise; 2. Δf=22.5KHz; 3. BAF = 300Hz to 15KHz, RBW <=10Hz; 4. |f2-f1|>1MHz, f0=2xf1-f2, AGC disable, Fin=76 to 108MHz; 5. PRF=60dBUV; 6. Δf=75KHz. 7. Measured at VEMF = 1 m V, f RF = 76 to 108MHz 8. At LOUT and ROUT pins The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 7 of 19 RDA Microelectronics, Inc. 6 6.1 RDA5800C FM Tuner V4.1 Serial Interface Three-wire Interface Timing Table 6-1 Three-wire Interface Timing Characteristics (VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified) PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT SCLK Cycle Time tCLK SCLK Rise Time tR 50 ns SCLK Fall Time tF 50 ns SCLK High Time tHI 10 ns SCLK Low Time tLO 10 ns SDIO Input, SEN to SCLK↑ Setup ts 10 - - ns SDIO Input, to SCLK↑ Hold th 10 - - ns 35 ns SCLK↑ to SDIO Output Valid tcdv Read 2 - 10 ns SEN↑ to SDIO Output High Z tsdz Read 2 - 10 ns 5 pF Digital Input Pin Capacitance Figure 6-1. Three-wire Interface Write Timing Diagram Figure 6-2. Three-wire Interface Read Timing Diagram The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 8 of 19 RDA Microelectronics, Inc. 6.2 RDA5800C FM Tuner V4.1 I2C Interface Timing Table 6-2 I2C Interface Timing Characteristics (VDD = 2.7 to 5.5 V, TA = -25 to 85 °C, unless otherwise specified) PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT SCLK Frequency fscl 0 - 400 KHz SCLK High Time thigh 0.6 - - μs SCLK Low Time tlow 1.3 - - μs Setup Time for START Condition tsu:sta 0.6 - - μs Hold Time for START Condition thd:sta 0.6 - - μs Setup Time for STOP Condition tsu:sto 0.6 - - μs SDIO Input to SCLK↑ Setup tsu:dat 100 - - ns SDIO Input to SCLK↓ Hold thd:dat 0 - 900 ns STOP to START Time tbuf 1.3 - - μs SDIO Output Fall Time tf:out 20+0.1Cb - 250 ns tr:in / tf:in 20+0.1Cb - 300 ns Input Spike Suppression tsp - - 50 ns SCLK, SDIO Capacitive Loading Cb - - 50 pF 5 pF SDIO Input, SCLK Rise/Fall Time Digital Input Pin Capacitance Figure 6-3. I2C Interface Write Timing Diagram Figure 6-4. I2C Interface Read Timing Diagram The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 9 of 19 RDA Microelectronics, Inc. 7 RDA5800C FM Tuner V4.1 Register Definition REG BITS 00H 15:8 02H 03H 04H NAME FUNCTION DEFAULT CHIPID[7:0] Chip ID. 0x58 15 DHIZ 0 14 DMUTE Audio Output High-Z Disable. 0 = High impedance; 1 = Normal operation Mute Disable. 0 = Mute; 1 = Normal operation 13 MONO 0 12 BASS Mono Select. 0 = Stereo; 1 = Force mono Bass Boost. 0 = Disabled; 1 = Bass boost enabled Seek Up. 0 = Seek down; 1 = Seek up Seek. 0 = Disable; 1 = Enable Seek begins in the direction specified by SEEKUP and ends when a channel is found with RSSI level above SEEKTH[5:0], or the entire band has been searched. The SEEK bit is set low and the STC bit is set high when the seek operation completes. Power Up Enable. 0 = Disabled; 1 = Enabled Channel Select. BAND = 0 Frequency = Channel Spacing (kHz) x CHAN+ 87.5 MHz BAND = 1 Frequency = Channel Spacing (kHz) x CHAN + 76.0 MHz CHAN is updated after a seek operation. Channel Spacing. 0 = see SPACE bit; 1 = 50 kHz Band Select. 0 = 87.5-108 MHz (US/Europe) 1 = 76-91 MHz (Japan) Channel Spacing. 0 = 100 kHz; 1 = 200 kHz Seek/Tune Complete Interrupt Enable. 0 = Disable Interrupt; 1 = Enable Interrupt Setting STCIEN = 1 will generate a 5 ms low pulse on GPIO2 when the interrupt occurs. De-emphasis. 0 = 75 µs; 1 = 50 µs I2S Bus Enable. 0 = disabled; 1 = enabled. General Purpose I/O 3. 00 = High impedance 01 = Mono/Stereo indicator (ST) 0 9 SEEKUP 8 SEEK 0 ENABLE 15:8 CHAN[7:0] 2 SPACE_50K 1 BAND 0 SPACE 14 STCIEN 11 DE 6 5:4 I2SEN GPIO3[1:0] 0 0 0 0 0x00 0 0 0 0 0 0 00 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 10 of 19 RDA Microelectronics, Inc. REG 05H BITS 3:2 GPIO2[1:0] 1:0 GPIO1[1:0] 15 INTMODE 13:8 0AH NAME SEEKTH[5:0] 7:4 VOLUME_DSP[3:0] 3:0 VOLUME_DAC[3:0] 14 STC 13 SF 8 ST 7:0 0BH 13:8 10H 14:13 READCHAN[7:0] RSSI LNA_PORT_SEL[1:0] RDA5800C FM Tuner V4.1 FUNCTION 10 = Low 11 = High General Purpose I/O 2. 00 = High impedance 01 = Interrupt (INT) 10 = Low 11 = High General Purpose I/O 1. 00 = High impedance 01 = Reserved 10 = Low 11 = High INT Mode Select. 0 = Generate 5ms interrupt; 1 = Interrupt last until write action occurs. Seek Threshold in Logarithmic. 000000 = min RSSI; 111111 = max RSSI DSP Volume Control. 0000=min -15db; 1111=max 0db DAC Gain Control Bits (Volume). 0000=min; 1111=max Volume scale is logarithmic Seek/Tune Complete. 0 = Not complete; 1 = Complete The seek/tune complete flag is set when the seek or tune operation completes. Seek Fail. 0 = Seek successful; 1 = Seek failure The seek fail flag is set when the seek operation fails to find a channel with an RSSI level greater than SEEKTH[5:0]. Stereo Indicator. 0 = Mono; 1 = Stereo Stereo indication is available on GPIO3 by setting GPIO1[1:0] =01. Read Channel. BAND = 0 Frequency = Channel Spacing (kHz) x READCHAN + 87.5 MHz BAND = 1 Frequency = Channel Spacing (kHz) x READCHAN + 76.0 MHz READCHAN is updated after a tune or seek operation. RSSI in Logarithmic. 000000 = min; 111111 = max LNA input port selection bit. 01 = LNAN input 10 = LNAP input 11 = dual port input DEFAULT 00 00 0 000100 1111 0000 0 0 1 0x00 0x00 10 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 11 of 19 RDA Microelectronics, Inc. 8 RDA5800C FM Tuner V4.1 Pins Description Figure 0-1. RDA5800C Top View Table 0-1 RDA5800C Pins Description SYMBOL GND LNAN,LNAP PIN 1,5,14,17,24 2,4 DESCRIPTION Ground. Connect to ground plane on PCB LNA input port. For single-ended input, LNAN should be connected to RFGND RFGND 3 LNA ground. Connect to ground plane on PCB XTAL 6 Crystal oscillator input. RST 7 Latch reset (active low) input for serial control bus SEN 8 Latch enable (active low) input for serial control bus SCLK 9 Clock input for serial control bus SDIO 10 Data input/output for serial control bus RCLK 11 32.768KHz external reference clock input VIO 12 Power supply for I/O AVDD 13 Power supply for analog section ROUT,LOUT DVDD GPIO1,GPIO2,GPIO3 NC 15,16 18 19,20,21 22,23 Right/Left audio output Power supply for digital section General purpose input/output No Connect The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 12 of 19 RDA Microelectronics, Inc. 9 RDA5800C FM Tuner V4.1 Application Diagram 9.1 Audio Loading Resistance Larger than 32Ω & TCXO Application: Notes: 1. J1: Common 32Ω Resistance Headphone; 2. U1: RDA5800C Chip; Resistor; GPIO3 GPIO2 GPIO1 NC NC GND 19 3. R1,R2 I2C 3-wire Bus Pull-up 4. V1: Analog and Digital Power Supply (2.7~5.5V); 5. FM Choke (L3 and C3) for Audio Common and LNA Input VIO RCLK SDIO SEN SCLK 6. Pins NC(22, 23),XTAL Should be Leaved Floating; 7. Place C6 Close to AVDD pin. 7 RST Common; Figure 9-1. RDA5800C FM Tuner Application Diagram (TCXO Application) 9.1.1 Bill of Materials: COMPONENT U1 VALUE RDA5800C J1 DESCRIPTION Broadcast FM Radio Tuner SUPPLIER RDA Common 32Ω Resistance Headphone R1,R2 10KΩ I2C Bus Pull-up Resistor L3/C3 100nH/24pF LC Chock for LNA Input C4,C5 125µF Audio AC Couple Capacitors C6 24nF Power Supply Bypass Capacitor The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 13 of 19 RDA Microelectronics, Inc. 9.2 RDA5800C FM Tuner V4.1 Audio Loading Resistance Lower than 32Ω & TCXO Application: Notes: 1. J1: Resistance Lower than 32Ω Audio Speaker or Headphone 2. U1: RDA5800C Chip 3. R1,R2 I2C 3-wire Bus Pull-up Resistor 4. V1: Analog and Digital Power Supply (2.7~5.5V) 5. FM Choke (L3 and C3) for Audio Common and LNA Input Common 6. Pins NC(22, 23),XTAL Should be Leaved Floating 7. Place C6 Close to AVDD pin 8. Changing the Resistor R4 and R5 Value can Change the Output Volume. Figure 9-2. RDA5800C FM Tuner Application Diagram (Audio Amplifier Application) 9.2.1 Bill of Materials: COMPONENT U1 VALUE RDA5800C DESCRIPTION Broadcast FM Radio Tuner U2 Audio Amplifier J1 Audio Speaker R1,R2 10KΩ I2C Bus Pull-up Resistor L1/C1; L2/C2 100nH/24pF LC Chock for Audio Output L3/C3 100nH/24pF LC Chock for LNA Input C6 24nF Power Supply Bypass Capacitor R4,R5 20KΩ Audio Amplifier Feedback Resistors R2/C7; R3/C8 20KΩ/0.39µF SUPPLIER RDA Audio High-passed Filter and Amplifier Input Resistors The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 14 of 19 RDA Microelectronics, Inc. 9.3 RDA5800C FM Tuner V4.1 Audio Loading Resistance Larger than 32Ω & DCXO Application: Notes: 1. J1: Common 32Ω Resistance Headphone; 2. U1: RDA5800C Chip; 3. U2: 32.768KHz Crystal oscillator 4. R1,R2: I2C 3-wire Bus Pull-up Resistor; 4. V1: Analog and Digital Power Supply (2.7~5.5V); 5. FM Choke (L3 and C3) for Audio Common and LNA Input Common; 6. Pins NC(22, 23) Should be Leaved Floating; 7. Place C6 Close to AVDD pin. 8.Load of Crystal oscillator (C6,C7,R3,R2) 9. Place U2 Close to U1 Figure 9-3. RDA5800C FM Tuner Application Diagram (DCXO Application) 9.3.1 Bill of Materials: COMPONENT VALUE DESCRIPTION U1 RDA5800C Broadcast FM Radio Tuner U2 DCXO Crystal oscillator 32.768KHz J1 SUPPLIER RDA Common 32Ω Resistance Headphone R1,R2 10KΩ I2C Bus Pull-up Resistor L3/C3 100nH/24pF LC Chock for LNA Input C4,C5 125µF Audio AC Couple Capacitors C2 24nF Power Supply Bypass Capacitor C6,C7 22pF Load Capacitor of DCXO R3,R4 5MΩ/250KΩ Load Resistor f DCXO The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 15 of 19 RDA Microelectronics, Inc. 9.4 RDA5800C FM Tuner V4.1 MCU CODEC Application: Notes: 1. J1: Common 32Ω Resistance Headphone; 2. U1: RDA5800C Chip; 3. U2: 32.768KHz Crystal oscillator 4. R1,R2: I2C 3-wire Bus Pull-up Resistor; 4. V1: Analog and Digital Power Supply (2.7~5.5V); 5. FM Choke L3 for LNA Input Common; 6. Pins NC(22, 23) Should be Leaved Floating; 7. Place C6 Close to AVDD pin. 8.Load of Crystal oscillator (C6,C7,R3,R2) 9. Place U2 Close to U1 Figure 9-4. RDA5800C FM Tuner Application Diagram (DCXO+MCU CODEC Application) 9.4.1 Bill of Materials: COMPONENT VALUE DESCRIPTION U1 RDA5800C Broadcast FM Radio Tuner U2 DCXO Crystal oscillator 32.768KHz J1 SUPPLIER RDA Common 32Ω Resistance Headphone R1,R2 10KΩ I2C Bus Pull-up Resistor L3 600R/100M Common for LNA Input C4,C5 125µF Audio AC Couple Capacitors C2 24nF Power Supply Bypass Capacitor C6,C7 22pF Load Capacitor of DCXO R3,R4 5MΩ/250KΩ Load Resistor f DCXO The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 16 of 19 RDA Microelectronics, Inc. RDA5800C FM Tuner V4.1 10 Package Physical Dimension Figure 10-1 illustrates the package details for the RDA5800. The package is lead-free and RoHS-compliant. MIN NOM MAX 4.00 BSC D □ 4.00 BSC E □ D2 2.00 2.15 2.25 E2 2.00 2.15 2.25 0.50 BSC e □ L 0.30 0.40 0.50 b 0.18 0.25 0.30 A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 0.20 ref Figure 10-2. 24-Pin 4x4 Quad Flat No-Lead (QFN) The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 17 of 19 RDA Microelectronics, Inc. RDA5800C FM Tuner V4.1 11 Change List REV DATE AUTHER CHANGE DESCRIPTION V1.0 2006-11-28 Chun Zhao, Lin Li, Hua Li Original Draft. V2.0 2007-03-08 Chun Zhao, XiaoQi You Up data test result; add DCXO application V2.1 2007-03-18 XiaoQi You Up data Package Physical Dimension V2.2 2007-04-23 XiaoQi You Add Table 3-1,3-2; Up data Application Diagram, Add Pull-Up Resister R2; Add note 4; V3.0 2007-07-16 XiaoQi You Up data to RDA5800C; Add Application Diagram 9.4 V3.1 2007-07-21 XiaoQi You Change some wrong in Application Diagram V4.0 2007-10-10 XiaoQi You Change some wrong in Notes V4.1 2007-11-12 XiaoQi You Change some wrong in register definition 12 Notes： 1： 在 使 用 I 2 C 模 式 控 制 芯 片 时 ， 把 Pin： /SEN 直 接 连 接 到 Pin： VIO； 2： RDA5800C 支 持 32.768KHz crystal oscillator 作 为 参 考 时 钟 输 入 。 （ 详 见 图 9-3,9-4） 3: 可 以 通 过 硬 件 电 路 设 置 芯 片 工 作 在 I2C 总 线 控 制 模 式 。 详 细 电 路 如 下 图 ： 附图：I2C 总线电路接口电路 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 18 of 19 RDA Microelectronics, Inc. RDA5800C FM Tuner V4.1 13 Contact Information RDA Microelectronics (Shanghai), Inc. Suite 1108 Block A, e-Wing Center, 113 Zhichun Road Haidian District, Beijing Tel: 86-10-62635360 Fax: 86-10-82612663 Postal Code: 100086 Suite 302 Building 2, 690 Bibo Road Pudong District, Shanghai Tel: 86-21-50271108 Fax: 86-21-50271099 Postal Code: 201203 Copyright © RDA Microelectronics Inc. 2006. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 19 of 19