ETC FM11-GE-300

FM11-GE-300
Low-Power Voice Processor
Data Sheet v1.0
August 2008
FM11-GE-300
Preliminary Data Sheet
PRELIMINARY INFORMATION
THIS DOCUMENT CONTAINS INFORMATION ON A PREPRODUCTION PRODUCT. SPECIFICATIONS AND PREPRODUCTION
INFORMATION HEREIN ARE SUBJECT TO CHANGE WITHOUT NOTICE.
FORTEMEDIA, INC. PRODUCTS ARE NOT INTENDED FOR LIFE SAVING NOR LIFE SUSTAINING APPLICATIONS AND FORTEMEDIA,
INC. THUS, ASSUMES NO LIABILITY IN SUCH USAGES. FORTEMEDIA, INC. PRODUCTS MAY ONLY BE USED IN LIFE-SUPPORT
DEVICES OR SYSTEMS WITH THE EXPRESS WRITTEN APPROVAL OF FORTEMEDIA, INC., IF A FAILURE OF SUCH COMPONENTS
CAN REASONABLY BE EXPECTED TO CAUSE THE FAILURE OF THAT LIFE-SUPPORT DEVICE OR SYSTEM, OR TO AFFECT THE
SAFETY OR EFFECTIVENESS OF THAT DEVICE OR SYSTEM. LIFE SUPPORT DEVICES OR SYSTEMS ARE INTENDED TO BE
IMPLANTED IN THE HUMAN BODY, OR TO SUPPORT AND/OR MAINTAIN AND SUSTAIN AND/OR PROTECT HUMAN LIFE. IF THEY
FAIL, IT IS REASONABLE TO ASSUME THAT THE HEALTH OF THE USER OR OTHER PERSONS MAY BE ENDANGERED.
WE HEREIN DISCLAIM ANY AND ALL WARRANTIES, INCLUDING BUT NOT LIMITED TO WARRANTIES OF NON-INFRINGEMENT,
REGARDING CIRCUITS, DESCRIPTIONS AND CHARTS STATED HEREIN.
Fortémedia, SAM, fortémedia and SAM logos are trademarks of Fortémedia, Inc.
All other trademarks belong to their respective companies.
Copyright © 2007-2008 Fortémedia. All rights reserved.
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FM11-GE-300
Preliminary Data Sheet
TABLE OF CONTENT
1. INTRODUCTION .................................................................................................................... 7
1.1 OVERVIEW ...........................................................................................................................................................7
1.2 KEY FEATURES ....................................................................................................................................................7
1.3 INTERNAL HARDWARE BLOCK DIAGRAM ............................................................................................................8
2. FUNCTIONAL BLOCKS DESCRIPTION ................................................................................... 9
2.1 SERIAL EEPROM INTERFACE (PINS 15, 16) ........................................................................................................9
2.2 UART INTERFACE (PINS 12, 13)..........................................................................................................................9
2.3 SHI (SERIAL HOST INTERFACE) (PINS 23, 24)....................................................................................................10
2.4 SERIAL PORT (PINS 8, 9, 10, 11).........................................................................................................................11
2.5 ADC (PINS 39, 40, 41, 42, 43, 44)......................................................................................................................12
2.6 DAC (PINS 3, 47, 48) .........................................................................................................................................12
3. SYSTEM OPERATIONAL DESCRIPTION ............................................................................... 13
3.1 MODES OF OPERATION ......................................................................................................................................13
3.2 POWER-UP OPTION PINS (STRAP OPTIONS) .......................................................................................................16
3.3 POWER ON/OFF TIMING .....................................................................................................................................17
3.4 SYSTEM CLOCK .................................................................................................................................................18
3.5 ACCESSING FM11-GE-300 THROUGH EEPROM, UART, SHI .........................................................................18
3.5.1 Accessing Through EEPROM ...................................................................................................................18
3.5.2 Examples of Accessing Through EEPROM...............................................................................................18
3.5.3 Accessing Through UART .........................................................................................................................19
3.5.4 Examples of Accessing Through UART.....................................................................................................19
3.6 MISCELLANEOUS FUNCTIONS ............................................................................................................................20
4. ELECTRICAL & TIMING SPECIFICATION ............................................................................ 21
4.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................21
4.2 RECOMMENDED OPERATING CONDITIONS .........................................................................................................21
4.3 DC CHARACTERISTICS .......................................................................................................................................21
4.4 AC CHARACTERISTICS .......................................................................................................................................22
4.5 DSP PERFORMANCE DETAILS ............................................................................................................................23
4.6 TIMING CHARACTERISTICS ................................................................................................................................23
5. PIN DEFINITION ................................................................................................................. 26
6. PACKAGING......................................................................................................................... 30
7. ORDERING INFORMATION ................................................................................................. 31
APPENDIX I: REQUIRED EXTERNAL COMPONENTS FOR OPERATION.................................... 32
APPENDIX II: AUDIO MEASUREMENT SYSTEM ...................................................................... 33
APPENDIX III: SUGGESTED EXTERNAL POWER CIRCUITRY.................................................. 34
REFERENCES ........................................................................................................................... 35
I. TERMINOLOGY .....................................................................................................................................................35
II. RELATED DOCUMENTS ........................................................................................................................................35
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FM11-GE-300
Preliminary Data Sheet
FIGURES
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1: Internal Hardware Block Diagram.......................................................................................8
2: UART Interface: 8-bit/character, 1 stop-bit protocol .............................................................9
3: UART Transfers(TX & RX) .................................................................................................9
4: SHI Start, Restart, & Stop ............................................................................................... 10
5: SHI Burst write (on SDA) ................................................................................................ 10
6: SHI Read (on SDA)......................................................................................................... 10
7: Serial Port - One Clock Delay ........................................................................................... 11
8: Serial Port - Zero Clock Delay .......................................................................................... 11
9: FM11-GE-300 ADC Details ............................................................................................... 12
10: FM11-GE-300 DAC Details ............................................................................................. 12
11: State Transition Diagram............................................................................................... 14
12: Timing Chart of State Transitions ................................................................................... 15
13: Timing Chart of Power Down Transition .......................................................................... 15
14: Timing Chart of External Reset....................................................................................... 16
15: Timing Chart of Power On/Off Sequence ......................................................................... 17
16: Power-down to Speaker-out Timing ................................................................................ 24
17: Digital Input Timing (No Clock Delay) ............................................................................. 24
18: Digital Input Timing (One Clock Delay) ........................................................................... 24
19: Digital Output Timing (No Clock Delay) .......................................................................... 25
20: Digital Output Timing (One Clock Delay) ......................................................................... 25
21: FM-GE-300 Pin Configuration ......................................................................................... 28
22: PAD_IN Symbol for Digital Input Pins.............................................................................. 28
23: PAD_BI Symbol for Digital Input/Output Pins................................................................... 29
24: LQFP Packaging Drawings ............................................................................................. 30
25: External XTAL_IN Clock Source ...................................................................................... 32
26: Echo Cancellation Test Setup ......................................................................................... 33
27: Noise Suppression Test Setup ....................................................................................... 33
28: Suggested External Power Circuitry ................................................................................ 34
TABLES
Table
Table
Table
Table
Table
Table
Table
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Table
Table
Table
Table
Table
Table
Table
Table
Table
1: Status of Serial Port Output Pins ....................................................................................... 11
2: Strap Option Pins to Select Desired Operation .................................................................... 16
3: Strap Option Pins for EEPROM ........................................................................................ 16
4: Strap Pin settings for default internal mode ........................................................................ 17
5: Command Entry Data Pattern ........................................................................................... 18
6: Command Entries........................................................................................................... 18
7: Examples of Accessing Through EEPROM .......................................................................... 18
8: Examples of Accessing Through UART ............................................................................... 19
9: Absolute Maximum Ratings............................................................................................... 21
10: Recommended Operating Conditions ............................................................................... 21
11: DC Characteristics ......................................................................................................... 21
12: AC Characteristics.......................................................................................................... 22
13: ADC(Mic0/Mic1/Line_in) PGA Gain ................................................................................... 22
14: DAC(Line_out, Speaker Out) PGA Gain............................................................................. 23
15: DSP Performance Details ................................................................................................ 23
16: Timing Characteristics .................................................................................................... 23
17: Pin Number sorted Description ........................................................................................ 26
18: Ordering Information ..................................................................................................... 31
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FM11-GE-300
Preliminary Data Sheet
Table
Table
Table
Table
Table
19:
20:
21:
22:
23:
External Components Recommendation ........................................................................... 32
Echo Cancellation Measurement ...................................................................................... 33
Noise Suppression Measurement ..................................................................................... 33
Terminology.................................................................................................................. 35
Related Reference Documents ........................................................................................ 35
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FM11-GE-300
Preliminary Data Sheet
Revision History
Revision
0.1
1.0
DS v0.1, Aug08
Description
Initial Draft
Initial Release
Date
Aug 2008
Sept 2008
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FM11-GE-300
Preliminary Data Sheet
1. Introduction
Fortemedia’s FM11-GE-300 voice processor is a high-performance, low-power single chip solution for echo
cancellation and noise suppression. Providing SAM (small array microphone) technology supporting beam forming
capability while consuming only 30mW power, FM11-GE-300 is ideal for any portable application with stringent
requirements for battery life and power consumption. Offered in a 7x7mm² LQFP package, the FM11-GE-300 is
ideally suited for applications such as hands free car kit, cordless desktop speaker phone, notebook computers and
VoIP phones.
For more information, please refer to the Fortemedia Technology White Paper.
1.1 Overview
To achieve the lowest power consumption, FM11-GE-300 features an integrated hardware accelerator to speed up
voice related applications. This new device is designed to achieve the lowest power while providing the highest
performance. With an enhanced CODEC, FM11-GE-300 provides high SNR for the best voice quality. FM11-GE300 provides excellent noise suppression and full duplex capabilities, including non-linear echo cancellation and
side tone cancellation.
1.2 Key Features
Highly integrated single chip solution
▪ 16-bit DSP w/ Hardware Accelerator
▪ 3 ADC (Analog to Digital Converter)
▪ 2 DAC (Digital to Analog Converter)
▪ RAM, ROM
▪ On-chip microphone amplifier
▪ SHI, UART interface to external controller
▪ Serial port interface supports 16-bit & 13-bit PCM format
Low power consumption (30mW)
High performance
▪ Powerful AEC (acoustic echo cancellation) (60dB)
▪ Superior full-duplex
▪ Supports 1 & 2 microphone modes
▪ Run-time microphone select mode
♦ Select Mic0 or Mic1 as the main microphone (when using small array microphone with beam-forming)
▪ Differential I/O to reduce RF interference and increase noise immunity
▪ Dynamic range control (DRC) to increase voice intelligibility
▪ Side tone cancellation of 25 to 35dB
▪ Acoustic echo tail length coverage: 64 to 100ms
▪ Mic_in, Line_in, Line_out, & Spk_out PGA (programmable gain amplification)
Supports 2 clock inputs: 4.096MHz or 13MHz
48-pin LQFP package option
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FM11-GE-300
Preliminary Data Sheet
PGA
PGA
M IC 1 I/ F
PGA
PGA
PGA
L INEOUTI/F
LINE IN I /F
SPK OUT
M IC0 I / F
1.3 Internal Hardware Block Diagram
Figure 1: Internal Hardware Block Diagram
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FM11-GE-300
Preliminary Data Sheet
2. Functional Blocks Description
With many built-in functions and modes of operation, designers can easily implement their low power voice
processing systems with the FM11-GE-300. The IC can be analyzed in different interface blocks which include
EEPROM serial interface, UART, Serial Host Interface (SHI), serial port, ADC and DAC. UART and SHI
communication are just some examples of FM11-GM-300’s digital interfaces.
Please refer to Figure 1 for an overview of the internal block functions.
2.1 Serial EEPROM Interface (Pins 15, 16)
FM11-GE-300 supports a serial interface to an optional external EEPROM. It supports 256 bytes (small sized) and
1Kbytes (large sized) EEPROM. Most of the internal variables can be accessed through this EEPROM interface. See
section 3 for more details.
2.2 UART Interface (Pins 12, 13)
FM11-GE-300 has one UART port which is used to transmit and receive control commands. Each transfer will have
one command byte, one or two address bytes, and up to two data bytes. UART needs a sync word “FCF3” to sync
up each transfer. See section 3 for more details.
NOTE: The UART port is recommended as the standard interface to access FM11-GE-300.
8-bit/character 1 stop-bit protocol
S
T
A
R
T
1
2
3
4
5
6
7
8
ST
OP
LSB
Figure 2: UART Interface: 8-bit/character, 1 stop-bit protocol
8-bit
character
S
T
A
R
T
SS
TT
OA
PR
T
S
T
O
P
S
T
A
R
T
The UART_RX / UART_TX pins are normally held high between transfers
Figure 3: UART Transfers(TX & RX)
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FM11-GE-300
Preliminary Data Sheet
2.3 SHI (Serial Host Interface) (Pins 23, 24)
The SHI block is the interface to an external micro-controller which can initialize FM11-GE-300 through this
interface. SHI supports slave mode with 8 bit address mode. The maximum clock speed that the SHI interface can
support is 100 KHz. Each transfer will have one command byte, one or two address bytes, and up to two data bytes.
SHI needs a sync word “FCF3” to sync up each transfer. Please note that SHI is used for transferring parameters
during power-up, and is off after the DSP is in normal operation mode. Please refer to section 3 and FM11-GE-300
SHI Implementation Application Note for more details.
S: start, Sr: restart, P: stop, Ack: acknowledge
Start, Restart and Stop
S
P
or
2
1
Sr
7
8
MSB
9
1
2
3 -8
ACK
or
9
Sr
ACK
Figure 4: SHI Start, Restart, & Stop
Burst Write
S
T
A
R
T
Control
byte
1st data byte
2nd data byte
S
T
O
P
Last data byte
S
s
r
P
1 1 0 0 0 0 0W
A
C
K
A
C
K
A
C
K
Figure 5: SHI Burst write (on SDA)
Read
S
T
A
R
T
Control
byte
1
st
data byte
Last data byte
R
E
S
T
A
R
T
S
S
s 1 1 0 0 0 0 0W
r
s 1 1 0 0 0 0 0 R
r
A
C
K
S
T
O
P
Control
byte
A
C
K
P
A
C
K
N
O
A
C
K
Figure 6: SHI Read (on SDA)
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FM11-GE-300
Preliminary Data Sheet
2.4 Serial Port (Pins 8, 9, 10, 11)
The serial port provides an interface to an existing host (micro-controller) for digital voice data transfer. Both the
master and the slave modes support either an internal or external clock source for the BCLK signal. While operating
with the internal clock, “FSYNC” runs at 8KHz.
The serial port data format can be 16-bit or 13-bit linear pulse code modulation (linear PCM). The default setting is
to run 16-bit linear PCM mode. The format can be selected by EEPROM or an external controller.
In slave mode, FM11-GE-300 supports both short (one clock delay) and long (zero clock delay) “FSYNC”. In
master mode, FM11-GE-300 drives short “FSYNC”. Table 1 below shows the status of the serial port output pins
during different modes.
Table 1: Status of Serial Port Output Pins
Powerdown
Tri-state
Tri-state
Tri-state
Master Mode
Serial Port
Enabled (1)
Normal
Normal
Tri-state
Analog
Mode (2)
“0”
“0”
Tri-state
Powerdown
n/a
n/a
Tri-state
Slave Mode
Serial Port
Enabled (1)
n/a
n/a
Tri-state
Analog
Mode (2)
“0”
“0”
Tri-state
BCLK
FSYNC
PCM_OUT
Notes:
(1) CHI_EN (bit2 of 0x3fe1) set to “0” (Refer to FM11-GE-300 Parameter Tuning Guide)
(2) ANA_COM asserted during reset; otherwise, asserting ANA_COM will turn off all digital clocks and leave
states unknown
BCLK
FSYNC
PCM_OUT
MSB
1
0
MSB
PCM_IN
MSB
1
0
MSB
Figure 7: Serial Port - One Clock Delay
BCLK
FSYNC
PCM_OUT
MSB
1
0
MSB
PCM_IN
MSB
1
0
MSB
Figure 8: Serial Port - Zero Clock Delay
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FM11-GE-300
Preliminary Data Sheet
2.5 ADC (Pins 39, 40, 41, 42, 43, 44)
FM11-GE-300 includes 3 analog-to-digital converters (ADC). The converters are at 16-bit precision and 8k
sampling rate with sigma-delta architecture. All 3 converters are differential; they are used for 2 microphone inputs
with built-in microphone pre-amplifier and 1 line level input. The full scale of the input is 2.4Vpp. See figure 10 for
details.
For more information on how to program the attenuation/gains for the ADC and DAC blocks, please refer to the
FM11GE-300 Parameter Tuning Guide.
Figure 9: FM11-GE-300 ADC Details
2.6 DAC (Pins 3, 47, 48)
FM11-GE-300 includes two digital-to-analog converters (DAC). The converters are at 16-bit precision and 8k
sampling rate with sigma-delta architecture. One of the converters (differential) is used to feed into an external
power amplifier to drive the speaker (Spk_out). The other converter (single-ended) provides programmable
attenuations/gains that can be connected to a PC’s analog input (Line_out). See figure 11 for more details.
For more information on how to program the attenuation/gains for the ADC and DAC blocks, please refer to the
FM11-GE-300 Parameter Tuning Guide.
2 dB gain
Digital
Domain
16-bit
Spk_out
DAC
+
Max 1.5Vpp
-
Max 1.5Vpp
PGA
2 dB gain
Digital
Domain
16-bit
Max 1.5Vpp
Line_out
DAC
PGA
Figure 10: FM11-GE-300 DAC Details
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FM11-GE-300
Preliminary Data Sheet
3. System Operational Description
3.1 Modes of Operation
Depending on the condition, the FM11-GE-300 chip may enter into in one of the following four modes.
Hardware Reset Mode
Whenever power is applied, the chip will enter this mode and remain until 10ms after the RST_ pin is pulled high.
In this mode, the chip samples the strap-options (section 3.2), adjusts the clock source, and waits for the external
clock (XTAL_IN or BCLK) and internal PLL to become stable. After the 10ms, the chip enters the Software Reset
Mode. The chip re-enters the Hardware Reset Mode whenever the RST_ pin is pulled low externally.
Software Reset Mode
In this mode, the embedded DSP software reads the strap-options (section 3.2), determines where the parameters
will be coming from, and then either waits passively for the download from an external host (UART, SHI) or
actively reads the parameters from an external EEPROM. The chip exits this mode when parameter at 1E3A
becomes 0 (handled by embedded DSP when parameter configuration is done). Except when RST_ is pulled low,
the chip moves to the Operational Mode after the Software Reset Mode.
Operational Mode
In this mode, software will set up hardware MMREGs according to the parameter configuration, followed by a
nominal 70ms for initialization. This is the mode where the chip samples its input and delivers its outputs through
the analog/digital interfaces. After that, the chip may enter the Power Down Mode if the PWD_ pin is pulled low.
Power Down Mode
The chip enters the Power Down Mode 10ms after the PWD_ pin is pulled low. During the Power Down Mode, the
PLL source clock can also be turned off because the on-chip PLL is turned off. After the Power Down Mode, the
chip may move to either the Software Reset Mode or the Operational Mode (depending on the setting of the
pwrdwn_set parameter, 1E51). In order for the chip to exit the Power Down Mode correctly, the external PLL
source clock must resume 10ms before PWD_ is pulled high. After that, the chip will need another 13ms for housecleaning work before it can take the new round of parameter download, or resume to the Operational Mode.
The following figures show the state transition diagram and the timing chart when the FM11-GE-300 chip moves
between these 4 states.
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FM11-GE-300
Preliminary Data Sheet
Power Off
apply power
remove power
HW Reset
10ms after
RST_ high
RST_ low
SW Reset
RST_ low
parm(1E3A) 0
parm(1E51), bit12 == 1,
13ms after PWD_ high
Operational
parm(1E51), bit12 == 0,
13ms after PWD_ high
10ms after
PWD_ low
RST_ low
Power Down
Figure 11: State Transition Diagram
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FM11-GE-300
Preliminary Data Sheet
VDD_D
VDD_S
V10
POR_
(internal)
0 ms
5 ms
may power down
RST_
PWD_
XTAL_IN
UART_TX
UART_RX
parm(1E3A)0
parms download
HW Reset Mode
(PLL-on)
SW Reset Mode
10 ms
Operational Mode
70 ms
for XTAL_IN and PLL
to stabilize
initialization
Figure 12: Timing Chart of State Transitions
VDD_D
VDD_S
V10
RST_
PWD_
XTAL_IN can
be turned off
XTAL_IN
UART_TX
UART_RX
parms download
skipped if parm(1E51) bit 12 is 0
Operational Mode
10ms
(optional) SW Reset
Mode
Power Down Mode
10ms
for internal housekeeping operations
Operational Mode
70 ms
13ms
for XTAL_IN and PLL
to stabilize
initialization
Figure 13: Timing Chart of Power Down Transition
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FM11-GE-300
Preliminary Data Sheet
VDD_D
VDD_S
V10
2ms
RST_
XTAL_IN
UART_TX
UART_RX
parm(1E3A)0
parms download
SW Reset Mode
HW Reset Mode
SW Reset Mode
Operational Mode
Operational Mode
10 ms
Power Down Mode
70 ms
for XTAL_IN and PLL
to stabilize
initialization
Figure 14: Timing Chart of External Reset
3.2 Power-Up Option Pins (Strap Options)
Strap options are used by the chip to determine the desired operation of the chip. All the strap options mentioned
below must be pulled high or low using a weak 100k resistor. If left floating, the status will be unknown.
In the software reset mode, the chip samples 5 different strap options to determine desired operation, such as where
the chip will load its parameters from (through an external EEPROM or from an external µP through the UART or
SHI interface).
Table 2: Strap Option Pins to Select Desired Operation
Pin 17
(GPIO7)
0
0
1
1
1
1
Mode
Pin 20
(STRAP0)
0
1
0
1
0
1
Internal(1)
Reserved
Small EEPROM (256 Byte)
Large EEPROM (1 KByte)
SHI
UART
Notes:
(1) Uses pre-defined parameters; please refer to Appendix section for more details
Pin 21
(MUTE_OUT)
X
X
0
0
1
1
If one of the EEPROM modes is selected, use the strap option pins shown in the table below to select which section
of the EEPROM to load parameters from.
Table 3: Strap Option Pins for EEPROM
Starting Address
Segment
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Small (256 Byte)
Large (1 KByte)
16
Pin 10
(PCM_OUT)
Pin 13
(UART_TX)
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
0
1
2
3
0x00
0x40
0x80
0xC0
0x000
0x100
0x200
0x300
0
0
1
1
0
1
0
1
The below table shows the pre-defined settings of internal mode operation. The strap pin settings are for default
internal mode profiles.
Table 4: Strap Pin settings for default internal mode
Profile
1-mic (uni), analog
1-mic (omni), analog
Uni-omni (default), analog
Omni-omni, analog
Pin 13
0
0
1
1
Pin 21
0
1
0
1
3.3 Power On/Off Timing
The following timing chart shows the power on sequence of 3 power pins, namely VDD_D, VDD_S and V10. The
power off sequence is just the reverse order of power on.
VDD_D
VDD_S
V10
tv_settle
tvdd_dly
VDD_S : for analog circuits, including PLL, CODEC, etc.
VDD_D : for digital pads.
VDD_D : for digital core.
tv_settle : Time for voltage to settle within 5% of the final voltage; 20µs < tv_settle < 10ms
tvdd_dly : Delay from VDD_D settle to VDD_S/V10 settle; 100µs < tvdd_dly.
Note:
1. To avoid voltage leakage between VDD_S and V10, these two suppy pins should be supplied together
with a ferret bead separating them similar to the configuration provided in the reference board design.
2. The 100us t vdd_dly is recommended to guarantee proper power-on reset. However, if the pull-high of the
RST_ is delayed sufficiently long (> 5ms) after the VDD_S/V10 settle, this delay can be ignored.
Figure 15: Timing Chart of Power On/Off Sequence
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FM11-GE-300
Preliminary Data Sheet
3.4 System Clock
A user can apply a clock source (crystal or oscillator) of either 4.096MHz or 13MHz to pin 27 (XTAL_IN). A
crystal applied to pins 27(XTAL_IN) and 28(XTAL_OUT) will also work. For more information on crystal
specifications, please refer to the Appendix section.
3.5 Accessing FM11-GE-300 Through EEPROM, UART, SHI
Users can read or write to registers in FM11-GE-300 (ex: to update parameters) through one of 3 interfaces:
EEPROM, UART, or SHI. To access the registers in FM11-GE-300, designers must use a pre-defined command
entry pattern. The UART or SHI interfaces are used if applications require control through an external host (SHI is
off after DSP is in normal operation mode).
Table 5: Command Entry Data Pattern
Command Byte
Address Byte(s)
Data Byte(s)
The table below shows the available command entries and the associated number of bytes required for each entry.
Table 6: Command Entries
Command Entry
Available for Interface
Command
Byte
Mem_write
Mem_read
Short_reg_write
Long_reg_write
reg_read
UART, SHI, EEPROM
UART, SHI
UART
UART
UART, SHI
3B
37
68
6A
60
No. of
Address
Bytes
2
2
1
1
1
No. of
Data
Bytes
2
0
1
2
0
Total
No. of
Bytes
5
3
3
4
2
3.5.1 Accessing Through EEPROM
Users can have a maximum of 4 different sets of parameters in the same EEPROM. Every time a reset is initiated,
the user can select which set of parameters to access. For a large size EEPROM (1 KByte), the absolute maximum
number of bytes is 256 in each section.
When the EEPROM mode is selected to be the source to initialize the parameters after reset, the EEPROM access is
set to burst mode up to 256 bytes. FM11-GE-300 will retrieve data continuously in burst mode until the end of
transfer byte, “F0,” is detected. Then FM11-GE-300 will enter the normal operation mode.
3.5.2 Examples of Accessing Through EEPROM
The table below provides a few examples of how to update parameters in FM11-GE-300 through the EEPROM
interface. For more details, please refer to the FM11GE-300 Parameter Tuning Guide.
Table 7: Examples of Accessing Through EEPROM
a. setup speaker volume
3b
1E
3E
02
00
b. set microphone PGA
3b
1E
34
00
33
DS v0.1, Aug08
18
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
c. set mic_in volume
3b
1E
3D
08
00
d. terminate EEPROM transfer
3b
1E
3A
00
00
F0
-- end of EEPROM initial read command (required)
3.5.3 Accessing Through UART
UART serves as an interface between the FM11-GE-300 and a host PC or controller which can send commands to
program the chip’s parameters. UART is an asynchronous bi-directional serial interface; the protocol is determined
by a start bit, number of character bits, a parity bit and a stop bit. The transfer speed is determined by the baud rate
which can be programmed internally. There is no clock signal between the transmitter and receiver.
There are 5 different types of command entries for the FM11-GE-300 UART interface. A sync word, “FCF3,” is
required before each command entry. Since the speed of the UART interface is much slower than the internal clock
of FM11-GE-300, it is safe to continue a write transfer without checking the status of the data transfer.
There are two access modes: mem_read and reg_read. Mem_read is used to read the memory contents and save
them in registers 25 and 26 of FM11-GE-300. Reg_read then transfers the register contents to the UART interface
output pin TXD. The micro-controller host will then receive the register contents by monitoring the TXD pin.
No partial command entry is allowed. A partial command entry may cause system mal-function.
3.5.4 Examples of Accessing Through UART
The table below provides a few examples of how to update parameters in FM11-GE-300 through the UART
interface. For more details, please refer to the FM11GE-300 Parameter Tuning Guide.
Table 8: Examples of Accessing Through UART
a. mem_write transfer
FC F3 3B 1E 34 00 55
-- write memory 1E34 with 0055
b. mem_read
FC F3 37 1E 34
-- read memory contents of 1E34
c. long_reg_write
FC F3 6A 2A 00 30
-- software reset of DSP
d. reg_read
FC F3 60 25
-- read register 25
e. read out contents of memory location 1E34
FC F3 37 1E 34
FC F3 60 26
-- MSB of 1E34 will transmit through TXD
FC F3 60 25
-- LSB of 1E34 will transmit through TXD
DS v0.1, Aug08
19
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
3.6 Miscellaneous Functions
Speaker Volume Control (Pins 25, 26)
The speaker volume of FM11-GE-300 can be controlled by the Vol- (pin 25) and Vol+ (pin 26) pins. These input
signals are level triggered and active high. The DSP will increase/decrease the volume by one step once it senses a
high signal on either pin (minimum length of active state is 80ms). If either pin is held high continuously, the DSP
will increase/decrease the volume by 4 steps in 1 second. The step-size and maximum volume is programmable (see
FM11GE-300 Parameter Tuning Guide).
If these pins are not used, they must be pulled low using a weak 100K resistor.
Microphone Mute (Pins 21, 24)
A user can mute the microphone input of FM11-GE-300 by using mute_in (pin 24). This signal is level triggered
and active high. The default setting after reset is the “no mute” mode, and will toggle between “no mute” and
“mute” every time the signal is active (minimum length of the active state is 80ms). Please note that the mute
function is not available in SHI mode, as pin 24 serves as the SDA pin of the SHI bus. The mute_out (pin 21) signal
is active high and is a status indication of the “mute” mode. It will output a “high” if in “mute” mode.
If this pin is not used, it must be pulled low using a weak 100 kΩ resistor.
Earpiece and Speaker Mode (Pin 23)
This input signal is edge triggered. On the falling edge, FM11-GE-300 will switch to the “earpiece” mode, which
has a lower internal power amplifier gain. On the rising edge, FM11-GE-300 will switch to the “speaker” mode,
which has the standard internal power amplifier gain. If the built-in power amplifier is not used, the speaker PGA
will be changed accordingly. Please note that this feature is not available in SHI mode, as pin 23 serves as the SCL
pin of the SHI bus.
If this pin is not used, it must be pulled high with a weak 100 kΩ resistor to be in speakerphone mode.
DS v0.1, Aug08
20
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
4. Electrical & Timing Specification
4.1 Absolute Maximum Ratings
Table 9: Absolute Maximum Ratings
Parameter
Power Supply Voltage
Digital Input Voltage
Digital Output Voltage
Storage Temperature
Symbol
VDD_S
VIN
VOUT
Tstg
Condition
-
Rating
2.0
3.6
3.6
-40 to 150
Unit
V
V
V
0
C
4.2 Recommended Operating Conditions
Table 10: Recommended Operating Conditions
Parameter
Symbol
Condition
Min
ESD Protection
HBM
Power Supply
VDD_S
1.62
Voltage(1)
I/O Supply
VDD_D
1.62
Voltage
Operating
Tamb
-5
Temperature
Input High
VIH
VDD_DVoltage
0.3
Input Low
VIL
0
Voltage
Master Clock
fmck
XTAL_IN
Frequency
Master Clock
Dmck
XTAL_IN
40
Duty Ratio
Bit Clock
fbck
BCLK (Master
128
Frequency
Mode)
Bit Clock
fbck
BCLK (Slave
128
Frequency
Mode)
Bit Clock Duty
Dbck
BCLK
45
Cycle
Sync Signal
fsync
FSYNC
Frequency
Notes: The power ripple (AC element) has to be limited within 100mV
Typ
Max
Unit
1.8
2
2.0
kV
V
3.6
V
50
°C
VDD_D
V
0.3
V
1.8 or
3.3
25
4.096,
13
50
MHz
60
%
256
1,024
kHz
256
4,096
kHz
50
55
%
8
kHz
4.3 DC Characteristics
Table 11: DC Characteristics
Parameter
Digital Supply
for Core
Power Supply
Current
Power Down
DS v0.1, Aug08
Symbol
V10
ISU
IPD
Condition
Operating, Analog +
Digital
PWD_ is low
21
Min
1.62
Typ
1.8
Max
2.0
Unit
V
-
17
19
mA
-
40*
-
µA
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
Current
Input Leakage
Current
High Level
Digital Output
Voltage
IIH
IIL
VOH
VI = VDD_D
VI = 0 V
No Load
VDD_D
-
Low Level
VOL
No Load
Digital Output
Voltage
Digital Output
IO
Leakage Current
Input
CIN
10
Capacitance
Power
PSYS
30.6
V10 =1.8V, Tamb=25°C
Dissipation
Notes:
º IPD is only for V10. VDD_D and VDD_S leakage current may be up to additional 20µA.
10
10
µA
µA
V
0
V
10
µA
-
pF
34.2
mW
4.4 AC Characteristics
Table 12: AC Characteristics
AC Characteristics (room temperature, gain set to 0dB)
Parameter
Condition
Mic0 & Mic1 Input Range
Reference as 0dB full
(differential)
scale
Line_in Input Range
Reference as 0dB full
(differential)
scale
Spk_out Full Scale Output
Reference as 0dB full
(differential)
scale
Line_out Full Scale Output
@ 0dB PGA gain;
(single-ended)
@ 2dB PGA gain
SNR for Line_in (digital or
analog) to Spk_out Path
SNR for Mic0 & Mic1 to Digital
Line_out Path
SNR for Mic0 & Mic1 to
Analog Line_out Path
CODEC Sampling Frequency
Input Impedance for
Reference as 0dB full
Mic/Line_in
scale
Load impedance for Line_out /
Spk_out
Min
Typ
2.4
Max
2.4
Unit
Vpp
Vpp
2.2
2.4
2.6
Vpp
1.1
1.2
1.5
77
1.3
Vpp
Vpp
dB
80
dB
72
dB
8
27.5
KHz
kΩ
600
Ω
Table 13: ADC(Mic0/Mic1/Line_in) PGA Gain
Parameter
Gain Range
Step Size
Step Size
Step Size Error
Step Size Error
DS v0.1, Aug08
Condition
Range: -2dB to 0dB
Range: 0dB to 26dB
Range: -2dB to 0dB
Range: 0dB to 26dB
22
Min
-2
-0.5
-1
Typ
1
2
-
Max
26
0.5
1
Unit
dB
dB
dB
dB
dB
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
Table 14: DAC(Line_out, Speaker Out) PGA Gain
Parameter
Gain Range
Step Size
Step Size Error
Condition
Range: -29dB to 2dB
Range: -29dB to 2dB
Min
-29
-0.5
Typ
1
-
Max
2
0.5
Unit
dB
dB
dB
Min
-
Typ
12
20
Max
60
Unit
dB
dB
dB
4.5 DSP Performance Details
Table 15: DSP Performance Details
Parameter
Acoustic Echo Cancellation
Stationary Noise Suppression
Non-stationary Noise
Suppression
Beam-forming angle
Side Tone Cancellation
Acoustic Echo Tail Length
Echo Convergence
Non-stationary Noise
Convergence
Stationary Noise Convergence
Condition
2-mic mode
For Mic0, Mic1
For Mic0 & Mic1 Beamforming
U+O SAM mode*
25
64
2-mic mode
2-mic beam forming
operating mode
1-mic mode
120
30
200
35
100
1.5
º
dB
ms
ms
ms
s
4.6 Timing Characteristics
Table 16: Timing Characteristics
Parameter
Power-down to power-up time
Set parameter timing after
reset
Data delay after parameter
setting
Speaker out delay after
parameter setting
Mic to Line_out delay
Bit clock frequency
FSYNC Setup Time
FSYNC Hold Time
Input Setup Time
Input Hold Time
Digital Output Delay Time
FSYNC Output Delay Time
DS v0.1, Aug08
Symbol
tpdu
tparam
Min.
100
4
Typ.
-
Max.
-
Unit
us
ms
tdata
-
70
-
ms
tspk
-
75
-
ms
128
10
10
10
10
-
54
256
-
1,024
30
30
ms
kHz
ns
ns
ns
ns
ns
ns
tmlo
fbclk
tfs
tfh
tds
tdh
tdd
tfd
Condition
2 mic mode
Output Mode
Output Mode
Output Mode
23
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
tpdu
x
PWD_
tparam
SHI, UART,
EEPROM
x
Set Parameters
tdata
PCM,
Analog Line In
x
tspk
Speaker Out
x
Figure 16: Power-down to Speaker-out Timing
BCLK
tfs
tfh
FSYNC
tds
RX
tdh
MSB
MSB
Figure 17: Digital Input Timing (No Clock Delay)
BCLK
tfs
tfh
FSYNC
tds
RX
tdh
MSB
MSB
Figure 18: Digital Input Timing (One Clock Delay)
DS v0.1, Aug08
24
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
BCLK
tfs
tfh
tfd
FSYNC
tdd
TX
MSB
LSB
Figure 19: Digital Output Timing (No Clock Delay)
BCLK
tfs
tfh
tfd
FSYNC
tdd
TX
MSB
LSB
Figure 20: Digital Output Timing (One Clock Delay)
DS v0.1, Aug08
25
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
5. Pin Definition
Table 17: Pin Number sorted Description
Pin #
Pin Name
1
2
3
4
5
6
7
8
9
10
NC
NC
SPK_OUT_N
NC
NC
NC
VSS_D
BCLK
FSYNC
PCM_OUT
I/O
Type
NC
NC
O
NC
NC
NC
GND
I/O
I/O
I/O
11
PCM_IN
I
12
13
UART_RX
UART_TX
I
I/O
14
ANA_COM
I
15
16
17
SDA_EE
SCL _EE
GPIO7
I/O
I/O
I/O
18
19
20
VSS_D
VDD_D
STRAP0
GND
VDD
I/O
21
MUTE_OUT
I/O
22
VAD_LED
I/O
23
SCL
I/O
DS v0.1, Aug08
Pin Description
No connect
No connect
Speaker output (-)
No connect
No connect
No connect
Digital ground
BCLK signal for Serial Port
Frame sync signal for Serial Port
During power up, used as strap
option (section 7.2); after power
up, transmits voice data to Serial
Port
Receive voice data from Serial
Port
Serial commands from UART port
During power up, used as strap
option (section 7.2); after power
up, transmits serial commands to
UART port
For analog communications mode,
which will bypass DSP (1)
Serial data access for EEPROM
Serial clock for EEPROM
Mode select strap option (section
7.2)
Digital ground
Digital power (2)
During power up, used as strap
option (section 7.2); not used
during normal operation
During power up, used as strap
option (section 7.2); after power
up, serves as output LED to
indicate microphone “mute” status
Must pull low using weak 100K
resistor to select XTAL_IN as PLL
clock source; after power up,
serves as LED output to indicate
internal status for VAD (Voice
Activity Detection) tuning
Serial clock for SHI interface, if
selected; if SHI is not selected,
serves as input pin to select
“earpiece” mode where the speaker
output gain will be reduced to
support earpiece function (3) ; if not
used, pull high using weak 100 kΩ
resistor to be in speaker-phone
26
PowerDown
Status
NC
NC
Tri-State
NC
NC
NC
GND
I
I
I
I
I
I
I
I
In
GND
VDD
I
I
I
I
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
24
SDA/MUTE_IN
I/O
25
Vol-
I/O
26
Vol+
I/O
27
28
29
30
31
32
XTAL_IN
XTAL_OUT
GND_D
PWD_
RST_
TEST1
I
O
GND
I
I
I
33
V10
VDD
mode
Serial data access for SHI
interface, if selected; if SHI is not
selected, serves as input pin to
select “mute” function on the
microphone (4) ; if not used, pull
low using weak 100kΩ resistor
Volume Down input pin (level
triggered, active high); if not used,
pull low using weak 100kΩ
resistor
Volume Up input pin (level
triggered, active high); if not used,
pull low using weak 100K resistor
Crystal input
Crystal output
Digital ground
Power-down pin, active low
Reset pin, active low
Connect a 100kΩ resistor to
ground
connect a 1µF capacitor to ground
and connect a ferrite bead to
VDD_S
No Connect
Power supply
No Connect
connect a 1µF capacitor to ground
Analog Ground for CODEC
Mic0 (+) input
Mic0 (-) input
Mic1 (+) input
Mic1 (-) input
Line_in (+) input
Line_in (-) input
Connect to ground
Connect a 1µF capacitor to ground
Analog output
Speaker output (+)
I
I
I
I
O
GND
I
I
I
VDD
34
NC
NC
NC
35
VDD_S
VDD
VDD
36
NC
NC
NC
37
VREF
VDD
Tri-state
38
VSS_A
GND
GND
39
MIC0_P
I
I
40
MIC0_N
I
I
41
MIC1_P
I
I
42
MIC1_N
I
I
43
LINE_IN_P
I
I
44
LINE_IN_N
I
I
45
VSS_REF
GND
GND
46
BG_REF
I/O
Tri-state
47
LINE_OUT
O
Tri-state
48
SPK_OUT_P
O
Tri-state
Notes:
(1)
active high; when “high,” DSP will be in idle state; DSP will restart on high to low transition
(2)
this separate voltage source is designed to adapt to the level of the digital interface voltage
level; it can either be 1.8V or 3.3V, depending on the interface logic level
(3)
edge triggered, with falling edge to “earpiece” and rising edge to “speaker” mode
(4)
level triggered with active high, and it will toggle between “mute” and “not mute”; the default
after reset is always “not mute”
DS v0.1, Aug08
27
CONFIDENTIAL
FM11-GE-300
Vol-
PWD_
GND_D
XTAL_OUT
XTAL_IN
Vol+
RST_
37
25
FM1182E - G
GE
FM11-GE-300
XXXXX.DD
YWWSV
LQFP
View
LQFP- 48
48 pin
pinTop
Top
View
13
Pin 1
13
SDA/MUTE_IN
SCL
VAD_LED
MUTE_OUT
STRAP0
VDD_D
VSS_D
GPIO7
SCL_EE
SDA_EE
ANA_COM
UART_TX
PCM_OUT
PCM_IN
UART_RX
FSYNC
VSS_D
BCLK
NC
SPK_OUT_N
NC
NC
NC
11
NC
MIC0_N
MIC1_P
MIC1_N
LINE_IN_P
LINE_IN_N
VSS_REF
BG_REF
LINE_OUT
SPK_OUT_P
25
37
VREF
VSS_A
MIC0_P
NC
V10
TEST1
NC
VDD_S
Preliminary Data Sheet
Figure 21: FM-GE-300 Pin Configuration
In
PAD
Weak Latch
Note: The pin status of the pins on power-up will depend on the external pull up or pull down connection. If there is
no external connection, pin status on power-up is unknown.
Figure 22: PAD_IN Symbol for Digital Input Pins
DS v0.1, Aug08
28
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
EN
Out
In
PAD
Weak Latch
Note: The pin status of the pins on power-up will depend on the external pull up or pull down connection. If there is
no external connection, pin status on power-up is unknown.
Figure 23: PAD_BI Symbol for Digital Input/Output Pins
DS v0.1, Aug08
29
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
6. Packaging
LQFP Top View
Wafer lot code
X: internal
G: LQFP
E: Extended Grade
Date code:
D: internal
S: engineering sample
FM11-GE-300
XXXXX.DD
YWWSV
Pin 1
LQFP- 48 pin Top View
LQFP Side View
Note: The third line of the package marking contains date code. “Y” indicates the year and WW indicates the week of the year.
Figure 24: LQFP Packaging Drawings
DS v0.1, Aug08
30
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
7. Ordering Information
Table 18: Ordering Information
Package
48-pin LQFP
Green
Yes
Temperature Grade
Extended (-20 to +70ºC)
Ordering Code
FM11-GE-300
Shipping Method
Tray
Consumer = 0 to 70º degrees C
Extended = -20 to 70º degrees C
NOTE: Fortemedia recommends consuming the devices within 192 hours after opening of the vacuum seal. Devices
still on the reel, which cannot withstand high temperatures, are not recommended for re-baking. For more
information, please refer to the “Handling Precautions” document.
DS v0.1, Aug08
31
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
Appendix I: Required External Components for Operation
Table 19: External Components Recommendation
Microphone Specification
Parameter
Value
Type
Electret Condenser Microphone
Sensitivity
-44 ~ -47 dB (1V/PA)
Operating Voltage
2V (standard)
Impedance
2.2kΩ maximum
External Headphone Driver
An amplifier with 20kΩ input impedance is preferred
Crystal Specification
Parameter
Table Operating Frequency
Resonant Mode
Frequency Tolerance
Aging per Year
Operating Mode
Crystal CO
Crystal RS (ESR)
RS (external)
CL (external load capacitance)
Drive Level
Value
4.096 MHz to 13 MHz
Parallel
+/- 30ppm
+/- 5ppm/yr
Fundamental Mode
< 10 pF
< 150 Ω
330 Ω
16 pF (Xtal spec dependent)
500 µW
FM11-GE-300
To Internal Clock
Circuitry
XTAL_IN
XTAL_OUT
RS
Y1
CL
CL
Figure 25: External XTAL_IN Clock Source
Serial EEPROM (optional)
Fortemedia recommends using a 1.8V serial EEPROM such as 24AA02 (256Byte – small size) or 24AA08
(1KByte – large size).
DS v0.1, Aug08
32
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
Appendix II: Audio Measurement System
Settings
PC microphone: -45dB sensitivity
Speaker:
8W
Table 20: Echo Cancellation Measurement
Parameter
Acoustic Echo Cancellation
Condition
Voice band
83dB @ Mic
Typical
50 to 60dB
By Pass
60cm
Echo Canceller
FM11-GE300
Line_out
Line_in
90dB
30cm
Figure 26: Echo Cancellation Test Setup
Table 21: Noise Suppression Measurement
Parameter
Condition
Stationary Noise
1kHz tone and
Suppression
white noise
Note: Adaptive time is between 1 to 2 seconds
Typical
12dB
FM11-GE-300 Demo Board
110dB
Mic._in
Noise
Canceller
FM11-GE-300
Line_out
30cm
1kHz tone and white noise
Figure 27: Noise Suppression Test Setup
DS v0.1, Aug08
33
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
Appendix III: Suggested External Power Circuitry
FM11-GE-300 requires an external voltage supply of 1.8V for VDD_S. Please see below figure for suggested
circuitry.
Figure 28: Suggested External Power Circuitry
DS v0.1, Aug08
34
CONFIDENTIAL
FM11-GE-300
Preliminary Data Sheet
References
I. Terminology
Table 22: Terminology
Term
ADC
AEC
DAC
DRC
DSP
PA
PGA
PM
PWM
RAM
ROM
SHI
UART
USB
Definition
Analog to Digital
Acoustic echo-cancellation
Digital to Analog
Dynamic range control
Digital Signal Processor
Power Amplifier
Programmable Gain Amplification
Program Memory
Pulse Width Modulation
Random Access Memory
Read Only Memory
Serial Host Interface
Universal Asynchronous Receiver/Transmitter
Universal Serial Bus
II. Related Documents
Table 23: Related Reference Documents
Fortemedia Technology White Paper
FM11-GE-300 Parameters Tuning Guide
FM11-GE-300 SHI Implementation Application Note
DS v0.1, Aug08
Document Location
Contact Fortemedia Sales
Contact Fortemedia Sales
35
CONFIDENTIAL