TI TAS5760MD

DCA-48 (TSSOP)
12.5mm ´ 8.1mm
TAS5760MD
www.ti.com
SLOS741B – MAY 2013 – REVISED JULY 2013
2
General Purpose I S Input Class D Amplifier with DirectPath™ Headphone / Line Driver
Check for Samples: TAS5760MD
FEATURES
1
•
•
•
Audio I/O Configuration:
– Single Stereo I²S Input
– Stereo Bridge Tied Load (BTL) or Mono
Parallel Bridge Tied Load (PBTL) Operation
– 32, 44.1, 48, 88.2, 96 kHz Sample Rates
– Headphone Amplifier / Line Driver
General Operational Features:
– Selectable Hardware or Software Control
– Integrated Digital Output Clipper
– Programmable I²C Address (1101100[R/W] or
1101101[R/W])
– Closed Loop Amplifier Architecture
– Adjustable Switching Frequency for
Speaker Amplifier
Robustness Features:
– Clock Error, DC and Short Circuit
Protection
– Over Temperature and Programmable
Overcurrent Protection
Audio Performance (PVDD = 19V, RSPK = 8Ω,
SPK_GAIN[1:0] Pins = 01)
– Idle Channel Noise = <80 µVrms (A-Wtd)
DVDD
Internal
Voltage
Supplies
DRVDD
ANA_REG
APPLICATIONS
•
•
•
LCD/LED TV and Multi-Purpose Monitors
Sound Bars, Docking Stations, PC Audio
General Purpose Audio Equipment
Power at 10% THD+N vs PVDD
50
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
4 Ω Thermal Limit
6 Ω Thermal Limit
8 Ω Thermal Limit
45
40
35
30
25
20
15
10
5
0
THD+N = 10%
4
8
10
PVDD
Internal Reference
Regulators
DRVDD
6
12 14 16 18
Supply Voltage (V)
20
22
24
26
G001
NOTE: Thermal Limits were determined via the
TAS5760xxEVM
AVDD
GVDD_REG
Internal Gate
Drive Regulator
Closed Loop Class D Amplifier
SFT_CLIP
MCLK
SCLK
LRCK
SDIN
– THD+N = 0.03 % (at 1 W, 1 kHz)
– SNR = 100 dB A-Wtd (Ref. to THD+N = 1%)
Maximum Output Power (W)
•
23
Serial
Audio
Port
Digital
Boost
&
Volume
Control
Digital to
PWM
Conversion
Digital
Clipper
Soft
Clipper
Analog
Gain
Gate
Drives
Gate
Drives
Full Bridge
Power Stage
A
SPK_OUTA+
OverCurrent
Protection
Full Bridge
Power Stage
B
SPK_OUTASPK_OUTB+
SPK_OUTB-
Clock Monitoring
DRVDD
DR_INA+
DR_INADR_INB+
DR_INB-
DirectPathTM Ground
Centered Headphone /
Line Driver
DR_OUTA
DR_OUTB
Charge Pump
DRVSS DR_CP DR_CN
Die
Temp. Monitor
Internal Control Registers and State Machines
PBTL/ SPK_GAIN0 SPK_GAIN1 SPK_SD SPK_FAULT SPK_SLEEP/ FREQ/
ADR
SDA
SCL
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DirectPath is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TAS5760MD
SLOS741B – MAY 2013 – REVISED JULY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The TAS5760MD is a stereo I2S input device which includes hardware and software (I²C) control modes,
integrated digital clipper, several gain options, and a wide power supply operating range to enable use in a
multitude of applications. The TAS5760MD operates with a nominal supply voltage from 4.5 to 24 VDC. The
device has an integrated DirectPath™ headphone amplifier / line driver to increase system level integration and
reduce total solution costs.
An optimal mix of thermal performance and device cost is provided in the 120 mΩ RDS(ON) of the output
MOSFETs. Additionally, a thermally enhanced 48-Pin TSSOP provides excellent operation in the elevated
ambient temperatures found in modern consumer electronic devices.
The entire TAS5760xx family is pin to pin compatible in the 48-Pin TSSOP package. Alternatively, to achieve the
smallest possible solutions size for applications where pin to pin compatibility and a headphone or line driver are
not required, a 32-Pin TSSOP package is offered for the TAS5760M and TAS5760L devices. The I2C register
map in all of the TAS5760xx family is identical, to ensure low development overhead when choosing between
devices based upon system level requirements.
TAS5760xx FAMILY INFORMATION
Device
Description
Package
TAS5760MDDCA
Flexible, general purpose I²S input class D Amplifier with
integrated headphone / line driver and integrated digital clipper,
which supports PVDD levels ≤ 24 V
48 Pin, 0.5mm Lead-Pitch, Pad-down TSSOP
(DCA)
TAS5760MDCA
TAS5760MDAP
TAS5760LDDCA
Flexible, general purpose I²S input class D Amplifier with
integrated digital clipper, which supports PVDD levels ≤ 24 V
Flexible, general purpose I²S input class D Amplifier with
integrated headphone / line driver and integrated digital clipper,
which supports PVDD levels ≤ 15V
TAS5760LDCA
TAS5760LDAP
Flexible, general purpose I²S input class D Amplifier with
integrated digital clipper, which supports PVDD levels ≤ 15V
2
48 Pin, 0.5mm Lead-Pitch, Pad-down TSSOP
(DCA)
32 Pin, 0.65mm Lead Pitch, Pad-down TSSOP
(DAP)
48 Pin, 0.5mm Lead-Pitch, Pad-down TSSOP
(DCA)
48 Pin, 0.5mm Lead-Pitch, Pad-down TSSOP
(DCA)
32 Pin, 0.65mm Lead Pitch, Pad-down TSSOP
(DAP)
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
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SLOS741B – MAY 2013 – REVISED JULY 2013
PINOUT AND PIN DESCRIPTIONS
TSSOP PACKAGE
DCA-48
(TOP VIEW)
SFT_CLIP
ANA_REG
VCOM
ANA_REF
SPK_FAULT
SPK_SD
FREQ/SDA
PBTL/SCL
DVDD
SPK_GAIN0
SPK_GAIN1
SPK_SLEEP/ADR
MCLK
SCLK
SDIN
LRCK
DGND
DR_INADR_INA+
DR_OUTA
DRGND
DR_MUTE
DRVSS
DR_CN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PowerPAD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GVDD_REG
GGND
AVDD
PVDD
PVDD
BSTRPA+
SPK_OUTA+
PGND
SPK_OUTABSTRPABSTRPBSPK_OUTBPGND
SPK_OUTB+
BSTRPB+
PVDD
PVDD
DR_INBDR_INB+
DR_OUTB
DR_UVE
DRGND
DRVDD
DR_CP
Pin Descriptions
TAS5760MD
Name
No.
Type
Internal
Termination
Description
AVDD
46
P
-
Power supply for internal analog circuitry
ANA_REF
4
P
-
Connection point for internal reference used by ANA_REG and VCOM filter capacitors.
ANA_REG
2
P
-
Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection
point for filtering capacitors for this supply and must not be used to power any external circuitry)
BSTRPA-
39
P
-
Connection point for the SPK_OUTA- bootstrap capacitor, which is used to create a power
supply for the high-side gate drive for SPK_OUTA-
BSTRPA+
43
P
-
Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to create a power
supply for the high-side gate drive for SPK_OUTA+
BSTRPB-
38
P
-
Connection point for the SPK_OUTB- bootstrap capacitor, which is used to create a power
supply for the high-side gate drive for SPK_OUTB-
BSTRPB+
34
P
-
Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to create a power
supply for the high-side gate drive for SPK_OUTB+
DGND
17
G
-
Ground for digital circuitry (NOTE: This terminal should be connected to the system ground)
DR_CN
24
P
-
Negative terminal for capacitor connection used in headphone amplifier/line driver charge pump
DR_CP
25
P
-
Positive terminal for capacitor connection used in headphone amplifier/line driver charge pump
DR_INA-
18
AI
-
Negative differential input for channel A of headphone amplifier/line driver
DR_INA+
19
AI
-
Positive differential input for channel A of headphone amplifier/line driver
DR_INB-
31
AI
-
Negative differential input for channel B of headphone amplifier/line driver
DR_INB+
30
AI
-
Positive differential input for channel B of headphone amplifier/line driver
DR_MUTE
22
DI
-
Places the headphone amplifier/line driver in mute
DR_OUTA
20
AO
-
Output for channel A of headphone amplifier/line driver
DR_OUTB
29
AO
-
Output for channel B of headphone amplifier/line driver
DR_UVE
28
AI
-
Sense pin for under-voltage protection circuit for the headphone amplifier/line driver
DR_VSS
23
P
-
Negative power supply generated by charge pump from the DRVDD supply for ground centered
headphone/line driver output
DRGND
21
G
-
Ground for headphone amplifier/line driver circuitry (NOTE: This terminal should be connected to
the system ground)
3
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
SLOS741B – MAY 2013 – REVISED JULY 2013
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Pin Descriptions (continued)
TAS5760MD
No.
Type
Internal
Termination
Description
DRGND
27
G
-
Ground for headphone amplifier/line driver circuitry (NOTE: This terminal should be connected to
the system ground)
DRVDD
26
P
-
Power supply for internal headphone/line driver circuitry
DVDD
9
P
-
Power supply for the internal digital circuitry
Name
FREQ/SDA
7
DI
Weak PullDown
GGND
47
G
-
Ground for gate drive circuitry (NOTE: This terminal should be connected to the system ground)
GVDD_REG
48
P
-
Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a connection
point for filtering capacitors for this supply and must not be used to power any external circuitry)
LRCK
16
DI
Weak PullDown
Serial Audio Port Word Clock. Word select clock for the digital signal that is active on the serial
port's input data line
MCLK
13
DI
Weak PullDown
Master Clock used for internal clock tree, sub-circuit/state machine, and Serial Audio Port
clocking
PBTL/SCL
8
DI
Weak PullDown
Dual function terminal that functions as an I²C clock input terminal in Software Control Mode or
configures the device to operate in pre-filter Parallel Bridge Tied Load (PBTL) mode when in
Hardware Control Mode
PGND
36, 41
G
-
Ground for power device circuitry (NOTE: This terminal should be connected to the system
ground)
PVDD
32, 33,
44, 45
P
-
Power supply for interal power circuitry
SCLK
14
DI
Weak PullDown
Serial Audio Port Bit Clock. Bit clock for the digital signal that is active on the serial data port's
input data line
SDIN
15
DI
Weak PullDown
Serial Audio Port Serial Data In. Data line to the serial data port
SFT_CLIP
1
AI
-
SPK_FAULT
5
DO
Open-Drain
Speaker amplifier fault terminal, which is pulled "LOW" when an internal fault occurs
Adjusts the LSB of the multi-bit gain of the speaker amplifier
Adjusts the MSB of the multi-bit gain of the speaker amplifier
SPK_GAIN0
10
DI
Weak PullDown
SPK_GAIN1
11
DI
Weak PullDown
SPK_SLEEP/ADR
12
DI
Weak Pull-Up
Dual function terminal that functions as an I²C data input terminal in I²C Control Mode or as a
Frequency Select terminal when in Hardware Control Mode.
Sense pin which sets the maximum output voltage before clipping when the soft clipper circuit is
active
In Hardware Control Mode, places the speaker amplifier in sleep mode. In Software Control
Mode, is used to determine the I²C Address of the device
SPK_OUTA-
40
AO
-
Negative terminal for differential speaker amplifier output "A"
SPK_OUTA+
42
AO
-
Positive terminal for differential speaker amplifier output "A"
SPK_OUTB-
37
AO
-
Negative terminal for differential speaker amplifier output "B"
SPK_OUTB+
35
AO
-
Positive terminal for differential speaker amplifier output "B"
SPK_SD
6
AO
-
Places the speaker amplifier in shutdown
VCOM
3
P
-
Bias voltage for internal PWM conversion block
PowerPAD™
-
G
-
Provides both electrical and thermal connection from the device to the board. A matching ground
pad must be provided on the PCB and the device connected to it via solder. For proper electrical
operation, this ground pad must be connected to the system ground.
4
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
www.ti.com
SLOS741B – MAY 2013 – REVISED JULY 2013
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Parameter
Min
Max
Unit
Ambient Operating Temperature, TA
–25
85
°C
Ambient Storage Temperature, TS
–40
125
°C
AVDD Supply
–0.3
30
V
PVDD Supply
–0.3
30
V
DRVDD and DVDD Supply
–0.3
4
V
DVDD Referenced Digital
Input Voltages
Digital Inputs referenced to DVDD supply
-0.5
DVDD + 0.5
V
DRVDD Referenced Digital
Input Voltages
Digital Inputs referenced to DRVDD supply
-0.5
DRVDD + 0.5
V
Headphone Load
RHP
12.8
-
Ω
Line Driver Load
RLD
600
-
Ω
Speaker Amplifier Output
Voltage
VSPK_OUTxx, measured at the output pin
-0.3
32
V
Temperature
Supply Voltage
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
TAS5760MD
THERMAL METRIC (1)
48 Pin DCA (1)
48 Pin DCA (2)
UNIT
θJA
Junction-to-ambient thermal resistance
60.3
30.2
°C/W
θJC(bottom)
Junction-to-case (bottom) thermal resistance
16.0
14.3
°C/W
θJB
Junction-to-board thermal resistance
12.0
12.7
°C/W
ψJT
Junction-to-top characterization parameter
0.4
0.6
°C/W
ψJB
Junction-to-board characterization parameter
11.9
12.7
°C/W
θJC(top)
Junction-to-case (top) thermal resistance
0.8
0.7
°C/W
(1)
(2)
JEDEC Standard 2 Layer Board
JEDEC Standard 4 Layer Board
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
Min
Typ
Max
Unit
TA
Ambient Operating Temperature
Parameter
Test Conditions
–25
-
85
°C
AVDD
AVDD Supply
4.5
-
26.4
V
PVDD
PVDD Supply
4.5
-
26.4
V
DRVDD,
DVDD
DRVDD and DVDD Supply
2.8
-
3.63
V
VIH(DR)
Input Logic "HIGH" for DVDD and DRVDD
Referenced Digital Inputs
-
DVDD
-
V
VIL(DR)
Input Logic "LOW" for DVDD and DRVDD
Referenced Digital Inputs
-
0
-
V
RHP
Headphone Load
16
-
-
Ω
RLD
Line Driver Load
1k
-
-
Ω
RSPK
(BTL)
Minimum Speaker Load in BTL Mode
4
-
-
Ω
RSPK
(PBTL)
Minimum Speaker Load in PBTL Mode
2
-
-
Ω
5
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
SLOS741B – MAY 2013 – REVISED JULY 2013
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ELECTRICAL SPECIFICATIONS AND CHARACTERISTICS
DIGITAL I/O PINS
over operating free-air temperature range (unless otherwise noted)
Min
Typ
Max
Unit
VIH1
Input Logic "HIGH" threshold for DVDD
Referenced Digital Inputs
Parameter
All digital pins except for
DR_MUTE
Test Conditions
70
-
-
%DVDD
VIL1
Input Logic "LOW" threshold for DVDD
Referenced Digital Inputs
All digital pins except for
DR_MUTE
-
-
30
%DVDD
|IIH|1
Input Logic "HIGH" Current Level
All digital pins except for
DR_MUTE
-
-
15
µA
|IIL|1
Input Logic "LOW" Current Level
All digital pins except for
DR_MUTE
-
-
-15
µA
VOH
Output Logic "HIGH" Voltage Level
IOH = 2 mA
90
-
-
%DVDD
VOL
Output Logic "LOW" Voltage Level
IOH = -2 mA
-
-
10
%DVDD
VIH2
Input Logic "HIGH" threshold for DRVDD
For DR_MUTE Pin
Referenced Digital Inputs
-
60
-
%DRVDD
VIL2
Input Logic "LOW" threshold for DRVDD
Referenced Digital Inputs
For DR_MUTE Pin
-
40
-
%DRVDD
|IIH|2
Input Logic "HIGH" Current Level
For DR_MUTE Pin
-
-
1
µA
|IIL|2
Input Logic "LOW" Current Level
For DR_MUTE Pin
-
-
-1
µA
Min
Typ
Max
Unit
45
50
55
%
128
-
512
x fS
Unit
MASTER CLOCK
over operating free-air temperature range (unless otherwise noted)
Parameter
DMCLK
Allowable MCLK Duty Cycle
fMCLK
Supported MCLK Frequencies
Test Conditions
Values include: 128, 192, 256,
384, 512.
SERIAL AUDIO PORT
over operating free-air temperature range (unless otherwise noted)
Min
Typ
Max
Allowable SCLK Duty Cycle
Parameter
45
50
55
%
Required LRCK to SCLK Rising Edge
15
-
-
ns
Required SDIN Hold Time after SCLK
Rising Edge
15
-
-
ns
tsu
Required SDIN Setup Time before SCLK
Rising Edge
15
-
-
ns
fS
Supported Input Sample Rates
Sample rates above 48kHz
supported by "double speed
mode," which is activated
through the I²C control port
32
-
96
kHz
fSCLK
Supported SCLK Frequencies
Values include: 32, 48, 64
32
-
64
x fS
DSCLK
tHLD
Test Conditions
6
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
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SLOS741B – MAY 2013 – REVISED JULY 2013
PROTECTION CIRCUITRY
over operating free-air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
OVERTHRES(PVDD)
PVDD Over-Voltage Error Threshold
PVDD Rising
-
28
-
V
OVEFTHRES(PVDD)
PVDD Over-Voltage Error Threshold
PVDD Falling
-
27.3
-
V
UVEFTHRES(PVDD)
PVDD Under-Voltage Error (UVE)
Threshold
PVDD Falling
-
3.95
-
V
UVERTHRES(PVDD)
PVDD UVE Threshold (PVDD Rising)
PVDD Rising
-
4.15
-
V
OTETHRES
Over-Temperature Error (OTE)
Threshold
-
150
-
°C
OTEHYST
Over-Temperature Error (OTE)
Hysteresis
-
15
-
°C
7
-
A
OCETHRES
Over-Current Error (OCE) Threshold
for each BTL Output
PVDD= 15V, TA = 25 °C
-
DCETHRES
DC Error (DCE) Threshold
PVDD= 12V, TA = 25 °C
-
2.6
-
V
TSPK_FAULT
Speaker Amplifier Fault Time Out
period
DC Detect Error
-
650
-
ms
UVETHRES(DRVDD)
ILIMIT(DR)
OTE or OCP Fault
Under-Voltage Error (UVE) Threshold
for headphone / line driver amplifier
1.3
Sensed on DR_UVE pin
Current Sourcing Limit of the
Headphone / Line Driver Amplifier
s
-
1.25
-
V
-
68
-
mA
SPEAKER AMPLIFIER IN ALL MODES
over operating free-air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
-
25.2
-
dBV
AV00
Speaker Amplifier Gain with
SPK_GAIN[1:0] Pins = 00
Hardware Control Mode
(Additional gain settings
available in Software Control
Mode) (1)
AV01
Speaker Amplifier Gain with
SPK_GAIN[1:0] Pins = 01
Hardware Control Mode
(Additional gain settings
available in Software Control
Mode) (1)
-
28.6
-
dBV
AV10
Speaker Amplifier Gain with
SPK_GAIN[1:0] Pins = 10
Hardware Control Mode
(Additional gain settings
available in Software Control
Mode) (1)
-
30
-
dBV
AV11
Speaker Amplifier Gain with
SPK_GAIN[1:0] Pins = 11
(This setting places the device
in Software Control Mode)
-
(Set via
I²C)
-
-
BTL, Worst case over voltage,
gain settings
-
-
10
mV
PBTL, Worst case over voltage,
gain settings
-
-
15
mV
|VOS|(SPK_
Speaker Amplifier DC Offset
AMP)
fSPK_AMP(0)
Speaker Amplifier Switching Frequency
when PWM_FREQ Pin = 0
(Hardware Control Mode.
Additional switching rates
available in Software Control
Mode.)
-
16
-
x fS
fSPK_AMP(1)
Speaker Amplifier Switching Frequency
when PWM_FREQ Pin = 1
(Hardware Control Mode.
Additional switching rates
available in Software Control
Mode.)
-
8
-
x fS
PVDD = 15 V, TA = 25 °C, Die
Only
-
120
-
mΩ
PVDD= 15V, TA = 25 °C,
Includes: Die, Bond Wires,
Leadframe
-
150
-
mΩ
RDS(ON)
(1)
On Resistance of Output MOSFET (both
high-side and low-side)
The digital boost block contributes +6dB of gain to this value. The audio signal must be kept below -6dB to avoid clipping the digital
audio path.
7
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
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SLOS741B – MAY 2013 – REVISED JULY 2013
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SPEAKER AMPLIFIER IN ALL MODES (continued)
over operating free-air temperature range (unless otherwise noted)
Parameter
fC
Test Conditions
-3dB Corner Frequency of High-Pass
Filter
Min
Typ
Max
fS = 44.1 kHz
-
3.7
-
fS = 48 kHz
-
4
-
fS = 88.2 kHz
-
7.4
-
fS = 96 kHz
-
8
-
Unit
Hz
SPEAKER AMPLIFIER IN STEREO BRIDGE TIED LOAD (BTL) MODE
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
Parameter
ICN(SPK)
Po(SPK)
Idle Channel Noise
Maximum Instantaneous
Output Power Per. Ch.
Min
Typ
Max
Unit
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, A-Weighted
Test Conditions
-
66
-
µVrms
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted
-
75
-
µVrms
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted
-
79
-
µVrms
PVDD = 24 V, SPK_GAIN[1:0] Pins =10,
RSPK = 8Ω, A-Weighted
-
120
-
µVrms
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 4Ω, THD+N = 0.1%,
-
14.2
-
W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, THD+N = 0.1%
-
8
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%,
-
21.9
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%
-
12.5
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%,
-
33.5
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%
-
20
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 4Ω, THD+N = 0.1%,
-
55.2
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 8Ω, THD+N = 0.1%
-
31.8
-
W
8
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
www.ti.com
SLOS741B – MAY 2013 – REVISED JULY 2013
SPEAKER AMPLIFIER IN STEREO BRIDGE TIED LOAD (BTL) MODE (continued)
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
Parameter
Po(SPK)
SNR(SPK)
THD+N(SPK)
(1)
Maximum Continuous
Output Power Per. Ch. (1)
Signal to Noise Ratio
(Referenced to THD+N =
1%)
Total Harmonic Distortion
and Noise
Test Conditions
Min
Typ
Max
Unit
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 4Ω, THD+N = 0.1%,
-
14
-
W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, THD+N = 0.1%
-
8
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%,
-
13.25
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%
-
12.5
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%,
-
12.25
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%
-
20
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 4Ω, THD+N = 0.1%,
-
11
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 8Ω, THD+N = 0.1%
-
24
-
W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, A-Weighted, -60dBFS Input
-
99.7
-
dB
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted, -60dBFS Input
-
98.2
-
dB
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted, -60dBFS Input
-
100.4
-
dB
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 8Ω, A-Weighted, -60dBFS Input
-
98.8
-
dB
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 4Ω, Po = 1 W
-
0.02
-
%
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, Po = 1 W
-
0.03
-
%
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, Po = 1 W
-
0.03
-
%
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, Po = 1 W
-
0.03
-
%
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, Po = 1 W
-
0.03
-
%
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, Po = 1 W
-
0.04
-
%
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 4Ω, Po = 1 W
-
0.03
-
%
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 8Ω, Po = 1 W
-
0.04
-
%
The continuous power output of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on
it by the system around it, such as the PCB configuration and the ambient operating temperature. The performance characteristics listed
in this section are achievable on the TAS5760MD's EVM, which is representative of the poplular "2 Layers / 1oz Copper" PCB
configuration in a size that is representative of the amount of area often provided to the amplifier section of popular consumer audio
electronics. As can be seen in the instantaneous power portion of this table, more power can be delivered from the TAS5760MD if steps
are taken to pull more heat out of the device. For instance, using a board with more layers or adding a small heatsink will result in an
increase of continuous power, up to and including the instantaneous power level. This behavior can also been seen in the POUT vs.
PVDD plots shown in the typical performance plots section of this data sheet.
9
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
SLOS741B – MAY 2013 – REVISED JULY 2013
www.ti.com
SPEAKER AMPLIFIER IN STEREO BRIDGE TIED LOAD (BTL) MODE (continued)
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
Parameter
X-Talk(SPK)
Cross-talk (worst case
between LtoR and RtoL
coupling)
Test Conditions
Min
Typ
Max
Unit
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, Input Signal 250 mVrms, 1kHz
Sine
-
-92
-
dB
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, Input Signal 250 mVrms, 1kHz
Sine
-
-93
-
dB
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, Input Signal 250 mVrms, 1kHz
Sine
-
-94
-
dB
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 8Ω, Input Signal 250 mVrms, 1kHz
Sine
-
-93
-
dB
10
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
www.ti.com
SLOS741B – MAY 2013 – REVISED JULY 2013
SPEAKER AMPLIFIER IN MONO PARALLEL BRIDGE TIED LOAD (PBTL) MODE
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
-
69
-
µVrms
-
85
-
µVrms
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted
-
85
-
µVrms
PVDD = 24 V, SPK_GAIN[1:0] Pins =10,
RSPK = 8Ω, A-Weighted
-
131
-
µVrms
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 2Ω, THD+N = 0.1%,
-
28.6
-
W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 4Ω, THD+N = 0.1%,
-
15.9
-
W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, THD+N = 0.1%
-
8.4
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 2Ω, THD+N = 0.1%,
-
43.2
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%,
-
25
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%
-
13.3
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 2Ω, THD+N = 0.1%,
-
68.3
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%,
-
40
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%
-
21.3
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 2Ω, THD+N = 0.1%,
-
114.7
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 4Ω, THD+N = 0.1%,
-
63.5
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 8Ω, THD+N = 0.1%
-
34.1
-
W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, A-Weighted
ICN
PO(SPK)
Idle Channel Noise
Maximum Instantaneous Output
Power
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted
11
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
SLOS741B – MAY 2013 – REVISED JULY 2013
www.ti.com
SPEAKER AMPLIFIER IN MONO PARALLEL BRIDGE TIED LOAD (PBTL) MODE (continued)
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
Parameter
PO(SPK)
SNR
Maximum Continuous Output
Power (1)
Signal to Noise Ratio (Referenced
to THD+N = 1%)
Min
Typ
Max
Unit
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 2Ω, THD+N = 0.1%,
Test Conditions
-
30
-
W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 4Ω, THD+N = 0.1%,
-
15.9
-
W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, THD+N = 0.1%
-
8.4
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 2Ω, THD+N = 0.1%,
-
28.5
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%,
-
25
-
W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%
-
13.3
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 2Ω, THD+N = 0.1%,
-
26.5
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%,
-
40
-
W
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%
-
21.3
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 2Ω, THD+N = 0.1%,
-
24
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 4Ω, THD+N = 0.1%,
-
40
-
W
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 8Ω, THD+N = 0.1%
-
34.1
-
W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, A-Weighted, -60dBFS Input
-
100.4
-
dB
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted, -60dBFS Input
-
99.5
-
dB
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted, -60dBFS Input
-
100.1
-
dB
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 8Ω, A-Weighted, -60dBFS Input
-
99.5
-
dB
(1)
The continuous power output of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on
it by the system around it, such as the PCB configuration and the ambient operating temperature. The performance characteristics listed
in this section are achievable on the TAS5760MD's EVM, which is representative of the poplular "2 Layers / 1oz Copper" PCB
configuration in a size that is representative of the amount of area often provided to the amplifier section of popular consumer audio
electronics. As can be seen in the instantaneous power portion of this table, more power can be delivered from the TAS5760MD if steps
are taken to pull more heat out of the device. For instance, using a board with more layers or adding a small heatsink will result in an
increase of continuous power, up to and including the instantaneous power level. This behavior can also been seen in the POUT vs.
PVDD plots shown in the typical performance plots section of this data sheet.
12
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
www.ti.com
SLOS741B – MAY 2013 – REVISED JULY 2013
SPEAKER AMPLIFIER IN MONO PARALLEL BRIDGE TIED LOAD (PBTL) MODE (continued)
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
Parameter
THD+N(SPK)
Total Harmonic Distortion and
Noise
Min
Typ
Max
Unit
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 2Ω, Po = 1 W
Test Conditions
-
0.03
-
%
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 4Ω, Po = 1 W
-
0.02
-
%
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, Po = 1 W
-
0.02
-
%
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 2Ω, Po = 1 W
-
0.03
-
%
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, Po = 1 W
-
0.02
-
%
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, Po = 1 W
-
0.02
-
%
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 2Ω, Po = 1 W
-
0.03
-
%
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, Po = 1 W
-
0.02
-
%
PVDD = 19 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, Po = 1 W
-
0.03
-
%
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 2Ω, Po = 1 W
-
0.03
-
%
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 4Ω, Po = 1 W
-
0.02
-
%
PVDD = 24 V, SPK_GAIN[1:0] Pins = 10,
RSPK = 8Ω, Po = 1 W
-
0.03
-
%
HEADPHONE AMPLIFIER / LINE DRIVER
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
Min
Typ
Max
Unit
Input to Output Attenuation when muted
Parameter
Test Conditions
-
80
-
dB
|VOS|(DR)
Output Offset Voltage of Headphone
Amplifier and Line Driver
-
0.5
-
mV
fCP
Charge Pump Switching Frequency
200
300
400
kHz
ICN(HP)
Idle Channel Noise
R(HP) = 32 Ω, A-Weighted
-
13
-
µVrms
ICN(LD)
Idle Channel Noise
R(LD) = 3 kΩ, A-Weighted
-
11
-
µVrms
Headphone Amplifier Output Power
R(HP) = 16 Ω, THD+N = 1%,
Outputs in Phase
-
40
-
mW
-
80
-
dB
Po(HP)
PSRR(DR)
Power Supply Rejection Ratio of
Headphone Amplifier and Line Driver
SNR(HP)
Signal to Noise Ratio
(Referenced to 25 mW Output
Signal), R(HP) = 16 Ω, AWeighted
-
96
-
dB
SNR(LD)
Signal to Noise Ratio
(Referenced to 2 Vrms Output
Signal), R(LD) = 3 kΩ, AWeighted
90
105
-
dB
THD+N(HP)
Total Harmonic Distortion and Noise for
the Headphone Amplifier
PO(HP) = 10 mW
-
0.01
-
%
THD+N(LD)
Total Harmonic Distortion and Noise for
the Line Driver
VO(LD) = 2 Vrms
-
0.002
-
%
Line Driver Output Voltage
THD+N = 1%, R(LD) = 3kΩ,
Outputs in Phase
2
2.4
-
Vrms
X-Talk(HP)
Cross-talk (worst case between LtoR
and RtoL coupling)
PO(HP) = 20 mW
-
-90
-
dB
X-Talk(LD)
Cross-talk (worst case between LtoR
and RtoL coupling)
Vo = 1 Vrms
-
-111
-
dB
Output Impedance when muted
DR_MUTE = "LOW"
-
110
-
mΩ
Vo(LD)
ZO(DR)
13
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
SLOS741B – MAY 2013 – REVISED JULY 2013
www.ti.com
HEADPHONE AMPLIFIER / LINE DRIVER (continued)
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
-
12
-
mA
IMUTE(DR)
Current drawn from DRVDD supply in
mute
IDRVDD(HP)
Current drawn from DRVDD supply with DR_MUTE = "HIGH", PO(HP) =
headphone
25 mW, Input = 1kHz
-
60
-
mA
IDRVDD(LD)
Current drawn from DRVDD supply with DR_MUTE = "HIGH", VO(LD) =
line driver
2 Vrms, Input = 1kHz
-
12
-
mA
Min
Typ
Max
Units
-
-
400
pF
-
-
400
kHz
1.3
-
-
µS
DR_MUTE = "LOW"
I²C CONTROL PORT
specifications are over operating free-air temperature range (unless otherwise noted)
Parameter
CL(I²C)
Allowable Load Capacitance for Each I²C
Line
fSCL
Support SCL frequency
tbuf
Bus Free time between stop and start
conditions
tf(I²C)
Test Conditions
No Wait States
Rise Time, SCL and SDA
-
-
300
ns
th1(I²C)
Hold Time, SCL to SDA
0
-
-
ns
th2(I²C)
Hold Time, start condition to SCL
0.6
-
-
µs
I²C Startup Time
-
-
12
mS
tr(I²C)
Rise Time, SCL and SDA
-
-
300
ns
tsu1(I²C)
Setup Time, SDA to SCL
100
-
-
ns
tsu2(I²C)
Setup Time, SCL to start condition
0.6
-
-
µS
tsu3(I²C)
Setup Time, SCL to stop condition
0.6
-
-
µS
Tw(H)
Required Pulse Duration, SCL High
0.6
-
-
µS
Tw(L)
Required Pulse Duration, SCL "LOW"
1.3
-
-
µS
tI²C(start)
14
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
www.ti.com
SLOS741B – MAY 2013 – REVISED JULY 2013
TYPICAL IDLE, MUTE, SHUTDOWN, OPERATIONAL POWER CONSUMPTION
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
VPVDD
[V]
RSPK
[Ω]
Speaker Amplifier State
4
Idle
8
4
8
4
Mute
fSPK_AMP =
384kHz
Sleep
8
4
Shutdown
8
4
Idle
8
4
6
8
4
Mute
fSPK_AMP =
768kHz
Sleep
8
4
Shutdown
8
4
Idle
8
4
8
4
8
4
8
Mute
fSPK_AMP =
1152kHz
Sleep
Shutdown
IPVDD+AVDD
[mA]
IDVDD
[mA]
PDISS
[W]
23.48
3.73
0.15
23.44
3.72
0.15
23.53
3.72
0.15
23.46
3.72
0.15
13.26
0.48
0.08
13.27
0.53
0.08
0.046
0.04
0
0.046
0.03
0
30.94
3.71
0.2
30.94
3.71
0.2
29.37
3.71
0.19
29.39
3.71
0.19
13.24
0.5
0.08
13.23
0.52
0.08
0.046
0.03
0
0.046
0.03
0
39.39
3.7
0.25
39.43
3.7
0.25
36.91
3.7
0.23
36.9
3.69
0.23
13.17
0.53
0.08
13.13
0.45
0.08
0.046
0.03
0
0.046
0.03
0
15
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
SLOS741B – MAY 2013 – REVISED JULY 2013
www.ti.com
TYPICAL IDLE, MUTE, SHUTDOWN, OPERATIONAL POWER CONSUMPTION (continued)
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
VPVDD
[V]
RSPK
[Ω]
Speaker Amplifier State
4
Idle
8
4
8
4
Mute
fSPK_AMP =
384kHz
Sleep
8
4
Shutdown
8
4
Idle
8
4
12
8
4
Mute
fSPK_AMP =
768kHz
Sleep
8
4
Shutdown
8
4
4
4
8
4
8
IDVDD
[mA]
PDISS
[W]
32.95
3.74
0.41
32.93
3.73
0.41
32.98
3.73
0.41
32.97
3.73
0.41
12.71
0.47
0.15
12.75
0.5
0.15
0.053
0.04
0
0.053
0.04
0
44.84
3.73
0.55
44.82
3.73
0.55
42.71
3.72
0.52
42.66
3.72
0.52
12.71
0.49
0.15
12.73
0.52
0.15
0.063
0.03
0
0.053
0.03
0
59.3
3.73
0.72
59.3
3.73
0.72
55.74
3.72
0.68
55.74
3.72
0.68
12.67
0.49
0.15
12.61
0.43
0.15
0.053
0.02
0
0.053
0.03
0
Idle
8
8
IPVDD+AVDD
[mA]
Mute
fSPK_AMP =
1152kHz
Sleep
Shutdown
16
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
www.ti.com
SLOS741B – MAY 2013 – REVISED JULY 2013
TYPICAL IDLE, MUTE, SHUTDOWN, OPERATIONAL POWER CONSUMPTION (continued)
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
VPVDD
[V]
RSPK
[Ω]
Speaker Amplifier State
4
Idle
8
4
8
4
Mute
fSPK_AMP =
384kHz
Sleep
8
4
Shutdown
8
4
Idle
8
4
19
8
4
Mute
fSPK_AMP =
768kHz
Sleep
8
4
Shutdown
8
4
Idle
8
4
8
4
8
4
8
Mute
fSPK_AMP =
1152kHz
Sleep
Shudown
IPVDD+AVDD
[mA]
IDVDD
[mA]
PDISS
[W]
42
3.73
0.81
41.92
3.73
0.81
41.93
3.73
0.81
41.97
3.72
0.81
12.95
0.47
0.25
13
0.52
0.25
0.072
0.04
0
0.072
0.03
0
55.86
3.73
1.07
55.82
3.73
1.07
51.72
3.72
0.99
51.69
3.72
0.99
12.96
0.47
0.25
12.95
0.51
0.25
0.072
0.03
0
0.062
0.03
0
74.87
3.72
1.43
74.81
3.72
1.43
67.96
3.71
1.3
67.91
3.71
1.3
12.94
0.51
0.25
12.84
0.42
0.25
0.062
0.03
0
0.062
0.03
0
17
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TYPICAL IDLE, MUTE, SHUTDOWN, OPERATIONAL POWER CONSUMPTION (continued)
input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
VPVDD
[V]
RSPK
[Ω]
IPVDD+AVDD
[mA]
IDVDD
[mA]
PDISS
[W]
48.03
3.73
1.17
47.98
3.73
1.16
Mute
47.99
3.72
1.16
48
3.72
1.16
Sleep
13.12
0.49
0.32
13.14
0.48
0.32
0
Speaker Amplifier State
4
Idle
8
4
8
4
fSPK_AMP =
384kHz
8
4
0.088
0.03
8
Shutdown
0.088
0.03
0
4
62.84
3.72
1.52
62.84
3.72
1.52
57.12
3.71
1.38
57.07
3.71
1.38
13.19
0.47
0.32
13.14
0.49
0.32
0.078
0.03
0
0.078
0.03
0
84.86
3.71
2.05
84.83
3.71
2.05
75.07
3.7
1.81
75.01
3.71
1.81
13.11
0.51
0.32
13.03
0.43
0.31
0.078
0.03
0
0.078
0.03
0
Idle
8
4
24
8
4
Mute
fSPK_AMP =
768kHz
Sleep
8
4
Shutdown
8
4
Idle
8
4
8
4
8
4
8
Mute
fSPK_AMP =
1152kHz
Sleep
Shutdown
18
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SLOS741B – MAY 2013 – REVISED JULY 2013
TYPICAL SPEAKER AMPLIFIER PERFORMANCE CHARACTERISTICS (Stereo BTL Mode)
At TA = 25°C, fSPK_AMP = 384kHz, input signal is 1 kHz Sine, unless otherwise noted.
Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless
otherwise noted.
50
40
35
30
25
20
0.1
15
0.01
10
5
0
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
THD+N (%)
45
Maximum Output Power (W)
10
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
4 Ω Thermal Limit
6 Ω Thermal Limit
8 Ω Thermal Limit
THD+N = 10%
4
6
8
10
12 14 16 18
Supply Voltage (V)
20
22
24
0.001
26
20
100
G001
NOTE: Thermal Limits are referenced to TAS5760xxEVM Rev D
Figure 1. Output Power vs PVDD
10
Noise (µVRMS)
THD+N (%)
0.1
0.01
0.001
20
100
1k
Frequency (Hz)
10k
20k
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
Idle Channel
RL = 8 Ω
8
1
1
THD+N (%)
THD+N (%)
10
0.1
G024
12
Ch1 ICN @ Gain = 00
Ch2 ICN @ Gain = 00
Ch1 ICN @ Gain = 01
Ch2 ICN @ Gain = 01
Ch1 ICN @ Gain = 10
Ch2 ICN @ Gain = 10
14
16
18
Supply Voltage (V)
20
22
24
G026
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
0.1
0.01
RL = 4Ω
RL = 6Ω
RL = 8Ω
0.1
20k
Figure 4. Idle Channel Noise vs PVDD
10
0.001
0.01
10
G025
Figure 3. THD+N vs Frequency with
PVDD = 24 V, POSPK = 1 W
0.01
10k
Figure 2. THD+N vs Frequency with
PVDD = 12 V, POSPK = 1 W
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
1k
Frequency (Hz)
1
Output Power (W)
10
50
0.001
0.01
G027
Figure 5. THD+N vs Output Power with
PVDD = 12 V, Both Channels Driven
0.1
1
Output Power (W)
10
50
G028
Figure 6. THD+N vs Output Power with
PVDD = 18 V, Both Channels Driven
19
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TYPICAL SPEAKER AMPLIFIER PERFORMANCE CHARACTERISTICS (Stereo BTL
Mode) (continued)
At TA = 25°C, fSPK_AMP = 384kHz, input signal is 1 kHz Sine, unless otherwise noted.
Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless
otherwise noted.
10
RL = 8 Ω
95
90
Power Efficiency (%)
1
THD+N (%)
100
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
0.1
0.01
85
80
75
70
65
PVDD = 12 V
PVDD = 18 V
PVDD = 24 V
60
55
0.001
0.01
0.1
1
Output Power (W)
10
50
80
0
5
0
PVCC = 24 V
RL = 4 Ω
Right−to−Left
Left−to−Right
20 25 30 35 40 45
Total Output Power (W)
RL = 8 Ω
−10
50
55
60
G030
PVDD = 12 V
PVDD = 18 V
PVDD = 24 V
−20
−30
−40
−50
−60
−70
−80
20
100
1k
Frequency (Hz)
10k
−90
20k
20
100
G031
Figure 9. Crosstalk vs Frequency
0
RL = 8 Ω
DVDD = 3.3 V + 200 mVP-P
−10
−20
1k
Frequency (Hz)
10k
20k
G019
Figure 10. PVDD PSRR vs Frequency
40
PVDD = 12 V
PVDD = 18 V
PVDD = 24 V
RL = 8 Ω
35
−30
Current (mA)
PSRR (dB)
15
Figure 8. Efficiency vs Output Power
PSRR (dB)
Crosstalk (dB)
Figure 7. THD+N vs Output Power with
PVDD = 24 V, Both Channels Driven
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
10
G029
−40
−50
−60
30
25
−70
−80
−90
20
100
1k
Frequency (Hz)
10k
20k
20
8
G020
Figure 11. DVDD PSRR vs Frequency
10
12
14
16
18
PVDD (V)
20
22
24
G042
Figure 12. Idle Current Draw vs PVDD (Filterless)
20
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SLOS741B – MAY 2013 – REVISED JULY 2013
TYPICAL SPEAKER AMPLIFIER PERFORMANCE CHARACTERISTICS (Stereo BTL
Mode) (continued)
At TA = 25°C, fSPK_AMP = 384kHz, input signal is 1 kHz Sine, unless otherwise noted.
Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless
otherwise noted.
40
60
RL = 8 Ω
55
Current (µA)
Current (mA)
35
30
25
20
RL = 8 Ω
50
45
40
8
10
12
14
16
18
PVDD (V)
20
22
24
35
8
G023
Figure 13. Idle Current Draw vs PVDD (With LC Filter as
shown on the EVM)
10
12
14
16
18
PVDD (V)
20
22
24
G022
Figure 14. Shutdown Current Draw vs PVDD (Filterless)
21
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TYPICAL SPEAKER AMPLIFIER PERFORMANCE CHARACTERISTICS (Stereo BTL
Mode) (continued)
At TA = 25°C, fSPK_AMP = 768 kHz, input signal is 1 kHz Sine, unless otherwise noted.
Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless
otherwise noted.
50
40
35
30
25
20
15
0.1
0.01
10
5
0
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
THD+N (%)
Maximum Output Power (W)
10
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
4 Ω Thermal Limit
6 Ω Thermal Limit
8 Ω Thermal Limit
45
THD+N = 10%
4
6
8
10
12 14 16 18
Supply Voltage (V)
20
22
24
0.001
26
20
100
G039
NOTE: Thermal Limits are referenced to TAS5760xxEVM Rev D
Figure 15. Output Power vs PVDD
10
Noise (µVRMS)
THD+N (%)
0.1
0.01
0.001
20
100
1k
Frequency (Hz)
10k
20k
130
120
110
100
90
80
70
60
50
40
30
20
10
0
8
10
12
14
16
18
PVDD (V)
20
22
24
G006
Figure 18. Idle Channel Noise vs PVDD
10
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
0.1
0.01
0.001
0.01
G002
Ch1 ICN @ Gain = 00
Ch2 ICN @ Gain = 00
Ch1 ICN @ Gain = 01
Ch2 ICN @ Gain = 01
Ch1 ICN @ Gain = 10
Ch2 ICN @ Gain = 10
G003
THD+N (%)
THD+N (%)
1
20k
Idle Channel
RL = 8 Ω
Figure 17. THD+N vs Frequency with
PVDD = 24 V, POSPK = 1 W
10
10k
Figure 16. THD+N vs Frequency with
PVDD = 12 V, POSPK = 1 W
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
1k
Frequency (Hz)
0.1
0.01
0.1
1
Output Power per Channel (W)
10
30
0.001
0.01
0.1
1
Output Power per Channel (W)
G008
Figure 19. THD+N vs Output Power with
PVDD = 12 V, Both Channels Driven
10
40
G009
Figure 20. THD+N vs Output Power with
PVDD = 18 V, Both Channels Driven
22
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SLOS741B – MAY 2013 – REVISED JULY 2013
TYPICAL SPEAKER AMPLIFIER PERFORMANCE CHARACTERISTICS (Stereo BTL
Mode) (continued)
At TA = 25°C, fSPK_AMP = 768 kHz, input signal is 1 kHz Sine, unless otherwise noted.
Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless
otherwise noted.
10
RL = 8 Ω
95
90
Efficiency (%)
1
THD+N (%)
100
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
0.1
85
80
75
70
65
0.01
PVDD = 12 V
PVDD = 18 V
PVDD = 24 V
60
55
0.001
0.01
0.1
1
10
Output Power per Channel (W)
50
60
0
5
G010
Figure 21. THD+N vs Output Power with
PVDD = 24 V, Both Channels Driven
0
PVDD = 24 V
RL = 4 Ω
−20
Right-to-Left
Left-to-Right
Crosstalk (dB)
RL = 8 Ω
−10
PSRR (dB)
−40
−50
−60
−70
−30
−40
−50
−70
−90
−80
−100
20
100
1k
Frequency (Hz)
10k
−90
20k
20
100
G018
Figure 23. Crosstalk vs Frequency
70
60
RL = 8 Ω
65
55
60
50
55
50
45
25
14
16
18
PVDD (V)
20
G019
22
24
RL = 8 Ω
35
35
12
20k
40
30
10
10k
45
40
8
1k
Frequency (Hz)
Figure 24. PVDD PSRR vs Frequency
Current (mA)
Current (mA)
G014
−60
−80
30
30
PVDD = 12 V
PVDD = 18 V
PVDD = 24 V
−20
−30
−110
25
Figure 22. Efficiency vs Output Power
0
−10
10
15
20
Output Power per Channel (W)
20
8
G045
Figure 25. Idle Current Draw vs PVDD (Filterless)
10
12
14
16
18
PVDD (V)
20
22
24
G044
Figure 26. Idle Current Draw vs PVDD (with LC Filter as
shown on EVM)
23
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TYPICAL SPEAKER AMPLIFIER PERFORMANCE CHARACTERISTICS (Stereo BTL
Mode) (continued)
At TA = 25°C, fSPK_AMP = 768 kHz, input signal is 1 kHz Sine, unless otherwise noted.
Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless
otherwise noted.
60
RL = 8 Ω
Current (µA)
55
50
45
40
35
8
10
12
14
16
18
PVDD (V)
20
22
24
G022
Figure 27. Shutdown Current Draw vs PVDD (Filterless)
24
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SLOS741B – MAY 2013 – REVISED JULY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (Mono PBTL Mode)
At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine unless otherwise noted.
10
0.1
0.01
0.001
RL = 2 Ω
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
THD+N (%)
1
THD+N (%)
10
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
0.1
0.01
20
100
1k
Frequency (Hz)
10k
0.001
20k
20
100
G032
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
10
8
10
12
20
22
0.1
0.001
0.01
24
50
G035
1
0.01
0.1
RL = 2 Ω
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
0.01
0.1
10
10
RL = 2 Ω
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
0.1
0.001
0.01
1
Output Power (W)
Figure 31. THD+N vs Output Power with
PVDD = 12 V with 1 kHz Sine Input
THD+N (%)
THD+N (%)
1
0.1
G034
Figure 30. Idle Channel Noise vs PVDD
10
G033
0.01
Gain = 00
Gain = 01
Gain = 10
14
16
18
Supply Voltage (V)
20k
RL = 2 Ω
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
Idle Channel
RL = 8 Ω
10k
Figure 29. THD+N vs Frequency with
PVDD = 24 V, POSPK = 1 W
THD+N (%)
Noise (µVRMS)
Figure 28. THD+N vs Frequency with
PVDD = 12 V, POSPK = 1 W
1k
Frequency (Hz)
1
Output Power (W)
10
100
0.001
0.01
0.1
G036
Figure 32. THD+N vs Output Power with
PVDD = 18 V with 1 kHz Sine Input
1
10
Output Power (W)
100 200
G037
Figure 33. THD+N vs Output Power with
PVDD = 24 V with 1 kHz Sine Input
25
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TYPICAL PERFORMANCE CHARACTERISTICS (Mono PBTL Mode) (continued)
At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine unless otherwise noted.
100
RL = 4 Ω
95
Power Efficiency (%)
90
85
80
75
70
65
PVDD = 12 V
PVDD = 18 V
PVDD = 24 V
60
55
50
0
5
10
15
20 25 30 35 40 45
Total Output Power (W)
50
55
60
G038
Figure 34. Efficiency vs Output Power
26
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SLOS741B – MAY 2013 – REVISED JULY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (Mono PBTL Mode) (continued)
At TA = 25°C, fSPK_AMP = 768 kHz, input signal is 1 kHz Sine unless otherwise noted.
10
0.1
0.01
0.001
RL = 2 Ω
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
THD+N (%)
1
THD+N (%)
10
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
0.1
0.01
20
100
1k
Frequency (Hz)
10k
0.001
20k
20
100
G004
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
10
8
10
12
16
18
PVDD (V)
20
22
0.1
0.001
0.01
24
10
RL = 2 Ω
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
10
50
G011
RL = 2 Ω
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
0.1
0.01
0.001
0.01
1
Output Power (W)
Figure 38. THD+N vs Output Power with
PVDD = 12 V
THD+N (%)
THD+N (%)
1
0.1
G007
Figure 37. Idle Channel Noise vs PVDD
10
G005
0.01
ICN @ Gain = 00
ICN @ Gain = 01
ICN @ Gain = 10
14
20k
RL = 2 Ω
RL = 4 Ω
RL = 6 Ω
RL = 8 Ω
1
Idle Channel
RL = 8 Ω
10k
Figure 36. THD+N vs Frequency with
PVDD = 24 V, POSPK = 1 W
THD+N (%)
Noise (µVRMS)
Figure 35. THD+N vs Frequency with
PVDD = 12 V, POSPK = 1 W
1k
Frequency (Hz)
0.1
0.01
0.1
1
Output Power (W)
10
100
0.001
0.01
0.1
G012
Figure 39. THD+N vs Output Power with
PVDD = 18 V
1
10
Output Power (W)
100 200
G013
Figure 40. THD+N vs Output Power with
PVDD = 24 V
27
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TYPICAL PERFORMANCE CHARACTERISTICS (Mono PBTL Mode) (continued)
At TA = 25°C, fSPK_AMP = 768 kHz, input signal is 1 kHz Sine unless otherwise noted.
100
RL = 4 Ω
95
Efficiency (%)
90
85
80
75
70
65
PVDD = 12 V
PVDD = 18 V
PVDD = 24 V
60
55
50
0
10
20
30
40
Output Power (W)
50
60
G015
Figure 41. Efficiency vs Output Power
28
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SLOS741B – MAY 2013 – REVISED JULY 2013
Theory of Operation and Detailed Description
DVDD
Internal
Voltage
Supplies
DRVDD
ANA_REG
AVDD
Internal Reference
Regulators
DRVDD
GVDD_REG
Internal Gate
Drive Regulator
Closed Loop Class D Amplifier
SFT_CLIP
MCLK
SCLK
LRCK
SDIN
PVDD
Serial
Audio
Port
Digital
Boost
&
Volume
Control
Digital
Clipper
Digital to
PWM
Conversion
Soft
Clipper
Analog
Gain
Gate
Drives
Gate
Drives
Full Bridge
Power Stage
A
SPK_OUTA+
OverCurrent
Protection
Full Bridge
Power Stage
B
SPK_OUTASPK_OUTB+
SPK_OUTB-
Clock Monitoring
Die
Temp. Monitor
DRVDD
DR_INA+
DR_INADR_INB+
DR_INB-
DirectPathTM Ground
Centered Headphone /
Line Driver
DR_OUTA
DR_OUTB
Charge Pump
DRVSS DR_CP DR_CN
Internal Control Registers and State Machines
PBTL/ SPK_GAIN0 SPK_GAIN1 SPK_SD SPK_FAULT SPK_SLEEP/ FREQ/
ADR
SDA
SCL
Device Overview and Summary
The TAS5760MD is a flexible and easy to use stereo Class D speaker amplifier with an I²S input serial audio
port. The TAS5760MD device also includes a dual-purpose headphone and line driver, which features pop/clickless operation, great audio performance, variable gain setting, and minimal bill of materials. The TAS5760MD
supports a variety of audio clock configurations via two speed modes. In Hardware Control mode, the device only
operates in single-speed mode. When used in Software Control mode, the device can be placed into double
speed mode to support higher sample rates, such as 88.2kHz and 96kHz. The outputs of the TAS5760MD can
be configured to drive two speakers in stereo Bridge Tied Load (BTL) mode or a single speaker in Parallel Bridge
Tied Load (PBTL) mode.
Only two power supplies are required for the TAS5760MD. They are a 3.3V power supply, called VDD, for the
small signal analog and digital and a higher voltage power supply, called PVDD, for the output stage of the
speaker amplifier. To enable use in a variety of applications, PVDD can be operated over a large range of
voltages, as specified in the Recommended Operating Conditions table.
To configure and control the TAS5760MD, two methods of control are available. In Hardware Control Mode, the
configuration and real-time control of the device is accomplished through hardware control pins. In Software
Control mode, the I²C control port is used both to configure the device and for real-time control. In Software
Control Mode, several of the hardware control pins remain functional, such as the SPK_SD, SPK_FAULT, and
SFT_CLIP pins. To allow the headphone amplifier / line driver to be used without needing the speaker amplifier
to be active, hardware controls are provided for the headphone amplifier via the DR_MUTE and DR_UVE pins.
Power Supplies
The power supply requirements for the TAS5760MD consist of one 3.3V supply to power the low voltage analog
and digital circuitry and one higher-voltage supply to power the output stage of the speaker amplifier. Several onchip regulators are included on the TAS5760MD to generate the voltages necessary for the internal circuitry of
the audio path. It is important to note that the voltage regulators which have been integrated are sized only to
provide the current necessary to power the internal circuitry. The external pins are provided only as a connection
point for off-chip bypass capacitors to filter the supply. Connecting external circuitry to these regulator outputs
may result in reduced performance and damage to the device.
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Speaker Amplifier Audio Signal Path
The block diagram for the TAS5760MD's speaker amplifier is shown below. In Hardware Control mode, a limited
subset of audio path controls are made available via external pins, which are pulled "HIGH" or "LOW" to
configure the device. In Software Control Mode, the additional features and configurations are available. All of
the available controls are discussed in this section, and the subset of controls that available in Hardware Control
Mode are discussed in the respective section below.
Digital Gain
(GDIG)
Analog Gain
(GANA)
Closed Loop Class D Amplifier
HPF
Serial
Audio In
Serial
Audio
Port
Digital
Boost
&
Volume
Control
Interpolation
Filter
123456
Digital
Clipper
Digital to PWM
Conversion
011010..
.
Gate
Drives
Gate
Drives
Full Bridge
Power Stage
A
Full Bridge
Power Stage
B
PWM
Audio Out
SFT_CLIP
Serial Audio Port (SAP)
The serial audio port (SAP) receives audio in either I²S, Left Justified, or Right Justified formats. In Hardware
Control mode, the device operates only in 32, 48 or 64 x fS I²S mode. In Software Control mode, additional
options for left-justified and right justified audio formats are available. The supported clock rates and ratios for
Hardware Control Mode and Software Control Mode are detailed in their respective sections below.
I²S Timing
I²S timing uses LRCK to define when the data being transmitted is for the left channel and when it is for the right
channel. LRCK is "LOW" for the left channel and "HIGH" for the right channel. A bit clock, called SCLK, runs at
32, 48, or 64 × fS and is used to clock in the data. There is a delay of one bit clock from the time the LRCK signal
changes state to the first bit of data on the data lines. The data is presented in 2's-complement form (MSB-first)
and is valid on the rising edge of bit clock.
Left-Justified
Left-justified (LJ) timing also uses LRCK to define when the data being transmitted is for the left channel and
when it is for the right channel. LRCK is "HIGH" for the left channel and "LOW" for the right channel. A bit clock
running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the
same time LRCK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The
TAS5760MD can accept digital words from 16 to 24 bits wide and pads any unused trailing data-bit positions in
the L/R frame with zeros before presenting the digital word to the audio signal path.
Right-Justified
Right-justified (RJ) timing also uses LRCK to define when the data being transmitted is for the left channel and
when it is for the right channel. LRCK is "HIGH" for the left channel and "LOW" for the right channel. A bit clock
running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock
periods (for 24-bit data) after LRCK toggles. In RJ mode the LSB of data is always clocked by the last bit clock
before LRCK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The
TAS5760MD pads unused leading data-bit positions in the left/right frame with zeros before presenting the digital
word to the audio signal path.
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DC Blocking Filter
Excessive DC content in the audio signal can damage loudspeakers and even small amounts of DC offset in the
signal path cause cause audible artifacts when muting and unmuting the speaker amplifier. For these reasons,
the amplifier employs two separate DC blocking methods for the speaker amplifier. The first is a high-pass filter
provided at the front of the data path to remove any DC from incoming audio data before it is presented to the
audio path. The -3dB corner frequencies for the filter are specified in the speaker amplifier electrical
characteristics table. In Hardware Control mode, the DC blocking filter is active and cannot be disabled. In
Software Control mode, the filter can be bypassed by writing a 1 to bit 7 of register 0x02. The second method is
a DC detection circuit that will shutdown the power stage and issue a latching fault if DC is found to be present
on the output due to some internal error of the device. This DC Error (DCE) protection is discussed in the
Protection Circuitry section below.
Digital Boost and Volume Control
Following the high-pass filter, a digital boost block is included to provide additional digital gain if required for a
given application as well as to set an appropriate clipping point for a given GAIN[1:0] pin configuration when in
Hardware Control mode. The digital boost block defaults to +6dB when the device is in Hardware Mode. In most
use cases, the digital boost block will remain unchanged when operating the device in Software Control mode, as
the volume control offers sufficient digital gain for most applications. The TAS5760MD's digital volume control
operates from Mute to +24dB, in steps of 0.5dB. The equation below illustrates how to set the 8-bit volume
control register at address 0x04:
spacer
DVC [Hex Value] = 0xCF + (DVC [dB] / 0.5 [dB] )
(1)
spacer
Transitions between volume settings will occur at a rate of 0.5dB every 8 LRCK cycles to ensure no audible
artifacts occur during volume changes. This volume fade feature can be disabled via Bit 7 of the Volume Control
Configuration Register.
Digital Clipper
A digital clipper is integrated in the oversampled domain to provide a component-free method to set the clip point
of the speaker amplifier. Via the "Digital Clipper Level x" controls in the I²C control port, the point at which the
oversampled digital path clips can be set directly, which in turns sets the 10% THD+N operating point of the
amplifier. This is useful for applications in which a single system is designed for use in several end applications
that have different power rating specifications. Its place in the oversampled domain ensures that the digital
clipper is acoustically appealing and reduces or eliminates tones which would otherwise foldback into the audio
band during clipping events. The block diagram of the digital clipper is shown below:
Digital Clipper
Digital to PWM
Conversion
22 Bit Audio Sample in Data Path
Mux
20 Bit Digital Clipper Level in Control Port
011010..
.
Digital
Comparator
Figure 42. Digital Clipper Simplified Block Diagram
As mentioned previously, the audio signature of the amplifier when the digital clipper is active is very smooth,
owing to its place in the signal chain. The typical behavior of the clipping events are shown in the screen shot
below.
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Figure 43. Digital Clipper Example Waveform for various settings of Digital Clip Level [19:0]
It is important to note that the actual signal developed across the speaker will be determined not only by the
digital clipper, but also the analog gain of the amplifier. Depending on the analog gain settings and the PVDD
level applied, clipping could occur as a result of the voltage swing that is determined by the gain being larger
than the available PVDD supply rail. The gain structures are discussed in detail below for both Hardware Control
Mode and Software Control Mode.
Closed Loop Class-D Amplifier
Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, whose
first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two
pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker
amplifer. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and
increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D
amplifier section of the device. The gain structures are discussed in detail below for both Hardware Control Mode
and Software Control Mode.
The switching rate of the amplifier is configurable in both Hardware Control Mode and Software Control Mode. In
both cases, the PWM switching frequency is a multiple of the sample rate. This behavior is described in the
respective Hardware Control Mode and Software Control Mode sections below.
Speaker Amplifier Protection Suite
The speaker amplifier in the TAS5760MD includes a robust suite of error handling and protection features. It is
protected against Over-Current, Under-Voltage, Over-Voltage, Over-Temperature, DC, and Clock Errors. The
status of these errors is reported via the SPK_FAULT pin and the appropriate error status register in the I²C
Control Port. The error or handling behavior of the device is characterized as being either "Latching" or "NonLatching" depending on what is required to clear the fault and resume normal operation (that is playback of
audio).
For latching errors, the SPK_SD pin or the SPK_SD bit in the control port must be toggled in order to clear the
error and resume normal operation. If the error is still present when the SPK_SD pin or bit transitions from
"LOW" back to "HIGH", the device will again detect the error and enter into a fault state resulting in the error
status bit being set in the control port and the SPK_FAULT line being pulled "LOW". If the error has been cleared
(for example, the temperature of the device has decreased below the error threshold) the device will attempt to
resume normal operation after the SPK_SD pin or bit is toggled and the required fault time out period
(TSPK_FAULT ) has passed. If the error is still present, the device will once again enter a fault state and must be
placed into and brought back out of shutdown in order to attempt to clear the error.
For non-latching errors, the device will automatically resume normal operation (that is playback) once the error
has been cleared. The non-latching errors, with the exception of clock errors will not cause the SPK_FAULT line
to be pulled "LOW". It is not necessary to toggle the SPK_SD pin or bit in order to clear the error and resume
normal operation for non-latching errors. Table 1 details the types of errors protected by the TAS5760MD's
Protection Suite and how each are handled.
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Speaker Amplifier Fault Notification (SPK_FAULT Pin)
In both hardware and Software Control mode, the SPK_FAULT pin of the TAS5760MD serves as a fault indicator
to notify the system that a fault has occurred with the speaker amplifier by being actively pulled "LOW". This pin
is an open drain output pin and, unless one is provided internal to the receiver, requires an external pull-up to set
the net to a known value. The behavior of this pin varies based upon the type of error which has occurred.
In the case of a latching error, the fault line will remain "LOW" until such time that the TAS5760MD has resumed
normal operation (that is the SPK_SD pin has been toggled and TSPK_FAULT has passed).
With the exception of clock errors, non-latching errors will not cause the SPK_FAULT pin to be pulled "LOW".
Once a non-latching error has been cleared, normal operation will resume. For clocking errors, the SPK_FAULT
line will be pulled "LOW", but upon clearing of the clock error normal operation will resume automatically, i.e. with
no TSPK_FAULT delay.
One method which can be used to convert a latching error into an auto-recovered, non-latching error is to
connect the SPK_FAULT pin to the SPK_SD pin. In this way, a fault condition will automatically toggle the
SPK_SD pin when the SPK_FAULT pin goes "LOW" and returns "HIGH" after the TSPK_FAULT period has passed.
Table 1. Protection Suite Error Handling Summary
Error
Cause
Fault Type
Error is cleared by:
PVDD level returning below OVETHRES(PVDD)
Over Voltage Error
(OVE)
PVDD level rises above that specified by
OVERTHRES(PVDD)
Non-Latching
(SPK_FAULT
Pin is not pulled
"LOW")
Under Voltage Error
(UVE)
PVDD voltage level drops below that
specified by UVEFTHRES(SPK)
Non-Latching
(SPK_FAULT
Pin is not pulled
"LOW")
PVDD level returning above UVETHRES(PVDD)
Non-Latching
(SPK_FAULT
Pin is pulled
"LOW")
Clocks returning to valid state
Speaker Amplifier output current has
increased above the level specified by
OCETHRES
Latching
TSPK_FAULT has passed AND SPK_SD Pin or Bit
Toggle
DC offset voltage on the speaker
amplifier output has increased above the
level specified by the DCETHRES
Latching
TSPK_FAULT has passed AND SPK_SD Pin or Bit
Toggle
The temperature of the die has increased
Over-Temperature Error
above the level specified by the
(OTE)
OTETHRES
Latching
TSPK_FAULT has passed AND SPK_SD Pin or Bit
Toggle AND the temperature of the device has
reached a level below that which is dictated by the
OTEHYST specification
Clock Error
(CLKE)
Over-Current Error
(OCE)
DC Detect Error
(DCE)
One or more of the following errors has
occured:
1. Non-Supported MCLK to LRCK
and/or SCLK to LRCK Ratio
2. Non-Supported MCLK or LRCK rate
3. MCLK, SCLK, or LRCK has stopped
DC DETECT PROTECTION
The TAS5760MD has circuitry which will protect the speakers from DC current which might occur due to an
internal amplifier error. The device behavior in response to a DCE event is detailed in the table in the previous
section.
A DCE event occurs when the output differential duty-cycle of either channel exceeds 60% for more than 420
msec at the same polarity. The table below shows some examples of the typical DCE Protection threshold for
several values of the supply voltage. This feature protects the speaker from large DC currents or AC currents
less than 2Hz.
The minimum output offset voltages required to trigger the DC detect are show in Table 2. The outputs must
remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.
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Table 2. DC Detect Threshold
PVDD [V]
|VOS|- OUTPUT OFFSET VOLTAGE [V]
4.5
0.96
6
1.30
12
2.60
18
3.90
Headphone / Line Driver Amplifier
The TAS5760MD also integrates a versatile low-voltage analog input amplifier that can be used as a headphone
amplifier or a line driver. This amplifier can operate as a ground centered 2-VRMS pop-free stereo line driver or 25
mW headphone amplifier, which allows the removal of the output dc-blocking capacitors for reduced component
count and cost.
FUNCTIONAL BLOCK DIAGRAM
DR_INA+
DR_INB+
Line
Driver
DR_INA–
Line
Driver
DR_OUTA
DR_INB–
DR_OUTB
DR_UVP
DRGND
Click and Pop
Suppression
Short-Circuit
Protection
DRGND
DR_MUTE
DRVSS
Bias
Circuitry
DR_CN
DRVDD
DR_CP
Designed using TI’s patented DirectPath™ technology, the device is capable of driving 2 VRMS into a 10-kΩ load
or 23 mW into a 32-Ω headphone load, with 3.3-V supply voltage. It includes differential inputs and uses external
gain-setting resistors to support a gain range of ±1 V/V to ±10 V/V. Additionally, gain can be configured
individually for each channel. The outputs have ±8-kV IEC ESD protection, requiring just a simple resistorcapacitor ESD protection circuit. The device includes built-in active-mute control for pop-free audio on/off control.
Additionally, an external undervoltage detector is included which will mute the output when the PVDD power
supply is removed, ensuring a pop-free shutdown.
As an integrated line drive amplifier, it does not require a power supply greater than 3.3 V to generate its output
signal, nor does it require a split-rail power supply. Instead, it integrates a charge pump to generate a negative
supply rail that provides a clean, pop-free ground-biased analog audio output.
Hardware Control Mode
For systems which do not require the added flexibility of the I²C control port or do not have an I²C host controller,
the TAS5760MD can be used in Hardware Control Mode. In this mode of operation, the device operates in its
default configuration and any changes to the device are accomplished via the hardware control pins, described
below. The audio performance between Hardware and Software Control mode is identical, however more
features and functionality are available when the device is operated in Software Control mode. The behavior of
these Hardware Control Mode pins is described in the sections below.
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Several static I/O's are present on the TAS5760MD which are meant to be configured during PCB design and not
changed during normal operation. Some examples of these are the GAIN[1:0] and PBTL/SCL pins. These pins
are often referred to as being tied or pulled "LOW" or tied or pulled "HIGH". A pin which is tied or pulled "LOW"
has been connected directly to the system ground. The TAS5760MD is configured such that the most popular
use cases for the device (that is BTL mode, 768kHz swicthing frequency, etc.) require the static I/O lines to be
tied "LOW". This ensures optimum thermal performance as well as BOM reduction.
pins that are to be tied or pulled "HIGH" are connected to DVDD. For these pins, a pull-up resistor is
recommended to limit the slew rate of the voltage which is presented to the pin during power up. Depending on
the output impedance of the supply, and the capacitance connected to the DVDD net on the board, slew rates of
this node could be high enough to trigger the integrated ESD protection circuitry at high current levels, causing
damage to the device. It is not necessary to have a separate pull-up resistor for each static digital I/O pin.
Instead, a single resistor can be connected to DVDD and all static I/O lines which are to be tied "HIGH" can be
connected to that pull-up resistor. This connectivity is shown in the Typical Application Circuits. These pull-up
resistors are not required when the digital I/O pins are driven by a controlled driver, such as a digital control line
from a systems processor, as the output buffer in the system processor will ensure a controlled slew rate.
Speaker Amplifier Shut Down (SPK_SD Pin)
In both Hardware and Software Control mode, the SPK_SD pin is provided to place the speaker amplifier into
shutdown. Driving this pin "LOW" will place the device into shutdown, while pulling it "HIGH" (to DVDD) will bring
the device out of shutdown. This is the lowest power consumption mode that the device can be placed in while
the power supplies are up. If the device is placed into shutdown while in normal operation, an audible artifact
may occur on the output. To avoid this, the device should first be placed into sleep mode, by pulling the
SPK_SLEEP/ADR pin "HIGH" before pulling the SPK_SD low.
Serial Audio Port in Hardware Control Mode
When used in Hardware Control Mode, the Serial Audio Port (SAP) accepts only I²S formatted data. Additionally,
the device operates in Single-Speed Mode (SSM), which means that supported sample rates, MCLK rates, and
SCLK rates are limited to those shown in the table below. Additional clocking options, including higher sample
rates, are available when operating the device in Software Control Mode.
The tables below detail the supported SCLK rates for each of the available sample rate and MCLK rate
configurations. For each fS and MCLK rate, the supported SCLK rates are shown and are represented in
multiples of the sample rate, which is written as "x fS".
Table 3. Supported SCLK Rates in Hardware Control Mode (Single Speed Mode)
MCLK Rate
[x fS]
Sample Rate [kHz]
128
192
12
N/S
N/S
16
N/S
N/S
24
N/S
32, 48, 64
32
32, 48, 64
38
32, 48, 64
44.1
48
256
384
512
N/S
N/S
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
Soft Clipper Control (SFT_CLIP Pin)
The TAS5760MD has a soft clipper that can be used to clip the output voltage level below the supply rail. When
this circuit is active, the amplifier operates as if it was powered by a lower supply voltage, and thereby enters into
clipping sooner than if the circuit wasn't active. The result is clipping behavior very similar to that of clipping at
the PVDD rail, in contrast to the digital clipper behavior which occurs in the oversampled domain of the digital
path. The point at which clipping begins is controlled by a resistor divider from GVDD_REG to ground, which sets
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the voltage at the SFT_CLIP pin. The precision of the threshold at which clipping occurs is dependent upon the
voltage level at the SFT_CLIP pin. Because of this, increasing the precision of the resistors used to create the
voltage divider, or using an external reference will increase the precision of the point at which the device enters
into clipping. To ensure stability, and soften the edges of the clipping event, a capacitor should be connected
from pin SFT_CLIP to ground.
Figure 44. Soft Clipper Example Wave Form
To move the output stage into clipping, the soft clipper circuit limits the duty cycle of the output PWM pulses to a
fixed maximum value. After filtering this limit applied to the duty cycle resembles a clipping event at a voltage
below that of the PVDD level. The peak voltage level attainable when the soft clipper circuit is active, called VP in
the example below, is approximately 4 times the voltage at the SFT_CLIP pin, noted as VSFT_CLIP. This voltage
can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance,
as shown in the equation below.
POUT
ææ
ö
ö
RL
çç ç
÷ ´ VP ÷÷
è RL + 2 ´ RS ø
ø
= è
2 ´ RL
2
for unclipped power
(2)
Where:
RS is the total series resistance including RDS(on), and output filter resistance.
RL is the load resistance.
VP is the peak amplitude achievable when the soft clipper circuit is active (As mentioned previously, VP = [4 x
VSFT_CLIP], provided that [4 x VSFT_CLIP] < PVDD.)
POUT (10%THD) ≈ 1.25 × POUT (unclipped)
It should be noted that, if the PVDD level is below (4 x VSFT_CLIP) clipping will occur due to clipping at PVDD
before the clipping due to the soft clipper circuit becomes active.
Table 4. Soft Clipper Example
(1)
PVDD [V]
SFT_CLIP Pin Voltage
[V] (1)
Resistor to GND
[kΩ]
24
GVDD
24
3.3
24
2.25
12
12
12
Resistor to GVDD [kΩ]
Output Voltage [Vrms]
(Open)
0
17.90
45
51
12.67
24
51
9.00
GVDD
0
(Open)
10.33
2.25
24
51
9.00
1.5
18
68
6.30
Output voltage measurements are dependent upon gain settings.
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Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
In Hardware Control mode, the PWM switching frequency of the TAS5760MD is configurable via the FREQ/SDA
pin. When connected to the system ground, the pin sets the output switching frequency to 16 × fS. When
connected to DVDD through a pull-up resistor, as shown in the Typical Application Circuits, the pin sets the
output switching frequency to 8 × fS. More switching frequencies are available when the TAS5760MD is used in
Software Control Mode.
Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
The TAS5760MD can be configured to drive a single speaker with the two output channels connected in parallel.
This mode of operation is called Parallel Bridge Tied Load (PBTL) mode. This mode of operation effectively
reduces the output impedance of the amplifier in half, which in turn reduces the power dissipated in the device
due to conduction losses through the output FETs. Additionally, since the output channels are working in parallel,
it also doubles the amount of current the speaker amplifier can source before hitting the over-current error
threshold.
It should be noted that the device can be placed operated in PBTL mode in either Hardware Control Mode or in
Software Control Mode, via the I²C Control Port. For instructions on placing the device in PBTL via the I²C
Control Port, please see the Software Control Mode section of this document.
In order to place the TAS5760MD into PBTL Mode when operating in Hardware Control Mode, the PBTL/SCL pin
should be pulled "HIGH" (that is, connected to the DVDD supply through a pull-up resistor). If the device is to
operate in BTL mode instead, the PBTL/SCL pin should be pulled "LOW", that is connected to the system supply
ground. When operated in PBTL mode, the output pins should be connected as shown in the Typical Application
Circuit Diagrams.
In PBTL mode, the amplifier selects its source signal from the left channel of the stereo signal presented on the
SDIN line of the Serial Audio Port. In order to select the right channel of the stereo signal, the LRCK can be
inverted in the processor that is sending the serial audio data to the TAS5760MD.
Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin )
In Hardware Control mode, pulling the SPK_SLEEP/ADR pin "HIGH" gracefully transitions the switching of the
output devices to a non-switching state or "High-Z" state. This mode of operation is similar to mute in that no
audio is present on the outputs of the device. However, unlike the 50/50 mute available in the I²C Control Port,
sleep mode saves quiescent power dissipation by stopping the speaker amplifier output transitors from switching.
This mode of operation saves quiescent current operation but keeps signal path blocks active so that normal
operation can resume more quickly than if the device were placed into shutdown. It is recommended to place the
device into sleep mode before stopping the audio signal coming in on the SDIN line or before bringing down the
power supplies connected to the TAS5760MD in order to avoid audible artifacts.
Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
In Hardware Control Mode, a combination of digital gain and analog gain is used to provide the overall gain of
the speaker amplifier. The decode of the two pins "SPK_GAIN1" and "SPK_GAIN0" sets the gain of the speaker
amplifier. Additionally, pulling both of the SPK_SPK_GAIN[1:0] pins "HIGH" places the device into software
control mode.
As seen in the figure below, the audio path of the TAS5760MD consists of a digital audio input port, a digital
audio path, a digital to PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop
which feeds the output information back into the DPC block to correct for distortion sensed on the output pins.
The total amplifier gain is comprised of digital gain, shown as GDIG in the digital audio path and the analog gain
from the input of the analog modulator GANA to the output of the speaker amplifier power stage.
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Digital Gain
(GDIG)
Analog Gain
(GANA)
Closed Loop Class D Amplifier
HPF
Serial
Audio
Port
Serial
Audio In
Digital
Boost
&
Volume
Control
Interpolation
Filter
Digital
Clipper
Digital to PWM
Conversion
123456
Gate
Drives
Gate
Drives
011010..
.
Full Bridge
Power Stage
A
Full Bridge
Power Stage
B
PWM
Audio Out
SFT_CLIP
As shown above, the first gain stage for the speaker amplifier is present in the digital audio path. It consists of
the volume control and the digital boost block. The volume control is set to 0dB by default and, in Hardware
Control mode, it does not change. For all settings of the SPK_GAIN[1:0] pins, the digital boost block remains at
+6 dB as analog gain block is transitioned through 19.2, 22.6, and 25 dBV.
The gain configurations provided in Hardware Control mode were chosen to align with popular power supply
levels found in many consumer electronics and to balance the trade-off between maximum power output before
clipping and noise performance. These gain settings ensure that the output signal can be driven into clipping at
those popular PVDD levels. If the power level required is lower than that which is possible with the PVDD level, a
lower gain setting can be used. Additionally, if clipping at a level lower than the PVDD supply is desired, the
digital clipper or soft clipper can be used.
The values of GDIG and GANA for each of the SPK_GAIN[1:0] settings are shown in the table below. Additionally,
the recommended PVDD level for each gain setting, along with the typical unclipped peak to peak output voltage
swing for a 0dBFS input signal is provided. The peak voltage levels in the table below should only be used to
understand the peak target output voltage swing of the amplifier if it had not been limited by clipping at the PVDD
rail.
Table 5. Gain Structure for Hardware Control Mode
PVDD Level
Recommended
SPK_GAIN[1:0] Pins Setting
Digital
Boost
[dB]
A_GAIN
[dBV]
VPk Acheivable Voltage Swing
(If output is not clipped at PVDD)
12
00
6
19.2
12.90
19
01
6
22.6
19.08
24
10
6
25
25.15
-
11
(Gain is controlled via I²C Port)
Considerations for Setting the Speaker Amplifier Gain Structure
Configuration of the gain of the amplifier is important to the overall noise and output power performance of the
TAS5760MD. Higher gain settings mean that more power can be driven from an amplifier before it becomes
voltage limited. Moreover, when output clipping "at the rail" is desired, it becomes important that there be enough
voltage gain in the signal path to drive the output signal above the PVDD level in order to "clip" the output signal
at the PVDD level in the output stage. Another desirable aspect of higher gain settings is that the dynamic
headroom of an amplifier is increased with higher gain settings, which increases the overall dynamic audio
quality of the signal being amplified.
With these advantages in mind, it may seem that setting the gain at the highest setting available would be
appropriate. However, there are some drawbacks to having a gain that is set arbitrarily high. The first drawback
is that a higher gain setting results in increased amplification of any noise that is present in the signal path. If the
gain is set too high, and the speaker is sensitive enough, this may result in an audible "hiss" at the speakers
when no audio is playing. Another consideration is that the speakers used in the system may not be rated for
operation at the power levels which would be possible for the given PVDD supply that is present in the system.
For this reason, it may be necessary to limit the voltage swing of the amplifier via a lower gain setting in order to
reduce the voltage presented, and therefore, the power delivered, to the speaker.
38
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Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
1. Determine the maximum power target and the speaker impedance which is required for the application.
2. Calculate the required output voltage swing for the given speaker impedance which will deliver the target
maximum power.
3. Chose the lowest gain setting via the SPK_GAIN[1:0] pins that produces an output voltage swing higher than
the required output voltage swing for the target maximum power.
NOTE
A higher gain setting can be used, provided the noise performance is acceptable and the
power delivered to the speaker remains within the safe operating area (SOA) of the
speaker, using the soft clipper if necessary to set the clip point within the SOA of the
speaker.
4. Characterize the clipping behavior of the system at the rated power.
– If the system does not produce the target power before clipping that is required, increase the gain setting.
– If the system meets the power requirements, but clipping is preferred at the rated power, use the soft
clipper to set the clip point
– If the system makes more power than is required but the noise performance is too high, consider
reducing the gain.
5. Repeat Step 4 above until the optimum balance of power, noise, and clipping behavior is achieved.
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Software Control Mode
The TAS5760MD can be used in Hardware Control Mode or Software Control Mode. In order to place the device
in software control mode, the two gain pins (GAIN[1:0]) should be pulled "HIGH". When this is done, the
PBTL/SCL and FREQ/SDA pins are allocated to serve as the clock and data lines for the I²C Control Port.
Speaker Amplifier Shut Down (SPK_SD Pin)
In both hardware and Software Control mode, the SPK_SD pin is provided to place the speaker amplifier into
shutdown. Driving this pin "LOW" will place the device into shutdown, while driving it "HIGH" (DVDD) will bring
the device out of shutdown. This is the lowest power consumption mode that the device can be placed in while
the power supplies are up. If the device is placed into shutdown while in normal operation, an audible artifact
may occur on the output. To avoid this, the device should first be placed into sleep mode, by pulling the
SPK_SLEEP/ADR pin "HIGH" before pulling the SPK_SD low.
Serial Audio Port Controls
In Software Control mode, additional digital audio data formats and clock rates are made available via the I²C
control port. With these controls, the audio format can be set to left justified, right justified, or I²S formatted data.
Serial Audio Port (SAP) Clocking
When used in Software Control mode, the device can be placed into double speed mode to support higher
sample rates, such as 88.2kHz and 96kHz. The tables below detail the supported SCLK rates for each of the
available sample rate and MCLK rate configurations. For each fS and MCLK Rate the support SCLK rates are
shown and are represented in multiples of the sample rate, which is written as "x fS".
Table 6. Supported SCLK Rates in Single Speed Mode
MCLK Rate [x fS]
Sample Rate [kHz]
128
192
256
384
512
12
N/S
N/S
N/S
N/S
32, 48, 64
16
N/S
N/S
32, 48, 64
32, 48, 64
32, 48, 64
24
N/S
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
38
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
44.1
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
48
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
Table 7. Supported SCLK Rates in Double Speed Mode
MCLK Rate [x fS]
Sample Rate [kHz]
128
192
256
88.2
32, 48, 64
32, 48, 64
32, 48, 64
96
32, 48, 64
32, 48, 64
32, 48, 64
Parallel Bridge Tied Load Mode via Software Control
The TAS5760MD can be configured to drive a single speaker with the two output channels connected in parallel.
This mode of operation is called Parallel Bridge Tied Load (PBTL) mode. This mode of operation effectively
reduces the on resistance of the amplifier in half, which in turn reduces the power dissipated in the device due to
conduction losses through the output FETs. Additionally, since the output channels are working in parallel, it also
doubles the amount of current the speaker amplifier can source before hitting the over-current error threshold.
It should be noted that the device can be placed operated in PBTL mode in either Hardware Control Mode or in
Software Control Mode, via the I²C Control Port. For instructions on placing the device in PBTL via the
PBTL/SCL Pin, please see the Hardware Control Mode section of this document.
40
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In order to place the TAS5760MD into PBTL Mode when operating in Software Control Mode, the Bit 7 of the
Analog Control Register (0x06) should be set in the control port. This bit is cleared by default to configure the
device for BTL mode operation. An additional control available in software mode control is PBTL Channel Select,
which selects which of the two channels presented on the SDIN line will be used for the input signal for the
amplifier. This is found at Bit 1 of the Analog Control Register (0x06). When operated in PBTL mode, the output
pins should be connected as shown in the Typical Application Circuit Diagrams.
Speaker Amplifier Gain Structure
As seen below, the audio path of the TAS5760MD consists of a digital audio input port, a digital audio path, a
digital to analog converter, an analog modulator, a gate driver stage, a Class D power stage, and a feedback
loop which feeds the output information back into the analog modulator to correct for distortion sensed on the
output pins. The total amplifier gain is comprised of digital gain, shown as GDIG in the digital audio path and the
analog gain from the input of the analog modulator GANA to the output of the speaker amplifier power stage.
Digital Gain
(GDIG)
Analog Gain
(GANA)
Closed Loop Class D Amplifier
HPF
Serial
Audio In
Serial
Audio
Port
Digital
Boost
&
Volume
Control
Interpolation
Filter
Digital
Clipper
123456
Digital to PWM
Conversion
011010..
.
Gate
Drives
Gate
Drives
Full Bridge
Power Stage
A
Full Bridge
Power Stage
B
PWM
Audio Out
SFT_CLIP
Speaker Amplifier Gain in Software Control Mode
The analog and digital gain are configured directly when operating in Software Control mode. It is important to
note that the digital boost block is separate from the volume control. The digital boost block should be set before
the speaker amplifier is brought out of mute and not changed during normal operation. In most cases, the digital
boost can be left in its default configuration, and no further adjustment is necessary. As mentioned previously,
the analog gain is directly set via the I²C control port in software control mode.
Considerations for Setting the Speaker Amplifier Gain Structure
Configuration of the gain of the amplifier is important to the overall noise and output power performance of the
TAS5760MD. Higher gain settings mean that more power can be driven from an amplifier before it becomes
voltage limited. Moreover, when output clipping "at the rail" is desired, it becomes important that there be enough
voltage gain in the signal path to drive the output signal above the PVDD level in order to "clip" the output signal
at the PVDD level in the output stage. Another desirable aspect of higher gain settings is that the dynamic
headroom of an amplifier is increased with higher gain settings, which increases the overall dynamic audio
quality of the signal being amplified.
With these advantages in mind, it may seem that setting the gain at the highest setting available would be
appropriate. However, there are some drawbacks to having a gain that is set arbitrarily high. The first drawback
is that a higher gain setting results in increased amplification of any noise that is present in the signal path. If the
gain is set too high, and the speaker is sensitive enough, this may result in an audible "hiss" at the speakers
when no audio is playing. Another consideration is that the speakers used in the system may not be rated for
operation at the power levels which would be possible for the given PVDD supply that is present in the system.
For this reason it may be necessary to limit the voltage swing of the amplifier via a lower gain setting in order to
reduce the voltage presented, and therefore the power delivered, to the speaker.
41
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Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
1. Determine the maximum power target and the speaker impedance which is required for the application.
2. Calculate the required output voltage swing for the given speaker impedance which will deliver the target
maximum power.
3. Chose the lowest analog gain setting via the A_GAIN[3:2] bits in the control port which will produce an output
voltage swing higher than the required output voltage swing for the target maximum power.
NOTE
A higher gain setting can be used, provided the noise performance is acceptable and the
power delivered to the speaker remains within the safe operating area (SOA) of the
speaker, using the soft clipper if necessary to set the clip point within the SOA of the
speaker.
4. Characterize the clipping behavior of the system at the rated power.
– If the system does not produce the target power before clipping that is required, increase the analog gain.
– If the system meets the power requirements, but clipping is preferred at the rated power, use the soft
clipper or the digital clipper to set the clip point
– If the system makes more power than is required but the noise performance is too high, consider
reducing the analog gain.
5. Repeat Step 4 above until the optimum balance of power, noise, and clipping behavior is achieved.
I²C Software Control Port
The TAS5760MD includes an I²C control port for increased flexibility and extended feature set.
Setting the I²C Device Address
Each device on the I²C bus has a unique address that allows it to appropriately transmit and receive data to and
from the I²C master controller. As part of the I²C protocol, the I²C master broadcast an 8-bit word on the bus that
contains a 7-bit device address in the upper 7 bits and a read or write bit for the LSB. The TAS5760MD has a
configurable I²C address. The SPK_SLEEP/ADR can be used to set the device address of the TAS5760MD. In
Software Control mode, the seven bit I²C device address is configured as “110110x[R/W]”, where “x” corresponds
to the state of the SPK_SLEEP/ADR pin at first power up sequence of the device. Upon application of the power
supplies, the device latches in the value of the SPK_SLEEP/ADR pin for use in determining the I²C address of
the device. If the SPK_SLEEP/ADR pin is tied "LOW" at power up (that is connected to the system ground), the
device address will be set to 1101100[R/W]. If it is pulled "HIGH" (that is connected to the DVDD supply), the
address will be set to 1101101[R/W] at power up.
General Operation of the I²C Control Port
The TAS5760MD device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol
and supports both 100-kHz and 400-kHz data transfer rates. This is a slave-only device that does not support a
multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the
device and to read device status.
The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is "HIGH" to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 45. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5760MD holds SDA "LOW" during the
acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte
of the sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND
connection. An external pullup resistor must be used for the SDA and SCL signals to set the "HIGH" level for the
bus.
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SDA
R/
A
W
7-Bit Slave Address
7
5
6
4
3
2
1
8-Bit Register Address (N)
7
0
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
7
0
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
Figure 45. Typical I²C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 45.
Writing to the I²C Control Port
As shown in Figure 46, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I²C and the read/write bit. The read/write bit determines the direction of the data
transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C and the read/write bit,
the TAS5760MD responds with an acknowledge bit. Next, the master transmits the address byte corresponding
to the TAS5760MD register being accessed. After receiving the address byte, the TAS5760MD again responds
with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address
being accessed. After receiving the data byte, the TAS5760MD again responds with an acknowledge bit. Finally,
the master device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
2
I C Device Address and
Read/Write Bit
A6
A5
A4
A3
A2
A1
A0 ACK D7
Subaddress
Acknowledge
D6
D5
D4
D3
Data Byte
D2
D1
D0 ACK
Stop
Condition
T0036-01
Figure 46. Write Transfer
Reading from the I²C Control Port
As shown in Figure 47, a data-read transfer begins with the master device transmitting a start condition, followed
by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a read are
actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As a result,
the read/write bit becomes a 0. After receiving the TAS5760MD address and the read/write bit, TAS5760MD
responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the
master device transmits another start condition followed by the TAS5760MD address and the read/write bit
again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the
read/write bit, the TAS5760MD again responds with an acknowledge bit. Next, the TAS5760MD transmits the
data byte from the register being read. After receiving the data byte, the master device transmits a notacknowledge followed by a stop condition to complete the data-read transfer.
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Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
Acknowledge
A0 R/W ACK A7
A6
2
A5
A4
A0 ACK
A6
A0 R/W ACK D7
A1
A5
2
I C Device Address and
Read/Write Bit
Subaddress
I C Device Address and
Read/Write Bit
Not
Acknowledge
Acknowledge
D6
D1
D0 ACK
Stop
Condition
Data Byte
T0036-03
Figure 47. Read Transfer
Table 8. Control Port Quick Reference Table
Adr.
(Dec)
Adr.
(Hex)
0
0
Device
Identification
1
1
Power Control
2
2
Register Name
Digital Control
Default (Binary)
B7
B6
B5
0
0
0
1
1
HPF
Bypass
Reserved
0
0
Fade
0
Left Channel
Volume Control
1
1
0
5
5
Right Channel
Volume Control
1
1
0
6
6
Analog Control
PBTL
Enable
1
0
1
Reserved Reserved
SPK_SL
EEP
SPK_SD
0
1
1
0
0
1
0
0
0
Mute R
Mute L
0
0
0
1
1
1
1
1
1
1
Fault
Configuration and
Error Status
0
0
0
9
Reserved
-
-
Reserved
-
-
1
0
0
1
0
0
0
0xFD
0x14
0x80
0xCF
0xCF
0x51
0x00
0
0
0
CLKE
OCE
DCE
OTE
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
0
0
OCE Thres
DigClipLev[13:6]
1
1
DigClipLev[5:0]
1
0x00
1
Reserved Reserved Reserved Reserved
0
Default
(Hex)
0
Reserved
0
PBTL Ch
Reserved
Sel
A_GAIN
Reserved
8
Digital Clipper 1
0
Serial Audio Input Format
0
0
0
8
11
0
1
SS/DS
PWM Rate Select
Reserved
17
0
Volume Right
7
Digital Clipper 2
1
1
0
7
10
B0
Volume Left
0
16
B1
Reserved Reserved Reserved Reserved Reserved
4
Reserved
0
1
Digital Boost
4
F
0
1
Volume Control
Configuration
15
B2
DigClipLev[19:14]
3
...
B3
Device Identification
3
9
B4
1
1
1
44
1
0x00
0xFF
0xFC
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Control Port Detailed Register Description
Device Identification (0 / 0x00)
Device Identification [7:0] (Read Only)
TAS5760Mx
0000000
00000000
Power Control (1 / 0x01)
DigClipLev[19:14] [7:2] (R/W)
11111101
The digital clipper is decoded from 3 registers- DigClipLev[19:14], DigClipLev[13:6], and DigClipLev[5:0].
DigClipLev[19:14], shown here, represents the upper 6 bits of the total of 20 bits that are used to set the Digital Clipping
Threshold.
(decoded)
Sleep Mode [1] (R/W)
11111101
Device is not in sleep mode
------0-
Device is placed in sleep mode (In this mode, the power stage is disabled to reduce quiescent power consumption over
a 50/50 duty cycle mute, while low-voltage blocks remain on standby. This reduces the time required to resume
playback when compared with entering and exiting full shut down.)
------1-
Speaker Shutdown [0] (R/W)
11111101
Speaker amplifier is shut down (This is the lowest power mode available when the device is connected to power
supplies. In this mode, circuitry in both the DVDD and PVDD domain are powered down to minimize power
consumption.)
-------0
Speaker amplifier is not shut down
-------1
Digital Control (2 / 0x02)
High-Pass Filter Bypass [7] (R/W)
00010100
The internal high-pass filter in the digital path is not bypassed.
0-------
The internal high-pass filter in the digital path is bypassed.
1-------
Reserved [6] (Read Only)
00010100
This control is reserved and must not be changed from its default setting.
-0------
Digital Boost [5:4] (R/W)
00010100
+0 dB is added to the signal in the digital path
--00----
+6 dB is added to the signal in the digital path
--01----
+12 dB is added to the signal in the digital path
--10----
+18 dB is added to the signal in the digital path
--11----
Single Speed / Double Speed Mode Select
00010100
Serial Audio Port will accept single speed sample rates (that is 32kHz, 44.1kHz, 48kHz)
----0---
Serial Audio Port will accept double speed sample rates (that is 64kHz, 88.2kHz, 96kHz)
----1---
Serial Audio Input Format
00010100
Serial Audio Input Format is 24 Bits, Right Justified
-----000
Serial Audio Input Format is 20 Bits, Right Justified
-----001
Serial Audio Input Format is 18 Bits, Right Justified
-----010
Serial Audio Input Format is 16 Bits, Right Justified
-----011
Serial Audio Input Format is I²S
-----100
Serial Audio Input Format is 16-24 Bits, Left Justified
Settings above 101 are reserved and must not be used
-----101
>-----101
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Volume Control Configuration (3 / 0x03)
Volume Fade Enable [7] (R/W)
10000000
Volume fading is disabled
0-------
Volume fading is enabled
1------Reserved [6:2] (Read Only)
10000000
This control is reserved and must not be changed from its default setting.
--------
Mute Right Channel [1] (R/W)
10000100
The right channel is not muted
------0-
The right channel is muted (In software mute, most analog and digital blocks remain active and the speaker amplifier
outputs transition to a 50/50 duty cycle.)
------1-
Mute Left Channel [0] (R/W)
10000000
The left channel is not muted
-------0
The left channel is muted (In software mute, most analog and digital blocks remain active and the speaker amplifier
outputs transition to a 50/50 duty cycle.)
-------1
Left Channel Volume Control (4 / 0x04)
Left/Right Channel Volume Control [7:0] (R/W)
11001111
Channel Volume is +24 dB
11111111
Channel Volume is +23.5 dB
11111110
Channel Volume is +23.0 dB
11111101
...
...
Channel Volume is 0 dB
11001111
...
...
Channel Volume is -100 dB
00000111
Any setting less than 00000111 places the channel in Mute
< 00000111
Right Channel Volume Control (5 / 0x05)
Left/Right Channel Volume Control [7:0] (R/W)
11001111
Channel Volume is +24 dB
11111111
Channel Volume is +23.5 dB
11111110
Channel Volume is +23.0 dB
11111101
...
...
Channel Volume is 0 dB
11001111
...
...
Channel Volume is -100 dB
00000111
Any setting less than 00000111 places the channel in Mute
< 00000111
Analog Control (6 / 0x06)
PBTL Enable [7] (R/W)
01010001
Device is placed in BTL mode
0-------
Device is placed in PBTL mode
1-------
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PWM Rate Select [6:4] (R/W)
01010001
Output switching rate of the Speaker Amplifier is 6 * LRCK
-000----
Output switching rate of the Speaker Amplifier is 8 * LRCK
-001----
Output switching rate of the Speaker Amplifier is 10 * LRCK
-010----
Output switching rate of the Speaker Amplifier is 12 * LRCK
-011----
Output switching rate of the Speaker Amplifier is 14 * LRCK
-100----
Output switching rate of the Speaker Amplifier is 16 * LRCK
-101----
Output switching rate of the Speaker Amplifier is 20 * LRCK
-110----
Output switching rate of the Speaker Amplifier is 24 * LRCK
-111----
Please note that all rates listed above are valid for single speed mode. For double speed mode, switching frequency is half of that
represented above.
A_GAIN[3:2] (R/W)
01010001
Analog Gain Setting is 19.2 dBV
----00--
Analog Gain Setting is 22.6 dBV
----01--
Analog Gain Setting is 25 dBV
----10--
This setting is reserved and must not be used
----11--
Channel Selection for PBTL Mode [1] (R/W)
01010001
When placed in PBTL mode, the audio information from the Left channel of the serial audio input stream is used by the
speaker amplifier
------0-
When placed in PBTL mode, the audio information from the Right channel of the serial audio input stream is used by
the speaker amplifier
------1-
Reserved [0] (R/W)
This control is reserved and must not be changed from its default setting.
01010001
--------
Reserved (7 / 0x07)
Reserved [7:0] (R/W)
Reserved
00000000
--------
Fault Configuration and Error Status (8 / 0x08)
Reserved [7:6] (R)
00000000
This control is reserved and must not be changed from its default setting.
--------
OCE Threshold [5:4] (R)
00000000
Threshold is set to the default level specified in the electrical characteristics table
--00----
Threshold is reduced to 75% of the evel specified in the electrical characteristics table
--01----
Threshold is reduced to 50% of the evel specified in the electrical characteristics table
--10----
Threshold is reduced to 25% of the evel specified in the electrical characteristics table
--11----
Clock Error Status [3] (R)
10000000
Clocks are valid and no error is currently detected
----0---
A clock error is occuring (This error is non-latching, so intermittent clock errors will be cleared when clocks re-enter
valid state and the device will resume normal operation automatically. This bit will likewise be cleared once normal
operation resumes.)
----1---
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Over Current Error Status[2] (R)
10000000
The output current levels of the speaker amplifier outputs are below the OCE threshold
-----0--
The DC offset level of the outputs has exceeded the OCE threshold, causing an error (This is a latching error and
SPK_SD must be toggled after an OCE event for the device to resume normal operation. This bit will remain "HIGH"
until SPK_SD is toggled.)
-----1--
Output DC Error Status [1] (R)
10000000
The DC offset level of the speaker amplifier outputs are below the DCE threshold
------0-
The DC offset level of the speaker amplifier outputs has exceeded the DCE threshold, causing an error (This is a
latching error and SPK_SD must be toggled after an DCE event for the device to resume normal operation. This bit will
remain "HIGH" until SPK_SD is toggled.)
------1-
Over-Temperature Error Status[1] (R)
10000000
A clock error will occur if SCLK is stopped
-------0
The temperature of the die has exceeded the level specified in the electrical characteristics table. (This is a latching
error and SPK_SD must be toggled for the device to resume normal operation. This bit will remain "HIGH" until
SPK_SD is toggled.)
-------1
Reserved Controls (9 / 0x09) - (15 / 0x0F)
The controls in this section of the control port are reserved and must not be used.
Digital Clipper Control 2 (16 / 0x10)
DigClipLev[13:6] [7:0] (R/W)
11111111
The digital clipper is decoded from 3 registers- DigClipLev[19:14], DigClipLev[13:6], and DigClipLev[5:0].
DigClipLev[13:6], shown here, represents the [13:6] bits of the total of 20 bits that are used to set the Digital Clipping
Threshold.
DigClipLev[5:0] [7:2] (R/W)
11111111
The digital clipper is decoded from 3 registers- DigClipLev[19:14], DigClipLev[13:6], and DigClipLev[5:0].
DigClipLev[13:6], shown here, represents the [5:0] bits of the total of 20 bits that are used to set the Digital Clipping
Threshold.
Reserved [1:0] (R/W)
These controls are reserved and should not be changed from there default values
48
(decoded)
(decoded)
11111100
--------
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APPLICATION INFORMATION
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular use cases.
Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible
modules allow full evaluation of the device in all available modes of operation. Additioanlly, some of the
application circuits are available as reference designs and can be found on the TI website. Also see the
TAS5760MD's product page for information on ordering the EVM. Note that not all configurations are available as
reference designs; however, any design variation can be supported by TI through schematic and layout reviews.
Visit support.ti.com for additional design assistance. Also, join the audio amplifier discussion forum at
http://e2e.ti.com.
TAS5760xD Typical Application Circuits
These application circuits detail the recommended component selection and board configurations for the
TAS5760MD or TAS5760LD device. Note that in Software Control mode, the clipping point of the amplifier and
thus the "rated power" of the end equipment can be set using the digital clipper if desired. Additionally, if the
sonic signature of the soft clipper is preferred, it can be used in addition to or in lieu of the digital clipper. The
software control application circuit detailed in this section shows the soft clipper in its bypassed state, which
results in a lower BOM count than when using the soft clipper. The trade-off between the sonic characteristics of
the clipping events in the amplifier and BOM minimization can be chosen based upon the design goals related to
the end product.
For further information regarding component selection, please refer to the EVM user guide.
VDD
1
1.0 …F
1.0 …F
10 lQ
2
3
4
5
6
7
8
VDD
9
1.0 …F
10
HIGH Æ 1101101[R/W]
LOW Æ 1101100[R/W]
10 lQ
11
12
13
14
15
16
17
18
System Processor
&
Associated Passive
Components
19
20
21
22
23
24
SFT_CLIP
ANA_REG
VCOM
ANA_REF
SPK_FAULT
SPK_SD
FREQ/SDA
PBTL/SCL
DVDD
SPK_GAIN0
SPK_GAIN1
SPK_SLEEP/ADR
MCLK
SCLK
SDIN
LRCK
DGND
DR_INADR_INA+
DR_OUTA
DRGND
DR_MUTE
DRVSS
DR_CN
GVDD_REG
GGND
AVDD
PVDD
PVDD
BSTRPA+
SPK_OUTA+
PGND
SPK_OUTABSTRPABSTRPB+
SPK_OUTBPGND
SPK_OUTB+
BSTRPBPVDD
PVDD
DR_INBDR_INB+
DR_OUTB
DR_UVE
DRGND
DRVDD
DR_CP
1 …F
PVDD
48
47
46
45
44
43
0.22…F
0.1 …F
LFILT
42
CFILT
41
40
39
38
CFILT
0.22…F
0.22…F
LFILT
LFILT
470 …F
37
CFILT
36
35
CFILT
0.22…F
34
LFILT
33
32
31
0.1 …F
30
RUVP1
29
28
27
VDD
RUVP2
26
25
1 …F
1 …F
1 …F
1.5…F
220 pF
10 lQ
5.6 lQ
HP
LD
10 lQ
10 lQ
10 lQ
1.5…F
5.6 lQ
220 pF
Figure 48. Stereo BTL using Software Control
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RCLIP1
VDD 1.0 …F
1
RCLIP2
1.0 …F
2
1.0 …F
10 lQ
3
4
5
VDD
HIGH Æ fSPK_AMP = 8 * fS
LOW Æ fSPK_AMP = 16 * fS
6
7
8
1.0 …F
9
Gain Set by Pin Decode
10
11
12
13
14
15
16
17
18
System Processor
&
Associated Passive
Components
19
20
21
22
23
24
SFT_CLIP
ANA_REG
VCOM
ANA_REF
SPK_FAULT
SPK_SD
FREQ/SDA
PBTL/SCL
DVDD
SPK_GAIN0
SPK_GAIN1
SPK_SLEEP/ADR
MCLK
SCLK
SDIN
LRCK
DGND
DR_INADR_INA+
DR_OUTA
DRGND
DR_MUTE
DRVSS
DR_CN
GVDD_REG
GGND
AVDD
PVDD
PVDD
BSTRPA+
SPK_OUTA+
PGND
SPK_OUTABSTRPABSTRPB+
SPK_OUTBPGND
SPK_OUTB+
BSTRPBPVDD
PVDD
DR_INBDR_INB+
DR_OUTB
DR_UVE
DRGND
DRVDD
DR_CP
1 …F
1.0 …F
PVDD
48
47
46
45
44
43
0.22…F
0.1 …F
LFILT
42
CFILT
41
40
39
38
CFILT
0.22…F
0.22…F
LFILT
LFILT
470 …F
37
CFILT
36
35
CFILT
0.22…F
34
LFILT
33
32
31
0.1 …F
30
RUVP1
29
28
27
VDD
RUVP2
26
25
1 …F
1 …F
1.5…F
220 pF
10 lQ
5.6 lQ
HP
LD
10 lQ
10 lQ
10 lQ
1.5…F
5.6 lQ
220 pF
Figure 49. Stereo BTL using Hardware Control
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VDD
1
1.0 …F
1.0 …F
10 lQ
2
3
4
5
6
7
8
VDD
9
1.0 …F
10
HIGH Æ 1101101[R/W]
LOW Æ 1101100[R/W]
10 lQ
11
12
13
14
15
16
17
18
System Processor
&
Associated Passive
Components
19
20
21
22
23
24
SFT_CLIP
ANA_REG
VCOM
ANA_REF
SPK_FAULT
SPK_SD
FREQ/SDA
PBTL/SCL
DVDD
SPK_GAIN0
SPK_GAIN1
SPK_SLEEP/ADR
MCLK
SCLK
SDIN
LRCK
DGND
DR_INADR_INA+
DR_OUTA
DRGND
DR_MUTE
DRVSS
DR_CN
GVDD_REG
GGND
AVDD
PVDD
PVDD
BSTRPA+
SPK_OUTA+
PGND
SPK_OUTABSTRPABSTRPB+
SPK_OUTBPGND
SPK_OUTB+
BSTRPBPVDD
PVDD
DR_INBDR_INB+
DR_OUTB
DR_UVE
DRGND
DRVDD
DR_CP
1 …F
PVDD
48
47
46
45
44
43
0.22…F
0.1 …F
LFILT
42
CFILT
41
40
0.22…F
0.22…F
39
38
470 …F
37
36
CFILT
35
0.22…F
34
LFILT
33
32
31
0.1 …F
30
RUVP1
29
28
27
VDD
RUVP2
26
25
1 …F
1 …F
1 …F
1.5…F
220 pF
10 lQ
5.6 lQ
HP
LD
10 lQ
10 lQ
10 lQ
1.5…F
5.6 lQ
220 pF
Figure 50. Mono PBTL using Software Control
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RCLIP1
VDD 1.0 …F
1
RCLIP2
1.0 …F
2
1.0 …F
10 lQ
3
4
5
VDD
HIGH Æ fSPK_AMP = 8 * fS
LOW Æ fSPK_AMP = 16 * fS
6
7
8
10 lQ
1.0 …F
Gain Set by Pin Decode
9
10
11
12
13
14
15
16
17
18
System Processor
&
Associated Passive
Components
19
20
21
22
23
24
SFT_CLIP
ANA_REG
VCOM
ANA_REF
SPK_FAULT
SPK_SD
FREQ/SDA
PBTL/SCL
DVDD
SPK_GAIN0
SPK_GAIN1
SPK_SLEEP/ADR
MCLK
SCLK
SDIN
LRCK
DGND
DR_INADR_INA+
DR_OUTA
DRGND
DR_MUTE
DRVSS
DR_CN
GVDD_REG
GGND
AVDD
PVDD
PVDD
BSTRPA+
SPK_OUTA+
PGND
SPK_OUTABSTRPABSTRPB+
SPK_OUTBPGND
SPK_OUTB+
BSTRPBPVDD
PVDD
DR_INBDR_INB+
DR_OUTB
DR_UVE
DRGND
DRVDD
DR_CP
1 …F
1.0 …F
PVDD
48
47
46
45
44
43
0.22…F
0.1 …F
LFILT
42
CFILT
41
40
39
38
0.22…F
0.22…F
470 …F
37
36
35
CFILT
0.22…F
34
LFILT
33
32
31
0.1 …F
30
RUVP1
29
28
27
VDD
RUVP2
26
25
1 …F
1 …F
1.5…F
220 pF
10 lQ
5.6 lQ
HP
LD
10 lQ
10 lQ
10 lQ
1.5…F
5.6 lQ
220 pF
Figure 51. Mono PBTL using Hardware Control
Component Selection and Hardware Connections
The Typical Application Circuits shown above detail the typical connections required for proper operation of the
device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from
this typical application circuit unless recommended by this document may produce unwanted results, which could
range from degradation of audio performance to destructive failure of the device.
I²C Pull-Up Resistors
It is important to note that when the device is operated in Software Control Mode, the customary pull-up resistors
are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, since they
are shared by all of the devices on the I²C bus and are considered to be part of the associated passive
components for the System Processor. These resistor values should be chosen per the guidance provided in the
I²C Specification.
Digital I/O Connectivity
The digital I/O lines of the TAS5760MD are described in previous sections. As discussed, whenever a static
digital pin (that is a pin that is hardwired to be "HIGH" or "LOW") is required to be pulled "HIGH", it should be
connected to DVDD through a pull-up resistor in order to control the slew rate of the voltage presented to the
digital I/O pins. It is not, however, necessary to have a separate pull-up resistor for each static digital I/O line.
Instead, a single resistor can be used to tie all static I/O lines "HIGH" to reduce BOM count. For instance, if
Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled "HIGH" through
a single pull-up resistor.
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Recommended Startup and Shutdown Procedures
The start up and shutdown procedures for both Hardware Control Mode and Software Control Mode are shown
below.
Startup Procedures- Hardware Control Mode
1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ,
GAIN, etc.)
2. Start with SPK_SD pin pulled "LOW" and SPK_SLEEP/ADR pin pulled "HIGH"
3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is
held in shutdown.)
4. Once power supplies are stable, start MCLK, SCLK, LRCK
5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring
SPK_SD "HIGH"
6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR "LOW"
7. The device is now in normal operation
Shutdown Procedures- Hardware Control Mode
1.
2.
3.
4.
5.
The device is in normal operation
Pull SPK_SLEEP/ADR "HIGH"
Pull SPK_SD "LOW"
The clocks can now be stopped and the power supplies brought down
The device is now fully shutdown and powered off
Startup Procedures- Software Control Mode
1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] =
11, ADR, etc.)
2. Start with SPK_SD Pin = "LOW"
3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is
held in shutdown.)
4. Once power supplies are stable, start MCLK, SCLK, LRCK
5. Configure the device via the control port in the manner required by the use case, making sure to mute the
device via the control port
6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD
"HIGH"
7. Unmute the device via the control port
8. The device is now in normal operation
It is important to note that control port register changes should only occur when the device is placed into
shutdown. This can be accomplished either by pulling the SPK_SD pin "LOW" or clearing the SPK_SD bit in the
control port.
Shutdown Procedures- Software Control Mode
1.
2.
3.
4.
5.
The device is in normal operation
Mute via the control port
Pull SPK_SD "LOW"
The clocks can now be stopped and the power supplies brought down
The device is now fully shutdown and powered off
It is important to note that any control port register changes excluding volume control changes should only occur
when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin "LOW" or
clearing the SPK_SD bit in the control port.
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Headphone and Line Driver Amplifier
Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 52
illustrates the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors
are often large in value. The line load (typical resistive values of 600 Ω to 10 kΩ) combines with the dc blocking
capacitors to form a high-pass filter. Equation 3 shows the relationship between the load impedance (RL), the
capacitor (CO), and the cutoff frequency (fC).
1
fc =
2p R L CO
(3)
CO can be determined using Equation 4, where the load impedance and the cutoff frequency are known.
1
CO =
2p R L f c
(4)
If fC is low, the capacitor must then have a large value because the load resistance is small. Large capacitance
values require large package sizes. Large package sizes consume PCB area, stand high above the PCB,
increase cost of assembly, and can reduce the fidelity of the audio output signal.
9 V–12 V
Conventional Solution
VDD
+
+
OPAMP
Mute Circuit
Co
+
Output
VDD/2
–
GND
Enable
3.3 V
TAS5760xD Solution
DirectPath
DRVDD
Mute Circuit
+
TAS5760xD
Output DRGND
–
DRVSS
Enable
Figure 52. Conventional and DirectPath Line Drivers
The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to
provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the
IC, the device operates in what is effectively a split-supply mode. The output voltages are now centered at zero
volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click and pop
reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors. The bottom block diagram
and waveform of Figure 52 illustrate the ground-referenced line-driver architecture. This is the architecture of the
headphone / line driver inside of the TAS5760MD.
CHARGE-PUMP FLYING CAPACITOR AND DR_VSS CAPACITOR
The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The PVSS capacitor must be at least equal to the charge-pump capacitor in order to allow maximum charge
transfer. Low-ESR capacitors are an ideal selection, and a value of 1 µF is typical. Capacitor values that are
smaller than 1 µF can be used, but the maximum output voltage may be reduced and the device may not
operate to specifications. If the TAS5760MD is used in highly noise-sensitive circuits, it is recommended to add a
small LC filter on the DRVDD connection.
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DECOUPLING CAPACITORS
The TAS5760MD contains a DirectPath line-driver amplifier that requires adequate power supply decoupling to
ensure that the noise and total harmonic distortion (THD) are low. A good, low equivalent-series-resistance
(ESR) ceramic capacitor, typically 1 µF, placed as close as possible to the device DRVDD lead works best.
Placing this decoupling capacitor close to the TAS5760MD is important for the performance of the amplifier. For
filtering lower-frequency noise signals, a 10-µF or greater capacitor placed near the audio power amplifier would
also help, but it is not required in most applications because of the high PSRR of this device.
GAIN-SETTING RESISTOR RANGES
The gain-setting resistors, RIN and Rfb, must be chosen so that noise, stability, and input capacitor size of the
headphone amplifier / line driver inside the TAS5760MD are kept within acceptable limits. Voltage gain is defined
as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are
too high increases the noise of the amplifier. Table 9 lists the recommended resistor values for different
inverting-input gain settings.
Table 9. Recommended Resistor Values
GAIN
INPUT RESISTOR VALUE, RIN
FEEDBACK RESISTOR VALUE, Rfb
–1 V/V
10 kΩ
10 kΩ
–1.5 V/V
8.2 kΩ
12 kΩ
–2 V/V
15 kΩ
30 kΩ
–10 V/V
4.7 kΩ
47 kΩ
USING THE LINE DRIVER AMPLIFIER IN THE TAS5760MD AS A SECOND-ORDER FILTER
Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible
with the headphone amplifier / line driver inside the TAS5760MD, as it can be used like a standard operational
amplifier. Several filter topologies can be implemented, both single-ended and differential. In Figure 53, multifeedback (MFB) with differential input and single-ended input are shown.
An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from
the source and lowers the dc gain to 1, helping to reduce the output dc offset to a minimum.
The component values can be calculated with the help of the TI FilterPro™ program available on the TI Web site
at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html
Inverting Input
Differential Input
R2
C3
R1
R2
C3
C1
R3
R1
C1
R3
DR_INA-
DR_INA–
C2
TAS5760xD
C2
–
TAS5760xD
+
+
DR_INA+
C3
R1
R3
C1
R2
Figure 53. Second-Order Active Low-Pass Filter
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small-size ac-coupling capacitor. With the proposed values of R1 = 15 kΩ, R2 = 30 kΩ, and R3 = 43 kΩ, a
dynamic range (DYR) of 106 dB can be achieved with a 1-mF input ac-coupling capacitor.
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EXTERNAL UNDERVOLTAGE DETECTION
External undervoltage detection can be used to mute/shut down the heaphone / line driver amplifier in the
TAS5760MD before an input device can generate a pop.The shutdown threshold at the UVP pin is 1.25 V. The
user selects a resistor divider to obtain the shutdown threshold and hysteresis for the specific application. The
thresholds can be determined as follows:
VUVP = (1.25 – 6 mA × R3) × (R1 + R2) / R2
Hysteresis = 5 µA × R3 × (R1 + R2) / R2
For example, to obtain VUVP = 3.8 V and 1-V hysteresis, we can use R1 = 3 kΩ, R2 = 1 kΩ, and R3 = 50 kΩ.
VSUP_MO
R1
R3
DR_UVP
R2
INPUT-BLOCKING CAPACITORS
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
headphone amplifier / line driver inside the TAS5760MD. These capacitors block the dc portion of the audio
source and allow the headphone / line driver amplifier inside the TAS5760MD.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 5. For this calculation, the capacitance used is the input-blocking capacitor, and the resistance is the
input resistor chosen from Table 9; then the frequency and/or capacitance can be determined when one of the
two values is given.
It is recommended to use electrolytic capacitors or high-voltage-rated capacitors as input blocking capacitors to
ensure minimal variation in capacitance with input voltages. Such variation in capacitance with input voltages is
commonly seen in ceramic capacitors and can increase low-frequency audio distortion.
1
1
fcIN =
or
CIN =
2p R INCIN
2p fcIN R IN
(5)
GAIN-SETTING RESISTORS
The gain-setting resistors, RIN and Rfb, must be placed close to their respective pins to minimize capacitive
loading on these input pins and to ensure maximum stability of the headphone / line driver inside the
TAS5760MD. For the recommended PCB layout, see the TAS5760MD EVM User's Guide.
56
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
TAS5760MD
www.ti.com
SLOS741B – MAY 2013 – REVISED JULY 2013
REVISION HISTORY
Changes from Original (May 2013) to Revision A
•
Page
Changed the Product Preview data sheet ............................................................................................................................ 1
Changes from Revision A (July 2013) to Revision B
Page
•
Changed Features list item, Audio Performance From: RLOAD = 8Ω To: RSPK = 8Ω ............................................................. 1
•
Changed From: Voltage at speaker amplifier output pins To: Speaker Amplifier Output Voltage in the Abs Max table ..... 5
•
Changed Figure 30 ............................................................................................................................................................. 25
•
Changed the Soft Clipper Control (SFT_CLIP Pin) section ................................................................................................ 35
•
Changed Figure 52 device number reference From: TAS5760MD to TAS5760xD ........................................................... 54
•
Changed paragraph text following Figure 52 From: This is the architecture of the TAS5760MD. To: This is the
architecture of the headphone / line driver inside of the TAS5760MD. .............................................................................. 54
57
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5760MD
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TAS5760MDDCA
ACTIVE
HTSSOP
DCA
48
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
TAS5760MD
TAS5760MDDCAR
ACTIVE
HTSSOP
DCA
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
TAS5760MD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5760MDDCAR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
DCA
48
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.8
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5760MDDCAR
HTSSOP
DCA
48
2000
367.0
367.0
45.0
Pack Materials-Page 2
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