19-3706; Rev 2; 6/09 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ ``````````````````````````````````` ᄂቶ NBY8141ဵ᎖ᑩĂ᎖ख႙ਜ਼၃BTL0PPLၫࡼ Oॊຫ၃खLj߲ޣᎾᒙᏲ݆ຫൈᆐ426NI{Ă456NI{† 544/:3NI{LjၫࠅၒႥൈࡉ44lcqt! )ൺႅᄂܠ൩* 77lcqt! )OS[ ൩*ăকୈభᆐ 61Ω ঌᏲᄋ ,21eCn ࡼ ࢜ቯၒ߲ൈLj࢜ቯ၃ഉැࣞᆐ.225eCnăNBY8141 ᎌࣖೂࡼख႙ਜ਼၃୭)QBPVUਜ਼MOBJO*Ljด ݝSGఎ ਈ᎖ख႙Ă၃୭Ꭷৢᄖሣࡼೌ఼ᒜă ♦ ࢟Ꮞ࢟ǖ,3/2W ᒗ,4/7W,5/6W ᒗ,6/6W NBY8141ࡼख႙ຫൈᎅጙৈ27ᆡॊၫOॊຫჄሤણ)QMM* ޘညLj၃ࡼ۾ᑩ)MP*ຫൈᐌᎅᑳၫOॊຫჄሤણޘညă ᎅ᎖ॊၫOॊຫQMMభख႙ຫൈᎾᒙᆐ᎖၃۾ᑩຫ ൈ21/8NI{LjჅጲᑚᒬஉ৩ᇄኊࣖೂࡼख႙ਜ਼၃ ᄏݬఠᑩă၃ጞݧৼࢾOॊຫQMMLjܜ೫ ॊၫOॊຫQMM୷ࡼ࢟ഗሿLjభถଢ଼ࢅ೫၃ࡼ ࢟ഗႼăჅᎌࡼຫൈखညᏄୈ࣒ጯૹ߅ᏴበຢดLj ᒑኊጙৈᄏĂጙৈ21/8NI{ࡼJG݆ਜ਼ጙቋॊೂᏄୈ ૾భဣሚጙ뀨ᑳࡼᄖሣ0ၫᔊၫஊऱښă ♦ ดᒙख႙ਜ਼၃QMMĂWDPਜ਼ણവ݆ NBY8141 ݧቃߛࡁ6nn! y! 6nnĂ43୭ĂۡቯRGOॖ ᓤLjး᎖ࡼޱᆨࣞपᆍ.51°Dᒗ,236°Dă ♦ ᄏ၃ख ♦ ߲ޣᎾᒙຫൈ)ᇄࠈాኊཇ* ♦ BTL0PPLࢯᒜ ♦ ᆐ61ΩঌᏲᄋ,21eCnၒ߲ൈ ♦ ดᒙUY0SYఎਈ ♦ > 56eCࡼຫጴᒜ ♦ ࢜ቯSGഉැࣞᆐ*ǖ.225eCn ♦ భᎅᅪݝ݆ኡᐋJGࡒ ♦ < 23/6nBࡼख႙ෝါ࢟ഗ ♦ < 7/8nBࡼ၃ෝါ࢟ഗ ♦ < 911oBࡼਈࣥ࢟ഗ ♦ Ⴅ࢟ဧถLj< 361μt ♦ ቃߛࡁĂ43୭ĂۡቯRGOॖᓤ * 1/3% CFSLj5lcqtൺႅᄂܠ൩ၫLj391lI{! JGࡒă ``````````````````````````````````` ። ၷሶጁ఼Ꮩߓ ڔཝᇹᄻ ``````````````````````````````` ࢾ৪ቧᇦ PART MAX7030_ATJ+ TEMP RANGE -40°C to +125°C PIN-PACKAGE 32 Thin QFN-EP** +ܭာᇄ)Qc*0९SpITܪᓰࡼॖᓤă ** FQ! = ൡă ᓖǖNBY8141ᄋޣᎾᒙࡼᔫຫൈLjᅲᑳࡼޘອܭޘອ ኡቯᒎฉă ଜᄭᔈࣅછ ጁ఼ ጁঢ ዌᇓۨவ ``````````````````````````` ޘອኡቯᒎฉ ెޱఎඡ ۾ᔈࣅހᇹᄻ PART MAX7030LATJ+ CARRIER FREQUENCY (MHz) 315 MAX7030MATJ+† 345 MAX7030HATJ+ 433.92 † ૡᓨౚ༿Ꭷޣೊᇹă ୭ᒙĂ࢜ቯ።࢟വਜ਼ถౖᅄᏴၫᓾ೯ࡼᔢઁ߲ă ________________________________________________________________ Maxim Integrated Products 1 ۾ᆪဵ፞ᆪၫᓾ೯ࡼፉᆪLjᆪᒦభถࡀᏴडፉࡼݙᓰཀྵࡇᇙăྙኊጙݛཀྵཱྀLj༿Ᏼิࡼଐᒦݬఠ፞ᆪᓾ೯ă ᎌਈଥৃĂૡૺࢿ৪ቧᇦLj༿ೊNbyjnᒴሾ၉ᒦቦǖ21911!963!235:!)۱ᒦਪཌ*Lj21911!263!235:!)ฉᒦਪཌ*Lj षᆰNbyjnࡼᒦᆪᆀᐶǖdijob/nbyjn.jd/dpnă NBY8141 ``````````````````````````````````` গၤ NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ ABSOLUTE MAXIMUM RATINGS HVIN to GND..........................................................-0.3V to +6.0V PAVDD, AVDD, DVDD to GND ................................-0.3V to +4.0V ENABLE, T/R, DATA, AGC0, AGC1, AGC2 to GND .......................................-0.3V to (HVIN + 0.3V) All Other Pins to GND ...............................-0.3V to (_VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin Thin QFN (derate 21.3mW/°C above +70°C).............................................................1702mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, AVDD = DVDD = HVIN = PAVDD = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at AVDD = DVDD = HVIN = PAVDD = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.1 2.7 3.6 V 4.5 5.0 5.5 V fRF = 315MHz 3.5 5.4 fRF = 434MHz 4.3 6.7 fRF = 315MHz 7.6 12.3 fRF = 434MHz 8.4 13.6 fRF = 315MHz 11.6 19.1 fRF = 434MHz 12.4 20.4 Receiver 315MHz 6.1 7.9 Receiver 434MHz 6.4 8.3 Deep-sleep (3V mode) 0.8 8.8 Deep-sleep (5V mode) 2.4 10.9 Receiver 315MHz 6.4 8.2 Receiver 434MHz 6.7 8.4 Deep-sleep (3V mode) 8.0 34.2 Deep-sleep (5V mode) 14.9 39.3 Supply Voltage (3V Mode) VDD HVIN, PAVDD, AVDD, and DVDD connected to power supply Supply Voltage (5V Mode) HVIN PAVDD, AVDD, and DVDD unconnected from HVIN, but connected together Transmit mode, PA off, VDATA at 0% duty cycle (Note 2) Transmit mode, VDATA at 50% duty cycle (Notes 3, 4) Transmit mode, VDATA at 100% duty cycle (Note 2) Supply Current IDD TA < +85°C, typ at +25°C (Note 4) TA < +125°C, typ at +125°C (Note 2) Voltage Regulator VREG mA μA mA μA HVIN = 5V, ILOAD = 15mA 3.0 V DIGITAL I/O Input-High Threshold VIH (Note 2) Input-Low Threshold VIL (Note 2) 2 0.9 x HVIN _______________________________________________________________________________________ V 0.1 x HVIN V ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ (Typical Application Circuit, 50Ω system impedance, AVDD = DVDD = HVIN = PAVDD = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at AVDD = DVDD = HVIN = PAVDD = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Pulldown Sink Current CONDITIONS MIN AGC0-2, ENABLE, T/R, DATA (HVIN = 5.5V) Output-Low Voltage VOL ISINK = 500μA Output-High Voltage VOH ISOURCE = 500μA TYP MAX UNITS 20 μA 0.15 V HVIN - 0.26 V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, PAVDD = AVDD = DVDD = HVIN = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Frequency Range Maximum Input Level PRFIN 315/345/ 433.92 MHz 0 dBm Transmit Efficiency 100% Duty Cycle fRF = 315MHz (Note 6) 32 fRF = 434MHz (Note 6) 30 Transmit Efficiency 50% Duty Cycle fRF = 315MHz (Note 6) 24 fRF = 434MHz (Note 6) 22 ENABLE or T/R transition low to high, transmitter frequency settled to within 50kHz of the desired carrier 200 ENABLE or T/R transition low to high, transmitter frequency settled to within 5kHz of the desired carrier 350 ENABLE transition low to high, or T/R transition high to low, receiver startup time (Note 5) 250 Power-On Time tON % % μs RECEIVER 0.2% BER, 4kbps Manchester data rate, 280kHz IF BW, average RF power Sensitivity 315MHz -114 434MHz -113 dBm Image Rejection 46 dB POWER AMPLIFIER Output Power POUT TA = +25°C (Note 4) TA = +125°C, PAVDD = AVDD = DVDD = HVIN = +2.1V (Note 2) TA = -40°C, PAVDD = AVDD = DVDD = HVIN = +3.6V (Note 4) Modulation Depth Maximum Carrier Harmonics Reference Spur With output-matching network 4.6 10.0 3.9 6.7 13.1 15.5 dBm 15.8 82 dB -40 dBc -50 dBc _______________________________________________________________________________________ 3 NBY8141 DC ELECTRICAL CHARACTERISTICS (continued) NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, 50Ω system impedance, PAVDD = AVDD = DVDD = HVIN = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER PHASE-LOCKED LOOP Transmit VCO Gain SYMBOL CONDITIONS KVCO Transmit PLL Phase Noise MIN TYP 340 10kHz offset, 200kHz loop BW -68 1MHz offset, 200kHz loop BW -98 Receive VCO Gain 340 Receive PLL Phase Noise Loop Bandwidth 10kHz offset, 500kHz loop BW -80 1MHz offset, 500kHz loop BW -90 Transmit PLL 200 Receive PLL 500 Reference Frequency Input Level 0.5 MAX UNITS MHz/V dBc/Hz MHz/V dBc/Hz kHz VP-P LOW-NOISE AMPLIFIER/MIXER (Note 8) LNA Input Impedance ZINLNA Normalized to 50Ω High-gain state Voltage-Conversion Gain Low-gain state Input-Referred, 3rd-Order Intercept Point IIP3 fRF = 315MHz 1 - j4.7 fRF = 434MHz 1- j3.3 fRF = 315MHz 50 fRF = 434MHz 45 fRF = 315MHz 13 fRF = 434MHz 9 High-gain state -42 Low-gain state -6 dB dBm Mixer-Output Impedance 330 Ω LO Signal Feedthrough to Antenna -100 dBm 330 Ω RSSI Input Impedance Operating Frequency 10.7 MHz 3dB Bandwidth fIF 10 MHz Gain 15 mV/dB Maximum Data-Filter Bandwidth 50 kHz Maximum Data-Slicer Bandwidth 100 kHz Maximum Peak-Detector Bandwidth 50 kHz ANALOG BASEBAND Maximum Data Rate 4 Manchester coded 33 Nonreturn to zero (NRZ) 66 _______________________________________________________________________________________ kbps ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CRYSTAL OSCILLATOR Crystal Frequency (fRF -10.7) /24 fXTAL MHz Maximum Crystal Inductance 50 mH Frequency Pulling by VDD 2 ppm/V 4.5 pF Crystal Load Capacitance Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: (Note 7) Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match. 100% tested at TA = +125°C. Guaranteed by design and characterization overtemperature. 50% duty cycle at 10kHz ASK data (Manchester coded). Guaranteed by design and characterization. Not production tested. Time for final signal detection; does not include baseband filter settling. Efficiency = POUT/(VDD x IDD). Dependent on PCB trace capacitance. Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degeneration from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series with ~2.2pF. The voltage conversion is measured with the LNA input-matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not include the IF filter insertion loss. ````````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ (Typical Application Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) RECEIVER 6.6 +85°C 6.4 6.2 +25°C 6.0 6.6 6.5 +85°C 6.4 6.1 5.6 6.0 2.7 3.0 SUPPLY VOLTAGE (V) +25°C 6.3 5.8 2.4 3.3 3.6 -40°C 18 MAX7030 toc03 +125°C 6.2 -40°C 2.1 DEEP-SLEEP CURRENT vs. TEMPERATURE MAX7030 toc02 6.7 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) MAX7030 toc01 +125°C 6.8 SUPPLY CURRENT vs. RF FREQUENCY 6.8 16 DEEP-SLEEP CURRENT (μA) SUPPLY CURRENT vs. SUPPLY VOLTAGE 7.0 14 VCC = +3.6V 12 VCC = +3.0V 10 VCC = +2.1V 8 6 4 2 0 300 325 350 375 400 RF FREQUENCY (MHz) 425 450 -40 -15 -10 35 60 85 110 TEMPERATURE (°C) _______________________________________________________________________________________ 5 NBY8141 AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, 50Ω system impedance, PAVDD = AVDD = DVDD = HVIN = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) `````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ* (Typical Application Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) RECEIVER BIT-ERROR RATE vs. AVERAGE INPUT POWER SENSITIVITY vs. TEMPERATURE 1.4 1 0.2% BER -111 -114 1.0 0.8 AGC SWITCH POINT 0.6 fRF = 315MHz 0.4 LOW-GAIN MODE -117 0.2 AGC HYSTERESIS: 3dB -120 -115 -113 -111 0 -40 -15 AVERAGE INPUT POWER (dBm) 50 2.5 40 1.5 30 1.2 0.5 0.9 -0.5 DELTA 0.3 0 -90 -70 -50 -30 -10 DELTA (%) RSSI 3.5 SYSTEM GAIN (dBm) 1.8 0.6 110 -130 -110 10 -1.5 0 -2.5 -10 -3.5 -20 -50 -30 fRF = 433MHz 46 fRF = 315MHz 44 42 5 10 15 20 25 30 -40 -15 10 35 60 85 S11 vs. RF FREQUENCY MAX7030 toc11 S11 SMITH PLOT OF RFIN S11 (dB) 433MHz -12 433.92MHz -18 400MHz -20 -24 1 10 IF FREQUENCY (MHz) 100 200 250 300 350 400 110 TEMPERATURE (°C) 0 -12 -16 10 48 -6 -8 -10 IMAGE REJECTION vs. TEMPERATURE IF FREQUENCY (MHz) MAX7030 toc10 -70 LOWER SIDEBAND 0 10 -90 RF INPUT POWER (dBm) FROM RFIN TO MIXOUT fRF = 434MHz 48dB IMAGE REJECTION 20 NORMALIZED IF GAIN vs. IF FREQUENCY -4 85 UPPER SIDEBAND IF INPUT POWER (dBm) 0 60 SYSTEM GAIN vs. IF FREQUENCY MAX7030 toc07 1.5 35 TEMPERATURE (°C) RSSI AND DELTA vs. IF INPUT POWER 2.1 10 MAX7030 toc12 -117 IMAGE REJECTION (dB) -119 MAX7030 toc08 -121 MAX7030 toc09 0.01 6 HIGH-GAIN MODE 1.2 fRF = 434MHz RSSI (V) fRF = 434MHz -108 MAX7030 toc06 1.6 10 fRF = 315MHz RSSI (V) 1.8 MAX7030 toc05 -105 0.1 NORMALIZED IF GAIN (dB) RSSI vs. RF INPUT POWER -102 MAX7030 toc04 100 SENSITIVITY (dBm) BIT-ERROR RATE (%) NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ 450 500 RF FREQUENCY (MHz) _______________________________________________________________________________________ 500MHz ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ RECEIVER INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION -220 90 -230 80 IMAGINARY IMPEDANCE -240 60 -250 50 -260 40 -270 REAL IMPEDANCE 30 20 10 1 -160 IMAGINARY IMPEDANCE 70 -180 50 -190 40 -200 -280 30 -290 20 REAL IMPEDANCE -220 100 INDUCTIVE DEGENERATION (nH) PHASE NOISE vs. OFFSET FREQUENCY MAX7030 toc15 fRF = 315MHz PHASE NOISE vs. OFFSET FREQUENCY -50 -70 -80 -90 -100 fRF = 433MHz -60 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) -210 10 1 INDUCTIVE DEGENERATION (nH) -60 -170 60 100 -50 -150 MAX7030 toc16 70 REAL IMPEDANCE (Ω) REAL IMPEDANCE (Ω) 80 IMAGINARY IMPEDANCE (Ω) fRF = 315MHz MAX7030 toc14 fRF = 434MHz IMAGINARY IMPEDANCE (Ω) MAX7030 toc13 90 -70 -80 -90 -100 -110 -110 -120 -120 100 1k 10k 100k OFFSET FREQUENCY (Hz) 1M 10M 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) _______________________________________________________________________________________ 7 NBY8141 `````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ* (Typical Application Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) `````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ* (Typical Application Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) TRANSMITTER SUPPLY CURRENT vs. SUPPLY VOLTAGE TA = +125°C TA = -40°C TA = +25°C 5.0 TA = +125°C 4.5 TA = +85°C 4.0 3.5 3.0 TA = +25°C 3.0 3.3 2.4 TA = +125°C 5.0 TA = +85°C 4.5 4.0 3.0 3.3 3.6 TA = +25°C TA = -40°C 10 9 PA ON 8 7 3.0 2.4 2.7 3.0 3.3 3.6 MAX7030 toc23-1 POWER -6 -2 2 12 4 0 CURRENT 8 -4 6 -8 fRF = 315MHz PA ON 1 10 100 EXTERNAL RESISTOR (Ω) 8 1k 10k SUPPLY CURRENT (mA) 14 OUTPUT POWER (dBm) SUPPLY CURRENT (mA) 16 8 0.1 MAX7030 toc19 8 50% DUTY CYCLE 6 10 -14 -10 -6 -2 2 MAX7030 toc23-2 POWER 16 12 8 12 4 CURRENT 10 0 8 -4 6 -8 -12 4 -16 2 -12 fRF = 433MHz PA ON -16 0.1 6 AVERAGE OUTPUT POWER (dBm) 18 16 12 2 9 SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR 14 4 PA ON 10 5 -10 -14 SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR 10 11 AVERAGE OUTPUT POWER (dBm) 16 3.6 6 SUPPLY VOLTAGE (V) 18 3.3 12 7 4 2.1 3.0 fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED 13 50% DUTY CYCLE 5 2.7 SUPPLY CURRENT vs. OUTPUT POWER 14 6 3.5 2.4 2.1 SUPPLY VOLTAGE (V) fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED 11 SUPPLY CURRENT (mA) fRF = 434MHz PA OFF 5.5 2.7 SUPPLY CURRENT vs. OUTPUT POWER 12 MAX7030 toc20 6.0 TA = +25°C SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. SUPPLY VOLTAGE TA = -40°C TA = +125°C 13 9 2.1 3.6 SUPPLY CURRENT (mA) 2.7 MAX7030 toc21 2.4 TA = +85°C TA = -40°C 2.0 2.1 15 11 2.5 8 fRF = 434MHz PA ON WITHOUT ENVELOPE SHAPING MAX7030 toc22 TA = +85°C 10 5.5 17 1 10 100 1k 10k EXTERNAL RESISTOR (Ω) _______________________________________________________________________________________ OUTPUT POWER (dBm) 14 SUPPLY CURRENT vs. SUPPLY VOLTAGE fRF = 315MHz PA OFF SUPPLY CURRENT (mA) MAX7030 toc17 fRF = 315MHz PA ON WITHOUT ENVELOPE SHAPING 12 6.0 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 16 MAX7030 toc18 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT (mA) NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ 10 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ TRANSMITTER 10 8 TA = +125°C TA = +25°C 10 8 TA = +125°C 3.0 3.3 3.6 2.4 SUPPLY VOLTAGE (V) 2.7 3.0 3.3 2.4 2.1 3.6 MAX7030 25-2 12 fRF = 315MHz PA ON TA = -40°C 35 TA = -40°C TA = +25°C 10 MAX7030 25-1 3.3 3.6 fRF = 434MHz PA ON TA = -40°C 35 TA = +85°C 25 TA = +125°C 3.0 EFFICIENCY vs. SUPPLY VOLTAGE 40 TA = +25°C 30 2.7 SUPPLY VOLTAGE (V) EFFICIENCY vs. SUPPLY VOLTAGE 40 EFFICIENCY (%) OUTPUT POWER (dBm) fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED 8 TA = +125°C TA = +85°C SUPPLY VOLTAGE (V) OUTPUT POWER vs. SUPPLY VOLTAGE 14 8 4 2.1 EFFICIENCY (%) 2.7 MAX7030 toc26 2.4 10 6 4 2.1 fRF = 434MHz PA ON ENVELOPE SHAPING DISABLED TA = -40°C TA = +25°C 12 TA = +85°C 6 4 14 MAX7030 24-2 12 TA = +85°C 6 fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED TA = -40°C OUTPUT POWER (dBm) TA = -40°C TA = +25°C OUTPUT POWER (dBm) OUTPUT POWER (dBm) 12 OUTPUT POWER vs. SUPPLY VOLTAGE OUTPUT POWER vs. SUPPLY VOLTAGE 14 MAX7030 24-1 fRF = 315MHz PA ON ENVELOPE SHAPING DISABLED MAX7030 toc27 OUTPUT POWER vs. SUPPLY VOLTAGE 14 TA = +25°C TA = +85°C 30 25 TA = +125°C TA = +125°C TA = +85°C 20 2.7 3.0 3.3 20 2.1 3.6 2.4 SUPPLY VOLTAGE (V) TA = -40°C EFFICIENCY (%) EFFICIENCY (%) 3.3 3.6 TA = +25°C 20 TA = +85°C TA = +125°C fRF = 434MHz 50% DUTY CYCLE 25 TA = +25°C 20 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 3.3 3.6 -40 fRF = 315MHz -50 -60 -70 -80 -90 -100 -110 -130 15 2.7 3.0 -120 TA = +125°C 10 2.7 PHASE NOISE vs. OFFSET FREQUENCY TA = +85°C 2.4 2.4 SUPPLY VOLTAGE (V) TA = -40°C 15 2.1 2.1 EFFICIENCY vs. SUPPLY VOLTAGE 30 MAX7030 toc28 fRF = 315MHz 50% DUTY CYCLE 25 3.0 SUPPLY VOLTAGE (V) EFFICIENCY vs. SUPPLY VOLTAGE 30 2.7 PHASE NOISE (dBc/Hz) 2.4 MAX7030 toc29 2.1 MAX7030 toc30 6 -140 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) _______________________________________________________________________________________ 9 NBY8141 `````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ* (Typical Application Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) `````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ* (Typical Application Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) TRANSMITTER REFERENCE SPUR MAGNITUDE vs. SUPPLY VOLTAGE PHASE NOISE vs. OFFSET FREQUENCY -70 -80 -90 -100 -110 -120 -45 MAX7030 toc32 -60 REFERENCE SPUR MAGNITUDE (dBc) fRF = 434MHz -50 -40 MAX7030 toc31 -40 PHASE NOISE (dBc/Hz) 434MHz -50 315MHz -55 -60 -65 -130 -70 -140 100 1k 10k 100k 1M 2.1 10M 2.4 2.7 3.0 SUPPLY VOLTAGE (V) OFFSET FREQUENCY (Hz) FREQUENCY STABILITY vs. SUPPLY VOLTAGE MAX7030 toc33 10 8 FREQUENCY STABILITY (ppm) NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ 6 fRF = 434MHz 4 2 0 -2 fRF = 315MHz -4 -6 -8 -10 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) 10 ______________________________________________________________________________________ 3.3 3.6 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ ถ ୭ ߂ 1 PAVDD ह࢟ᏎăᏴభถణத୭ࠀ1/12μGਜ਼331qGࡼവ࢟ྏࡵHOEă 2 ROUT ۞ᑳተၒ߲ăSPVU఼ᒜह۞ࡼဍਜ਼ሆଢ଼ဟମăSPVUೌࡵQBࡼ౯࢟ঢభኡࡼൈࢯஂ ࢟ᔜăྙ࢜ቯ።࢟വ ჅာLjᏴభถణத࢟ঢࠀ791qGਜ਼331qGࡼവ࢟ྏࡵHOEă 3 TX/RX1 ख႙0၃ఎਈăࡩU0Rᆐ࢟ຳဟUY0SY2ᎧUY0SY3വăࡩU0Rᆐࢅ࢟ຳဟUY0SY3ᎧUY0SY2 ࣥఎăถᄴUY0SY3ă 4 TX/RX2 ख႙0၃ఎਈăጙۅăݬ࢜ቯ።࢟വă 5 PAOUT हၒ߲ăক୭ኊገᄰਭጙৈ౯࢟ঢೌᒗ࢟Ꮞ)ྙኊገ۞ࢯᑳᐌೌᒗSPVU*Ljক࢟ঢభጲဵ ೌᄖሣࡼၒ߲ປᆀࡼጙݝॊă 6 AVDD ෝผ࢟Ꮞă6W࢟Ꮞ࢟ဟLjBWEE ೌᒗຢด,4/1WᆮኹăᏴభถణத୭ࠀLjᄰਭ1/2μGਜ਼331qG ࢟ྏBWEE വᒗHOEă 7 LNAIN ࢅᐅဉहࡍၒྜྷăܘኍୣഗẮă 8 LNASRC ᎖ೌ࢟ঢၱି࢟വࡼࢅᐅहᏎăೌጙৈ࢟ঢࡵHOEᒙMOBࡼၒྜྷᔜఝă 9 LNAOUT ࢅᐅဉहࡍၒ߲ăܘኍᄰਭጙৈ݀ೊMDቕᑩ݆ೌᒗBWEEăୣഗẮᒗNJYJO,ă 10 MIXIN+ ຫᄴሤၒྜྷăܘኍୣഗẮᒗMOBࡼၒ߲࣡ă 11 MIXIN- ຫनሤၒྜྷăᄰਭጙৈభถణதMOB! MDቕᑩ݆ࡼ࢟ྏവࡵBWEEă 12 MIXOUT 441Ωຫၒ߲ăೌࡵ21/8NI{݆ࡼၒྜྷ࣡ă 13 14 15 16 17 18 19 20 21, 25 IFINIFIN+ PDMIN PDMAX DSDS+ OP+ DF N.C. 441Ωᒦຫሢ७हࡍनሤၒྜྷăᄰਭጙৈ࢟ྏവᒗHOEă 441Ωᒦຫሢ७हࡍᄴሤၒྜྷăೌᒗ21/8NI{ᒦຫ݆ࡼၒ߲࣡ă ஊࢯၒ߲ࡼᔢࢅ࢟ຳख़ᒋଶ݆ă ஊࢯၒ߲ࡼᔢ࢟ຳख़ᒋଶ݆ă ၫሢ७नሤၒྜྷă ၫሢ७ᄴሤၒྜྷă Tbmmfo.Lfzၫ݆ࡼᏥहᄴሤၒྜྷă ၫ݆नౣஂ࢛ăTbmmfo.Lfzၫ݆ࡼनౣ࢟ྏၒྜྷă 22 T/R 23 ENABLE 24 DATA ၃૦ၫၒ߲0ख႙ၫၒྜྷă 26 DVDD ၫᔊ࢟ᏎăᏴభถణத୭ࠀ1/12μGਜ਼331qG࢟ྏവᒗHOEă 27 HVIN ࢟ኹ࢟Ꮞၒྜྷăݧ4W࢟Ꮞ࢟ဟLjIWJO ೌࡵBWEELjEWEE ਜ਼QBWEEăݧ6W࢟Ꮞ࢟ဟLj ஞIWJO ᒗ6WăᏴభถణத୭ࠀ1/12μGਜ਼331qG࢟ྏIWJO ୭വࡵHOEă ᎌೌăক୭ݙă ख႙0၃ኡᐋă࢟ຳဟୈࠀ᎖ख႙ෝါăࢅ࢟ຳኞహဟୈࠀ᎖၃ෝါăক୭Ᏼดۻݝ ౯ࢅă ဧถ࣡ă࢟ຳဟᑵޟᔫăࢅ࢟ຳኞహဟLjୈࠀ᎖ਈࣥෝါă ______________________________________________________________________________________ 11 NBY8141 ``````````````````````````````````````````````````````````````````````````````` ୭ႁී NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ ```````````````````````````````````````````````````````````````````````` ୭ႁී)ኚ* ถ ୭ ߂ 28 AGC2 BHDဧถ0ᓘഔဟମ఼ᒜ3! )NTC*ăݬܭ2ăᄰਭጙৈ21qG࢟ྏവᒗHOEă 29 AGC1 BHDဧถ0ᓘഔဟମ఼ᒜ2ăݬܭ2ăᄰਭጙৈ21qG࢟ྏവᒗHOEă 30 AGC0 BHDဧถ0ᓘഔဟମ఼ᒜ1! )MTC*ăݬܭ2ăᄰਭጙৈ21qG࢟ྏവᒗHOEă 31 XTAL1 ᄏၒྜྷ2ăྙਫᅪݬݝఠဟᒩᄰਭYUBM3ୣഗẮၒྜྷLjᐌവᒗHOEă 32 XTAL2 ᄏၒྜྷ3ăభᅪݬݝఠဟᒩୣഗẮདࣅYUBM3ă — EP ൡăᏢࡵ࢟വށࡼۇLjጲۣᑺᑵޟᔫă ```````````````````````````````` ሮᇼႁී 426NI{Ă456NI{ਜ਼544/:3NI{ࡼDNPT၃खNBY8141 ଝጙቋᅪݝᏄୈ૾భ৩߅࠭ᄖሣࡵၫᔊၫాࡼᅲ ᑳख႙ਜ਼၃വăকୈᓜ᎖၃ख BTL ၫăჅᎌ ख႙ຫൈ࣒ဵᎅጙৈ᎖ॊၫOॊຫࡼ߅ޘညLjభ gYUBM051:7ࡼޟऻޠݛறᇼࢯᑳຫൈă၃۾ᑩᎅጙৈ ࠅᄻࡼ᎖ᑳၫOॊຫࡼ߅ޘညăᄰਭኡᐋᏄୈLjၫ ࠅၒႥൈభጲࡉ44lcqt )ൺႅᄂ൩*77lcqt )OS[൩*ă ၃૦ ࢅᐅह)MOB* MOB ဵጙৈೊहࡍLjຢᅪ࢟ঢၱି࢟വLjభጲ ᄋࡍᏖ41eCࡼ࢟ኹᐐፄLjকᐐፄན᎖MOBၒྜྷ࣡ࡼ ᄖሣປᆀਜ਼MOBၒ߲࣡Ꭷຫၒྜྷ࣡ᒄମࡼMDቕ ᑩᆀă ຢᅪ࢟ঢၱି࢟വᄰਭᏴ MOBTSD ਜ਼ HOE ᒄମೌጙৈ ࢟ঢဣሚăক࢟ঢᒙ MOBJO ၒྜྷᔜఝࡼဣݝLjభഉ ປࢅၒྜྷᔜఝࡼQDCࡒᓨᄖሣăࡩၒྜྷᔜఝᆐ61ΩဟLj ক࢟ঢࡼ߂ܪᒋᏴ 426NI{ ဵ 23oILjᏴ 545NI{ ဵ 21oILj ࡣဵক࢟ঢથ၊QDCᔓሣࡼࣞޠ፬ሰăMOBTSDభጲ ࡵLjᐐଝࡍᏖ2eCࡼഉැࣞLjࡣၒྜྷᔜఝປܘኍᒮቤ ᎁછă 12 ೌࡵ MOBPVU ࡼ MD ቕᑩ݆ᎅ M6 ਜ਼ D: ᔝ߅)ݬ࢜ ቯ።࢟വ *ăᄰਭኡᐋM6ਜ਼D:ࡼᒋLjభጲቕᑩᏴჅገཇ ࡼSGၒྜྷຫൈࠀăকቕᑩຫൈᎅሆါ߲ǖ f= 1 2π L TOTAL × C TOTAL ᒦ Lj M U P U B M = M 6 , M Q B S B T J U J D T LjD U P U B M = D : , DQBSBTJUJDTă MQBSBTJUJDT ਜ਼DQBSBTJUJDT ۞౪QDCᔓሣĂॖᓤ୭Ăຫ ၒྜྷᔜఝਜ਼ࢅᐅहၒ߲ᔜఝࢀޘညࡼ࢟ঢਜ਼࢟ྏăᑚ ቋည።ᏴຫဟݙถۻLjభถ્࣪ቕᑩ݆ ࡼᒦቦຫൈޘညݙభᎾᒀࡼ፬ሰLjܘኍᄰਭဣዩᎁછቕ ᑩᒦቦຫൈăᔐည࢟ྏᒋᄰޟᏴ6qGࡵ8qGᒄମă ᔈࣅᐐፄ఼ᒜ)BHD* ࡩBHDဧถဟLjପހSTTJࡼၒ߲ăࡩSTTJࡼၒ߲ࡉࡵ 2/39WဟLj࣪።᎖ຫၒྜྷൈࡉࡵࡍᏖ.66eCnLjBHDࡌ ఎࢅᐅहᐐፄၱିăকၱିဧMOBࡼᐐፄି47eCLj ࠭ऎဧ STTJ ࡼၒ߲࢟ຳଢ଼ࢅ 651nW ࡵ 851nWăྦᏴጙࣤ భࡼ߈ܠBHDᓘഔဟମ)ݬܭ2*ମดLjSTTJၒ߲࢟ຳ ဪᒫࢅ᎖791nWጲሆ)Ꮦ.6:eCnຫၒྜྷ*LjᐌࢅᐅहMOB ૂআᐐፄෝါăBHD ࡍᏖᎌ 5eC ࡼᒣૄăBHD ᐐଝ೫ STTJࡼࣅზपᆍLjᏴຫၒྜྷࡉ1eCnLj༦ࢯᒜࣞᆐ 29eCဟLjNBY8141ጞถޘညభణࡼBTLၒ߲ăBHDݙ ဵܘኊࡼLjభጲۻਈࢬ)ܭ2*ă ______________________________________________________________________________________ ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ AGC2 AGC1 AGC0 DESCRIPTION 0 0 0 AGC disabled, high gain selected 0 0 1 K = 11 0 1 0 K = 13 0 1 1 K = 15 1 0 0 K = 17 1 0 1 K = 19 1 1 0 K = 21 1 1 1 K = 23 K ? 3.3 x log10 (500μs x 12.679) ≈ 12.546 ኡᐋBHD୭LjဧLᆐࡍ᎖23/657ࡼሆጙৈໜၫᒋLjጐ ဵ24ă૾ǖBHD2ۻᒙᆐLjBHD1ਜ਼BHD3ۻᒙᆐࢅă BHDᓘഔဟମᒙ Ᏼൈሆଢ଼ࡵ BHD ༤ધඡሢઁLjBHD ᓘഔࢾဟဧ BHD ᏴჅᒙࡼဟମดۣߒࢅᐐፄᓨზăᏴকᒙဟମ ᒄઁLjྙਫൈጞࢅ᎖BHD༤ધඡሢLjᐌMOBྜྷ ᐐፄᓨზăᑚ࣪᎖ BTL ႁऻޟᒮገLjፐᆐࢯۻᒜࡼၫ ࡼ࢟ຳభถ᎖ඡሢLjऎࢅ࢟ຳࢅ᎖ඡሢLjྙਫ ᎌᓘഔࢾဟLj્ࡴᒘBHDᏴඛጙᆡनআ༤ધă NBY8141 ಽྯৈ BHD఼ᒜ୭)BHD1ĂBHD2ĂBHD3* ᒙ໕ৈઓ఼ᒜࡼᓘഔࢾဟăBHD ࡼᓘഔဟମဵ ᎅᄏຫൈਜ਼ BHD ఼ᒜ୭ࡼᒙࢾăభጲጲሆ ါଐႯᓘഔဟମǖ Dwell Time = ᓘഔဟମ ࣪᎖ൺႅᄂ൩)61%ᐴహ*܈Ljᓘഔဟମᒗ።ᒙᆐᆡ ᒲ໐ࡼೝ۶ă࣪᎖ݙਙഃ)OS[*ၫLjᓘഔဟମ።ᒙᆐ ࡍ᎖21 ᔊ९ࠈࡼᔢޠᒲ໐ăಿྙLjݧൺႅᄂ൩Ᏼ 426NI{! )gYUBM! = 23/78:NI{*LjၫႥൈᆐ3lcqt! )ᆡᒲ໐ = 361μt*ဟLjᓘഔဟମኊገࡍ᎖611μtǖ 2K fXTAL Lᆐ22ࡵ34ᒄମࡼလᒜໜၫLjဵᎅܭ2Ⴥာࡼ఼ᒜ୭ ᒙࢾࡼă భሆါଐႯLᒋLjན܈ଐႯஉਫࡍࡼᔢதࡼໜၫǖ L!? 4/4!y!mph21 )ᓘഔဟମ y!gYUBM* ຫ NBY8141 ဵጙৈຫጴᒜຫăဏབྷ೫ࣶ።ᒦڜ ਣࡼ༄࣡TBX݆ăݙဧTBX݆ࡼੑࠀᏴ᎖ᐐ ଝ೫ഉැࣞLj଼છ೫ᄖሣປLjஂဏ೫ۇహମ݀ଢ଼ࢅ ೫߅۾ă ຫᏄဧጙ࣪ၷຳੰຫڳၒྜྷSGቧᒇሆ ܤຫ߅21/8NI{ࡼᒦຫ)JG* JRቧLj݀༦ݧࢅ࣡ᓖྜྷ)૾ gMP = gSG .! gJG *ăຫጴᒜ࢟വᔝᑚቋቧLjᏴᑳৈᆨ ࣞपᆍดဣሚ 57eC ࡼ࢜ቯຫጴᒜăݧࢅ࣡ᓖྜྷဵᎅ ᎖ຢดຫጴᒜݙᑽߒ࣡ᓖྜྷăᒦຫၒ߲ᎅጙৈᏎ ৌႲདࣅLjۻມᒙᆐདࣅ441ΩᔜఝLjጲೌຢᅪ441Ω ࡼჿࠣᒦຫ݆ăདࣅጙৈ441ΩঌᏲࡼ࢟ኹܤધᐐፄ ࡍᏖᆐ31eCăᓖፀNJYJO,ਜ਼NJYJO.ၒྜྷᏴถ࣒ဵጙ ዹࡼă ᑳၫOॊຫჄሤણ)QMM* NBY8141 ಽጙৈৼࢾࡼᑳၫ O ॊຫ QMM ޘည၃۾ ᑩăჅᎌࡼQMMᏄୈLj۞౪ણവ݆Ăኹ఼ᑩĂ࢟ ܃Ăፊݛ35۶ॊຫਜ਼ୂሤ࣒ૹ߅Ᏼຢดăણവࡒ ࡍᏖᆐ611lI{ăSGĂJGਜ਼ݬఠຫൈࡼਈᇹྙሆჅာǖ fREF = (fRF - fIF)/24 ______________________________________________________________________________________ 13 NBY8141 ܭ2/! NBY8141ࡼBHDᓘഔဟମᒙ NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ ᒦຫ)JG* ᒦຫࡼ 441Ω ތॊঌᏲປຢᅪჿ݆ࠣăดݝ 7ৈୣഗẮሢ७हࡍޘညᏖ76eCࡼᔐᐐፄLjࡒᄰ݆ ᒦቦຫൈᆐ 21/8NI{ ࡼᒦຫຫൈLj4eC ࡒᏖ 21NI{ă ࣪᎖ BTL ၫLjSTTJ ࢟വᒦຫஊࢯࡵࡒLjޘညጙৈ ᑵ܈᎖ᒦຫቧ࢟ຳࡼ࣪ၫᒋĂ܈ಿᏖᆐ26nW0eCࡼᒇഗ ၒ߲ă ၫ݆ ᎖ஊࢯၫࡼ݆ဵ 3 ࢅᄰ Tbmmfo.Lfz ݆ă ࢛ᆡᒙᎅೝৈຢด࢟ᔜਜ਼ೝৈᅪྏ࢟ݝࢾăᄰਭࢯᑳ ᅪࡍࡼྏ࢟ݝቃభৎখਅ࢛ຫൈLjጲ࣪ݙᄴၫႥൈ ቲᎁછăጲ lI{ ܭာࡼਅ࢛ຫൈ።ᒙᆐጲ lcqt ܭာࡼĂ ᔢൺႅᄂၫख႙Ⴅൈࡼ4۶)ᔢOS[ၫख႙Ⴅൈ ࡼ2/6۶*ăۣߒਅ࢛ຫൈதၫႥൈభጲጴᒜຫᐅဉLj ᐐࡍ၃૦ࡼഉැࣞă ᅄ2Ⴥာࡼஉ৩భጲޘညگᄂᆼᓼ۴ྭऑሰ።ăگᄂᆼ ᓼ݆ᎌऻޟຳუࡼᄰࡒ७ຫᄂቶLjೝ࢛݆ થభޘညඛလ۶ຫ߈ 51eC ࡼਦଢ଼ă۴ྭऑ݆ᎌሣ ቶሤᆡሰ።Ljးၫᔊၫ݆ăဧሆෂࡼါଐႯ ࢟ྏᒋLjሤਈࡼᇹၫྙܭ3Ⴥာă ၫሢ७ ၫሢ७ளਭၫ݆ࡼෝผၒ߲ᓞધ߅ၫᔊቧă ಽጙৈ୷܈୷܈ෝผၒྜྷਜ਼ඡሢ࢟ኹဣሚăඡሢ ࢟ኹᎅET.୭ࡼ࢟ኹࢾLjࡵೌۻၫሢ७୷܈ ࡼनሤၒྜྷă ੪ࣶஉ৩࣒భޘညၫሢ७ඡሢᒋăಿྙLjᅄ3Ⴥာࡼ ࢟വஞဧጙৈ࢟ᔜਜ਼ጙৈ࢟ྏăᑚৈஉ৩݆࣪ෝ ผၒ߲ቲຳLj݀ඡሢᒋᆐক७ࣞࡼ61%ăಽᑚ ৈஉ৩Ljࡩෝผቧܤછဟඡሢᒋ્ᔈࣅࢯᑳLjଢ଼ࢅޘ ညၫᇙࡼތభถቶăSਜ਼D፬ሰඡሢᒋৌᔍෝผቧ७ ࣞࡼႥࣞă።ཀྵۣ SD ࢟വࡼਅ࢛ຫൈᏐࢅ᎖)ࡍগ 21 ۶* ᔢࢅၫႥൈă Ᏼᑚৈஉ৩ᒦLjጙ ࠈޠOS[ ܠ൩ࡼ 1 2భถဧඡሢᒋມ ጤăྙਫဧൺႅᄂ൩กዹࡼᎌሤᄴၫ 1 ਜ਼ 2 ࡼܠ ൩ऱښLjᑚৈஉ৩భखિৎੑࡼᔫă ᅄ4Ⴥာᆐಽࢅख़ᒋଶ݆ޘညඡሢᒋࡼஉ৩ăᑚৈ உ৩భඡሢᒋᒙᆐၫ݆ၒ߲ᒦ࢛ă b a(100kΩ)(π)(fc ) a CF2 = 4(100kΩ)(π)(fc ) MAX7030 CF1 = RSSI 100kΩ gD ဵಯሯࡼ4eCਅ࢛ຫൈă DS+ OP+ ಿྙLjኡᐋጙৈਅ࢛ຫൈᆐ6lI{ࡼگᄂᆼᓼ݆ǖ 1.000 ≈ 450pF (1.414)(100kΩ)(3.14)(5kHz) 1.414 CF2 = ≈ 225pF (4)(100kΩ)(3.14)(5kHz) CF1 = ኡᐋܪᓰࡼ࢟ྏᒋLjDG2 ᆐ581qGLjDG3 ᆐ331qGăᏴ࢜ቯ። ࢟വ ᒦLjDG2 ਜ਼DG3 ॊܰD27ਜ਼D28ܭာă 14 CF2 100kΩ DF CF1 ᅄ2/! ! Tbmmfo.Lfzࢅᄰၫ݆ ܭ3/! ଐႯDG2 ਜ਼DG3 ᇹၫ FILTER TYPE a b Butterworth (Q = 0.707) 1.414 1.000 Bessel (Q = 0.577) 1.3617 0.618 ______________________________________________________________________________________ ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ NBY8141 MAX7030 MAX7030 DATA SLICER DS- DATA DS+ PEAK DET PEAK DET DATA SLICER R C DATA PDMAX R C ᅄ3/! ࢅᄰ݆ޘညၫሢ७ඡሢ ख़ᒋଶ݆ ᅄ 4 Ⴥာᆐࡒᎌ࢟ᔜĂ࢟ྏࡼᔢࡍख़ᒋଶ݆)QENBY* ਜ਼ᔢቃख़ᒋଶ݆)QENJO*Ljޘညࡼᒇഗၒ߲࢟ኹࢀ᎖ள ਭ݆ࡼஊࢯቧࡼࢅख़ᒋă࢟ᔜᄋ೫࢟ྏࡼह࢟ ᅆLjᏤख़ᒋଶ݆ࣅზৌႲၫ݆ၒ߲ࡼ࢟ኹख़ ᒋܤછă ဧᔢਜ਼ᔢࢅख़ᒋଶ݆ޘညጙৈᆡ᎖ၫഗᔢਜ਼ ᔢࢅ࢟ຳᒦ࢛ࡼၫሢ७ඡሢ)ݬఠၫሢ७ ݝॊਜ਼ ᅄ 4*ăख़ᒋଶ݆ᆀSDဟମޟၫ።ᒗᒙᆐၫᒲ ໐ࡼ6۶ă ྙਫ BHD ᐐፄ༤ધ࢟ࢀᅃखူୈဧࡒቧ७ࣞޘ ညመᓎܤછLjख़ᒋଶ݆భถ્ݔᓱࡵࡇᇙ࢟ຳăྙਫ ଶࡇࡵހᇙࡼख़ᒋLjᐌሢ७࢟ຳݙᑵཀྵăࡩ BHD ᓨზܤ છဟLjNBY8141 ख़ᒋଶ݆భጲဟৌᔍࡒ݆ࡼ ၒ߲࢟ኹኀᑵᑚৈᆰᄌǗጐభጲᄰਭဧถ୭ᎅࢅ࢟ຳ ᒗ࢟ຳࡼᄢܤU0Rᎅ࢟ຳᒗࢅ࢟ຳࡼᄢܤ༓ख़ᒋ ଶހৌᔍࡒ݆ࡼၒ߲࢟ኹLjᒇᒗჅᎌด࢟ݝവ ᆮࢾăख़ᒋଶހܭሚᆐႥߡૣ0ࢅႥၱିሰ።Ljး ᎖Ⴅࣅਜ਼BHDૂআă PDMIN R C ᅄ4/! ! ख़ᒋଶ݆ޘညၫሢ७ඡሢ ሣᔜఝᓞધᆐQBPVU )୭6*ࡼᔢଛᔜఝăQBPVUࡼᔢଛ ᔜఝᆐ361Ωă ࡩၒ߲ᆀᑵཀྵປဟLjQB ᔐൈࡉ 43%ăह۾ ࡼൈࡍ᎖57%ăၒ߲ൈᎅQBPVUࠀࡼᅪ࢟ݝᔜࢾLj ጐན᎖ᅪݝᄖሣਜ਼QBၒ߲ࡼᄖሣປᆀă ۞ࢯᑳ NBY8141ดݝᎌ۞ࢯᑳ࢟ᔜLjᏴQBࡼധఎവ ၒ߲ਜ਼࢟Ꮞᒄମ)ݬ࢜ቯ።࢟വ *ăᏴBTLෝါሆ۞ ࢯᑳ࢟ᔜିદ೫QBࡼఎਈਭ߈LjဧࢯᒜࡼQBၒ߲ቧᎌ ୷ᐥࡼຫໍࡒă ॊၫOॊຫჄሤણ)QMM* NBY8141ጙৈᅲཝૹ߅ࡼॊၫOॊຫჄሤણᔫᆐखຫ ൈ߅ăჅᎌࡼჄሤણᏄୈLj۞౪ણവ݆Lj࣒Ᏼ በຢดݝăણവࡒࡍᏖᆐ311lI{ă ࢟Ꮞೌ ख႙ ൈहࡍ)QB* NBY8141 ࡼहဵĂധఎവĂఎਈෝါहࡍă हᎧးࡩࡼၒ߲ປᆀถདࣅݙᄴᔜఝࡼᄖሣLj۞ ౪QDCણተᄖሣ61Ωᄖሣă61Ωᄖሣࡼၒ߲ປᆀ༿ ݬ ࢜ቯ።࢟വ ăၒ߲ປᆀጴᒜᏲ݆ቕ݆݀ᄖ NBY8141భᎅ3/2Wᒗ4/7W࢟Ꮞ࢟Ljጐభᎅ5/6Wᒗ6/6W ࢟Ꮞ࢟ăྙਫဧ 5/6W ᒗ 6/6W ࢟ᏎLjበຢดࡼሣቶᆮ ኹ્ڳ6Wၒྜྷܤᆐበຢᔫኊገࡼ4Wă ྙNBY8141Ᏼ4W࢟ᏎሆᔫLjQBWEEĂBWEEĂEWEE ਜ਼ IW JO ೌࡵ 4W ࢟Ꮞăဧ 6W ࢟ᏎဟLjஞ IW JO ࢟ᏎLj ڳBW EE ĂQBW EE ਜ਼ EW EE ೌᏴጙăᏴᑚೝᒬ༽ౚሆLj ______________________________________________________________________________________ 15 gQ ᆐᄏຫൈࡼᒋLjᆡᆐqqnă Dn ᆐᄏࡼࣅზ࢟ྏă DDBTF ᆐఫ࢟ྏă DTQFD ᆐਖࢾঌᏲ࢟ྏă DMPBE ᆐဣଔঌᏲ࢟ྏă ࡩᄏঌᏲ࢟ྏ൸ᔗਖࢾገཇLj૾ǖDMPBE = DTQFDLj ຫൈᆐ1ă ``````````````````````````````````` ୭ᒙ N.C. DF OP+ DS+ DS- TOP VIEW T/R 24 23 22 21 20 19 18 17 N.C. 25 16 PDMAX DVDD 26 15 PDMIN IFIN+ HVIN 27 14 AGC2 28 13 IFIN- AGC1 29 12 MIXOUT MAX7030 MIXIN- 10 MIXIN+ XTAL2 32 9 LNAOUT + 1 2 3 4 5 6 7 8 LNASRC 11 31 LNAIN 30 AVDD AGC0 XTAL1 PAOUT NBY8141ࡼYUBMᑩᏴYUBM2ਜ਼YUBM3୭ᒄମࢀ ᆐᏖ4qGࡼ࢟ྏăᏴࡍࣶၫ༽ౚሆLjఠQDCည።Lj ሤࡩ᎖ଝࡵᅪݝᄏ5/6qGࡼঌᏲ࢟ྏăኡᐋࡼᄏঌ Ᏺ࢟ྏ።ࢀ᎖ NBY8141 ᄏᑩ࢟ྏଝ QDC ည࢟ ྏLjᑚጙ࢛੪ᒮገăྙਫᄏࡼঌᏲ࢟ྏݙถ൸ᔗገཇLj กඐᑩຫൈມጤ߂ܪᔫຫൈLjᐆ߅ݬఠဟᒩຫൈ ᇙތăဧৎঌᏲ࢟ྏࡼᄏဟLjݬఠဟᒩຫൈᔐဵ ۻ౯ă ᒦ; TX/RX2 ᄏᑩ)YUBM* ⎞ Cm ⎛ 1 1 − x 106 ⎜ 2 ⎝ CCASE + CLOAD CCASE + CSPEC ⎟⎠ TX/RX1 ఎਈᓨზᎅU0R୭఼ᒜ)33୭*ăU0R୭ᆐ࢟ຳဟ ୈྜྷख႙ෝါǗU0R୭ᆐࢅ࢟ຳဟୈྜྷ၃ෝါă fP = ENABLE NBY8141 ดᒙ TQTU! SG ఎਈLjᄰਭဧጙቋᅪݝᏄୈLj Ꮴख႙ਜ਼၃୭ৢጙৈᄖሣ)ݬ࢜ቯ።࢟വ *ă Ᏼ၃ෝါLjఎਈࡌఎLjहਈܕLj߆ሚᔜLjጲဧMOB ঌᏲିࡵᔢቃăᏴख႙ෝါLjఎਈܕLjᏴQBၒ߲࣡ተ ߅ጙৈቕᑩݹവLjMOB ၒྜྷ࣡ SG വăᏴᑚᒬෝါሆLj ᅪࡼݝᇄᏎୈQBၒ߲ẮࡵᄖሣLj݀భܜMOBၒ ྜྷ၊୷༓ख႙ቧࡼ፬ሰă ྙਫᄏሤਈݬၫጯᒀLjऄᅪࡼభጲۻଐႯ߲ă ຫൈᎅሆါଐႯǖ ROUT ख႙0၃ᄖሣఎਈ ဣଔLjᄏᔐ્၊ᑩăፐࠥLjᄏৼᎌຫൈ ્ࢅ᎖ਖࢾຫൈăࡣྙਫঌᏲ࢟ྏ൸ᔗገཇLjᄏ્ۻ ࡵᒎࢾຫൈăᏴਖࢾᄏঌᏲ࢟ྏဟጯఠ೫ᑚᒬ ă DATA EW EE ĂIW JO ਜ਼ QBW EE ᄰਭ 1/12μG ਜ਼ 331qG ࢟ྏവࡵ HOELjBW EE ᄰਭ 1/2μG ਜ਼ 331qG ࢟ྏവᒗ HOEăU0RĂ FOBCMFĂEBUB ਜ਼ BHD1.3 21qG ࡼ࢟ྏവᒗ HOEă Ⴥᎌവ࢟ྏభถణதሤ።୭ă PAVDD NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ THIN QFN 16 ______________________________________________________________________________________ ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ NBY8141 ܭ4/! ࢜ቯ።࢟വࡼᏄୈᒋ COMPONENT VALUE FOR 433.92MHz RF VALUE FOR 315MHz RF DESCRIPTION C1 220pF 220pF 10% C2 680pF 680pF 10% C3 6.8pF 12pF 5% C4 6.8pF 10pF 5% C5 10pF 22pF 5% C6 220pF 220pF 10% C7 0.1μF 0.1μF 10% C8 100pF 100pF 5% C9 1.8pF 2.7pF ±0.1pF C10 100pF 100pF 5% C11 220pF 220pF 10% C12 100pF 100pF 5% C13 1500pF 1500pF 10% C14 0.047μF 0.047μF 10% C15 0.047μF 0.047μF 10% C16 470pF 470pF 10% C17 220pF 220pF 10% C18 220pF 220pF 10% C19 0.01μF 0.01μF 10% C20 100pF 100pF 5% C21 100pF 100pF 5% C22 220pF 220pF 10% C23 0.01μF 0.01μF 10% C24 0.01μF 0.01μF 10% L1 22nH 27nH Coilcraft 0603CS L2 22nH 30nH Coilcraft 0603CS L3 22nH 30nH Coilcraft 0603CS L4 10nH 12nH Coilcraft 0603CS L5 16nH 30nH Murata LQW18A L6 68nH 100nH Coilcraft 0603CS R1 100kΩ 100kΩ 5% R2 100kΩ 100kΩ 5% R3 0Ω 0Ω — Y1 17.63416MHz 12.67917MHz Crystal, 4.5pF load capacitance Y2 10.7MHz ceramic filter 10.7MHz ceramic filter Murata SFECV10.7 series ᓖፀǖᏄୈᒋ၊QDCۇݚ፬ሰă ______________________________________________________________________________________ 17 ```````````````````````````````````````````````````````````````````````` ࢜ቯ።࢟വ AGC0 AGC1 AGC2 VDD Y1 VDD 27 26 25 N.C. 28 DVDD 29 HVIN PAVDD 30 AGC2 1 31 AGC1 32 AGC0 VDD XTAL1 C23 C24 C19 C18 C20 C21 XTAL2 3.0V 2 24 DATA C22 ROUT R3* C1 4 L1 5 VDD 6 C5 OP+ 19 C17 C6 8 L4 LNAIN LNASRC 9 11 10 C10 12 C12 C9 13 C13 14 15 PDMAX DS+ 7 PDMIN L6 IFIN+ L3 EXPOSED PAD AVDD IFIN- C7 C8 20 DF PAOUT MIXOUT C4 C3 21 N.C. MAX7030 TX/RX2 MIXIN- L2 TRANSMIT/ RECEIVE TX/RX1 MIXIN+ C2 ENABLE 22 T/R 3 DATA 23 ENABLE LNAOUT NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ DS- 16 C16 18 17 R1 C15 VDD L5 IN GND C11 R2 OUT Y2 C14 *OPTIONAL POWER-ADJUST RESISTOR `````````````````````````````````` በຢቧᇦ ``````````````````````````````` ॖᓤቧᇦ PROCESS: CMOS ྙኊᔢதࡼॖᓤᅪተቧᇦਜ਼ݚLj༿އኯ china.maxim-ic.com/packagesă 18 ॖᓤಢቯ ॖᓤܠ൩ ᆪܠ 32୭ۡቯQFN-EP T3255-3 21-0140 ______________________________________________________________________________________ ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ LNAOUT MIXIN+ MIXIN9 10 MIXOUT IFIN+ IFIN- 12 14 13 11 IF LIMITING AMPS 0° LNAIN 7 LNASRC 8 LNA Σ 90° I Q RSSI 20 DF 100kΩ 19 OP+ RX FREQUENCY DIVIDER XTAL1 DATA FILTER 18 DS+ 31 CRYSTAL OSCILLATOR XTAL2 100kΩ RX VCO PHASE DETECTOR 32 TX FREQUENCY DIVIDER 15 PDMIN CHARGE PUMP 16 PDMAX TX VCO HVIN 27 3.0V REGULATOR LOOP FILTER 17 DSRX DATA AVDD 6 EXPOSED PAD MAX7030 30 AGC0 PA 29 AGC1 DIGITAL LOGIC 28 AGC2 24 DATA 2 1 5 3 4 22 26 23 ROUT PAVDD PAOUT TX/RX1 TX/RX2 T/R DVDD ENABLE ______________________________________________________________________________________ 19 NBY8141 ```````````````````````````````````````````````````````````````````````````````` ถౖᅄ NBY8141 ࢅ߅۾Ă426NI{Ă456NI{ਜ਼544/:3NI{ BTL၃खLjࡒᎌॊၫOॊຫჄሤણ ```````````````````````````````````````````````````````````````````````````` ኀࢿ಼ဥ ኀࢿ ኀࢿ྇໐ ႁී ኀখ 0 5/05 ᔢ߱۾ۈă — 1 9/08 ඛৈୈቯᄗଝ,Ljܭာᇄ0९SpITܪᓰࡼॖᓤǗීཀྵᒎ߲೫ᄂၐຫൈ ୈࡼૡᓨౚ༿Ꭷޣೊᇹă 1 2 6/09 ৎᑵ೫ൈहࡍ)QB*ݝॊă 15 Nbyjn ۱யࠀူێ ۱ய 9439ቧረ ᎆᑶܠ൩ 211194 ॅ࢟જǖ911!921!1421 ࢟જǖ121.7322 62:: ࠅᑞǖ121.7322 63:: Nbyjn࣪ݙNbyjnޘອጲᅪࡼྀੜ࢟വဧঌᐊLjጐݙᄋᓜಽభăNbyjnۣഔᏴྀੜဟମĂᎌྀੜᄰۨࡼ༄ᄋሆኀখޘອᓾ೯ਜ਼ਖৃࡼཚಽă 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Nbyjn ဵ Nbyjn!Joufhsbufe!Qspevdut-!Jod/ ࡼᓖݿܪă MAX7030 低成本、315MHz、345MHz和433.92MHz ASK收发器,带有N分频PLL - 概述 ENGLISH • 简体中文 • 日本語 • 한국어 • РУССКИЙ Login | Register 最新内容 产品 方案 设计 应用 技术支持 销售联络 公司简介 我的Maxim Maxim > 产品 > 无线与射频(RF) > MAX7030 Maxim > 产品 > 汽车电子 > MAX7030 MAX7030 低成本、315MHz、345MHz和433.92MHz ASK收发器,带有N分频PLL 概述 技术文档 定购信息 相关产品 用户说明 (0) 所有内容 状况 状况:生产中。 概述 数据资料 MAX7030是基于晶振的分数N型收发器,设计用于在工厂预置的载波(频率 为315MHz、345MHz†或433.92MHz)上发送和接收ASK/OOK数据,速率高达33kbps (曼彻斯特编 码)或66kbps (NRZ码)。该器件可为50Ω负载提供+10dBm的典型输出功率,典型接收灵敏度为114dBm。MAX7030具有独立的发送和接收引脚(PAOUT和LNAIN),提供内部RF开关,用于发送、接 收引脚与共用天线的连接。 完整的数据资料 英文 下载 Rev. 2 (PDF, 232kB) 中文 下载 Rev. 2 (PDF, 728kB) MAX7030的发送频率由一个16位、分数N型锁相环(PLL)产生,接收器的本振(LO)频率则由整 数N型PLL产生。由于分数N型PLL的频率被预设到超过接收本振10.7MHz的频点,因而这种混合架构 无需为发送和接收通道提供单独的基准晶体振荡器。接收器部分保留固定N型PLL可避免分 数N型PLL的高电流消耗问题,将接收器电流降至最低。所有频率合成元件都集成在芯片内,外部只需 一个晶体、一个10.7MHz IF滤波器和几个分立元件即可构成完整的天线/数字数据方案。 MAX7030采用小尺寸、5mm × 5mm、32引脚薄型QFN封装,可工作在汽车级-40°C至+125°C温度范 围。 关键特性 应用/使用 单电源供电:+2.1V至+3.6V或+4.5V至+5.5V 单晶体收发器 工厂预置频率(无需串行接口) ASK/OOK调制 为50Ω负载提供+10dBm输出功率 内置TX/RX开关 内置发送和接收PLL、VCO和环路滤波器 > 45dB的镜频抑制比 典型RF灵敏度为*:-114dBm 可由外部滤波器选择IF带宽 < 12.5mA的发送模式电流 < 6.7mA的接收模式电流 < 800nA的关断电流 快速上电启动,< 250µs 小尺寸,32引脚、薄型QFN封装 通过美国保险商实验室协会(UL)认证 双向遥控钥匙 车库开门器 家庭自动化 本地遥感勘测系统 远端控制 遥感 安全系统 烟雾报警器 Key Specifications: ISM RF Transceivers Part Number Solutions Features Applications Freq. ISUPPLY (MHz) (mA) Footprint (mm x Package/Pins mm) Smallest Available Pckg. (mm 2 ) max w/pins MAX7030 Automotive ISM, RKE, SRD; 315433.92MHz Bands Remote Controls Remote Sensing Security Systems Smoke Alarms +10dBm Output Power into 50Ω Load +2.1V to +3.6V or +4.5V to +5.5V Single-Supply > 45dB Image Rejection ASK/OOK Modulation Factory-Preset Frequency Integrated Tx/Rx Switch Small, 5x5, 32-Pin, Thin QFN Package Typical RF Sensitivity: - http://china.maxim-ic.com/datasheet/index.mvp/id/4754[2010-12-10 7:01:48] AMR ISM Remote Controls 300 to Rx: <6.7 5.0 x 5.0 Remote 450 Tx <12.5 Sensing Security Systems Smoke Alarms TQFN/32 26 Industry Qualified Price See Notes Automotive $2.75 - General @1k MAX7030 低成本、315MHz、345MHz和433.92MHz ASK收发器,带有N分频PLL - 概述 114dBm 查看所有ISM RF Transceivers (11) Pricing Notes: This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor. †供货状况请与工厂联系。 *0.2% BER、4kbps曼彻斯特编码数据,280kHz IF BW。 图表 典型应用电路 更多信息 新品发布 [ 2005-06-09 ] 没有找到你需要的产品吗? 应用工程师帮助选型,下个工作日回复 参数搜索 应用帮助 概述 技术文档 定购信息 相关产品 概述 关键特性 应用/ 使用 关键指标 图表 注释、注解 数据资料 应用笔记 评估板 设计指南 可靠性报告 软件/ 模型 价格与供货 样品 在线订购 封装信息 无铅信息 类似功能器件 类似应用器件 评估板 类似型号器件 配合该器件使用的产品 http://china.maxim-ic.com/datasheet/index.mvp/id/4754[2010-12-10 7:01:48] MAX7030 低成本、315MHz、345MHz和433.92MHz ASK收发器,带有N分频PLL - 概述 参考文献: 19- 3706 Rev. 2; 2010- 03- 08 本页最后一次更新: 2010- 09- 09 联络我们:信息反馈、提出问题 • 对该网页的评价 • 发送本网页 • 隐私权政策 • 法律声明 © 2010 Maxim Integrated Products版权所有 http://china.maxim-ic.com/datasheet/index.mvp/id/4754[2010-12-10 7:01:48] 19-3706; Rev 3; 11/10 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL Features The MAX7030 crystal-based, fractional-N transceiver is designed to transmit and receive ASK/OOK data at factory-preset carrier frequencies of 315MHz, 345MHz†, or 433.92MHz with data rates up to 33kbps (Manchester encoded) or 66kbps (NRZ encoded). This device generates a typical output power of +10dBm into a 50Ω load and exhibits typical sensitivity of -114dBm. The MAX7030 features separate transmit and receive pins (PAOUT and LNAIN) and provides an internal RF switch that can be used to connect the transmit and receive pins to a common antenna. o +2.1V to +3.6V or +4.5V to +5.5V Single-Supply Operation The MAX7030 transmit frequency is generated by a 16bit, fractional-N, phase-locked loop (PLL), while the receiver’s local oscillator (LO) is generated by an integer-N PLL. This hybrid architecture eliminates the need for separate transmit and receive crystal reference oscillators because the fractional-N PLL is preset to be 10.7MHz above the receive LO. Retaining the fixed-N PLL for the receiver avoids the higher current-drain requirements of a fractional-N PLL and keeps the receiver current drain as low as possible. All frequencygeneration components are integrated on-chip, and only a crystal, a 10.7MHz IF filter, and a few discrete components are required to implement a complete antenna/digital data solution. o Integrated Transmit and Receive PLL, VCO, and Loop Filter The MAX7030 is available in a small, 5mm x 5mm, 32pin thin QFN package, and is specified to operate over the automotive -40°C to +125°C temperature range. *0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW o Single-Crystal Transceiver o Factory-Preset Frequency (No Serial Interface Required) o ASK/OOK Modulation o +10dBm Output Power into 50Ω Load o Integrated TX/RX Switch o > 45dB Image Rejection o Typical RF Sensitivity*: -114dBm o Selectable IF Bandwidth with External Filter o < 12.5mA Transmit-Mode Current o < 6.7mA Receive-Mode Current o < 800nA Shutdown Current o Fast-On Startup Feature, < 250µs o Small, 32-Pin, Thin QFN Package Ordering Information Applications 2-Way Remote Keyless Entry Security Systems Home Automation Remote Controls Remote Sensing Smoke Alarms PART TEMP RANGE MAX7030_ATJ+ -40°C to +125°C PIN-PACKAGE 32 Thin QFN-EP** +Denotes a lead(Pb)-free/RoHS-compliant package. **EP = Exposed pad. Note: The MAX7030 is available with factory-preset operating frequencies. See the Product Selector Guide for complete part numbers. Garage Door Openers Product Selector Guide Local Telemetry Systems PART CARRIER FREQUENCY (MHz) MAX7030LATJ+ 315 MAX7030MATJ+† 345 MAX7030HATJ+ 433.92 †Contact factory for availability. Pin Configuration, Typical Application Circuit, and Functional Diagram appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX7030 General Description MAX7030 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL ABSOLUTE MAXIMUM RATINGS HVIN to GND .........................................................-0.3V to +6.0V PAVDD, AVDD, DVDD to GND..............................-0.3V to +4.0V ENABLE, T/R, DATA, AGC0, AGC1, AGC2 to GND ........................................-0.3V to (HVIN+ 0.3V) All Other Pins to GND ..............................-0.3V to (_VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin Thin QFN (derate 21.3mW/°C above +70°C).............................................................1702mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VHVIN = VPAVDD = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VHVIN = VPAVDD = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage (3V Mode) VDD HVIN, PAVDD, AVDD, and DVDD connected to power supply 2.1 2.7 3.6 V Supply Voltage (5V Mode) HVIN PAVDD, AVDD, and DVDD unconnected from HVIN, but connected together 4.5 5.0 5.5 V Supply Current IDD Transmit mode, PA off, VDATA at 0% duty cycle (Note 2) fRF = 315MHz 3.5 5.4 fRF = 434MHz 4.3 6.7 Transmit mode, VDATA at 50% duty cycle (Notes 3, 4) fRF = 315MHz 7.6 12.3 fRF = 434MHz 8.4 13.6 Transmit mode, VDATA at 100% duty cycle (Note 2) fRF = 315MHz 11.6 19.1 fRF = 434MHz 12.4 20.4 Receiver 315MHz 6.1 7.9 Receiver 434MHz 6.4 8.3 Deep-sleep (3V mode) 0.8 8.8 Deep-sleep (5V mode) 2.4 10.9 Receiver 315MHz 6.4 8.2 Receiver 434MHz 6.7 8.4 Deep-sleep (3V mode) 8.0 34.2 Deep-sleep (5V mode) 14.9 39.3 TA < +85°C, typ at +25°C (Note 4) TA < +125°C, typ at +125°C (Note 2) Voltage Regulator VREG mA µA mA µA VHVIN = 5V, ILOAD = 15mA 3.0 V DIGITAL I/O Input-High Threshold VIH (Note 2) Input-Low Threshold VIL (Note 2) 2 0.9 x HVIN _______________________________________________________________________________________ V 0.1 x HVIN V Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VHVIN = VPAVDD = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VHVIN = VPAVDD = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Pulldown Sink Current CONDITIONS MIN AGC0-2, ENABLE, T/R, DATA (VHVIN = 5.5V) Output-Low Voltage VOL ISINK = 500µA Output-High Voltage VOH ISOURCE = 500µA TYP MAX 20 UNITS µA 0.15 V VHVIN - 0.26 V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Frequency Range Maximum Input Level PRFIN Transmit Efficiency 100% Duty Cycle Transmit Efficiency 50% Duty Cycle Power-On Time tON 315/345/ 433.92 MHz 0 dBm fRF = 315MHz (Note 6) 32 fRF = 434MHz (Note 6) 30 fRF = 315MHz (Note 6) 24 fRF = 434MHz (Note 6) 22 ENABLE or T/R transition low to high, transmitter frequency settled to within 50kHz of the desired carrier 200 ENABLE or T/R transition low to high, transmitter frequency settled to within 5kHz of the desired carrier 350 ENABLE transition low to high, or T/R transition high to low, receiver startup time (Note 5) 250 % % µs RECEIVER 0.2% BER, 4kbps Manchester data rate, 280kHz IF BW, average RF power Sensitivity 315MHz -114 434MHz -113 dBm Image Rejection 46 dB POWER AMPLIFIER Output Power POUT TA = +25°C (Note 4) TA = +125°C, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V (Note 2) TA = -40°C, VPAVDD = VAVDD = VDVDD = VHVIN = +3.6V (Note 4) Modulation Depth Maximum Carrier Harmonics Reference Spur With output-matching network 4.6 10.0 3.9 6.7 13.1 15.5 dBm 15.8 82 dB -40 dBc -50 dBc _______________________________________________________________________________________ 3 MAX7030 DC ELECTRICAL CHARACTERISTICS (continued) MAX7030 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER PHASE-LOCKED LOOP Transmit VCO Gain SYMBOL CONDITIONS KVCO Transmit PLL Phase Noise MIN TYP 340 10kHz offset, 200kHz loop BW -68 1MHz offset, 200kHz loop BW -98 Receive VCO Gain 340 Receive PLL Phase Noise Loop Bandwidth 10kHz offset, 500kHz loop BW -80 1MHz offset, 500kHz loop BW -90 Transmit PLL 200 Receive PLL 500 Reference Frequency Input Level 0.5 MAX UNITS MHz/V dBc/Hz MHz/V dBc/Hz kHz VP-P LOW-NOISE AMPLIFIER/MIXER (Note 8) LNA Input Impedance ZINLNA Normalized to 50Ω High-gain state Voltage-Conversion Gain Low-gain state Input-Referred, 3rd-Order Intercept Point IIP3 fRF = 315MHz 1 - j4.7 fRF = 434MHz 1- j3.3 fRF = 315MHz 50 fRF = 434MHz 45 fRF = 315MHz 13 fRF = 434MHz dB 9 High-gain state -42 Low-gain state -6 dBm Mixer-Output Impedance 330 Ω LO Signal Feedthrough to Antenna -100 dBm 330 Ω RSSI Input Impedance Operating Frequency 10.7 MHz 3dB Bandwidth fIF 10 MHz Gain 15 mV/dB Maximum Data-Filter Bandwidth 50 kHz Maximum Data-Slicer Bandwidth 100 kHz Maximum Peak-Detector Bandwidth 50 kHz ANALOG BASEBAND Maximum Data Rate 4 Manchester coded 33 Nonreturn to zero (NRZ) 66 _______________________________________________________________________________________ kbps Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL (Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 315MHz, 345MHz, or 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CRYSTAL OSCILLATOR Crystal Frequency fXTAL (fRF -10.7) /24 MHz 2 ppm/V 4.5 pF Frequency Pulling by VDD Crystal Load Capacitance Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: (Note 7) Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match. 100% tested at TA = +125°C. Guaranteed by design and characterization overtemperature. 50% duty cycle at 10kHz ASK data (Manchester coded). Guaranteed by design and characterization. Not production tested. Time for final signal detection; does not include baseband filter settling. Efficiency = POUT/(VDD x IDD). Dependent on PCB trace capacitance. Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degeneration from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series with ~2.2pF. The voltage conversion is measured with the LNA input-matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not include the IF filter insertion loss. Typical Operating Characteristics (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) RECEIVER 6.6 +85°C 6.4 6.2 +25°C 6.0 6.6 6.5 +85°C 6.4 6.1 5.6 6.0 2.7 3.0 SUPPLY VOLTAGE (V) +25°C 6.3 5.8 2.4 3.3 3.6 -40°C 18 MAX7030 toc03 +125°C 6.2 -40°C 2.1 MAX7030 toc02 6.7 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) MAX7030 toc01 +125°C 6.8 DEEP-SLEEP CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. RF FREQUENCY 6.8 16 DEEP-SLEEP CURRENT (μA) SUPPLY CURRENT vs. SUPPLY VOLTAGE 7.0 14 VCC = +3.6V 12 VCC = +3.0V 10 VCC = +2.1V 8 6 4 2 0 300 325 350 375 400 RF FREQUENCY (MHz) 425 450 -40 -15 -10 35 60 85 110 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX7030 AC ELECTRICAL CHARACTERISTICS (continued) Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) RECEIVER BIT-ERROR RATE vs. AVERAGE INPUT POWER 1.6 1.4 fRF = 434MHz 1 0.2% BER -111 1.0 0.8 AGC SWITCH POINT 0.6 -114 fRF = 315MHz 0.4 LOW-GAIN MODE -117 0.2 AGC HYSTERESIS: 3dB 0 -120 -115 -113 -111 -40 -15 50 2.5 40 1.5 30 1.2 0.5 0.9 -0.5 -1.5 DELTA 0.3 0 -90 -70 -50 -30 -10 DELTA (%) RSSI 3.5 SYSTEM GAIN (dBm) 1.8 0.6 -130 -110 110 10 -10 -3.5 -20 10 -50 -30 48 fRF = 433MHz 46 44 42 5 10 15 20 25 30 -40 -15 10 35 60 85 IF FREQUENCY (MHz) TEMPERATURE (°C) S11 vs. RF FREQUENCY S11 SMITH PLOT OF RFIN MAX7030 toc11 0 S11 (dB) 433MHz -12 433.92MHz -12 -18 -16 -20 400MHz -24 1 10 IF FREQUENCY (MHz) 100 10 fRF = 315MHz -6 -8 -10 LOWER SIDEBAND 0 MAX7030 toc10 -70 IMAGE REJECTION vs. TEMPERATURE 0 -2.5 -90 RF INPUT POWER (dBm) FROM RFIN TO MIXOUT fRF = 434MHz 48dB IMAGE REJECTION 20 NORMALIZED IF GAIN vs. IF FREQUENCY -4 85 UPPER SIDEBAND IF INPUT POWER (dBm) 0 60 SYSTEM GAIN vs. IF FREQUENCY MAX7030 toc07 1.5 35 TEMPERATURE (°C) RSSI AND DELTA vs. IF INPUT POWER 2.1 10 MAX7030 toc09 -117 AVERAGE INPUT POWER (dBm) IMAGE REJECTION (dB) -119 MAX7030 toc08 -121 200 250 300 350 400 450 110 MAX7030 toc12 0.01 6 HIGH-GAIN MODE 1.2 fRF = 434MHz RSSI (V) SENSITIVITY (dBm) BIT-ERROR RATE (%) 10 -108 MAX7030 toc06 -105 fRF = 315MHz RSSI (V) 1.8 MAX7030 toc05 MAX7030 toc04 -102 0.1 NORMALIZED IF GAIN (dB) RSSI vs. RF INPUT POWER SENSITIVITY vs. TEMPERATURE 100 500 RF FREQUENCY (MHz) _______________________________________________________________________________________ 500MHz Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL RECEIVER INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION -220 90 -230 80 MAX7030 toc14 -240 60 -250 50 -260 40 -270 REAL IMPEDANCE 20 10 1 -160 IMAGINARY IMPEDANCE 70 60 -180 50 -190 40 -200 -280 30 -290 20 100 REAL IMPEDANCE -220 MAX7030 toc15 fRF = 315MHz PHASE NOISE vs. OFFSET FREQUENCY -50 -70 -80 -90 -100 -110 fRF = 433MHz -60 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) 100 INDUCTIVE DEGENERATION (nH) PHASE NOISE vs. OFFSET FREQUENCY -60 -210 10 1 INDUCTIVE DEGENERATION (nH) -50 -170 MAX7030 toc16 30 REAL IMPEDANCE (Ω) REAL IMPEDANCE (Ω) IMAGINARY IMPEDANCE 70 IMAGINARY IMPEDANCE (Ω) fRF = 315MHz 80 -150 fRF = 434MHz IMAGINARY IMPEDANCE (Ω) MAX7030 toc13 90 -70 -80 -90 -100 -110 -120 -120 100 1k 10k 100k OFFSET FREQUENCY (Hz) 1M 10M 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) _______________________________________________________________________________________ 7 MAX7030 Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) TRANSMITTER SUPPLY CURRENT vs. SUPPLY VOLTAGE TA = +85°C TA = +125°C TA = -40°C TA = +25°C 10 5.0 TA = +125°C 4.5 TA = +85°C 4.0 3.5 3.0 3.0 2.4 TA = +125°C 5.0 TA = +85°C 4.5 4.0 3.0 3.3 3.6 2.1 TA = +25°C 10 9 PA ON 8 7 TA = -40°C 3.0 2.4 2.7 3.0 3.3 3.6 -6 -2 2 MAX7030 toc23-1 POWER 14 12 4 10 0 SUPPLY CURRENT (mA) CURRENT -10 2 16 12 8 4 CURRENT -8 -12 4 -16 2 10k POWER -4 6 1k MAX7030 toc23-2 8 -8 100 -2 0 6 fRF = 315MHz PA ON -6 -12 fRF = 433MHz PA ON -16 0.1 6 AVERAGE OUTPUT POWER (dBm) 10 -4 10 MAX7030 toc19 50% DUTY CYCLE -14 10 6 12 8 EXTERNAL RESISTOR (Ω) 8 SUPPLY CURRENT (mA) 8 OUTPUT POWER (dBm) 14 1 8 18 16 16 0.1 9 SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR 12 2 PA ON 10 AVERAGE OUTPUT POWER (dBm) SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR 4 11 5 -10 SUPPLY VOLTAGE (V) 16 3.6 6 -14 18 3.3 12 7 4 2.1 3.0 fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED 13 50% DUTY CYCLE 5 2.7 SUPPLY CURRENT vs. OUTPUT POWER 14 6 3.5 2.4 SUPPLY VOLTAGE (V) fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED 11 SUPPLY CURRENT (mA) fRF = 434MHz PA OFF 5.5 2.7 SUPPLY CURRENT vs. OUTPUT POWER 12 MAX7030 toc20 6.0 TA = +25°C SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. SUPPLY VOLTAGE TA = -40°C TA = +125°C 13 9 2.1 3.6 3.3 SUPPLY CURRENT (mA) 2.7 MAX7030 toc21 2.4 TA = +85°C TA = -40°C TA = +25°C 2.0 2.1 15 11 2.5 8 fRF = 434MHz PA ON WITHOUT ENVELOPE SHAPING MAX7030 toc22 14 12 fRF = 315MHz PA OFF 5.5 1 10 100 1k 10k EXTERNAL RESISTOR (Ω) _______________________________________________________________________________________ OUTPUT POWER (dBm) fRF = 315MHz PA ON WITHOUT ENVELOPE SHAPING SUPPLY CURRENT vs. SUPPLY VOLTAGE 17 SUPPLY CURRENT (mA) MAX7030 toc17 6.0 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 16 MAX7030 toc18 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT (mA) MAX7030 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL 10 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL TRANSMITTER TA = +125°C TA = +85°C 6 8 TA = +125°C TA = +85°C 6 2.7 3.0 3.3 2.4 OUTPUT POWER vs. SUPPLY VOLTAGE 3.0 MAX7030 25-2 fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED 12 fRF = 315MHz PA ON 2.1 3.6 2.4 TA = -40°C TA = +25°C 10 MAX7030 25-1 3.3 3.6 fRF = 434MHz PA ON TA = -40°C 35 TA = +85°C 25 TA = +125°C 3.0 EFFICIENCY vs. SUPPLY VOLTAGE 40 TA = +25°C 30 2.7 SUPPLY VOLTAGE (V) TA = -40°C 35 8 3.3 EFFICIENCY vs. SUPPLY VOLTAGE 40 EFFICIENCY (%) OUTPUT POWER (dBm) 2.7 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 14 TA = +125°C TA = +85°C 4 2.1 3.6 EFFICIENCY (%) 2.4 MAX7030 toc26 2.1 8 6 4 4 10 MAX7030 toc27 8 TA = +25°C 10 fRF = 434MHz PA ON ENVELOPE SHAPING DISABLED TA = -40°C TA = +25°C 12 OUTPUT POWER (dBm) 10 fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED TA = -40°C 12 OUTPUT POWER (dBm) OUTPUT POWER (dBm) TA = -40°C TA = +25°C 14 MAX7030 24-2 fRF = 315MHz PA ON ENVELOPE SHAPING DISABLED 12 14 MAX7030 24-1 14 OUTPUT POWER vs. SUPPLY VOLTAGE OUTPUT POWER vs. SUPPLY VOLTAGE OUTPUT POWER vs. SUPPLY VOLTAGE TA = +25°C TA = +85°C 30 25 TA = +125°C TA = +125°C TA = +85°C 20 20 2.7 3.0 3.3 2.1 3.6 2.4 SUPPLY VOLTAGE (V) TA = -40°C EFFICIENCY (%) EFFICIENCY (%) 3.3 TA = +25°C 20 TA = +85°C TA = +125°C fRF = 434MHz 50% DUTY CYCLE 25 TA = +25°C 20 2.7 3.0 3.3 3.6 3.3 3.6 -40 fRF = 315MHz -50 -60 -70 -80 -90 -100 -110 -130 15 SUPPLY VOLTAGE (V) 3.0 -120 TA = +125°C 10 2.7 PHASE NOISE vs. OFFSET FREQUENCY TA = +85°C 2.4 2.4 SUPPLY VOLTAGE (V) TA = -40°C 15 2.1 2.1 3.6 EFFICIENCY vs. SUPPLY VOLTAGE 30 MAX7030 toc28 fRF = 315MHz 50% DUTY CYCLE 25 3.0 SUPPLY VOLTAGE (V) EFFICIENCY vs. SUPPLY VOLTAGE 30 2.7 PHASE NOISE (dBc/Hz) 2.4 MAX7030 toc29 2.1 MAX7030 toc30 6 -140 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) _______________________________________________________________________________________ 9 MAX7030 Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encoded, 0.2% BER, TA = +25°C, unless otherwise noted.) TRANSMITTER REFERENCE SPUR MAGNITUDE vs. SUPPLY VOLTAGE PHASE NOISE vs. OFFSET FREQUENCY -70 -80 -90 -100 -110 -120 -45 MAX7030 toc32 -60 REFERENCE SPUR MAGNITUDE (dBc) fRF = 434MHz -50 -40 MAX7030 toc31 -40 PHASE NOISE (dBc/Hz) 434MHz -50 315MHz -55 -60 -65 -130 -70 -140 100 1k 10k 100k 1M 2.1 10M 2.4 2.7 3.0 SUPPLY VOLTAGE (V) OFFSET FREQUENCY (Hz) FREQUENCY STABILITY vs. SUPPLY VOLTAGE MAX7030 toc33 10 8 FREQUENCY STABILITY (ppm) MAX7030 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL 6 fRF = 434MHz 4 2 0 -2 fRF = 315MHz -4 -6 -8 -10 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) 10 ______________________________________________________________________________________ 3.3 3.6 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL PIN NAME 1 PAVDD FUNCTION Power-Amplifier Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close as possible to the pin. 2 ROUT Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as close as possible to the inductor with 680pF and 220pF capacitors, as shown in the Typical Application Circuit. 3 TX/RX1 Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect TX/RX1 from TX/RX2. Functionally identical to TX/RX2. 4 TX/RX2 Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit. 5 PAOUT Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope shaping is desired), which can be part of the output-matching network to an antenna. 6 AVDD 7 LNAIN Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation. Bypass AVDD to GND with a 0.1µF and 220pF capacitor placed as close as possible to the pin. Low-Noise Amplifier Input. Must be AC-coupled. 8 LNASRC Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set the LNA input impedance. 9 LNAOUT Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank filter. AC-couple to MIXIN+. 10 MIXIN+ Noninverting Mixer Input. Must be AC-coupled to the LNA output. 11 MIXIN- Inverting Mixer Input. Bypass to AVDD with a capacitor as close as possible to the LNA LC tank filter. 12 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz filter. 13 14 15 16 17 18 19 20 21, 25 IFINIFIN+ PDMIN PDMAX DSDS+ OP+ DF N.C. Inverting 330Ω IF Limiter-Amplifier Input. Bypass to GND with a capacitor. Noninverting 330Ω IF Limiter-Amplifier Input. Connect to the output of the 10.7MHz IF filter. Minimum-Level Peak Detector for Demodulator Output Maximum-Level Peak Detector for Demodulator Output Inverting Data Slicer Input Noninverting Data Slicer Input Noninverting Op-Amp Input for the Sallen-Key Data Filter Data-Filter Feedback Node. Input for the feedback capacitor of the Sallen-Key data filter. No Connection. Do not connect to this pin. 22 T/R Transmit/Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to put the device in receive mode. It is internally pulled down. 23 ENABLE Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into shutdown mode. 24 DATA Receiver Data Output/Transmitter Data Input 26 DVDD Digital Power-Supply Voltage. Bypass to GND with a 0.01µF and 220pF capacitor placed as close as possible to the pin. 27 HVIN High-Voltage Supply Input. For 3V operation, connect HVIN to AVDD, DVDD, and PAVDD. For 5V operation, connect only HVIN to 5V. Bypass HVIN to GND with a 0.01µF and 220pF capacitor placed as close as possible to the pin. ______________________________________________________________________________________ 11 MAX7030 Pin Description Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 Pin Description (continued) PIN NAME 28 AGC2 AGC Enable/Dwell Time Control 2 (MSB). See Table 1. Bypass to GND with a 10pF capacitor. FUNCTION 29 AGC1 AGC Enable/Dwell Time Control 1. See Table 1. Bypass to GND with a 10pF capacitor. 30 AGC0 AGC Enable/Dwell Time Control 0 (LSB). See Table 1. Bypass to GND with a 10pF capacitor. 31 XTAL1 Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference. 32 XTAL2 Crystal Input 2. XTAL2 can be driven from an external AC-coupled reference. — EP Exposed Pad. Solder evenly to the board’s ground plane for proper operation. Detailed Description The MAX7030 315MHz, 345MHz, and 433.92MHz CMOS transceiver and a few external components provide a complete transmit and receive chain from the antenna to the digital data interface. This device is designed for transmitting and receiving ASK data. All transmit frequencies are generated by a fractional-Nbased synthesizer, allowing for very fine frequency steps in increments of fXTAL/4096. The receive LO is generated by a traditional integer-N-based synthesizer. Depending on component selection, data rates as high as 33kbps (Manchester encoded) or 66kbps (NRZ encoded) can be achieved. Receiver Low-Noise Amplifier (LNA) The LNA is a cascode amplifier with off-chip inductive degeneration that achieves approximately 30dB of voltage gain that is dependent on both the antenna-matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs. The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to GND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible match for low-input impedances such as a PCB trace antenna. A nominal value for this inductor with a 50Ω input impedance is 12nH at 315MHz and 10nH at 434MHz, but the inductance is affected by PCB trace length. LNASRC can be shorted to ground to increase sensitivity by approximately 1dB, but the input match must then be reoptimized. 12 The LC tank filter connected to LNAOUT consists of L5 and C9 (see the Typical Application Circuit). Select L5 and C9 to resonate at the desired RF input frequency. The resonant frequency is given by: f= 1 2π L TOTAL × C TOTAL where LTOTAL = L5 + LPARASITICS and CTOTAL = C9 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PCB traces, package pins, mixerinput impedance, LNA-output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. The total parasitic capacitance is generally between 5pF and 7pF. Automatic Gain Control (AGC) When the AGC is enabled, it monitors the RSSI output. When the RSSI output reaches 1.28V, which corresponds to an RF input level of approximately -55dBm, the AGC switches on the LNA gain-reduction attenuator. The attenuator reduces the LNA gain by 36dB, thereby reducing the RSSI output by about 540mV to 740mV. The LNA resumes high-gain mode when the RSSI output level drops back below 680mV (approximately -59dBm at the RF input) for a programmable interval called the AGC dwell time (see Table 1). The AGC has a hysteresis of approximately 4dB. With the AGC function, the RSSI dynamic range is increased, allowing the MAX7030 to reliably produce an ASK output for RF input levels up to 0dBm with a modulation depth of 18dB. AGC is not required and can be disabled (see Table 1). ______________________________________________________________________________________ Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL AGC2 AGC1 AGC0 0 0 0 AGC disabled, high gain selected DESCRIPTION 0 0 1 K = 11 0 1 0 K = 13 0 1 1 K = 15 1 0 0 K = 17 1 0 1 K = 19 1 1 0 K = 21 1 1 1 K = 23 AGC Dwell-Time Settings The AGC dwell timer holds the AGC in low-gain state for a set amount of time after the power level drops below the AGC switching threshold. After that set amount of time, if the power level is still below the AGC threshold, the LNA goes into high-gain state. This is important for ASK since the modulated data may have a high level above the threshold and low level below the threshold, which without the dwell timer would cause the AGC to switch on every bit. The MAX7030 uses the three AGC control pins (AGC0, AGC1, AGC2) to set seven user-controlled, dwell-timer settings. The AGC dwell time is dependent on the crystal frequency and the bit settings of the AGC control pins. To calculate the dwell time, use the following equation: Dwell Time = 2K fXTAL where K is an odd integer in decimal from 11 to 23, determined by the control pin settings shown in Table 1. To calculate the value of K, use the following equation and use the next integer higher than the calculated result: K ≥ 3.3 x log10 (Dwell Time x fXTAL) For Manchester Code (50% duty cycle), set the dwell time to at least twice the bit period. For nonreturn-tozero (NRZ) data, set the dwell to greater than the period of the longest string of zeros or ones. For example, using Manchester Code at 315MHz (f XTAL = 12.679MHz) with a data rate of 2kbps (bit period = 250µs), the dwell time needs to be greater than 500µs: K ≥ 3.3 x log10 (500µs x 12.679) ≈ 12.546 Choose the AGC pin settings for K to be the next oddinteger value higher than 12.546, which is 13. This says that AGC1 is set high and AGC0 and AGC2 are set low. Mixer A unique feature of the MAX7030 is the integrated image rejection of the mixer. This eliminates the need for a costly front-end SAW filter for many applications. The advantage of not using a SAW filter is increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double-balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz intermediate frequency (IF) with low-side injection (i.e., fLO = fRF - fIF). The image-rejection circuit then combines these signals to achieve a typical 46dB of image rejection over the full temperature range. Lowside injection is required as high-side injection is not possible due to the on-chip image rejection. The IF output is driven by a source follower, biased to create a driving impedance of 330Ω to interface with an off-chip 330Ω ceramic IF filter. The voltage-conversion gain driving a 330Ω load is approximately 20dB. Note that the MIXIN+ and MIXIN- inputs are functionally identical. Integer-N Phase-Locked Loop (PLL) The MAX7030 utilizes a fixed-integer-N PLL to generate the receive LO. All PLL components, including the loop filter, voltage-controlled oscillator, charge pump, asynchronous 24x divider, and phase-frequency detector are integrated internally. The loop bandwidth is approximately 500kHz. The relationship between RF, IF, and reference frequencies is given by: fREF = (fRF - fIF)/24 ______________________________________________________________________________________ 13 MAX7030 Table 1. AGC Dwell Time Settings for MAX7030 MAX7030 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL Intermediate Frequency (IF) The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The internal six AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass filter type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. For ASK data, the RSSI circuit demodulates the IF to baseband by producing a DC output proportional to the log of the IF signal level with a slope of approximately 15mV/dB. Data Filter The data filter for the demodulated data is implemented as a 2nd-order, lowpass, Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. Set the corner frequency in kHz to approximately 3 times the fastest expected Manchester data rate in kbps from the transmitter (1.5 times the fastest expected NRZ data rate). Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 1 can create a Butterworth or Bessel response. The Butterworth filter offers a very-flat-amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of the capacitors, use the following equations, along with the coefficients in Table 2: Data Slicer The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. The threshold voltage is set by the voltage on the DS- pin, which is connected to the negative input of the data slicer comparator. Numerous configurations can be used to generate the data-slicer threshold. For example, the circuit in Figure 2 shows a simple method using only one resistor and one capacitor. This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R and C affect how fast the threshold tracks the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower (about 10 times) than the lowest expected data rate. With this configuration, a long string of NRZ zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. Figure 3 shows a configuration that uses the positive and negative peak detectors to generate the threshold. This configuration sets the threshold to the midpoint between a high output and a low output of the data filter. MAX7030 RSSI b CF1 = a(100kΩ)(π)(fc ) a CF2 = 4(100kΩ)(π)(fc ) 100kΩ 100kΩ DS+ where fC is the desired 3dB corner frequency. For example, choose a Butterworth filter response with a corner frequency of 5kHz: OP+ DF CF2 CF1 Figure 1. Sallen-Key Lowpass Data Filter 1.000 CF1 = ≈ 450pF (1.414)(100kΩ)(3.14)(5kHz) 1.414 CF2 = ≈ 225pF (4)(100kΩ)(3.14)(5kHz) Choosing standard capacitor values changes CF1 to 470pF and CF2 to 220pF. In the Typical Application Circuit, CF1 and CF2 are named C16 and C17, respectively. 14 Table 2. Coefficients to Calculate CF1 and CF2 FILTER TYPE a b Butterworth (Q = 0.707) 1.414 1.000 Bessel (Q = 0.577) 1.3617 0.618 ______________________________________________________________________________________ Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 MAX7030 MAX7030 DATA SLICER DATA DS- DS+ PEAK DET PEAK DET DATA SLICER R C DATA Figure 2. Generating Data-Slicer Threshold Using a Lowpass Filter Peak Detectors The maximum peak detector (PDMAX) and minimum peak detector (PDMIN), with resistors and capacitors shown in Figure 3, create DC output voltages equal to the high- and low-peak values of the filtered demodulated signal. The resistors provide a path for the capacitors to discharge, allowing the peak detectors to dynamically follow peak changes of the data filter output voltages. The maximum and minimum peak detectors can be used together to form a data slicer threshold voltage at a value midway between the maximum and minimum voltage levels of the data stream (see the Data Slicer section and Figure 3). Set the RC time constant of the peak detector combining network to at least 5 times the data period. If there is an event that causes a significant change in the magnitude of the baseband signal, such as an AGC gain-switch or a power-up transient, the peak detectors may “catch” a false level. If a false peak is detected, the slicing level is incorrect. The MAX7030 peak detectors correct these problems by temporarily tracking the incoming baseband filter voltage when an AGC state switch occurs, or forcing the peak detectors to track the baseband filter output voltage until all internal circuits are stable following an enable pin low-to-high transition and also T/R pin high-to-low transition. The peak detectors exhibit a fast attack/slow decay response. This feature allows for an extremely fast startup or AGC recovery. Transmitter Power Amplifier (PA) The PA of the MAX7030 is a high-efficiency, opendrain, switch-mode amplifier. The PA with proper output-matching network can drive a wide range of antenna impedances, which includes a small-loop PCB PDMAX R C PDMIN R C Figure 3. Generating Data-Slicer Threshold Using the Peak Detectors trace and a 50Ω antenna. The output-matching network for a 50Ω antenna is shown in the Typical Application Circuit. The output-matching network suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at PAOUT (pin 5). The optimal impedance at PAOUT is 250Ω. When the output-matching network is properly tuned, the PA transmits power with a high overall efficiency of up to 32%. The efficiency of the PA itself is more than 46%. The output power is set by an external resistor at PAOUT and is also dependent on the external antenna and antenna-matching network at the PA output. Envelope Shaping The MAX7030 features an internal envelope-shaping resistor, which connects between the open-drain output of the PA and the power supply (see the Typical Application Circuit ). The envelope-shaping resistor slows the turn-on/turn-off of the PA in ASK mode and results in a smaller spectral width of the modulated PA output signal. Fractional-N Phase-Locked Loop (PLL) The MAX7030 utilizes a fully integrated, fractional-N, PLL for its transmit frequency synthesizer. All PLL components, including the loop filter, are integrated internally. The loop bandwidth is approximately 200kHz. Power-Supply Connections The MAX7030 can be powered from a 2.1V to 3.6V supply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is used, then the on-chip linear regulator reduces the 5V supply to the 3V needed to operate the chip. To operate the MAX7030 from a 3V supply, connect PAVDD, AVDD, DVDD, and HVIN to the 3V supply. When using a 5V supply, connect the supply to HVIN ______________________________________________________________________________________ 15 The switch state is controlled by the T/R pin (pin 22). Drive T/R high to put the device in transmit mode; drive T/R low to put the device in receive mode. fP = ⎞ Cm ⎛ 1 1 − x 106 ⎜ 2 ⎝ CCASE + CLOAD CCASE + CSPEC ⎟⎠ where: fp is the amount the crystal frequency is pulled in ppm. Cm is the motional capacitance of the crystal. CCASE is the case capacitance. CSPEC is the specified load capacitance. CLOAD is the actual load capacitance. When the crystal is loaded as specified, i.e., CLOAD = CSPEC, the frequency pulling equals zero. Crystal Oscillator (XTAL) Pin Configuration ENABLE T/R N.C. DF OP+ DS+ DS- TOP VIEW DATA 24 23 22 21 20 19 18 17 N.C. 25 16 DVDD 26 15 PDMIN 14 IFIN+ 13 IFIN- 12 MIXOUT HVIN 27 AGC2 28 AGC1 29 MAX7030 MIXIN+ XTAL2 32 9 LNAOUT 1 2 3 4 5 6 AVDD MIXIN- 10 PAOUT 11 31 TX/RX2 30 ROUT AGC0 + 7 8 THIN QFN 16 PDMAX XTAL1 TX/RX1 The XTAL oscillator in the MAX7030 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2 pins. In most cases, this corresponds to a 4.5pF load capacitance applied to the external crystal when typical PCB parasitics are added. It is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7030 crystal oscillator plus PCB parasitics. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. LNAIN Transmit/Receive Antenna Switch The MAX7030 features an internal SPST RF switch that, when combined with a few external components, allows the transmit and receive pins to share a common antenna (see the Typical Application Circuit). In receive mode, the switch is open and the power amplifier is shut down, presenting a high impedance to minimize the loading of the LNA. In transmit mode, the switch closes to complete a resonant tank circuit at the PA output and forms an RF short at the input to the LNA. In this mode, the external passive components couple the output of the PA to the antenna and protect the LNA input from strong transmitted signals. In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: LNASRC only and connect AVDD, PAVDD, and DVDD together. In both cases, bypass DVDD, HVIN, and PAVDD to GND with 0.01µF and 220pF capacitors and bypass AVDD to GND with 0.1µF and 220pF capacitors. Bypass T/R, ENABLE, DATA, and AGC0-2 with 10pF capacitors to GND. Place all bypass capacitors as close as possible to the respective pins. PAVDD MAX7030 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL ______________________________________________________________________________________ Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 Table 3. Component Values for Typical Application Circuit COMPONENT VALUE FOR 433.92MHz RF VALUE FOR 315MHz RF DESCRIPTION C1 220pF 220pF 10% C2 680pF 680pF 10% C3 6.8pF 12pF 5% C4 6.8pF 10pF 5% C5 10pF 22pF 5% C6 220pF 220pF 10% 10% C7 0.1µF 0.1µF C8 100pF 100pF 5% C9 1.8pF 2.7pF ±0.1pF C10 100pF 100pF 5% C11 220pF 220pF 10% C12 100pF 100pF 5% C13 1500pF 1500pF 10% C14 0.047µF 0.047µF 10% C15 0.047µF 0.047µF 10% C16 470pF 470pF 10% C17 220pF 220pF 10% C18 220pF 220pF 10% C19 0.01µF 0.01µF 10% C20 100pF 100pF 5% C21 100pF 100pF 5% C22 220pF 220pF 10% C23 0.01µF 0.01µF 10% C24 0.01µF 0.01µF 10% L1 22nH 27nH Coilcraft 0603CS L2 22nH 30nH Coilcraft 0603CS L3 22nH 30nH Coilcraft 0603CS L4 10nH 12nH Coilcraft 0603CS L5 16nH 30nH Murata LQW18A L6 68nH 100nH Coilcraft 0603CS R1 100kΩ 100kΩ 5% R2 100kΩ 100kΩ 5% R3 0Ω 0Ω — Y1 17.63416MHz 12.67917MHz Crystal, 4.5pF load capacitance Y2 10.7MHz ceramic filter 10.7MHz ceramic filter Murata SFECV10.7 series Note: Component values vary depending on PCB layout. ______________________________________________________________________________________ 17 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL MAX7030 Typical Application Circuit AGC0 AGC1 AGC2 VDD Y1 VDD 27 26 25 N.C. 28 DVDD 29 HVIN PAVDD 30 AGC2 1 31 AGC1 32 AGC0 VDD XTAL1 C23 C24 C19 C18 C20 C21 XTAL2 3.0V 2 24 DATA C22 ROUT 23 ENABLE R3* C1 4 L1 5 VDD 6 C5 OP+ 19 C17 C6 L4 LNAIN LNASRC 9 11 10 C10 12 C12 C9 13 C13 14 PDMIN 8 PDMAX DS+ 7 IFIN+ L6 IFIN- L3 EXPOSED PAD AVDD MIXOUT C7 C8 20 DF PAOUT MIXIN- C4 C3 21 N.C. MAX7030 TX/RX2 MIXIN+ L2 TRANSMIT/ RECEIVE TX/RX1 LNAOUT C2 ENABLE 22 T/R 3 DATA 15 16 DS- C16 18 17 R1 C15 VDD L5 IN GND C11 R2 OUT C14 Y2 *OPTIONAL POWER-ADJUST RESISTOR Package Information Chip Information PROCESS: CMOS 18 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 32 Thin QFN-EP T3255+3 21-0140 90-0001 ______________________________________________________________________________________ Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL LNAOUT MIXIN+ MIXIN9 10 MIXOUT IFIN+ IFIN- 12 14 13 11 IF LIMITING AMPS 0° LNAIN 7 LNASRC 8 LNA Σ 90° I Q 20 DF RSSI 100kΩ 19 OP+ RX FREQUENCY DIVIDER XTAL1 DATA FILTER 18 DS+ 31 CRYSTAL OSCILLATOR XTAL2 100kΩ RX VCO PHASE DETECTOR 32 TX FREQUENCY DIVIDER 15 PDMIN CHARGE PUMP 16 PDMAX TX VCO HVIN 27 3.0V REGULATOR ΔΣ MODULATOR LOOP FILTER 17 DSRX DATA AVDD 6 EXPOSED PAD MAX7030 30 AGC0 PA 29 AGC1 DIGITAL LOGIC 28 AGC2 24 DATA 2 1 5 3 4 22 ROUT PAVDD PAOUT TX/RX1 TX/RX2 T/R 26 23 DVDD ENABLE ______________________________________________________________________________________ 19 MAX7030 Functional Diagram MAX7030 Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL Revision History PAGES CHANGED REVISION NUMBER REVISION DATE 0 5/05 Initial release — 1 9/08 Added + to each part to denote lead-free/RoHS-compliant package and explicitly calling out the odd frequency as contact factory for availability 1 2 6/09 Made correction in Power Amplifier (PA) section 15 3 11/10 Updated AC Electrical Characteristics, Absolute Maximum Ratings, and Package Information DESCRIPTION 2, 5, 18 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.