19-4894; Rev 4; 8/10 ኔjCvuupo ``````````````````````````````````` ᄂቶ ET2::1S ኔ jCvuupo ® ဵጙᒬऻޟଫৼࡼభణၫ ᏲᄏLj᎖ᆐᔈࣅဤܰᇹᄻᄋ࢟ᔇᓖݿ൩ăၫݧ 2.Xjsf® ፇጲࠈቲऱါࠅ႙Ljᒑኊጙᄟၫሣਜ਼ጙᄟऩ ૄăඛৈET2::1Sᎅޣ૮రഺ೫ጙৈۣᑺᆎጙቶࡼ 75ᆡᓖݿ൩Ljᎌ࣪భႩቶăଫৼงࡼݙኄনjCvuupo ॖᓤ࣪᎖इೳણஹ)ಿྙᏺᇁĂޭဘਜ਼ߡૣ*ᎌ੪ࡼߌ ၊ೆăஜࡼిᓨᅪተ੪ྏጵᎧࣗቖᄿᔈቲ࣪ᓰLjፐ ऎཽݷᔫET2::1Sऻྏޟጵăಽᒬୈ੪ྏጵ ET2::1S! jCvuupoڔᓤ᎖ᒬᇕᄏLjಿྙૹᓤረĂૡਜ਼ ࡖᔇࢀă ♦ ET2::1Bࡼဍ۾ۈLjభޘည߿ሰ።൴ߡ ET2::1Sဵᅲཝରྏ᎖ET2::1BࡼዜညቯăᏴ࣪߿ ሰ።൴ߡᎌዏৃገཇࡼ።ᒦLjET2::1S܈ET2::1Bৎᆐ းă ``````````````````````````````````` ። ඡண఼ᒜ ♦ ࣗནဟମᏴ6ntጲด ♦ ᔫपᆍǖ3/9Wᒗ7/1WLj.51°Dᒗ,96°D ````````````````````````````` jCvuupoৢቶ ♦ ޣరྜྷࡼ75ᆡᆎጙᓖݿ൩ཀྵۣᑵཀྵᇄᇙࡼୈኡ ᐋਜ਼࣪భႩቶLjࡀݙᏴྀੜೝৈᎌሤᄴᓖݿ൩ࡼ ୈ ♦ ดᒙ఼ࣶ࢛ᒜLjး᎖2.Xjsfᆀ ♦ ဟମ߿ဣሚၫᔊဤܰ ♦ భጲڔᓤᏴ෭ጙᇕᄏĂ݀ࣗནၫ ♦ ᄰਭሣᎧᔐሣᓍ૦ቲၫᄰቧLjࠅၒႥൈభࡉ 27/4lcqtLjளဣૉ ♦ ిᅪተဧభጲᔈࣅ࣪ᓰۭᓨყހ ♦ ᓖݿ൩రᏴงࡼݙኄনᅪఫLjถ৫ள၊इೳࡼ ણஹ ᔫഗ߈ৌᔍ ♦ ڔᓤဟభጲ੪ྏጵᔈᐫୢᐫᄣ۳ෂĂৼࢾܟዘLj ༊ᓤણ৯ ಯ ెࡀ఼ᒜ ♦ ࡩᏞࣗ၅ࠨ࢟ဟቲᏴሣଶހ።ࡊ ``````````````````````````````` ࢾ৪ቧᇦ PART TEMP RANGE PIN-PACKAGE DS1990R-F5# -40°C to +85°C F5 iButton DS1990R-F3# -40°C to +85°C F3 iButton ``````````````````````````````` ୭ᒙ F3 SIZE F5 SIZE 3.10mm 5.89mm 0.51mm 0.51mm BRANDING $ ܭာୈ९SpITܪᓰLjభถ)Qc*Ljࡣ፱ᎌSpITཚă ® i 16.25mm 89 ``````````````````````````````` এୈာಿ DS9096P Self-Stick Adhesive Pad DS9101 Multipurpose Clip DS9093RA Mounting Lock Ring DS9093A Snap-In Fob DS9092 iButton Probe IO 1-Wire® W 5 W ACCESSORY #F YY PART ® 01 000000FBC52B ZZZ D S1990 R 17.35mm IO GND GND jCvuupoਜ਼2.XjsfဵNbyjn! Joufhsbufe! Qspevdut-! Jod/ࡼᓖݿܪă ________________________________________________________________ Maxim Integrated Products 1 ۾ᆪဵ፞ᆪၫᓾ೯ࡼፉᆪLjᆪᒦభถࡀᏴडፉࡼݙᓰཀྵࡇᇙăྙኊጙݛཀྵཱྀLj༿Ᏼิࡼଐᒦݬఠ፞ᆪᓾ೯ă ᎌਈଥৃĂૡૺࢿ৪ቧᇦLj༿ೊNbyjnᒴሾ၉ᒦቦǖ21911!963!235:!)۱ᒦਪཌ*Lj21911!263!235:!)ฉᒦਪཌ*Lj षᆰNbyjnࡼᒦᆪᆀᐶǖdijob/nbyjn.jd/dpnă ET2::1S ``````````````````````````````````` গၤ ET2::1S ኔjCvuupo ABSOLUTE MAXIMUM RATINGS IO Voltage Range to GND .....................................-0.5V to +6.0V IO Sink Current....................................................................20mA Junction Temperature ......................................................+125°C Storage Temperature Range .............................-55°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Notes 1, 2) 2.8 6.0 V 1-Wire Pullup Resistance RPUP (Notes 3, 4) 0.6 5 k CIO (Notes 5, 6) 800 pF Input Capacitance Input Load Current IL (Note 7) Input Low Voltage VIL (Notes 1, 3, 8) Input High Voltage VIH (Notes 1, 9) 100 0.25 μA 0.3 2.2 V V Output Low Voltage at 4mA VOL (Note 1) Operating Charge QOP (Notes 6, 10) 0.4 Recovery Time tREC (Note 3) 1 μs Time Slot Duration t SLOT (Note 3) 61 μs μs 30 V nC IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Reset Low Time tRSTL (Notes 3, 11) 480 Reset High Time tRSTH (Notes 3, 12) 480 Presence-Detect High Time t PDH Presence-Detect Low Time t PDL Presence-Detect Sample Time μs 15 60 μs (Note 13) 60 240 μs tMSP (Note 3) 60 75 μs Write-Zero Low Time tW0L (Notes 3, 14) 60 120 μs Write-One Low Time tW1L (Notes 3, 14) 1 15 μs tRL (Notes 3, 15) 1 15 - μs tMSR (Notes 3, 15) tRL + 15 μs IO PIN: 1-Wire WRITE IO PIN: 1-Wire READ Read Low Time Read Sample Time Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 2 All voltages are referenced to ground. External pullup voltage. See Figure 4. System requirement. Full RPUP range is guaranteed by design and simulation and not production tested. Production testing performed at a fixed RPUP value. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. Capacitance on the IO pin could be 800pF when power is first applied. If a 5kΩ resistor is used to pull up the IO line to VPUP, 5μs after power has been applied the parasite capacitance will not affect normal communications. Guaranteed by design, simulation only. Not production tested. Input load is to ground. _______________________________________________________________________________________ ኔjCvuupo Note 12: Note 13: Note 14: Note 15: The voltage on IO must be less than or equal to VILMAX whenever the master drives the line low. VIH is a function of the internal supply voltage. 30nC per 72 time slots at 5.0V pullup voltage with a 5kΩ pullup resistor and tSLOT ≤ 120μs. The reset low time (tRSTL) should be restricted to a maximum of 960μs to allow interrupt signaling. A longer duration could mask or conceal interrupt pulses if this device is used in parallel with a DS1994. An additional reset or communication sequence cannot begin until the reset high time has expired. Presence pulse after POR is guaranteed by design, not production tested. ε in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VIH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. δ in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. iButton CAN PHYSICAL SPECIFICATION SIZE See the Package Information section. WEIGHT (DS1990R) Ca. 2.5 grams ``````````````````````````````` ሮᇼႁී ᅄ2߲೫কୈࡼᓍገถౖᅄăET2::1S࠭JPᔐሣ ནჅኊࡼถLjྙည࢟ᏎᏇಯᅄჅာăSPNถ఼ᒜ Ꮔ۞౪2.Xjsfాਜ਼൝࢟വLj᎖ဣሚSPNถෘ എLjषᆰ75ᆡరSPNă PARASITE POWER DS1990R IO ROM FUNCTION CONTROL 64-BIT LASERED ROM ᅄ2/! ऱౖᅄ _______________________________________________________________________________________ 3 ET2::1S Note 8: Note 9: Note 10: Note 11: ET2::1S ኔjCvuupo ````````````````````````` 2.Xjsfᔐሣᇹᄻ 75ᆡరSPN ඛৈET2::1S۞ᆎጙࡼ75ᆡSPN൩Lj༄9ᆡဵ2.Xjsfଜᔙ ൩Ljሆࡼ59ᆡဵᆎጙࡼኔLjᔢઁ9ᆡဵ༄67ᆡࡼ DSDቅዩ൩ăሮᇼดྏ༿ݬఠᅄ3ă2.Xjsf! DSDဵᎅࣶሲါ खညޘညࡼLjࣶሲါखညᎅጤᆡࡀਜ਼Đፊđ൝ ඡ࢟വ৩߅Ljྙᅄ4ჅာăࣶሲါᆐǖY9 ,! Y6 ,! Y5 ,! 2ă ᎌਈ2.Xjsfክણྑቅዩ)DSD*ࡼሮᇼቧᇦLj༿ݬఠ። ܊38ǖಯஊਜ਼ᏥNbyjn jCvuupoޘອᒦࡼክણྑቅዩ )DSD*ă ጤᆡࡀጲ1ᆐဪᆡLjઁဵଜᔙ൩)ᔢࢅᎌᆡᏴ ༄*Ljඛࠨጤྜྷ2ᆡăጤྜྷ9ᆡଜᔙ൩ઁLjఎဪጤྜྷኔ ă59ᆡኔᅲཝጤྜྷઁLjጤᆡࡀดჅ۞ࡼᒋ ૾ᆐDSDቅዩ൩ăጤྜྷ9ᆡDSDቅዩ൩Ljጤᆡࡀཝ ݝਙ1ă 2.XjsfဵᏴጙᄟᔐሣೌጙৈᓍ఼ᒜጲૺጙৈࣶৈ ࠭૦ࡼᇹᄻăྀੜ༽ౚሆLjET2::1S࣒ဵ࠭૦ୈLjऎᔐ ሣᓍ఼ᒜޟᎅᆈ఼ᒜQDߠྀă࣪᎖ጙৈቃቯᇹᄻ ᒙLj2.XjsfᄰቧቧభጲᏴྟୈ఼ᒜሆᎅᆈ఼ᒜࡼጙ ৈ࣡ా୭ޘညăᅪLjጐభጲಽET3591C! 2.Xjsfሣད ࣅ᎖কୈࡼࠈాး)ET:1:8Vᇹ*ဣሚăᑚ ᒬᄰቧऱါ଼છ೫፮ୈଐLjऎ༦భጲஂဏᆈࠀಯࡼ ᓾᏎLjି༵ဣဟݷᔫྀᇗăᎌਈᔐሣᇹᄻࡼᄀ൙ॊᆐྯ ৈᓍᄌǖ፮ୈᒙĂࠀಯഗ߈ਜ਼2.Xjsfቧഎ)ቧಢቯਜ਼ ဟኔ*ă2.Xjsfፇਖࢾږᑍᄂࢾဟᇺᒦࡼᔐሣᓨზቲᔐ ሣݷᔫLjጲᓍ఼ᒜख႙ࡼᄴݛ൴ߡࡼሆଢ଼ዘᆐဪᓨზă ৎሮᇼࡼፇහၤLj༿ݬఠ።܊:48ǖCppl! pg! jCvuupo Tuboebset ࡼ႐ᐺă MSB LSB 8-BIT CRC CODE MSB 8-BIT FAMILY CODE (01h) 48-BIT SERIAL NUMBER LSB LSB MSB LSB MSB ᅄ3/! 75ᆡరSPN POLYNOMIAL = X8 + X5 + X4 + 1 1ST STAGE X0 2ND STAGE X1 3RD STAGE X2 4TH STAGE X3 5TH STAGE X4 6TH STAGE X5 7TH STAGE X6 8TH STAGE X7 INPUT DATA ᅄ4/! 2.Xjsf! DSDखည 4 _______________________________________________________________________________________ X8 ኔjCvuupo ``````````````````````````````` ࠀಯഗ߈ 2.Xjsfᔐሣஞࢾፃ೫ጙᄟቧሣLjჅጲཱུᔐሣඛৈୈ ࣒ᏴးࡩࡼဟరᏥቲဵऻޟᒮገࡼăᆐܣ᎖ࡉࡵᑚጙࡼLj ඛጙৈྜྷ2.Xjsfᔐሣࡼୈ࣒ݧധఎവྯზၒ ߲ăET2::1Sࡼ2.Xjsf࣡ాᆐധఎവၒ߲Ljดࢀݝ࢟ വྙᅄ5Ⴥာăࣶ࢛ᔐሣᏴጙᄟ2.Xjsfᔐሣਂ೫ࣶৈ ࠭૦ୈă2.Xjsfᔐሣࡼᔢܪᓰၫࠅၒൈᆐ27/4lcqtă ౯࢟ᔜࡼᔜᒋན᎖ᆀਖෝਜ਼ঌᏲᄟୈLj࣪᎖ࡍࣶၫ ።LjభኡᐋࡍᏖ3/3lΩࡼ౯࢟ᔜă2.Xjsfᔐሣࡼహሔ ᓨზᆐ࢟ຳLjྀੜ༽ౚሆኊገᄫݷᔫဟLjᔐሣܘኍ ᒙ᎖హሔᓨზLjጲܣႲઁૂআ2.Xjsfݷᔫăྙਫᎌቲ ၤݷᔫLjᔐሣᒙ᎖ࢅ࢟ຳࡼဟମިਭ231μtLjᐌᔐሣ ࡼጙৈࣶৈୈۻআᆡă ET2::1SᏴ2.Xjsfᔐሣࡼၫषᆰෘഎഗ߈ྙሆჅာǖ • ߱ဪછ • SPNถෘഎ ````````````````````````````````` ߱ဪછ 2.XjsfᔐሣჅᎌࡼࠅၒݷᔫᎅ߱ဪછኔఎဪă߱ဪ છኔᎅᓍ૦ख߲ࡼআᆡ൴ߡਜ਼࠭૦ख߲ࡼᏴሣ።ࡊ൴ ߡᔝ߅ăᏴሣ።ࡊ൴ߡဧᓍ૦ଶࡵހET2::1SᏴᔐሣLj ݀༦ጯளᓰ۸ኙăሮᇼดྏ༿ݬఠ 2.Xjsfቧഎݝॊă VPUP SIMPLE BUS MASTER DS1990R 1-Wire PORT RPUP DATA Rx Tx Tx Rx = RECEIVE Tx = TRANSMIT 100Ω MOSFET OPEN-DRAIN PORT PIN DS2480B BUS MASTER HOST CPU SERIAL IN SERIAL PORT SERIAL OUT Rx +5V VDD VPP POL 1-W RXD N.C. TXD GND TO 1-Wire DATA DS2480B ᅄ5/! ፮ୈᒙ _______________________________________________________________________________________ 5 ET2::1S ``````````````````````````````` ፮ୈᒙ ኔjCvuupo ET2::1S ```````````````````` 2.Xjsf! SPNถෘഎ ጙࡡᓍ૦ଶࡵހ።ࡊ൴ߡLjభጲख߲ET2::1Sᑽߒࡼ SPNถෘഎăჅᎌSPNถෘഎࡼࣞޠᆐ9ᆡăጲሆ ߲೫ᑚቋෘഎࡼ଼ገ)ഗ߈ᅄݬᅄ6*ă BUS MASTER Tx RESET PULSE BUS MASTER Tx ROM FUNCTION COMMAND 33h OR 0Fh READ ROM COMMAND? DS1990R Tx PRESENCE PULSE Sfbe! SPN! \44i^\1Gi^ F0h SEARCH ROM COMMAND? N Y Y DS1990R Tx FAMILY CODE (1 BYTE) DS1990R Tx BIT 0 DS1990R Tx BIT 0 MASTER Tx BIT 0 N BIT 0 MATCH? Y DS1990R Tx SERIAL NUMBER (6 BYTES) DS1990R Tx BIT 1 DS1990R Tx BIT 1 MASTER Tx BIT 1 N BIT 1 MATCH? Y DS1990R Tx CRC BYTE DS1990R Tx BIT 63 DS1990R Tx BIT 63 MASTER Tx BIT 63 N BIT 63 MATCH? N ࠥෘഎᏤᔐሣᓍ૦ࣗནET2::1Sࡼ9ᆡଜᔙ൩Ăᆎጙࡼ 59ᆡኔ൩ਜ਼9ᆡDSDቅዩ൩ăࠥෘഎஞᏴᔐሣᒑᎌጙ ৈ࠭૦ୈဟݣభጲဧăྦᔐሣࡼ࠭૦ިਭጙৈLj Ⴥᎌ࠭૦ᄴဟख႙ၫဟ્खၫߡᅃ)ఎധၒ߲ ޘညĐሣᎧđࡼஉਫ*LjᑚࡴᒘჅࡻࡵࡼଜᔙ൩ਜ਼59ᆡኔ ᎧDSDݙປă Tfbsdi! SPN! \G1i^ ࡩጙৈᇹᄻࣅ߱ဪછဟLjᔐሣᓍ૦భถ݀ݙᒀࡸ2.Xjsf ᔐሣਂࡼୈၫᓖݿăಽᔐሣࡼĐሣᎧđ ᄂ࢛Ljᔐሣᓍ૦ݧ߹जభጲဤܰᔐሣჅᎌ࠭૦ ୈࡼᓖݿăནᓖݿࡼඛጙᆡLj࠭ᔢࢅᎌᆡఎဪLj ᔐሣᓍ૦࣒ኊገளਭྯৈဟᇺăጙৈဟᇺLjඛৈݬᎧႝ Ⴣࡼ࠭૦ୈख႙ጙᆡᓖݿࡼᑞဣ൩ǗऔৈဟᇺLj ඛৈݬᎧႝჃࡼ࠭૦ୈख႙কᆡᓖݿࡼݗ൩Ǘྯ ৈဟᇺLjᓍ૦ቖኡᐋᆡࡼᑞဣ൩ăᎧᓍ૦ቖྜྷᆡݙᄴࡼ Ⴥᎌ࠭૦ୈᄫᒏݬᎧႝჃݷᔫăྙਫᏴ༄ೝৈဟᇺᒦ ࣗནᆡᆐ1Ljᔐሣᓍ૦భጲᇨሚᎌࡼ࠭૦ୈࡀᏴೝᒬ ᆡᓨზăᔐሣᓍ૦ኡᐋቖྜྷᆡઁLjSPN൩ Đၥđ ߲ሚ Đॊᑼđ ᅲ߅ጙࠨݷᔫഗ߈Ljᔐሣᓍ૦భጲࡻጙৈୈࡼᓖݿ ăᎌਈୈᓖݿဤܰࡼሮᇼቧᇦLj༿ݬఠ። ܊298ǖ2.XjsfႝჃႯजLjᒦથᄋ೫ጙৈဣಿă Nbudi! SPN! \66i^0Tljq! SPN! \DDi^ 2.Xjsf! SPNถෘഎࡼᔢቃᒙ۞౪Nbudi! SPNਜ਼Tljq SPNෘഎăፐᆐET2::1Sஞᎌጙৈ75ᆡSPN൩Ljᇄ এଝࡼࡀహମLjჅጲNbudi SPNਜ਼Tljq! SPNෘഎ࣒ݙ భဧăET2::1S၃ࡵጙৈݙᑽߒࡼSPNถෘഎ ဟLjۣߒĐ෦đ)ࣅݙᔫ*ăᑚዹభጲཀྵۣET2::1SᎧ ถ৫ሰ።Nbudi SPNTljq SPNࡼ2.Xjsfୈৢᄴ ਂᏴጙᄟࣶ࢛ᔐሣă Y ᅄ6/! SPNถഗ߈ᅄ 6 _______________________________________________________________________________________ ኔjCvuupo ࣗ0ቖဟᇺ ET2::1SኊገዏৃࡼᄰቧፇཀྵۣၫࡼᅲᑳቶLjࠥ ፇᏴሣࢾፃ೫႐ᒬಢቯࡼቧǖ۞౪আᆡ൴ߡਜ਼Ᏼ ሣ።ࡊ൴ߡࡼআᆡਭ߈Ăቖ1Ăቖ2ਜ਼ࣗၫă߹೫Ᏼሣ ።ࡊ൴ߡጲᅪLjಢቯࡼቧ࣒ᎅᔐሣᓍ૦ࣅă ᎧET2::1SࡼၫᄰቧږဟᇺቲLjඛဟᇺࠅၒጙᆡăၫ Ᏼቖဟᇺᎅᔐሣᓍ૦ࠅၒࡵ࠭૦LjၫᏴࣗဟᇺᎅ࠭ ૦ࠅၒࡵᓍ૦ăᅄ8߲೫ቖဟᇺਜ਼ࣗဟᇺࡼࢾፃă ࠭హሔࡵࣅᓨზLj2.Xjsfᔐሣ࢟ኹኊገ࠭W QVQ ሆଢ଼ࡵ WJMNBY ጲሆǗ࠭ࣅࡵహሔᓨზLjᔐሣ࢟ኹኊገ࠭WJMNBY ဍࡵWJINJO ጲă࢟ኹဍჅኊገࡼဟମ༿ݬఠᅄ7ᒦ ࡼεLjকᒋན᎖౯࢟ᔜ)SQVQ*ਜ਼2.Xjsfᆀ࢟ྏࡼࡍቃă ET2::1Sቲྀੜᄰቧ࣒ገቲ߱ဪછࠀಯLjྙᅄ7Ⴥာă ጙৈআᆡ൴ߡஜৌጙৈᏴሣ።ࡊ൴ߡීܭET2::1Sᓰ۸ ኙLjభ၃SPNถෘഎăྙਫᔐሣᓍ૦Ᏼሆଢ଼ዘݧ ೫ڼൈ఼ᒜLjᐌܘኍᔐሣ౯ࢅu STUM , u G Ljጲ࣪ܟዘ ቲޡݗă ᓍ૦ျहᔐሣઁྜྷ၃ෝါ)Sy*ăࠥဟ2.Xjsfᔐሣ࢟ຳ ۻ౯࢟ᔜET3591CདࣅࢀᎌᏎ࢟വ౯ᒗWQVQăࡩ ࢟ຳ᎖WJINJO ဟLjET2::1SࢀࡗuQEILjઁᄰਭᔐሣ ࢟ຳ౯ࢅۣ݀ߒuQEMLjख႙ጙৈ።ࡊ൴ߡăᆐ೫ଶހ።ࡊ ൴ߡLjᓍ૦ܘኍᏴuNTQ ဟମଶހ2.Xjsfᔐሣࡼ൝࢟ຳă Ⴥᎌᄰቧ࠭ᓍ૦౯ࢅၫሣఎဪLjࡩ2.Xjsfᔐሣࡼ࢟ ኹଢ଼ᒗW JMNBY ጲሆဟLjET2::1SࣅดࢾݝဟखညLj ᏴቖဟᇺཀྵࢾੜဟݧዹၫሣLjᏴࣗဟᇺཀྵࢾၫᎌ ࡼဟମă ᓍ૦ࡵ࠭૦ ࣪᎖ቖ2ဟᇺLjၫሣࡼ࢟ኹܘኍᏴቖ2ࡼࢅ࢟ຳဟମ uX2MNBY உၦ༄ࡉࡵWJINJO ጲă࣪᎖ቖ1ဟᇺLjၫሣ ࡼ࢟ኹᏴቖ1ࡼࢅ࢟ຳဟମu X1MNJO உၦ༄ܘኍۣߒᏴ W JMNBY ጲሆăᆐ೫ဣሚᔢభణࡼᄰቧLjၫሣࡼ࢟ኹ Ᏼᑳৈu X1M ဟମࠊాด࣒ݙ።ިਭW JMNBYăၫሣࡼ ࢟ኹިਭWJINJO ઁLjET2::1SᏴቲሆጙৈဟᇺ༄ኊገጙ ࣤૂআဟମuSFDă MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE" ε tMSP VPUP VIHMIN VILMAX 0V tRSTL tPDH tF tPDL tREC tRSTH RESISTOR MASTER DS1990R ᅄ7/! ߱ဪછഗ߈ǖআᆡਜ਼Ᏼሣ።ࡊ൴ߡ _______________________________________________________________________________________ 7 ET2::1S ````````````````````````````` 2.Xjsfቧഎ ET2::1S ኔjCvuupo WRITE-ONE TIME SLOT tW1L VPUP VIHMASTER VIHMIN VILMAX 0V ε tF tSLOT RESISTOR MASTER WRITE-ZERO TIME SLOT tW0L VPUP VIHMASTER VIHMIN VILMAX 0V ε tF tREC tSLOT RESISTOR MASTER READ-DATA TIME SLOT tMSR tRL VPUP VIHMASTER VIHMIN MASTER SAMPLING WINDOW VILMAX 0V δ tF tREC tSLOT RESISTOR MASTER DS1990R ᅄ8/! ࣗ0ቖဟኔᅄ 8 _______________________________________________________________________________________ ኔjCvuupo ᓍ૦ݧዹࠊా)uNTSNJO ᒗuNTSNBY*ᎅuSM , δ )ဍဟମ*ਜ਼ ET2::1SดࢾࡼݝဟखညࢾLjᓍ૦ܘኍᏴݧዹࠊాด ᒊቲጙࠨၫሣࣗݷᔫăᆐࡉࡵభణᄰቧLjuSM ဟମᏴᏤ पᆍด።Ljᓍ૦።কᏴதࡣݙᅵ᎖uNTSNBY ࡼ ဟମࣗནၫă࠭ၫሣࣗནၫઁLjᓍ૦ܘኍࢀࡗᒇ ᒗu TMPU உၦLjཀྵۣET2::1SᏴሆጙৈဟᇺᓰ۸ኙ༄ᎌ ᔗ৫ࡼૂআဟମuSFDă ```````````````````````````````````````````````````````````````````````````` ॖᓤቧᇦ ྙኊᔢதࡼॖᓤᅪተቧᇦਜ਼ݚLj༿އኯ china.maxim-ic.com/packagesă༿ᓖፀLjॖᓤܠ൩ᒦࡼĐ,đĂ Đ$đĐ.đஞܭာSpITᓨზă ॖᓤᅄᒦభถ۞ݙᄴࡼᆘᓮᔊ९LjࡣॖᓤᅄᒑᎧॖᓤᎌਈLjᎧSpITᓨზᇄਈă ॖᓤಢቯ ॖᓤܠ൩ ᅪተܠ ݚܠ F3 iButton IB#3NB 21-0252 — F5 iButton IB#5NB 21-0266 — _______________________________________________________________________________________ 9 ET2::1S ࠭૦ࡵᓍ૦ ࣗၫဟᇺఎဪဟᎧቖ2ဟᇺಢ႒ăၫሣࡼ࢟ኹᏴࣗ ࢅ࢟ຳဟମuSM உၦ༄ܘኍۣߒᏴWJMNBY ጲሆăᏴuSM ဟମ ࠊాLj።ࡊ1ဟLjET2::1Sఎဪ౯ࢅၫሣLjดࢾݝဟ खညࢾੜဟஉၦሆ౯Lj࢟ኹᒮቤఎဪဍǗ።ࡊ2ဟLj ET2::1Sߒۣݙၫሣࡼࢅ࢟ຳLjጙࡡu SM உၦLj࢟ኹ ૾రఎဪဍă ET2::1S ኔjCvuupo ```````````````````````````````````````````````````````````````````````````` ኀࢿ಼ဥ ኀࢿ ኀࢿ྇໐ 0 5/05 ᔢ߱۾ۈă — 1 8/06 VM$:24ጙሲৎখᆐĐଐ൸ᔗčđă 1 2 8/09 ৎቤ೫ࢾ৪ቧᇦܭLjଝྜྷ९SpITܪᓰࡼॖᓤୈǗ࠭ jCvuupoৢቶݝॊᒦ࿎߹೫VM$:24 ጙሲă 1 8/10 ࠎቤෝۇၫᓾ೯ǗᏴ Fmfdusjdbm! Dibsbdufsjtujdt ܭᒦLj࿎߹೫Đၒ߲࢟ኹđݬၫLjĐ2.Xjsf ౯࢟ኹđݬၫᎅܭᄿᆡᒙጤᒗܭᒦLjWJMNBY ᎅ1/9Wৎখᆐ1/4WLjᆐuX1M ᒎܪᐐଝ೫ᓖျ 25LjuX2MNBY ᎅ26μt! .! εৎখᆐ26μtLjᆐᓖျ25ਜ਼26ᐐଝ೫ৎࣶดྏǗᏴᅄ8ࡼቖ1ဟᇺᒦ ᐐଝ೫εဟମܪဤă 3 ႁී ኀখ 2, 3, 8 Nbyjn ۱யࠀူێ ۱ய 9439ቧረ ᎆᑶܠ൩ 211194 ॅ࢟જǖ911!921!1421 ࢟જǖ121.7322 62:: ࠅᑞǖ121.7322 63:: Nbyjn࣪ݙNbyjnޘອጲᅪࡼྀੜ࢟വဧঌᐊLjጐݙᄋᓜಽభăNbyjnۣഔᏴྀੜဟମĂᎌྀੜᄰۨࡼ༄ᄋሆኀখޘອᓾ೯ਜ਼ਖৃࡼཚಽă 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Nbyjn ဵ Nbyjn!Joufhsbufe!Qspevdut-!Jod/ ࡼᓖݿܪă DS1990R, DS1990R-F3, DS1990R-F5 序列号iButton - 概述 ENGLISH • 简体中文 • 日本語 • 한국어 • РУССКИЙ Login | Register 最新内容 产品 方案 设计 应用 技术支持 销售联络 公司简介 Maxim > 产品 > 1-Wire®器件 > DS1990R, DS1990R-F3, ... Maxim > 产品 > iButton®及其附件 > DS1990R, DS1990R-F3, ... DS1990R, DS1990R-F3, DS1990R-F5 序列号iButton 概述 技术文档 定购信息 相关产品 用户说明 (0) 所有内容 状况 型号 状况 DS1990R 状况：生产中。 DS1990R-F3 状况：生产中。详细情况请参考订购信息。 DS1990R-F5 状况：生产中。详细情况请参考订购信息。 概述 数据资料 DS1990R序列号iButton®是一种非常坚固的高可靠数据载体，用于为自动识别系统提供电子注册码。 数据采用1-Wire®协议以串行方式传送，只需一条数据线和一条返回地。每个DS1990R由工厂激光刻 录了一个保证唯一性的64位注册码，具有绝对可溯性。坚固耐用的不锈钢iButton封装对于恶劣环境(例 如脏污、潮湿和冲击)具有很高的承受力。紧凑的纽扣状外形很容易与读写头自行对准，因而人工操 作DS1990R非常容易。利用各种配件很容易将DS1990R iButton安装于各种物体上，例如集装箱、货 盘和袋子等。DS1990R是完全兼容于DS1990A的衍生型号。在对接触响应脉冲有严格要求的应用 中，DS1990R比DS1990A更为适合。 关键特性 完整的数据资料 英文 下载 Rev. 4 (PDF, 160kB) 中文 下载 Rev. 4 (PDF, 640kB) 应用/使用 唯一的、由工厂激光刻录的64位注册码，保证无差错设备选择和绝对可溯性，因为没有任何两 个元件是相同的 内置多节点控制器适用于1-Wire网络 “一触即得”的数字识别方案 固定于某物体上时也可读取数据 极为经济地通过单条数字信号线，以16.3kbps速率与总线主控通信 钮扣外形可自行对准杯状探头 坚固的不锈钢外壳，上刻注册码，可经受恶劣环境考验 易于安装，可采用自粘胶垫粘结，紧扣其凸缘，或用一个紧套于其外壳的环锁紧它 当阅读器首次上电时进行在线检测应答 门禁控制 库存控制 工具管理 工作流程跟踪 图表 没有找到你需要的产品吗？ 应用工程师帮助选型，下个工作日回复 参数搜索 应用帮助 概述 技术文档 定购信息 相关产品 概述 关键特性 应用/ 使用 关键指标 图表 注释、注解 数据资料 应用笔记 评估板 设计指南 可靠性报告 软件/ 模型 价格与供货 样品 在线订购 封装信息 无铅信息 类似功能器件 类似应用器件 评估板 类似型号器件 配合该器件使用的产品 参考文献： 19- 4894 Rev. 4; 2010- 09- 07 本页最后一次更新: 2010- 12- 08 http://china.maxim-ic.com/datasheet/index.mvp/id/4787[2011-1-8 10:36:53] 我的Maxim DS1990R, DS1990R-F3, DS1990R-F5 序列号iButton - 概述 联络我们：信息反馈、提出问题 • 对该网页的评价 • 发送本网页 • 隐私权政策 • 法律声明 © 2010 Maxim Integrated Products版权所有 http://china.maxim-ic.com/datasheet/index.mvp/id/4787[2011-1-8 10:36:53] 19-4894; Rev 4; 8/10 Serial Number iButton The DS1990R serial number iButton® is a rugged data carrier that serves as an electronic registration number for automatic identification. Data is transferred serially through the 1-Wire® protocol, which requires only a single data lead and a ground return. Every DS1990R is factory lasered with a guaranteed unique 64-bit registration number that allows for absolute traceability. The durable stainless-steel iButton package is highly resistant to environmental hazards such as dirt, moisture, and shock. Its compact coin-shaped profile is selfaligning with mating receptacles, allowing the DS1990R to be used easily by human operators. Accessories enable the DS1990R iButton to be mounted on almost any object, including containers, pallets, and bags. The DS1990R is a fully compatible variant of the DS1990A. In applications where a presence pulse on contact is critical, the DS1990R should be preferred over the DS1990A. Applications Access Control Work-In-Progress Tracking Features ♦ Upgrade of DS1990A Guarantees Presence Pulse on Contact ♦ Can Be Read in Less Than 5ms ♦ Operating Range: 2.8V to 6.0V, -40°C to +85°C Common iButton Features ♦ Unique Factory-Lasered 64-Bit Registration Number Ensures Error-Free Device Selection and Absolute Traceability Because No Two Parts are Alike ♦ Built-In Multidrop Controller for 1-Wire Net ♦ Digital Identification by Momentary Contact ♦ Data Can Be Accessed While Affixed to Object ♦ Economically Communicates to Bus Master with a Single Digital Signal at 16.3kbps ♦ Button Shape is Self-Aligning with Cup-Shaped Probes ♦ Durable Stainless-Steel Case Engraved with Registration Number Withstands Harsh Environments Ordering Information PART TEMP RANGE PIN-PACKAGE DS1990R-F5# -40°C to +85°C F5 iButton DS1990R-F3# -40°C to +85°C F3 iButton ♦ Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed Onto its Rim ♦ Presence Detector Acknowledges When Reader First Applies Voltage #Denotes a RoHS-compliant device that may include lead(Pb) that is exempt under the RoHS requirements. Pin Configurations 3.10mm ACCESSORY Multipurpose Clip DS9093RA Mounting Lock Ring DS9093A Snap-In Fob DS9092 iButton Probe BRANDING ut 89 t o n ®. c om Self-Stick Adhesive Pad DS9101 0.51mm 16.25mm ® 01 000000FBC52B YY DS9096P 5.89mm 0.51mm iB PART F5 SIZE F3 SIZE Examples of Accessories W IO 1-Wire® W 5 Inventory Control #F Tool Management ZZZ D S1990 R 17.35mm IO GND GND iButton and 1-Wire are registered trademarks of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1990R General Description DS1990R Serial Number iButton ABSOLUTE MAXIMUM RATINGS IO Voltage Range to GND .....................................-0.5V to +6.0V IO Sink Current....................................................................20mA Junction Temperature ......................................................+125°C Storage Temperature Range .............................-55°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 6.0 V 5 k IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP 1-Wire Pullup Resistance (Notes 1, 2) 2.8 0.6 RPUP (Notes 3, 4) Input Capacitance CIO (Notes 5, 6) Input Load Current IL (Note 7) Input Low Voltage VIL (Notes 1, 3, 8) Input High Voltage VIH (Notes 1, 9) Output Low Voltage at 4mA VOL (Note 1) Operating Charge QOP (Notes 6, 10) Recovery Time tREC (Note 3) 1 μs Time Slot Duration t SLOT (Note 3) 61 μs 100 800 0.25 pF μA 0.3 V 0.4 V 2.2 V 30 nC IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Reset Low Time tRSTL (Notes 3, 11) 480 μs Reset High Time tRSTH (Notes 3, 12) 480 μs Presence-Detect High Time t PDH 15 60 μs Presence-Detect Low Time t PDL (Note 13) 60 240 μs Presence-Detect Sample Time tMSP (Note 3) 60 75 μs Write-Zero Low Time tW0L (Notes 3, 14) 60 120 μs Write-One Low Time tW1L (Notes 3, 14) 1 15 μs tRL (Notes 3, 15) 1 15 - μs tMSR (Notes 3, 15) tRL + 15 μs IO PIN: 1-Wire WRITE IO PIN: 1-Wire READ Read Low Time Read Sample Time Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 2 All voltages are referenced to ground. External pullup voltage. See Figure 4. System requirement. Full RPUP range is guaranteed by design and simulation and not production tested. Production testing performed at a fixed RPUP value. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. Capacitance on the IO pin could be 800pF when power is first applied. If a 5kΩ resistor is used to pull up the IO line to VPUP, 5µs after power has been applied the parasite capacitance will not affect normal communications. Guaranteed by design, simulation only. Not production tested. Input load is to ground. _______________________________________________________________________________________ Serial Number iButton Note 12: Note 13: Note 14: Note 15: The voltage on IO must be less than or equal to VILMAX whenever the master drives the line low. VIH is a function of the internal supply voltage. 30nC per 72 time slots at 5.0V pullup voltage with a 5kΩ pullup resistor and tSLOT ≤ 120µs. The reset low time (tRSTL) should be restricted to a maximum of 960µs to allow interrupt signaling. A longer duration could mask or conceal interrupt pulses if this device is used in parallel with a DS1994. An additional reset or communication sequence cannot begin until the reset high time has expired. Presence pulse after POR is guaranteed by design, not production tested. ε in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VIH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. δ in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. iButton CAN PHYSICAL SPECIFICATION SIZE See the Package Information section. WEIGHT (DS1990R) Ca. 2.5 grams Detailed Description The block diagram in Figure 1 shows the major function blocks of the device. The DS1990R takes the energy it needs to operate from the IO line, as indicated by the parasite power block. The ROM function control unit includes the 1-Wire interface and the logic to implement the ROM function commands, which access 64 bits of lasered ROM. PARASITE POWER DS1990R IO ROM FUNCTION CONTROL 64-BIT LASERED ROM Figure 1. Block Diagram _______________________________________________________________________________________ 3 DS1990R Note 8: Note 9: Note 10: Note 11: DS1990R Serial Number iButton 1-Wire Bus System 64-Bit Lasered ROM Each DS1990R contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. See Figure 2 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the 1-Wire Cyclic Redundancy Check (CRC) is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products. The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC returns the shift register to all 0s. The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances, the DS1990R is a slave device. The bus master is typically a microcontroller or PC. For small configurations, the 1-Wire communication signals can be generated under software control using a single port pin. Alternatively, the DS2480B 1-Wire line driver chip or serial-port adapters based on this chip (DS9097U series) can be used. This simplifies the hardware design and frees the microprocessor from responding in real time. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Application Note 937: Book of iButton Standards. MSB LSB 8-BIT CRC CODE MSB 8-BIT FAMILY CODE (01h) 48-BIT SERIAL NUMBER LSB MSB LSB MSB LSB Figure 2. 64-Bit Lasered ROM POLYNOMIAL = X8 + X5 + X4 + 1 1ST STAGE X0 2ND STAGE X1 3RD STAGE X2 4TH STAGE X3 5TH STAGE X4 6TH STAGE X5 7TH STAGE X6 8TH STAGE X7 INPUT DATA Figure 3. 1-Wire CRC Generator 4 _______________________________________________________________________________________ X8 Serial Number iButton for more than 120µs, one or more devices on the bus may be reset. The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or three-state outputs. The 1-Wire port of the DS1990R is open drain with an internal circuit equivalent to that shown in Figure 4. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed, the 1-Wire bus has a maximum data rate of 16.3kbps. The value of the pullup resistor primarily depends on the network size and load conditions. For most applications, the optimal value of the pullup resistor is approximately 2.2kΩ. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low Transaction Sequence The protocol for accessing the DS1990R through the 1-Wire port is as follows: • Initialization • ROM Function Command Initialization All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1990R is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. VPUP SIMPLE BUS MASTER DS1990R 1-Wire PORT RPUP DATA Rx Tx Tx Rx = RECEIVE Tx = TRANSMIT 100Ω MOSFET OPEN-DRAIN PORT PIN DS2480B BUS MASTER SERIAL IN SERIAL PORT +5V VDD HOST CPU SERIAL OUT Rx VPP POL 1-W RXD N.C. TXD GND TO 1-Wire DATA DS2480B Figure 4. Hardware Configuration _______________________________________________________________________________________ 5 DS1990R Hardware Configuration Serial Number iButton DS1990R 1-Wire ROM Function Commands Once the bus master has detected a presence pulse, it can issue one of the ROM function commands the DS1990R supports. All ROM function commands are 8 bits long. A list of these commands follows. (See Figure 5 for a flowchart.) BUS MASTER Tx RESET PULSE BUS MASTER Tx ROM FUNCTION COMMAND 33h OR 0Fh READ ROM COMMAND? DS1990R Tx PRESENCE PULSE Read ROM [33h] or [0Fh] F0h SEARCH ROM COMMAND? N Y Y DS1990R Tx FAMILY CODE (1 BYTE) DS1990R Tx BIT 0 DS1990R Tx BIT 0 MASTER Tx BIT 0 N BIT 0 MATCH? Y DS1990R Tx SERIAL NUMBER (6 BYTES) DS1990R Tx BIT 1 DS1990R Tx BIT 1 MASTER Tx BIT 1 N BIT 1 MATCH? Y DS1990R Tx CRC BYTE DS1990R Tx BIT 63 DS1990R Tx BIT 63 MASTER Tx BIT 63 N BIT 63 MATCH? Y Figure 5. ROM Functions Flowchart 6 N This command allows the bus master to read the DS1990R’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave device on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number results in a mismatch of the CRC. Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the ROM code tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Match ROM [55h]/Skip ROM [CCh] The minimum set of 1-Wire ROM function commands includes a Match ROM and a Skip ROM command. Because the DS1990R contains only the 64-bit ROM without any additional data fields, Match ROM and Skip ROM are not applicable. The DS1990R remains silent (inactive) upon receiving a ROM function command that it does not support. This allows the DS1990R to coexist on a multidrop bus with other 1-Wire devices that do respond to Match ROM or Skip ROM. _______________________________________________________________________________________ Serial Number iButton detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP. The DS1990R requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. Except for the presence pulse, the bus master initiates all these signals. To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP to below VILMAX. To get from active to idle, the voltage needs to rise from VILMAX to above VIHMIN. The time it takes for the voltage to make this rise, referenced as ε in Figure 6, depends on the value of the pullup resistor (RPUP) and capacitance of the 1-Wire network attached. The initialization sequence required to begin any communication with the DS1990R is shown in Figure 6. A reset pulse followed by a presence pulse indicates that the DS1990R is ready to receive a ROM function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate for the edge. After the bus master has released the line, it goes into receive mode (Rx). Now the 1-Wire bus is pulled to VPUP through the pullup resistor or, in the case of a DS2480B driver, by active circuitry. When the VIHMIN is crossed, the DS1990R waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To Read/Write Time Slots Data communication with the DS1990R takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. The definitions of the write and read time slots are illustrated in Figure 7. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below VILMAX, the DS1990R starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. Master-to-Slave For a write-one time slot, the voltage on the data line must have risen above VIHMIN after the write-one low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below VILMAX until the write-zero low time tW0LMIN is expired. For most reliable communication, the voltage on the data line should not exceed VILMAX during the entire tW0L window. After the voltage has risen above V IHMIN, the DS1990R needs a recovery time tREC before it is ready for the next time slot. MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE" ε tMSP VPUP VIHMIN VILMAX 0V tRSTL tPDH tF tPDL tREC tRSTH RESISTOR MASTER DS1990R Figure 6. Initialization Procedure: Reset and Presence Pulses _______________________________________________________________________________________ 7 DS1990R 1-Wire Signaling DS1990R Serial Number iButton WRITE-ONE TIME SLOT tW1L VPUP VIHMASTER VIHMIN VILMAX 0V ε tF tSLOT RESISTOR MASTER WRITE-ZERO TIME SLOT tW0L VPUP VIHMASTER VIHMIN VILMAX 0V ε tF tREC tSLOT RESISTOR MASTER READ-DATA TIME SLOT tMSR tRL VPUP VIHMASTER VIHMIN MASTER SAMPLING WINDOW VILMAX 0V δ tF tREC tSLOT RESISTOR MASTER DS1990R Figure 7. Read/Write Timing Diagram 8 _______________________________________________________________________________________ Serial Number iButton The sum of tRL + δ (rise time) on one side and the internal timing generator of the DS1990R on the other side define the master sampling window (t MSRMIN to tMSRMAX) in which the master must perform a read from the data line. For most reliable communication, t RL should be as short as permissible and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS1990R to get ready for the next time slot. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. F3 iButton IB#3NB 21-0252 — F5 iButton IB#5NB 21-0266 — _______________________________________________________________________________________ 9 DS1990R Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VILMAX until the read low time tRL is expired. During the tRL window, when responding with a 0, the DS1990R starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS1990R does not hold the data line low at all, and the voltage starts rising as soon as tRL is over. DS1990R Serial Number iButton Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 5/05 Initial release — 1 8/06 Reworded the UL#913 bullet to “Designed to meet...” 1 2 8/09 Updated the Ordering Information table to include RoHS-compliant packages; removed the UL#913 bullet from the Common iButton Features section 1 8/10 Created newer template-style data sheet; in the Electrical Characteristics table, deleted the Output High Voltage parameter, moved the 1-Wire Pullup voltage parameter from table header to table body, changed VILMAX from 0.8V to 0.3V, added Note 14 to the tW0L specification, changed tW1LMAX from 15μs – to 15μs, and added more details to Notes 14 and 15; added the epsilon timing to the Write-Zero Time Slot in Figure 7 3 2, 3, 8 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.