ETC DS2431

19-4675; Rev 9; 12/10
2135ᆡ2.Xjsf! FFQSPN
``````````````````````````````````` ᄂቶ
ET3542ဵጙ౒2135ᆡ2.Xjsf® FFQSPNበຢǈᎅ႐ৈࡀ߼
໭጑ᔝ߅ǈඛ጑367ᆡăၫ௣ሌ‫ۻ‬ቖྜྷጙৈ9ᔊஂ᏷ࡀ໭
ᒦǈளቅዩᇄᇙઁআᒜࡵFFQSPNࡀ߼໭ă໚ᄂ࢛Ᏼ᎖ǈ
႐ৈࡀ߼໭጑ሤઑࣖೂǈభጲ࡝ࣖ࿸ᒙቖۣઐ૞FQSPN
शᑞෝါǈᏴFQSPNशᑞෝါሆǈჅᎌᆡࡼᓨზᒑถ࠭2
‫߅ܤ‬1ăET3542ᄰਭ࡝߿࢛2.Xjsfᔐሣ஠ቲᄰቧǈᄰቧ‫ݧ‬
፿‫ܪ‬ᓰࡼ2.Xjsf቏ፇăඛৈ໭ୈ࣒ᎌᆎጙࡼĂ‫ݙ‬ถৎখࡼ
75ᆡSPNᓖ‫ݿ‬൩ǈকᓖ‫ݿ‬൩ᎅ৔‫ޣ‬਒రቖྜྷበຢăᏴࣶ
࢛ࡼ2.Xjsfᆀ൥ણஹᒦǈকᓖ‫ݿ‬൩፿᎖࣪໭ୈ஠ቲኰᒍă
♦ 2135ᆡFFQSPNࡀ߼໭ǈॊᆐ႐጑ǈඛ጑367ᆡ
``````````````````````````````````` ።፿
๼ୈ0QDCဤܰ
♦ ࣖೂࡼࡀ߼໭጑ǈభጲ፼௉ቖۣઐ૞࿸ᒙ߅FQSPN
शᑞෝါ)Đቖྜྷ1đ*
♦ ᄰਭ༤ધ࢛ᒣૄᎧ൉݆ǈ࣪ᐅဉᄟୈሆࡼቶถ஠ቲ
ᎁછ
♦ JFD! 2111.5.3! 5଀FTEۣઐ)࢜ቯ±9lW୻߿ह࢟ෝါĂ
±26lW໮ᇺह࢟ෝါ*
♦ భᏴ.51°Dᒗ,96°DᆨࣞपᆍĂ3/9Wᒗ6/36W࢟ኹप
ᆍด஠ቲࣗቖ‫ݷ‬ᔫ
♦ ‫ږ‬ᑍ2.Xjsf቏ፇǈᏴ26/5lcqt૞236lcqtႥൈሆဧ፿
࡝ৈၫᔊቧ੓Ꭷᓍ૦ᄰቧ
ጛ೦ࠅঢ໭ቅᓰၫ௣ࡀ߼
۞౪JFFF! Q2562/5ᒝถࠅঢ໭Ᏼดࡼෝผࠅঢ໭ቅᓰ
ࡌ፝෥ਫ਼ጲૺᇞ৴ဤܰ
੒‫ݢ‬၉ઁ਌ಯ
``````````````````````````` ࢜ቯ৔ᔫ࢟വ
``````````````````````````````` ࢾ৪ቧᇦ
PART
VCC
RPUP
IO
μC
DS2431
GND
TEMP RANGE
PIN-PACKAGE
DS2431+
-40°C to +85°C
3 TO-92
DS2431+T&R
-40°C to +85°C
3 TO-92
DS2431P+
-40°C to +85°C
6 TSOC
DS2431P+T&R
-40°C to +85°C
6 TSOC
DS2431G+
-40°C to +85°C
2 SFN
DS2431G+T&R
-40°C to +85°C
2 SFN
DS2431Q+T&R
-40°C to +85°C
6 TDFN-EP* (2.5k pcs)
DS2431X-S+
-40°C to +85°C
3x3 UCSPR (2.5k pcs)
DS2431X+
-40°C to +85°C
3x3 UCSPR (10k pcs)
ᓖǖ௳ࡒᒦUP.:3ॖᓤࡼ፛୭ମ௦Ꮦᆐ211njm! )3/65nn*ǈሮᇼቧ
ᇦ༿‫ݬ‬ఠॖᓤᅄă
+‫ܭ‬ာᇄ໺)Qc*0९੝SpIT‫ܪ‬ᓰࡼॖᓤă
U'S! >! ௳ࡒ۞ᓤă
*FQ! >! ൡ੆๤ă
፛୭๼ᒙᏴၫ௣ᓾ೯ࡼᔢઁ৊߲ă
2.XjsfဵNbyjn! Joufhsbufe! Qspevdut-! Jod/ࡼᓖ‫ݿ‬࿜‫ܪ‬ă
________________________________________________________________ Maxim Integrated Products
1
‫۾‬ᆪဵ፞ᆪၫ௣ᓾ೯ࡼፉᆪǈᆪᒦభถࡀᏴडፉ࿟ࡼ‫ݙ‬ᓰཀྵ૞ࡇᇙăྙኊ஠ጙ‫ݛ‬ཀྵཱྀǈ༿Ᏼิࡼ࿸ଐᒦ‫ݬ‬ఠ፞ᆪᓾ೯ă
ᎌਈଥৃĂ৙ૡૺࢿ৪ቧᇦǈ༿ೊ൥Nbyjn዇ᒴሾ၉ᒦቦǖ21911!963!235:!)۱ᒦਪཌ*ǈ21911!263!235:!)ฉᒦਪཌ*ǈ
૞षᆰNbyjnࡼᒦᆪᆀᐶǖdijob/nbyjn.jd/dpnă
ET3542
``````````````````````````````````` গၤ
ET3542
2135ᆡ2.Xjsf! FFQSPN
ABSOLUTE MAXIMUM RATINGS
IO Voltage Range to GND .......................................-0.5V to +6V
IO Sink Current ...................................................................20mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (excluding UCSP, soldering, 10s).....+300°C
Soldering Temperature (reflow)
TO-92 ............................................................................+250°C
AIl other packages, excluding SFN ..............................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
VPUP
(Note 2)
2.8
5.25
V
1-Wire Pullup Resistance
RPUP
(Notes 2, 3)
0.3
2.2
k
Input Capacitance
CIO
(Notes 4, 5)
1000
pF
Input Load Current
IL
0.05
6.7
μA
0.5
VPUP 1.8
V
0.5
V
V
IO pin at VPUP
High-to-Low Switching Threshold
VTL
(Notes 5, 6, 7)
Input Low Voltage
VIL
(Notes 2, 8)
Low-to-High Switching Threshold
VTH
(Notes 5, 6, 9)
1.0
VPUP 1.0
Switching Hysteresis
VHY
(Notes 5, 6, 10)
0.21
1.70
V
Output Low Voltage
VOL
At 4mA (Note 11)
0.4
V
Recovery Time
(Notes 2,12)
tREC
Rising-Edge Hold-Off Time
(Notes 5, 13)
tREH
Time Slot Duration
(Notes 2, 14)
t SLOT
Standard speed, RPUP = 2.2k
Overdrive speed, RPUP = 2.2k
Overdrive speed, directly prior to reset
pulse; RPUP = 2.2k
Standard speed
Overdrive speed
5
2
μs
5
0.5
5.0
Not applicable (0)
Standard speed
65
Overdrive speed
8
μs
μs
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time (Note 2)
tRSTL
Presence-Detect High Time
t PDH
Presence-Detect Low Time
t PDL
Presence-Detect Sample Time
(Notes 2, 15)
tMSP
2
Standard speed
480
640
Overdrive speed
48
80
Standard speed
15
60
Overdrive speed
2
6
Standard speed
60
240
Overdrive speed
8
24
Standard speed
60
75
Overdrive speed
6
10
_______________________________________________________________________________________
μs
μs
μs
μs
2135ᆡ2.Xjsf! FFQSPN
(TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire WRITE
Standard speed
Write-Zero Low Time
(Notes 2, 16, 17)
Write-One Low Time
(Notes 2, 17)
tW0L
tW1L
60
120
Overdrive speed, VPUP > 4.5V
5
15.5
Overdrive speed
6
15.5
Standard speed
1
15
Overdrive speed
1
2
Standard speed
5
15 - Overdrive speed
1
2-
Standard speed
tRL + 15
Overdrive speed
tRL + 2
μs
μs
IO PIN: 1-Wire READ
Read Low Time
(Notes 2, 18)
tRL
Read Sample Time
(Notes 2, 18)
tMSR
μs
μs
EEPROM
Programming Current
I PROG
(Notes 5, 19)
0.8
mA
Programming Time
t PROG
(Notes 20, 21)
10
ms
Write/Erase Cycles (Endurance)
(Notes 22, 23)
NCY
Data Retention
(Notes 24, 25, 26)
tDR
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
At +25°C
200k
At +85°C (worst case)
50k
At +85°C (worst case)
40
Years
Specifications at TA = -40°C are guaranteed by design only and not production tested.
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2kΩ resistor is used to pull
up the data line, 2.5μs after VPUP has been applied, the parasite capacitance does not affect normal communications.
Guaranteed by design, characterization, and/or simulation only. Not production tested.
VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of
VTL, VTH, and VHY.
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.
The I-V characteristic is linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to tW0LMIN + tRECMIN.
Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS2431 present.
Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN.
Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table.
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
_______________________________________________________________________________________
3
ET3542
ELECTRICAL CHARACTERISTICS (continued)
ET3542
2135ᆡ2.Xjsf! FFQSPN
Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval
should be such that the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, a lowimpedance bypass of RPUP, which can be activated during programming, may need to be added.
Note 20: Interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by
the device has returned from IPROG to IL.
Note 21: tPROG for units branded version “A1” is 12.5ms. tPROG for units branded version “A2” and later is 10ms.
Note 22: Write-cycle endurance is degraded as TA increases.
Note 23: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 24: Data retention is degraded as TA increases.
Note 25: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 26: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
࣪ᑍ‫ܭ‬
LEGACY VALUES
PARAMETER
STANDARD SPEED
(μs)
DS2431 VALUES
OVERDRIVE SPEED
(μs)
STANDARD SPEED
(μs)
OVERDRIVE SPEED
(μs)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
61
(undefined)
7
(undefined)
65*
(undefined)
8*
(undefined)
tRSTL
480
(undefined)
48
80
480
640
48
80
t PDH
15
60
2
6
15
60
2
6
t PDL
60
240
8
24
60
240
8
24
tW0L
60
120
6
16
60
120
6
15.5
t SLOT (including tREC)
*ᎌፀ஠ቲࡼኀখǗᎅ᎖ৎখ೫2.Xjsf༄࣡ǈኊገৎ‫ૂࡼޠ‬আဟମă
ᓖǖ࠰ᄏၫ௣‫ݙ‬९੝ࠅᄻࡼ2.Xjsf‫ޘ‬ອਖৃă
4
_______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
፛୭
෗߂
TSOC
TO-92
TDFN-EP
SFN
UCSPR
3, 4, 5, 6
3
1, 4, 5, 6
—
A2, A3, C2,
C3
N.C.
2
2
2
1
C1
IO
1
1
3
2
A1
GND
—
—
EP
—
—
EP
৖ถ
ᇄೌ୻ă
2.Xjsfᔐሣ୻ాǈധ૵ఎവǈኊᅪ୻࿟
౯࢟ᔜă
‫ݬ‬ఠ࢐ă
ൡ੆๤ǈ୓ൡ੆๤௿Ꮲ੆୻ᒗ࢟വ‫ࡼۇ‬
࢐‫ށ‬ǈጲۣᑺᑵ‫ޟ‬৔ᔫǈሮᇼቧᇦ༿‫ݬ‬
ఠ።፿‫܊‬଑4384ǖFyqptfe! Qbet;! B! Csjfg
Jouspevdujpoă
``````````````````````````````` ሮᇼႁී
ET3542࡝በຢ۞਺2135ᆡࡼFFQSPNĂ9ᔊஂ଎ࡀ໭0఼ᒜ
጑)፿ઓᔢࣶభࣗ0ቖ8ৈᔊஂ*ጲૺཝ৖ถ2.Xjsf୻ాăඛ
ຢET3542߲‫ޣ‬ဟ࣒ࡒᎌ૮਒రྜྷࡼ75ᆡSPNᓖ‫ݿ‬൩ǈጲ
ۣᑺ໚௾࣪భႩቶăၫ௣‫ږ‬ᑍ2.Xjsf቏ፇࠈቲࠅၒǈᒑኊ
ገጙᄟၫ௣ሣਜ਼ऩૄ࢐ሣăET3542ᎌጙৈ߂ᆐ᏷ࡀ໭ࡼ
এଝࡀ߼ཌǈᏴሶᓍࡀ߼໭૞଎ࡀ໭጑ቖྜྷၫ௣ဟ፿ᔫ
દࡀ໭ăၫ௣၅ሌ‫ۻ‬ቖྜྷ᏷ࡀ໭ǈ݀భ࠭ᑚಱૄࣗăၫ
௣ளਭቅዩᇄᇙઁǈDpqz Tdsbudiqbeෘഎ୓ၫ௣ࠅ႙ࡵᔢ
ᒫࡀ߼໭࡝ᏄăET3542ࡼ࢜ቯ።፿۞౪๼ୈ0QDCဤܰĂ
ጛ೦ࠅঢ໭ቅᓰၫ௣ࡀ߼Ă۞౪JFFF! Q2562/5ᒝถࠅঢ໭
Ᏼดࡼෝผࠅঢ໭ቅᓰĂࡌ፝෥ਫ਼ጲૺᇞ৴ဤܰਜ਼੒‫ݢ‬
၉ઁ਌ಯă
PARASITE POWER
IO
1-Wire
FUNCTION CONTROL
64-BIT
LASERED ROM
DS2431
MEMORY
FUNCTION
CONTROL UNIT
ᔐၤ
CRC-16
GENERATOR
ᅄ2Ⴥာࡼऱౖᅄႁී೫ET3542ᓍ఼࡝ᏄᎧࡀ߼໭‫ݝ‬ॊࡼ
ਈᇹăET3542۞౪႐ৈᓍገၫ௣‫ݝ‬ୈǖ75ᆡ਒రSPNĂ
75ᆡ᏷ࡀ໭Ă႐ৈ43ᔊஂFFQSPN጑ጲૺ75ᆡ଎ࡀ໭጑ă
DATA MEMORY
4 PAGES OF
256 BITS EACH
64-BIT
SCRATCHPAD
REGISTER PAGE
64 BITS
ᅄ2/! ऱౖᅄ
_______________________________________________________________________________________
5
ET3542
``````````````````````````````````````````````````````````````````````````` ፛୭ႁී
ET3542
2135ᆡ2.Xjsf! FFQSPN
DS2431 COMMAND LEVEL:
1-Wire ROM FUNCTION COMMANDS
(SEE FIGURE 9)
DS2431-SPECIFIC
MEMORY FUNCTION COMMANDS
(SEE FIGURE 7)
AVAILABLE COMMANDS:
DATA FIELD AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT REG. #, RC-FLAG, OD-FLAG
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
READ MEMORY
64-BIT SCRATCHPAD, FLAGS
64-BIT SCRATCHPAD
DATA MEMORY, REGISTER PAGE
DATA MEMORY, REGISTER PAGE
ᅄ3/! 2.Xjsf቏ፇ‫ށ‬உ৩
MSB
LSB
8-BIT
CRC CODE
MSB
8-BIT FAMILY CODE
(2Dh)
48-BIT SERIAL NUMBER
LSB MSB
LSB MSB
LSB
ᅄ4/! 75ᆡ਒రSPN
2.Xjsf቏ፇࡼ‫ࠨށ‬உ৩ྙᅄ3Ⴥာǈᓍ૦‫ܘ‬ኍ၅ሌख႙ྙ
ሆ໕ᄟSPN৖ถෘഎᒦࡼጙᄟǖSfbe! SPNĂNbudi! SPNĂ
Tfbsdi! SPNĂTljq! SPNĂSftvnfĂPwfsesjwf.Tljq! SPN૞
Pwfsesjwf.Nbudi! SPNăᏴ‫ږ‬ᑍ‫ܪ‬ᓰႥൈᒊቲᅲ߅Pwfsesjwf.
Tljq! SPN૞Pwfsesjwf.Nbudi! SPNෘഎᔊஂઁǈ໭ୈ஠ྜྷ
ਭདࣅෝါǈႲઁࡼᄰቧ‫ݧ‬፿ৎ঱Ⴅൈ஠ቲăᎧSPN৖
ถෘഎᎌਈࡼ቏ፇႁී୅ᅄ:ă߅৖࢐ᒊቲ೫SPN৖ถෘ
എઁǈ௓భጲ஠ቲࡀ߼໭‫ݷ‬ᔫǈᓍ૦భख߲႐ᄟࡀ߼໭
৖ถෘഎᒦࡼྀጙᄟăᎧࡀ߼໭৖ถෘഎᎌਈࡼ቏ፇႁ
ී୅ᅄ8ăჅᎌၫ௣ࣗቖဟǈ࣒ဵࢅᆡᏴ༄ă
75ᆡ਒రSPN
ඛৈET3542࣒ᎌጙৈᆎጙࡼ75ᆡSPN൩ǈ໚ᒦ༄9ᆡဵ2.
Xjsfଜᔙ൩ǈᒦମ59ᆡဵᆎጙࡼኔ೰੓ǈᔢઁ9ᆡဵ༄67
ᆡࡼክણྑ᎜ቅዩ)DSD*൩ǈሮ୅ᅄ4Ⴥာă2.Xjsf! DSD
ቅዩ൩ᄰਭጙৈ۞౪ጤᆡ଎ࡀ໭ਜ਼YPSඡࡼࣶሲါखည
໭‫ޘ‬ညǈྙᅄ 5 ჅာăকࣶሲါᆐǖY 9 ,! Y 6 ,! Y 5 ,! 2ă
ᎌਈ2.Xjsf DSDቅዩ൩ࡼৎࣶቧᇦ༿‫ݬ‬ఠ።፿‫܊‬଑38ǖಯ
ஊਜ਼Ꮵ፿Nbyjn jCvuupo® ‫ޘ‬ອᒦࡼክણྑ᎜ቅዩ)DSD*ă
ጤᆡ଎ࡀ໭߱ဪછဟ‫༹ۻ‬1ă཭ઁ࠭ଜᔙ൩ࡼᔢࢅᎌ቉ᆡ
ఎဪǈඛࠨጤྜྷጙᆡăࡩଜᔙ൩ࡼ࢒9ᆡ‫ۻ‬ጤྜྷઁǈᏳጤ
ྜྷኔ೰੓ăࡩኔ೰੓ࡼᔢઁጙᆡጐ‫ۻ‬ጤྜྷဟǈጤᆡ଎ࡀ
໭ࡼᒋ૾ᆐDSD൩ࡼᒋăଖኚጤྜྷ9ᆡDSD൩ઁǈጤᆡ଎
ࡀ໭Ⴥᎌᆡਙ1ă
jCvuupoဵNbyjn! Joufhsbufe! Qspevdut-! Jod/ࡼᓖ‫ݿ‬࿜‫ܪ‬ă
6
_______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
ET3542
POLYNOMIAL = X8 + X5 + X4 + 1
1ST
STAGE
X0
2ND
STAGE
X1
3RD
STAGE
X2
4TH
STAGE
5TH
STAGE
X3
6TH
STAGE
X4
X5
7TH
STAGE
X6
8TH
STAGE
X7
X8
INPUT DATA
ᅄ5/! 2.Xjsf! DSDखည໭
````````````````````````````` ࡀ߼໭षᆰ
ၫ௣ࡀ߼໭ਜ਼଎ࡀ໭ᆡ᎖ጙৈሣቶ࢐ᒍహମǈྙᅄ6Ⴥာă
ၫ௣ࡀ߼໭ਜ਼଎ࡀ໭࣪ࣗ‫ݷ‬ᔫ඗ᎌሢᒜăET3542 ࡼ
FFQSPNᑫ೰ৢᎌ29ቲǈඛቲ9ᔊஂă༄27ቲ‫ࢀۻ‬ॊᆐ5
ৈࡀ߼໭጑)ඛ጑43ᔊஂ*ǈᑚ5጑ᆐᓍၫ௣ࡀ߼໭ǈభጲ
ᄰਭ࿸ᒙ଎ࡀ໭ቲᒦሤ።ࡼۣઐᔊஂ୓ඛጙ጑࡝ࣖ࿸ᒙ
߅ఎह)ᇄۣઐ*Ăቖۣઐ૞FQSPNෝါăᔢઁೝቲ۞౪
ۣઐ଎ࡀ໭ਜ਼ۣഔᔊஂă଎ࡀ໭ቲ۞౪5ৈۣઐ఼ᒜᔊஂĂ
2ৈআᒜۣઐᔊஂĂ2ৈ৔‫ޣ‬Ꮎᒙᔊஂਜ਼3ৈ፿ઓᔊஂ0‫ޣ‬࿜
JEᔊஂă‫ޣ‬࿜JEభጲဵఱઓᄋ৙ࡼ‫ܪ‬ဤ൩ǈ፿᎖‫ۑ‬ᓐ።
፿ྟୈဤܰᎧET3542ᎌਈࡼ‫ޘ‬ອă
ྙኊ࿸ᒙ݀ᓖ‫ࢾݿ‬ᒜࡼJEǈ༿Ꭷ৔‫ޣ‬ೊᇹăᔢઁጙቲᆐ୓
౶ࡼ።፿Ⴥۣഔǈ඗ᎌࢾፃS0X৖ถǈ‫ݙ‬ถဧ፿ᑚቋ‫ݷ‬ᔫă
ADDRESS RANGE
TYPE
DESCRIPTION
PROTECTION CODES
0000h to 001Fh
R/(W)
Data Memory Page 0
—
0020h to 003Fh
R/(W)
Data Memory Page 1
—
0040h to 005Fh
R/(W)
Data Memory Page 2
—
0060h to 007Fh
R/(W)
Data Memory Page 3
—
0080h*
R/(W)
Protection Control Byte Page 0
55h: Write Protect P0; AAh: EPROM Mode P0;
55h or AAh: Write Protect 80h
0081h*
R/(W)
Protection Control Byte Page 1
55h: Write Protect P1; AAh: EPROM Mode P1;
55h or AAh: Write Protect 81h
0082h*
R/(W)
Protection Control Byte Page 2
55h: Write Protect P2; AAh: EPROM Mode P2;
55h or AAh: Write Protect 82h
0083h*
R/(W)
Protection Control Byte Page 3
55h: Write Protect P3; AAh: EPROM Mode P3;
55h or AAh: Write Protect 83h
0084h*
R/(W)
Copy Protection Byte
55h or AAh: Copy Protect 0080h:008Fh, and Any
Write-Protected Pages
0085h
R
Factory Byte. Set at Factory.
AAh: Write Protect 85h, 86h, 87h;
55h: Write Protect 85h; Unprotect 86h, 87h
0086h
R/(W)
User Byte/Manufacturer ID
—
0087h
R/(W)
User Byte/Manufacturer ID
—
0088h to 008Fh
—
Reserved
—
*ጙࡡ‫߈ܠ‬ᆐBBi૞66iઁǈক࢐ᒍ‫ܤ‬ᆐᒑࣗăభۣࡀ໚჈Ⴥᎌࡔ൩ǈࡣ࢐ᒍቖۣઐጲૺྀੜ૮૚৖ถ߹ᅪă
ᅄ6/! ࡀ߼໭፯࿴
_______________________________________________________________________________________
7
ET3542
2135ᆡ2.Xjsf! FFQSPN
߹FFQSPNᓍᑫ೰ᅪǈથ۞਺ጙৈ9ᔊஂጵပ᏷ࡀ໭ăሶ
FFQSPNᑫ೰ቖྜྷၫ௣۞౪ೝৈ‫ݛ‬ᒾă၅ሌǈၫ௣ሌቖࡵ
᏷ࡀ໭ǈ཭ઁ‫ۻ‬আᒜࡵᓍᑫ೰ăᑚ௓Ꮴ኏፿ઓᏴ୓ၫ௣আ
ᒜࡵᓍᑫ೰༄ሌ࣪ቖྜྷ᏷ࡀ໭ࡼၫ௣஠ቲቅዩă໭ୈஞᑽ
ߒᑳቲ)9ᔊஂ*আᒜ‫ݷ‬ᔫăᆐۣᑺ᏷ࡀ໭ᒦ፿᎖আᒜ‫ݷ‬ᔫࡼ
ၫ௣ᎌ቉ǈXsjuf Tdsbudiqbeෘഎᄋ৙ࡼ࢐ᒍ‫ܘ‬ኍఎဪ᎖ጙ
ቲࡼ‫ܟ‬ஏࠀǈऎ༦᏷ࡀ໭‫ܘ‬ኍቖྜྷ9ৈᅲᑳࡼᔊஂă
ۣઐ఼ᒜ଎ࡀ໭௼ࢾᒊቲXsjuf Tdsbudiqbeෘഎဟၒྜྷၫ௣
ྙੜ‫ۻ‬ଝᏲࡵ᏷ࡀ໭ăۣઐ఼ᒜ଎ࡀ໭࿸ᒙᆐ66i )ቖۣઐ*
ဟǈၒྜྷࡼၫ௣‫ۻ‬઄൒ǈᆡ᎖෹‫࢐ܪ‬ᒍࡼᓍࡀ߼໭ၫ௣
‫ۻ‬ଝᏲࡵ᏷ࡀ໭ăۣઐ఼ᒜ଎ࡀ໭࿸ᒙᆐBBi )FQSPNෝ
ါ*ဟǈၒྜྷၫ௣Ꭷ෹‫࢐ܪ‬ᒍࡼᓍࡀ߼໭ၫ௣஠ቲ൝૷Ꭷǈ
ଐႯஉਫ‫ۻ‬ଝᏲࡵ᏷ࡀ໭ăۣઐ఼ᒜ଎ࡀ໭ࡼ໚჈ྀፀ࿸
ᒙᒋဧሤਈࡀ߼໭጑ࠀ᎖‫ݙ‬ሢᒜቖ‫ݷ‬ᔫࡼఎहᓨზăۣ
ઐ఼ᒜᔊஂ࿸ᒙ߅66i૞BBiဟǈকᔊஂᔈ࿽ጐ၊ቖۣઐă
ۣઐ఼ᒜᔊஂ࿸ᒙ߅66iဟ݀‫ݙ‬ᔜᒏআᒜ‫ݷ‬ᔫăᑚ௓Ꮴ኏
‫ۻ‬ቖۣઐࡼၫ௣Ᏼ໭ୈด‫ݝ‬஠ቲၮቤ)૾፿ࡩ༄ၫ௣ᒮቤ
‫*߈ܠ‬ă
আᒜۣઐᔊஂ፿᎖ৎ঱ࡼ‫ڔ‬ཝ଀ܰǈஞ።Ᏼ໚჈Ⴥᎌۣઐ
఼ᒜᔊஂĂ፿ઓᔊஂਜ਼ቖۣઐ጑‫ۻ‬࿸ᒙ߅ᔢᒫᒋઁ‫ۻݣ‬
ဧ፿ăྙਫআᒜۣઐᔊஂᒙᆐ66i૞BBiǈ୓ᔜᒏჅᎌ၂
ᅄሶ଎ࡀ໭ቲਜ਼፿ઓᔊஂቲআᒜࡼ‫ݷ‬ᔫăࠥᅪǈჅᎌ၂ᅄ
ሶቖۣઐࡼᓍࡀ߼໭጑আᒜࡼ‫ݷ‬ᔫ)૾ၮቤ*ጐ‫ۻ‬ᔜᒏă
࢐ᒍ଎ࡀ໭ਜ਼ࠅၒᓨზ
ET3542ဧ፿4ৈ࢐ᒍ଎ࡀ໭ǖUB2ĂUB3ጲૺF0T )ᅄ7*ă
ᑚቋ଎ࡀ໭Ᏼ኏ࣶ໚჈2.Xjsf໭ୈᒦ࣒੪‫ޟ‬୅ǈࡣ፿जᎧ
ET3542൒ᎌ‫ݙ‬ᄴă଎ࡀ໭UB2ਜ਼UB3‫ܘ‬ኍଝᏲ஠ቲၫ௣ቖ
ྜྷ૞߲ࣗࡼ෹‫࢐ܪ‬ᒍă଎ࡀ໭F0Tဵጙৈᒑࣗࡼࠅၒᓨზ
଎ࡀ໭ǈ፿౶ቅዩቖ‫ݷ‬ᔫෘഎࡼၫ௣ᅲᑳቶăF0TࡼF\3;1^
ᆡଝᏲXsjuf TdsbudiqbeෘഎჅၒྜྷࡼU\3;1^ᆡǈඛၒྜྷጙ
ৈၫ௣ᔊஂଝ2ăᑚဣଔ࿟ဵጙৈ9ᔊஂ᏷ࡀ໭ด‫ࡼݝ‬ᔊ
ஂஉၦມጤଐၫ໭ăF0T଎ࡀ໭ࡼ࢒6ᆡǈ߂ᔫQGǈྙਫ᏷
ࡀ໭ၫ௣ፐࢬ࢟૞ᓍ૦ख႙ࡼၫ௣ᔊஂᆚถ‫ږ‬ገཇᄘ൸
ᑳৈ᏷ࡀ໭ऎᇄ቉ǈᐌকᆡ‫ۻ‬ᒙᆐ൝૷2ăᆐ೫ဧቖྜྷ᏷
ࡀ໭ၫ௣ᎌ቉ǈU\3;1^ᆡ‫ܘ‬ኍᆐ1ǈऎ༦ᓍ૦‫ܘ‬ኍख႙9ৈ
ၫ௣ᔊஂă࢒4Ă5Ă7ᆡ඗ᎌࢾፃ৖ถǈ໚ࣗၫᔐᆐ1ăF0T
଎ࡀ໭ࡼᔢ঱ᆡǈ߂ᆐ၈ཚ኏భ)BB*ǈᔫᆐᒎာ᏷ࡀ໭
ၫ௣ጯ‫ۻ‬আᒜࡵ෹‫߼ࡀܪ‬໭࢐ᒍࡼ‫ܪ‬ᒔᆡǈሶ᏷ࡀ໭ᒦ
ቖྜྷၫ௣୓༹߹ࠥ‫ܪ‬ᒔᆡă
ࡒቅዩࡼቖ‫ݷ‬ᔫ
ሶET3542ቖྜྷၫ௣ဟǈ‫ܘ‬ኍ‫ڳ‬᏷ࡀ໭፿ᔫᒦମࡀ߼໭ǈ
၅ሌᓍ૦ख႙Xsjuf Tdsbudiqbeෘഎ݀ᒎࢾ෹‫࢐ܪ‬ᒍǈႲઁ
ख႙ገቖྜྷ᏷ࡀ໭ࡼၫ௣ăᓖፀDpqz! Tdsbudiqbeෘഎ‫ܘ‬ኍ
Ᏼࡉࡵ9ᔊஂ‫ܟ‬ஏဟᒊቲǈ૾෹‫࢐ܪ‬ᒍࡼࢅ4ᆡ)U3ĂU2Ă
U1*‫ܘ‬ኍࢀ᎖ 111căྙਫ U\3;1^ဵऻ 1 ᒋǈআᒜෘഎ୓‫ۻ‬
BIT #
7
6
5
4
3
2
1
0
TARGET ADDRESS (TA1)
T7
T6
T5
T4
T3
T2
T1
T0
TARGET ADDRESS (TA2)
T15
T14
T13
T12
T11
T10
T9
T8
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
AA
0
PF
0
0
E2
E1
E0
ᅄ7/! ࢐ᒍ଎ࡀ໭
8
_______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
ྙਫጙ༤ᑵ‫ޟ‬ǈೝৈ‫ܪ‬ᒔᆡ௿‫༹ۻ‬ഃăࠥဟᓍ૦૾భଖ
ኚࣗནਜ਼ዩᑺඛৈၫ௣ᔊஂăᓍ૦ᅲ߅ၫ௣ቅዩઁǈ௓
భख႙ಿྙDpqz Tdsbudiqbeෘഎăࠥෘഎᒄઁ‫ܘ‬ኍஜႲྯ
ৈ࢐ᒍ଎ࡀ໭UB2ĂUB3ਜ਼F0Tᒦࡼၫ௣ăᓍ૦።ᄰਭࣗ
᏷ࡀ໭૝ནᑚቋ଎ࡀ໭ࡼดྏă
````````````````````````` ࡀ߼໭৖ถෘഎ
ࡀ߼໭৖ถഗ߈ᅄ)ᅄ8*ႁී೫षᆰET3542ࡀ߼໭Ⴥኊገ
ࡼ቏ፇă‫۾‬ᆪࡼ ࡀ߼໭৖ถာಿ ‫ݝ‬ॊ৊߲೫ጙৈྙੜಽ
፿ᑚቋ৖ถࣗནਜ਼ቖྜྷၫ௣ࡼာಿăᓍ૦ਜ਼ET3542ᒄମ
భᏴ‫ܪ‬ᓰႥൈ)෦ཱྀᒋǈPE > 1*૞঱Ⴅෝါ)PE > 2*ሆᄰ
ቧăྙ඗ᎌීཀྵ࿸ᒙ߅঱ႥෝါǈET3542෦ཱྀጲ‫ܪ‬ᓰႥ
ൈᄰቧă
Xsjuf! Tdsbudiqbe! \1Gi^
Xsjuf! Tdsbudiqbeෘഎး፿᎖ၫ௣ࡀ߼໭ਜ਼଎ࡀ໭጑ᒦࡼభ
ቖ࢐ᒍăᆐ೫ۣᑺ᏷ࡀ໭ᒦࡼၫ௣ถ৫‫ۻ‬ᑵཀྵআᒜࡵࡀ߼
໭ᑫ೰ᒦǈ፿ઓ‫ܘ‬ኍۣᑺXsjuf! Tdsbudiqbeෘഎᒦࡼ9ৈၫ௣
ᔊஂఎဪ᎖ጙৈᎌ቉ቲ‫ܟ‬ஏࠀăXsjuf! Tdsbudiqbeෘഎ୻၊
ᇄ቉࢐ᒍਜ਼‫ݙ‬ᅲᑳࡼࡀ߼໭ቲǈࡣઁኚࡼDpqz! Tdsbudiqbe
ෘഎ୓‫ۻ‬ᔜᒏă
ख߲Xsjuf Tdsbudiqbeෘഎઁǈᓍ૦‫ܘ‬ኍ၅ሌख႙3ৈᔊஂ
ࡼ෹‫࢐ܪ‬ᒍǈ୻ᓹख႙ገቖྜྷ᏷ࡀ໭ࡼၫ௣ăቖྜྷ᏷ࡀ
໭ࡼၫ௣໦ဪᔊஂມጤ೟ᆐU\3;1^ăF0TࡼF\3;1^ᆡଝᏲ໦
ဪᔊஂມጤ೟ǈઁෂඛ၃ࡵጙৈၫ௣ᔊஂଝ2ăF\3;1^ᔢᒫ
உਫᆐᔢઁ‫ۻ‬ቖྜྷ᏷ࡀ໭ࡼᅲᑳᔊஂࡼມጤ೟ăஞ୻၊
ᅲᑳၫ௣ᔊஂă
ࡩᒊቲXsjuf TdsbudiqbeෘഎဟǈET3542ด‫ࡼݝ‬DSDखည໭
)ᅄ24*ଐႯᑳৈၫ௣ഗࡼDSDቅዩ൩ǈၫ௣ഗ໦ဪ᎖ෘഎ
ࡔ൩ǈᒫᒏ᎖ᓍ૦ख႙ࡼᔢઁጙৈၫ௣ᔊஂăকDSDቅዩ
൩ᎅDSD.27ࣶሲါည߅ǈଐႯဟ၅ሌ༹߹DSDखည໭ǈ཭
ઁၿኔጤྜྷXsjuf Tdsbudiqbeෘഎࡼෘഎࡔ൩)1Gi*Ă෹‫࢐ܪ‬
ᒍ)UB2ਜ਼UB3*ጲૺჅᎌၫ௣ᔊஂăገᓖፀࡼဵǈDSD.27
ଐႯဟဧ፿ࡼဵᎅᓍ૦ဣଔख႙ࡼUB2ĂUB3ਜ਼ၫ௣ᔊஂă
ᓍ૦భᏴྀፀဟମᒫᒏXsjuf! Tdsbudiqbeෘഎăࡣྙਫቖྜྷ
ၫ௣ࡉࡵ᏷ࡀ໭࿟ሢ)F\3;1^ > 222c*ǈᓍ૦భख႙27ৈࣗ
ဟᇺ݀၃ࡵET3542‫ޘ‬ညࡼDSDቅዩ൩ă
ྙਫXsjuf Tdsbudiqbeෘഎ၂ᅄ࣪ቖۣઐཌᎮ஠ቲቖྜྷǈ᏷
ࡀ໭୓ଝᏲࡀ߼໭Ꮗᎌࡼၫ௣ǈऎ‫ဵݙ‬ᓍ૦ख႙ࡼၫ௣ă
ಢ႒࢐ǈྙਫ෹‫࢐ܪ‬ᒍ጑ᆐFQSPNෝါǈ᏷ࡀ໭ଝᏲࡼ
ᐌဵᓍ૦ख႙ࡼၫ௣Ꭷࡀ߼໭Ꮗᎌၫ௣൝૷Ꭷࡼஉਫă
_______________________________________________________________________________________
9
ET3542
ᒦᒏăᏴጙࢾᄟୈሆ)୅ Xsjuf! Tdsbudiqbe! \1Gi^‫ݝ‬ॊ*ǈᓍ૦
୓୻၃ࡵጙৈन൩ࡼDSD.27ቅዩ൩ǈ፿᎖ቅዩෘഎĂ࢐
ᒍ)ဣଔख႙ࡼ࢐ᒍ*ਜ਼ᆡ᎖Xsjuf Tdsbudiqbeෘഎኔ೰෣ᆘ
ࡼၫ௣ă၃ࡵকDSDቅዩ൩ઁǈᓍ૦୓໚Ꭷᔈ଄ࡼଐႯ
உਫ஠ቲ‫୷܈‬ǈ๨ࣥᄰቧဵ॥߅৖ǈ݀௼ࢾဵ॥ଖኚᒊ
ቲDpqz Tdsbudiqbeෘഎăྙਫᓍ૦඗ᎌ୻၃ࡵDSD.27൩ǈ
ᓍ૦።ख႙ጙᄟSfbe Tdsbudiqbeෘഎ౶ዩᑺၫ௣ࡼᅲᑳቶă
Ᏼૄ႙᏷ࡀ໭ၫ௣༄ǈET3542ሌᒮআ෹‫࢐ܪ‬ᒍUB2ਜ਼UB3ǈ
݀ख႙F0T଎ࡀ໭ᒋăྙਫQG‫ܪ‬ᒔᆡᒙᆡǈႁීၫ௣ᆚถ
ᑵཀྵ႙ࡉ᏷ࡀ໭૞ᑗ࿟ጙࠨቖ᏷ࡀ໭ઁखညਭࢬ࢟৺ᑇă
ᑚዹᓍ૦௓ᇄኊଖኚࣗྜྷၫ௣ǈऎభጲᒮቤఎဪሶ᏷ࡀ
໭ቖྜྷၫ௣ăಢ႒࢐ǈྙਫBB‫ܪ‬ᒔᆡᒙᆡǈᄴဟQG‫ܪ‬ᒔ
ᆡ༹ഃǈᐌႁී໭ୈᆚถཱྀ߲ቖෘഎă
ET3542
2135ᆡ2.Xjsf! FFQSPN
FROM ROM FUNCTIONS
FLOWCHART (FIGURE 9)
BUS MASTER Tx MEMORY
FUNCTION COMMAND
0Fh
WRITE SCRATCHPAD?
AAh
READ SCRATCHPAD?
N
Y
Y
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
BUS MASTER Rx
TA1 (T[7:0]), TA2 (T[15:8]),
AND E/S BYTE
DS2431
SETS PF = 1
CLEARS AA = 0
SETS E[2:0] = T[2:0]
DS2431 SETS
SCRATCHPAD
BYTE COUNTER = T[2:0]
MASTER Tx DATA BYTE
TO SCRATCHPAD
DS2431
INCREMENTS
E[2:0]
MASTER Tx RESET?
APPLIES ONLY
IF THE MEMORY
AREA IS NOT
PROTECTED.
Y
N
N
Y
BUS MASTER Rx
DATA BYTE FROM
SCRATCHPAD
DS2431
INCREMENTS
BYTE COUNTER
IF WRITE PROTECTED,
THE DS2431 COPIES
THE DATE BYTE FROM
THE TARGET ADDRESS
INTO THE SCRATCHPAD.
IF IN EPROM MODE,
THE DS2431 LOADS
THE BITWISE LOGICAL
AND OF THE TRANSMITTED
BYTE AND THE DATA
BYTE FROM THE TARGETED
ADDRESS INTO THE
SCRATCHPAD.
E[2:0] = 7?
T[2:0] = 0?
TO FIGURE 7b
N
MASTER Tx RESET?
Y
N
N
BYTE COUNTER
= E[2:0]?
Y
N
BUS MASTER Rx CRC-16
OF COMMAND, ADDRESS,
E/S BYTE, AND DATA BYTES
AS SENT BY THE DS2431
Y
PF = 0
BUS MASTER
Rx "1"s
DS2431 Tx CRC-16 OF
COMMAND, ADDRESS,
AND DATA BYTES AS THEY
WERE SENT BY THE BUS
MASTER
BUS MASTER
Rx "1"s
N
N
MASTER Tx RESET?
Y
MASTER Tx RESET?
Y
FROM FIGURE 7b
TO ROM FUNCTIONS
FLOWCHART (FIGURE 9)
ᅄ8b/! ࡀ߼໭৖ถഗ߈ᅄ
10
______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
55h
COPY SCRATCHPAD?
Y
Y
T[15:0] < 0090h?
N
Y
APPLICABLE TO ALL R/W
MEMORY LOCATIONS.
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
AND E/S BYTE
AUTH. CODE
MATCH?
F0h
READ MEMORY?
N
ET3542
FROM FIGURE 7a
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
ADDRESS < 90h?
Y
Y
N
N
DS2431 SETS MEMORY
ADDRESS = (T[15:0])
N
N
PF = 0?
Y
BUS MASTER Rx
DATA BYTE FROM
MEMORY ADDRESS
DS2431
INCREMENTS
ADDRESS
COUNTER
Y
COPY PROTECTED?
MASTER Tx RESET?
Y
BUS MASTER
Rx "1"s
N
N
AA = 1
N
Y
DURATION: tPROG
BUS MASTER
Rx "1"s
DS2431 COPIES
SCRATCHPAD
DATA TO ADDRESS
MASTER Tx RESET?
ADDRESS < 8Fh?
*
Y
N
DS2431 Tx "0"
BUS MASTER
Rx "1"s
N
MASTER Tx RESET?
Y
MASTER Tx RESET?
Y
N
Y
MASTER Tx RESET?
N
DS2431 Tx "1"
MASTER Tx RESET?
N
Y
TO FIGURE 7a
* 1-Wire IDLE HIGH FOR POWER.
ᅄ8c/! ࡀ߼໭৖ถഗ߈ᅄ)ኚ*
______________________________________________________________________________________
11
ET3542
2135ᆡ2.Xjsf! FFQSPN
Sfbe! Tdsbudiqbe! \BBi^
````````````````````````` 2.Xjsfᔐሣᇹᄻ
Sfbe! Tdsbudiqbeෘഎభጲ፿౶ቅዩ෹‫࢐ܪ‬ᒍਜ਼᏷ࡀ໭ၫ௣
ࡼᅲᑳቶăᓍ૦ख႙ෘഎࡔ൩ઁఎဪࣗནၫ௣ăఎᄿࡼ
ೝৈᔊஂဵ෹‫࢐ܪ‬ᒍǈሆጙৈᔊஂဵஉၦມጤ೟0ၫ௣ᓨ
ზᔊஂ)F0T*ǈ୻ᓹဵ᏷ࡀ໭ၫ௣ǈᑚቋၫ௣భถᎧᓍ૦
ख႙ࡼᏇဪၫ௣ᎌჅ‫ݙ‬ᄴăࡩ෹‫࢐ܪ‬ᒍᆡ᎖଎ࡀ໭጑૞
ᆡ᎖ቖۣઐ૞FQSPNෝါဟǈᑚጙ࢛ᎄ໚ᒮገăሮᇼቧ
ᇦ୅ Xsjuf Tdsbudiqbe \1Gi^ ‫ݝ‬ॊăᓍ૦።ሌࣗᅲ᏷ࡀ໭ᒦ
Ⴥᎌၫ௣)F\3;1^ . U\3;1^ , 2ৈᔊஂ*ǈ཭ઁ௓భጲ၃ࡵन
൩ࡼDSDǈকDSD൩ো௣ET3542ख႙ࡼၫ௣‫ޘ‬ညăྙਫ
ᓍ૦Ᏼ၃ࡵDSD൩ઁଖኚࣗནၫ௣ǈࡻࡵࡼჅᎌၫ௣௿
ᆐ൝૷2ă
2.Xjsfᔐሣဵጙৈ௥ᎌጙგ࡝ᔐሣࡼᓍ૦ਜ਼ጙგ૞ࣶგ࠭
૦࿸۸ࡼᇹᄻăᏴჅᎌࡼ༽ౚሆǈET3542࣒ᒑถᔫᆐ࠭
૦࿸۸౶ဧ፿ăᔐሣᓍ૦ဵጙৈ࢜ቯࡼᆈ఼ᒜ໭ăਈ᎖
কᔐሣᇹᄻࡼᄀ൙ॊᆐྯৈ‫ݝ‬ॊǖ፮ୈ๼ᒙĂࠅၒഗ߈
ਜ਼2.Xjsfቧഎ)ቧ੓ಢቯਜ਼ဟኔ*ă2.Xjsf቏ፇਖࢾᔐሣࡼ
၃ख‫ږ‬ᑍᄂၐဟᇺሆࡼᔐሣᓨზ஠ቲǈᎅᔐሣᓍ૦ख߲
ࡼᄴ‫ݛ‬൴ߡሆଢ଼ዘ߱ဪછă
Dpqz! Tdsbudiqbe! \66i^
Dpqz! Tdsbudiqbeෘഎ፿౶୓᏷ࡀ໭ᒦࡼၫ௣আᒜࡵభቖ
ࡼࡀ߼໭ཌᎮǈख߲Dpqz! Tdsbudiqbeෘഎઁǈᓍ૦‫ܘ‬ኍ
ᄋ৙ጙৈ4ᔊஂࡼ၈ཚෝ‫ۇ‬ǈকෝ‫ۇ‬።কᄰਭ༄ጙৈSfbe
Tdsbudiqbeෘഎ૝ࡻăক4ᔊஂෝ‫ۇ‬ၫ௣‫ܘ‬ኍᎧྯৈ࢐ᒍ଎
ࡀ໭)ጞࠨᆐUB2ĂUB3ĂF0T*ᒦࡼၫ௣ᅲཝປ๼ăྙਫෝ
‫ۇ‬ປ๼Ă෹‫࢐ܪ‬ᒍᎌ቉ĂQG‫ܪ‬ᒔᆡᆚ‫ۻ‬ᒙᆡ݀༦෹‫ࡀܪ‬
߼໭඗ᎌআᒜۣઐǈᐌBB‫ܪ‬ᒔᆡᒙᆡǈఎဪᒊቲআᒜ‫ݷ‬
ᔫă᏷ࡀ໭ᒦࡼ9ᔊஂၫ௣ཝ‫ۻݝ‬আᒜࡵ෹‫߼ࡀܪ‬໭ă໭
ୈด‫ݝ‬ၫ௣ࠅၒࡼဟମᆐuQSPHǈᏴࠥ໐ମ2.Xjsfᔐሣ࿟
ࡼ࢟ኹ‫ܘ‬ኍۣᑺ‫ࢅݙ‬᎖3/9Wăၫ௣আᒜᅲ߅ઁ્ख႙ጙᔝ
Đ1đਜ਼Đ2đୣᄐࡼቧ੓ǈᒇࡵᓍ૦ख႙আᆡ൴ߡᆐᒏăྙ
ਫQG‫ܪ‬ᒔᆡ‫ۻ‬ᒙᆡ૞෹‫߼ࡀܪ‬໭ࠀ᎖আᒜۣઐෝါǈᐌ
‫્ݙ‬ᒊቲআᒜ‫ݷ‬ᔫऎ༦BB‫ܪ‬ᒔᆡ‫્ݙ‬ᒙᆡă
Sfbe! Nfnpsz! \G1i^
Sfbe! Nfnpszෘഎᄰ‫ޟ‬፿᎖࠭ET3542ࣗནၫ௣ăख߲ෘഎ
ઁǈᓍ૦ኊገᄋ৙3ৈᔊஂࡼ෹‫࢐ܪ‬ᒍăᏴᑚ3ৈᔊஂᒄ
ઁǈᓍ૦ఎဪࣗན໦ဪ᎖෹‫࢐ܪ‬ᒍࡼၫ௣ǈభೌኚࣗᒗ
࢐ᒍ119Giࠀăྙਫᓍ૦Ᏻଖኚ஠ቲࣗ‫ݷ‬ᔫǈᐌࣗནஉਫ
୓ဵ൝૷2ă໭ୈด‫ࡼݝ‬UB2ĂUB3ĂF0Tጲૺ᏷ࡀ໭ดྏ
‫ݙ‬၊Sfbe Nfnpszෘഎ፬ሰă
``````````````````````````````` ፮ୈ๼ᒙ
2.Xjsfᔐሣᒑࢾፃ೫ጙোၫ௣ሣǈፐࠥᔐሣ࿟ࡼඛৈ࿸۸
ถ৫Ᏼးࡩဟరདࣅᔐሣဵऻ‫ޟ‬ᒮገࡼăᆐ೫ဣሚࠥ෹
ࡼǈਂ୻Ᏼ2.Xjsfᔐሣ࿟ࡼჅᎌ࿸۸࣒‫ܘ‬ኍ‫ݧ‬፿ധ૵ఎവ
૞ྯზၒ߲ăET3542ࡼ2.Xjsf࣡ాᆐധ૵ఎവǈด‫ࢀݝ‬቉
࢟വ୅ᅄ9ă
ࣶ࢛ᔐሣᎅೌ୻೫ࣶৈ࠭૦࿸۸ࡼ2.Xjsfᔐሣᔝ߅ăET3542
ॊܰᑽߒ26/5lcqt )ᔢࡍᒋ*ࡼ‫ܪ‬ᓰᄰቧႥൈਜ਼236lcqt )ᔢ
ࡍᒋ*ࡼ঱ႥᄰቧႥൈăᓖፀࠅᄻࡼ2.Xjsf‫ޘ‬ອॊܰᑽߒ
27/4lcqt ࡼ‫ܪ‬ᓰᄰቧႥൈਜ਼ 253lcqt ࡼ঱ႥᄰቧႥൈă
ET3542Ⴅൈ൒ᎌଢ଼ࢅǈᏇፐဵᆐᐐ༓2.Xjsfᇕಯ୻ా࣪ᐅ
ဉࡼጴᒜऎᐐଝ೫ૂআဟମă࿟౯࢟ᔜࡼᔜᒋᓍገᎅᆀ
൥ࡼࡍቃਜ਼ঌᏲᄟୈ௼ࢾăET3542ᏴྀੜႥࣞሆᏥቲ࣒
ኊገጙৈ3/3lΩ )ᔢࡍᒋ*ࡼ࿟౯࢟ᔜă
2.Xjsfᔐሣࡼహሔᓨზᆐ঱࢟ຳăྙਫᎅ᎖෭ᒬᏇፐኊ᏷
ᄫᄰቧǈྦથኊገૂআᄰቧࡼજǈᔐሣ‫ܘ‬ኍۣߒᏴహሔ
ᓨზăྙਫᆚ࿸ᒙᆐహሔᓨზǈ݀༦ᔐሣࠀ᎖ࢅ࢟ຳࡼ
ဟମިਭ27μt )঱Ⴅෝါ*૞ᑗ231μt )‫ܪ‬ᓰෝါ*ǈᔐሣ࿟
ࡼጙৈ૞ࣶৈ໭ୈ୓‫ۻ‬আᆡă
``````````````````````````````` ࠀಯഗ߈
ᄰਭ2.Xjsf࣡ాषᆰET3542ࡼ቏ፇྙሆǖ
• ߱ဪછ
• SPN৖ถෘഎ
• ࡀ߼໭৖ถෘഎ
• ࠅၒ0ၫ௣
12
______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
ET3542
VPUP
BUS MASTER
DS2431 1-Wire PORT
RPUP
DATA
Rx
Tx
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
PORT PIN
Rx
IL
Tx
100Ω MOSFET
ᅄ9/! ፮ୈ๼ᒙ
````````````````````````````````` ߱ဪછ
Tfbsdi! SPN! \G1i^
Ⴥᎌ2.Xjsfᔐሣ࿟ࡼၫ௣ࠅၒ࣒ጲ߱ဪછਭ߈ఎဪă߱ဪ
છਭ߈۞౪ᔐሣᓍ૦ख႙ጙৈআᆡ൴ߡǈ৉࠭૦Ⴒઁख
႙።ࡊ൴ߡă።ࡊ൴ߡཱུᓍ૦ࡻᒀET3542Ᏼሣ݀༦ᓰ۸
௓ኙăৎࣶቧᇦ༿‫ݬ‬୅ 2.Xjsfቧഎ‫ݝ‬ॊă
ᇹᄻধ໪ࣅဟǈᔐሣᓍ૦భถ݀‫ݙ‬ᒀࡸ2.Xjsfᔐሣ࿟ਂ୻
ࡼ໭ୈၫ೟ૺ჈ඣࡼᓖ‫ݿ‬൩ăᓍ૦భಽ፿ᔐሣࡼሣᎧᄂ
ቶǈ‫ݧ‬፿๝߹ज౶ဤܰᔐሣ࿟Ⴥᎌ࠭૦ࡼᓖ‫ݿ‬൩ăᑣ࣪
ᔢࢅᎌ቉ᆡᏴ༄ࡼᓖ‫ݿ‬൩ࡼඛጙᆡǈᔐሣᓍ૦࣒ख႙ྯ
ৈဟᇺăᏴ࢒ጙৈဟᇺǈඛৈ‫ݬ‬ᎧႝჃࡼ࠭૦࣒ၒ߲৉
ᔈᓖ‫ݿ‬൩ᆡࡼᏇ൩ăᏴ࢒औৈဟᇺǈඛৈ‫ݬ‬ᎧႝჃࡼ࠭
૦࣒ၒ߲৉ᔈᓖ‫ݿ‬൩ᆡࡼ‫ݗ‬൩ᒋăᏴ࢒ྯৈဟᇺǈᓍ૦
ቖྜྷჅኡᆡࡼᏇ൩ăჅᎌᎧᎅᓍ૦ቖྜྷࡼকᆡ‫ݙ‬ປ๼ࡼ
࠭૦࣒‫ݙ‬Ᏻ‫ݬ‬ଝႝჃăྙਫᓍ૦ೝࠨࣗࡵࡼᒋ௿ဵ1ǈᐌ
ႁී࠭૦কᆡࡼೝৈᓨზ࣒ࡀᏴăᔐሣᓍ૦ᄰਭቖྜྷࡼ
ᓨზᒋ౶ኡᐋႝჃSPN൩ၥࡼ‫ݙ‬ᄴॊᑽăளਭጙࠨᅲᑳ
ႝჃਭ߈ǈᔐሣᓍ૦૾భᒀࡸ෭ৈ࠭૦ࡼᓖ‫ݿ‬൩ă഍ᅪ
ࡼႝჃਭ߈భጲဤܰ໚᎜࠭૦ࡼᓖ‫ݿ‬൩ăሮᇼᄀ൙༿‫ݬ‬
ఠ።፿‫܊‬଑298ǖ2.XjsfႝჃႯजǈ໚ᒦ۞౪ጙৈာಿă
```````````````````` 2.Xjsf! SPN৖ถෘഎ
ጙࡡᔐሣᓍ૦ଶ‫ࡵހ‬ጙৈ።ࡊ൴ߡǈ‫ܣ‬భख႙ET3542ᑽ
ߒࡼ໕ৈSPN৖ถෘഎᒦࡼྀጙৈăჅᎌࡼSPN৖ถෘ
എ‫ࣞޠ‬௿ᆐ9ᆡăሆෂ೰߲೫Ⴥᎌࡼᑚቋෘഎ)‫ݬ‬ఠᅄ:ᒦ
ࡼഗ߈ᅄ*ă
Sfbe! SPN! \44i^
Sfbe! SPNෘഎᏤ኏ᔐሣᓍ૦ࣗནET3542ࡼ9ᆡଜᔙ൩Ă
ᆎጙࡼ59ᆡኔ೰੓ਜ਼9ᆡDSDቅዩ൩ăࠥෘഎး፿᎖ᔐሣ
࿟ஞᎌጙৈ࠭૦ࡼ༽ౚăྙਫᔐሣ࿟ೌ୻೫ࣶৈ࠭૦࿸
۸ǈࡩჅᎌ࠭૦၂ᅄᄴဟख႙ၫ௣ဟǈ୓્खညၫ௣ߡ
ᅃ)ധ૵ఎവၒ߲‫ޘ‬ညጙৈሣᎧࡼஉਫ*ăࡴᒘᓍ૦၃ࡵࡼ
ଜᔙ൩ਜ਼59ᆡኔ೰੓ᎧDSDቅዩ൩‫ݙ‬ປ๼ă
Nbudi! SPN! \66i^
Nbudi! SPNෘഎઁෂৌႲጙৈ75ᆡSPNᓖ‫ݿ‬൩ǈᏤ኏ᔐ
ሣᓍ૦ኰᒍࣶ࢛ᔐሣ࿟ࡼጙৈᄂࢾET3542ăᒑᎌᎧক75
ᆡSPNᓖ‫ݿ‬൩ᅲཝປ๼ࡼET3542‫ઁ્࣪ݣ‬ෂࡼࡀ߼໭৖
ถෘഎ஠ቲሰ።ă໚჈Ⴥᎌ࠭૦௿ࢀࡗሆጙৈআᆡ൴ߡă
ᑚᄟෘഎ଒း፿᎖࡝࠭૦ᇹᄻǈጐး፿᎖ࣶ࠭૦ᇹᄻă
Tljq! SPN! \DDi^
Ᏼ࡝࠭૦ᔐሣᇹᄻᒦǈᔐሣᓍ૦భဧ፿ࠥෘഎषᆰࡀ߼
໭ऎ‫ݙ‬ኊገᄋ৙75ᆡSPN൩ǈ࠭ऎஂဏ೫ဟମăྙਫᔐ
ሣ࿟‫ݙ‬ᒏጙৈ࠭૦ǈᏴTljq! SPNෘഎઁख႙ࣗෘഎဟǈ
્ፐࣶৈ࠭૦ᄴဟख႙ၫ௣ऎࡴᒘၫ௣ߡᅃ)ധ૵ఎവၒ
߲ሆ౯୓‫ޘ‬ညጙৈሣᎧஉਫ*ă
______________________________________________________________________________________
13
ET3542
2135ᆡ2.Xjsf! FFQSPN
BUS MASTER Tx
RESET PULSE
FROM FIGURE 9b
FROM MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)
OD
RESET PULSE?
N
OD = 0
Y
BUS MASTER Tx ROM
FUNCTION COMMAND
33h
READ ROM
COMMAND?
DS2431 Tx
PRESENCE PULSE
N
55h
MATCH ROM
COMMAND?
F0h
SEARCH ROM
COMMAND?
N
N
CCh
SKIP ROM
COMMAND?
Y
Y
Y
Y
RC = 0
RC = 0
RC = 0
RC = 0
DS2431 Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
TO FIGURE 9b
DS2431 Tx BIT 0
DS2431 Tx BIT 0
MASTER Tx BIT 0
BIT 0 MATCH?
N
N
BIT 0 MATCH?
Y
Y
DS2431 Tx
SERIAL NUMBER
(6 BYTES)
N
DS2431 Tx BIT 1
MASTER Tx BIT 1
DS2431 Tx BIT 1
MASTER Tx BIT 1
BIT 1 MATCH?
N
N
BIT 1 MATCH?
Y
Y
DS2431 Tx BIT 63
DS2431 Tx
CRC BYTE
MASTER Tx BIT 63
DS2431 Tx BIT 63
MASTER Tx BIT 63
BIT 63 MATCH?
N
N
BIT 63 MATCH?
Y
Y
RC = 1
RC = 1
TO FIGURE 9b
FROM FIGURE 9b
TO MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)
ᅄ:b/! SPN৖ถഗ߈ᅄ
14
______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
ET3542
TO FIGURE 9a
FROM FIGURE 9a
A5h
RESUME
COMMAND?
3Ch
OVERDRIVESKIP ROM?
N
N
Y
Y
N
Y
RC = 0; OD = 1
RC = 1?
69h
OVERDRIVEMATCH ROM?
RC = 0; OD = 1
N
Y
MASTER Tx BIT 0
MASTER Tx
RESET?
N
Y
BIT 0 MATCH?
N
OD = 0
Y
MASTER Tx BIT 1
MASTER Tx
RESET?
N
Y
BIT 1 MATCH?
N
OD = 0
Y
MASTER Tx BIT 63
BIT 63 MATCH?
N
OD = 0
Y
FROM FIGURE 9a
RC = 1
TO FIGURE 9a
ᅄ:c/! SPN৖ถഗ߈ᅄ)ኚ*
______________________________________________________________________________________
15
ET3542
2135ᆡ2.Xjsf! FFQSPN
Sftvnf! \B6i^
ᆐ೫ᔢࡍ߈ࣞᄋ঱ࣶ࢛ણஹᒦࡼၫ௣ᅔᅊൈǈᇹᄻᄋ৙೫
Sftvnf৖ถăࠥ৖ถଶ‫އ‬SDᆡࡼᓨზǈྙਫᒙᆡǈᐌᒇ
୻‫఼ڳ‬ᒜཚୣ৊ࡀ߼໭৖ถǈᎧTljq! SPNෘഎಢ႒ăSD
ࡼᒙᆡᒑถᄰਭ߅৖࢐ᒊቲNbudi! SPNĂTfbsdi! SPN૞
Pwfsesjwf.Nbudi! SPNෘഎ౶ဣሚăጙࡡSDᒙᆡǈ૾భಽ
፿Sftvnfෘഎᒮআषᆰࠥ໭ୈăषᆰᔐሣ࿟ࡼ໚჈໭ୈ
્༹߹SDᆡǈጲऴᒏೝৈ૞ৎࣶࡼ࠭૦ᄴဟሰ።Sftvnf
ෘഎă
Pwfsesjwf.Tljq! SPN! \4Di^
Ᏼጙৈ࡝࠭૦ᔐሣ࿟ဧ፿কෘഎဟǈᓍ૦‫ݙ‬ኊገᄋ৙75
ᆡࡼSPN࢐ᒍ൩௓భጲषᆰࡀ߼໭৖ถǈ࠭ऎஂဏ೫ဟ
ମăᎧᄰ‫ࡼޟ‬Tljq SPNෘഎ‫ݙ‬ᄴǈPwfsesjwf.Tljq SPNෘ
എ୓ET3542࿸ᒙᆐ঱Ⴅෝါ)PE > 2*ăকෘഎઁࡼჅᎌᄰ
ቧ௿ᆐ঱Ⴅෝါǈᒇࡵᎌጙৈᔢ࣢ߒኚ591μtဟମࡼআᆡ
൴ߡ୓ᔐሣ࿟ࡼჅᎌ໭ୈআᆡ߅‫ܪ‬ᓰႥൈ)PE! >! 1*ă
ྙਫᏴጙৈࣶ࢛ᔐሣ࿟ख႙কෘഎǈᐌᔐሣ࿟Ⴥᎌᑽߒ
঱Ⴅෝါࡼ໭ୈ࣒‫ۻ‬࿸ᒙ߅঱ႥෝါăႲઁǈᆐ೫ኰᒍ
ᄂࢾࡼ঱Ⴅෝါ໭ୈǈ‫ܘ‬ኍख߲ጙৈ঱Ⴅෝါࡼআᆡ൴
ߡǈ୻ᓹᏥ፿Nbudi SPN૞Tfbsdi SPNෘഎăᑚዹถ৫
ଝႥႝჃਭ߈ăྙਫᔐሣ࿟ᎌࣶৈᑽߒ঱Ⴅෝါࡼ࠭૦ǈ
ऎ༦Pwfsesjwf.Tljq SPNෘഎઁৌᓹጙᄟࣗෘഎǈ્ፐࣶ
ৈ࠭૦ᄴဟख႙ၫ௣ऎ‫ޘ‬ညၫ௣ߡᅃ)ധ૵ఎവၒ߲ሆ౯
୓‫ޘ‬ညጙৈሣᎧஉਫ*ă
Pwfsesjwf.Nbudi! SPN! \7:i^
ᄰਭPwfsesjwf.Nbudi SPNෘഎǈઁ୻ጲ঱Ⴅෝါख႙ࡼ
75ᆡSPN࢐ᒍ൩ǈถ৫ဧᔐሣᓍ૦Ᏼࣶ࢛ᔐሣ࿟षᆰጙ
ৈᄂࢾࡼET3542ǈᄴဟ୓໚࿸ᒙ߅঱ႥෝါăᒑᎌᎧক
75ᆡSPN࢐ᒍ൩ᑵཀྵປ๼ࡼET3542‫ઁ્࣪ݣ‬ኚࡼࡀ߼໭
৖ถෘഎᔪ߲न።ăጯள‫ۻ‬༄ෂࡼPwfsesjwf.Tljq! SPN૞
Pwfsesjwf.Nbudi! SPNෘഎ߅৖࿸ᒙ߅঱Ⴅෝါࡼ࠭૦୓ଖ
ኚۣߒ঱ႥෝါăჅᎌᑽߒ঱Ⴅෝါࡼ࠭૦Ᏼሆጙৈߒኚ
ဟମᔢቃᆐ591μtࡼআᆡ൴ߡઁૄࡵ‫ܪ‬ᓰႥൈăPwfsesjwf.
Nbudi! SPNෘഎး፿᎖ᔐሣ࿟ᎌ࡝ৈ૞ࣶৈ໭ୈࡼ༽ౚă
16
````````````````````````````` 2.Xjsfቧഎ
ET3542ኊገዏৃࡼ቏ፇ౶ۣᑺၫ௣ᅲᑳቶăক቏ፇᏴጙ
োሣ࿟ࢾፃ೫႐ᒬಢቯࡼቧ੓ǖ۞౪আᆡ൴ߡਜ਼።ࡊ൴
ߡࡼআᆡኔ೰Ăቖ1Ăቖ2ਜ਼ࣗၫ௣ă߹።ࡊ൴ߡᅪǈᔐ
ሣᓍ૦ख߲໚჈Ⴥᎌቧ੓ࡼሆଢ଼ዘăET3542ถጲ‫ܪ‬ᓰႥ
ࣞ૞঱Ⴅೝᒬෝါᄰቧăྙਫ඗ᎌීཀྵ࿸ᒙᆐ঱Ⴅෝါǈ
ET3542௓ጲ‫ܪ‬ᓰႥࣞᄰቧăᏴ঱ႥෝါሆǈჅᎌ݆ተ௿
‫ݧ‬፿౐Ⴅࢾဟă
࠭హሔᓨზ઩ታဟǈ2.Xjsfᔐሣ࢟ኹኊገ࠭WQVQ ଢ଼ࡵWUM
ඡሢ࢟ኹጲሆă࠭৔ᔫᓨზऩૄహሔᓨზဟǈ࢟ኹኊገ
࠭W JMNBY ࿟ဍᒗW UI ඡሢ࢟ኹጲ࿟ă࢟ኹ࿟ဍဟମᏴᅄ
21ᒦ፿ε‫ܭ‬ာǈߒኚဟମན௼᎖Ⴥဧ፿ࡼ࿟౯࢟ᔜ)S QVQ*
ਜ਼2.Xjsfᆀ൥ࡼএଝ࢟ྏăET3542ো௣WJMNBY ࢟ኹ๨ࣥ
൝૷࢟ຳǈ‫߿્ݙ‬खྀੜူୈă
ᅄ21Ⴥာဵఎ໪ጙࠨᎧET3542ᄰቧჅኊࡼ߱ဪછਭ߈ă
আᆡ൴ߡઁࡼ።ࡊ൴ߡ‫ීܭ‬ET3542ጯளᓰ۸௓ኙǈᒑገ
၃ࡵᑵཀྵࡼSPNਜ਼ࡀ߼໭৖ถෘഎǈ૾భ୻၃ၫ௣ăྙ
ਫᔐሣᓍ૦Ᏼሆଢ଼ዘ‫ݧ‬፿‫ڼ‬ൈ఼ᒜǈ‫ܘ‬ኍ୓ሣ࿟ࡼ࢟ຳ
౯ࢅۣ݀ߒu STUM , u G ࡼဟମǈጲ‫ܟޡݗ‬ዘă঱Ⴅෝါሆ
ྦuSTUM ߒኚ591μt૞ৎ‫ޠ‬ဟǈభ୓࠭૦ૂআࡵ‫ܪ‬ᓰႥࣞă
ྙਫET3542ࠀ᎖঱Ⴅෝါ݀༦uSTUM ‫ࡍݙ‬᎖91μtǈᐌ໚྆
ۣߒ঱Ⴅෝါăྙਫ໭ୈࠀ᎖঱ႥෝါǈuSTUM ஑᎖ 91μt
ਜ਼591μtᒄମǈ໭ୈ୓আᆡǈᄰቧႥൈ‫ݙ‬ཀྵࢾă
ᔐሣᓍ૦ျहᔐሣઁ஠ྜྷ୻၃ෝါăࠥဟ2.Xjsfᔐሣ࢟ຳ
‫ۻ‬࿟౯࢟ᔜ૞ET3593.y11૞ET3591Cདࣅ໭ࢀᎌᏎ࢟വ࿟
౯ᒗWQVQăࡩ࢟ຳ঱᎖ඡሢWUI ဟǈET3542ࢀࡗuQEI ဟମǈ
཭ઁᄰਭ୓ᔐሣ࢟ຳ౯ࢅۣ݀ߒuQEM ဟମǈ౶ख႙ጙৈ።
ࡊ൴ߡăᆐ೫ଶ‫ހ‬።ࡊ൴ߡǈᓍ૦‫ܘ‬ኍᏴu NTQ ဟମଶ‫ހ‬
2.Xjsfᔐሣࡼ൝૷ᓨზă
uSTUI ࠊాဟମ‫ܘ‬ኍᒗ࿩ࢀ᎖uQEINBYĂuQEMNBY ᎧuSFDNJO
ࡼᔐਜ਼ăጙࡡuSTUI உၦǈET3542૾భఎဪၫ௣ᄰቧăᏴ
ጙৈ૘ਜ਼࿸۸ᔝ߅ࡼᆀ൥ᒦǈᆐ೫ରྏ໚჈2.Xjsf࿸۸ǈ
uSTUI Ᏼ‫ܪ‬ᓰႥࣞሆᔢቃ።ᆐ591μtǈᏴ঱Ⴅෝါሆᔢቃ።
ᆐ59μtă
______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
ET3542
MASTER Tx "RESET PULSE"
MASTER Rx "PRESENCE PULSE"
ε
tMSP
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tPDH
tRSTL
tF
tPDL
tREC
tRSTH
RESISTOR
MASTER
DS2431
ᅄ21/! ߱ဪછਭ߈ǖআᆡਜ਼።ࡊ൴ߡ
ࣗ0ቖဟᇺ
ᎧET3542ࡼၫ௣ᄰቧᏴဟᇺด஠ቲǈඛৈဟᇺࠅၒጙᆡă
ၫ௣Ᏼቖဟᇺᎅᔐሣᓍ૦ࠅၒࡵ࠭૦ǈၫ௣Ᏼࣗဟᇺᎅ࠭
૦ࠅၒࡵᓍ૦ăᅄ22৊߲೫ቖဟᇺਜ਼ࣗဟᇺࡼࢾፃă
Ⴥᎌᄰቧ௿ጲᓍ૦౯ࢅၫ௣ሣఎဪǈࡩ2.Xjsfᔐሣ࿟ࡼ࢟
ኹଢ଼ᒗඡሢ࢟ኹWUM ጲሆဟǈET3542໪ࣅด‫ࢾݝ‬ဟखည໭ǈ
Ᏼቖဟᇺဟཀྵࢾੜဟ‫ݧ‬ዹၫ௣ሣǈᏴࣗဟᇺဟཀྵࢾၫ௣ᎌ
቉ࡼဟମă
ᓍ૦ࡵ࠭૦
࣪᎖ቖ2ဟᇺǈၫ௣ሣ࿟ࡼ࢟ኹ‫ܘ‬ኍᏴቖ2ࢅဟମuX2MNBY
உၦ༄঱ਭඡሢ࢟ኹWUIă࣪᎖ቖ1ဟᇺǈၫ௣ሣ࿟ࡼ࢟ኹ
Ᏼቖ1ࢅဟମuX1MNJO உၦ༄‫ܘ‬ኍۣߒࢅ᎖ඡሢ࢟ኹWUIă
ᆐ೫ဣሚᔢభణࡼᄰቧǈၫ௣ሣ࿟ࡼ࢟ኹᏴᑳৈu X1M ૞
u X2M ဟମࠊాด࣒‫ݙ‬።ިਭ W JMNBY ă࢟ኹިਭ W UI ઁǈ
ET3542Ᏼ஠ቲሆጙৈဟᇺ༄ኊገጙৈૂআဟମuSFDă
࠭૦ࡵᓍ૦
ࣗၫ௣ဟᇺᏴఎဪဟᎧቖ2ဟᇺಢ႒ăၫ௣ሣ࿟ࡼ࢟ኹᏴ
ࣗࢅဟମuSM உၦ༄‫ܘ‬ኍۣߒࢅ᎖WUMăᏴuSM ࠊాǈ።ࡊ1
ဟǈET3542ఎဪ౯ࢅၫ௣ሣǈ໚ด‫ࢾݝ‬ဟखည໭௼ࢾੜ
ဟஉၦሆ౯ǈ݀༦࢟ຳᒮቤఎဪဍ঱ă።ࡊ2ဟǈET3542
݀‫ߒۣݙ‬ၫ௣ሣࡼࢅ࢟ຳǈuSM ጙஉၦǈ࢟ຳ૾ఎဪ࿟ဍă
ᓍ૦‫ݧ‬ዹࠊా)uNTSNJO ࡵuNTSNBY*ᎅuSM , δ )࿟ဍဟମ*ਜ਼
ET3542ด‫ࢾݝ‬ဟखည໭௼ࢾǈᓍ૦‫ܘ‬ኍᏴ‫ݧ‬ዹࠊాดᒊ
ቲၫ௣ሣࣗ‫ݷ‬ᔫăᆐဣሚᔢభణࡼᄰቧǈu SM ᏴᏤ኏पᆍ
ด።஧೟࣢ǈᓍ૦።কᏴ୻தࡣ‫ݙ‬ᅵ᎖uNTSNBY ࡼဟମࣗ
ནၫ௣ă࠭ၫ௣ሣࣗནၫ௣ઁǈᓍ૦‫ܘ‬ኍࢀࡗᒇᒗuTMPU
உၦăᑚཀྵۣ೫ET3542Ᏼሆጙৈဟᇺᓰ۸௓ኙ༄ᎌᔗ৫
ࡼૂআဟମuSFDăኊᓖፀࡼဵǈᑚಱᒎࢾࡼuSFD ஞး፿᎖
2.Xjsfᔐሣ࿟ᒑ୻ጙৈET3542ࡼ༽ౚă࣪᎖ࣶ࢛๼ᒙǈᆐ
೫း።໚჈2.Xjsf໭ୈࡼၒྜྷ࢟ྏǈ።ዓ‫ޠ‬u SFDă഍ᅪǈ
થభဧ፿ET3593.y11૞ET3591Cࢀ2.Xjsfᔐሣདࣅ໭୻ా
໭ୈǈᏴ2.Xjsfૂআဟମด஠ቲᎌᏎ࿟౯ă
______________________________________________________________________________________
17
ET3542
2135ᆡ2.Xjsf! FFQSPN
WRITE-ONE TIME SLOT
tW1L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tSLOT
RESISTOR
MASTER
WRITE-ZERO TIME SLOT
tW0L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tREC
tSLOT
RESISTOR
MASTER
READ-DATA TIME SLOT
tMSR
tRL
VPUP
VIHMASTER
VTH
MASTER
SAMPLING
WINDOW
VTL
VILMAX
0V
δ
tF
tREC
tSLOT
RESISTOR
MASTER
DS2431
ᅄ22/! ࣗ0ቖဟኔᅄ
18
______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
Ᏼ2.Xjsfણஹᒦǈሣവ࣡୻ᒑᎌᏴᔐሣᓍ૦)2.Xjsfདࣅ໭*
఼ᒜࡼ࣢ဟମด‫ݣ‬ᎌభถăፐࠥǈ2.Xjsfᆀ൥૵ጵ၊ࡵ৉
ᒬ౶Ꮞࡼᐅဉছཷăᎅ᎖ᆀ൥ࡼᇕಯߛࡁਜ਼ᅠແஉ৩‫ݙ‬
ᄴǈ࢛࠭࣡૞ᑽവஂ࢛न࿴ࡼቧ੓భถᏴ෭ᒬ߈ࣞ࿟ሤ
ઑଝ༓૞ࢎሿăᑚቋन࿴ቧ੓Ᏼ2.Xjsfᄰቧሣവ࿟‫ܭ‬ሚᆐ
ඇࠦ૞ᑩഅă࠭ᅪ‫ݝ‬Ắ੝ࡵ2.Xjsfሣവ࿟ࡼᐅဉጐถࡴᒘ
ቧ੓ඇࠦࡼ‫ޘ‬ညăᏴጙৈဟᇺ࿟ဍዘ‫ޘ‬ညࡼඇ્ࠦࡴᒘ
࠭૦Ꭷᓍ૦ပབྷᄴ‫ݛ‬ǈଖऎࡴᒘ࣪Tfbsdi! SPNෘഎပབྷ
न።ǈ૞ࡴᒘ࠭૦ᄂࢾ৖ถෘഎࡼᒦᒏăᆐ೫ဣሚৎੑ
ࡼᆀ൥ቶถǈET3542ဧ፿೫ጙᒬቤࡼ2.Xjsf༄࣡ǈଢ଼ࢅ೫
໚࣪ᐅဉࡼැঢࣞă
ET3542ࡼ2.Xjsf༄࣡Ꭷࠅᄻࡼ࠭૦໭ୈሤ‫܈‬ᎌ4࢛ᄂቶ
‫ݙ‬ᄴă
2* Ᏼ࢟വᒦএଝ೫ጙৈࢅᄰ൉݆໭౶ଶ‫ހ‬ဟᇺఎဪဟࡼ
ሆଢ଼ዘăᑚଢ଼ࢅ೫࣪঱ຫᐅဉࡼැঢࣞă঱Ⴅෝါሆ
‫ݙ‬ဧ፿ࠥএଝ൉݆໭ă
3* Ᏼࢅࡵ঱ࡼఎਈඡሢW UI ࠀ࿸ᎌጙৈᒣૄǈྙਫᎌጙ
ৈঌඇࠦࢅ᎖WUI ࡣથ඗ᎌࢅ᎖WUI . WIZǈ୓‫ۻ્ݙ‬
ߌཱྀ)ᅄ23ࡼာಿB*ăᒣૄᏴྀੜ2.XjsfႥࣞෝါሆ௿
ᎌ቉ă
4* ᎅ࿟ဍዘۣߒਈ‫ܕ‬ဟମu SFI ࢾፃ೫ጙৈဟମࠊాǈᏴ
কဟମࠊాด૾ဧඇࠦࢅ᎖W UI . W IZ ጐ્‫ۻ‬઄൒)ᅄ
23ࡼာಿCǈuHM = u SFI*ăࡍࡼኹଢ଼૞ࠃਭWUI ඡሢઁ
tREH
ዓኚဟମި߲uSFI ࠊాࡼඇࠦᐌᇄज൉߹ǈ્‫ࡩۻ‬ᔫጙ
ৈቤဟᇺࡼఎဪ)ᅄ23ࡼာಿDǈuHM ≥ uSFI*ă
ᒑᎌᏴ࢟໮ᄂቶᒦᒎී‫ݬ‬ၫWIZ ਜ਼uSFI ࡼ໭ୈဧ፿೫খ஠
ࡼ2.Xjsf༄࣡ă
```````````````````````````````` ည߅DSD൩
ET3542ᎌೝᒬ‫ݙ‬ᄴಢቯࡼDSD൩ăጙᒬᆐ9ᆡǈࡀ߼Ᏼ75
ᆡSPNࡼᔢ঱ᎌ቉ᔊஂᒦăᔐሣᓍ૦ถো௣75ᆡSPN൩
ࡼ༄67ᆡଐႯ߲কDSD൩ǈ݀୓໚Ꭷࡀ߼ᏴET3542ᒦࡼ
ᒋ஠ቲ‫୷܈‬ǈ๨ࣥSPNၫ௣ဵ॥୻၃ᇄᇙăଐႯকDSDቅ
ዩ൩ࡼࢀ቉ࣶሲါᆐǖY 9 ,! Y 6 ,! Y 5 ,! 2ă୻၃ࡵࡼ9ᆡ
DSDᆐᏇ൩)‫ݙ‬ནन*ተါăকᒋᏴ৔‫ۻޣ‬ଐႯ݀਒రቖྜྷ
SPNᒦă
഍ጙᒬDSD൩ᆐ27ᆡǈ‫ݧ‬፿‫ܪ‬ᓰࡼDSD.27ࣶሲါ਽ၫY27
,! Y26 ,! Y3 ,! 2‫ޘ‬ညăকDSDቅዩ൩፿౶࣪ࣗቖ᏷ࡀ໭ဟ
ࠅၒࡼၫ௣஠ቲ౐ႥቅዩăᎧ9ᆡDSDቅዩ൩ሤ‫܈‬ǈ27ᆡ
DSDቅዩ൩ᔐဵጲन൩ࡼተါࠅၒăET3542በຢด‫ࡼݝ‬
DSDखည໭)ᅄ24*ଐႯጙৈቤࡼ27ᆡDSDቅዩ൩ǈྙෘഎ
ഗ߈ᅄ)ᅄ8*Ⴥာăᔐሣᓍ૦ᄰਭ‫࠭࠭୷܈‬૦ࣗནࡼDSD
ቅዩ൩ਜ਼ಽ፿୻၃ၫ௣ଐႯ߲ࡼDSDቅዩ൩ǈ௣ࠥ౶௼ࢾ
ဵ॥ଖኚ෭ጙ‫ݷ‬ᔫથဵᒮቤࣗནDSD൩ᎌᇙࡼၫ௣‫ݝ‬ॊă
ᏴXsjuf Tdsbudiqbeෘഎᒦǈገည߅DSDቅዩ൩ǈ၅ሌ༹హ
DSDखည໭ǈ཭ઁጤྜྷෘഎࡔ൩Ă෹‫࢐ܪ‬ᒍUB2ਜ਼UB3Ăጲ
ૺᔐሣᓍ૦ख႙ࡼჅᎌၫ௣ᔊஂăET3542ᒑᎌᏴF\3;1^! >
222cဟ‫ݣ‬ख႙DSDቅዩ൩ă
tREH
VPUP
VTH
VHY
CASE A
CASE B
CASE C
0V
tGL
tGL
ᅄ23/! ᐅဉጴᒜာፀᅄ
______________________________________________________________________________________
19
ET3542
```````````````````` খ࿖ᆀ൥ቶถ)༤ધ࢛ᒣૄ*
ET3542
2135ᆡ2.Xjsf! FFQSPN
POLYNOMIAL = X16 + X15 + X2 + 1
1ST
STAGE
3RD
STAGE
2ND
STAGE
X0
X2
X1
9TH
STAGE
X8
4TH
STAGE
10TH
STAGE
X9
11TH
STAGE
X10
X3
12TH
STAGE
X11
5TH
STAGE
6TH
STAGE
X4
13TH
STAGE
X12
X5
14TH
STAGE
X13
7TH
STAGE
X6
8TH
STAGE
X7
15TH
STAGE
X14
16TH
STAGE
X15
X16
CRC OUTPUT
INPUT DATA
ᅄ24/! DSD.27፮ୈႁීૺࣶሲါ
ᏴSfbe Tdsbudiqbeෘഎᒦǈገည߅DSDቅዩ൩ǈ၅ሌ༹హ
DSDखည໭ǈ཭ઁጤྜྷෘഎࡔ൩Ă෹‫࢐ܪ‬ᒍUB2ਜ਼UB3Ă
F0TᔊஂጲૺET3542ख႙ࡼ᏷ࡀ໭ၫ௣ăET3542ᒑᎌᏴೌ
ኚࣗན᏷ࡀ໭ၫ௣ᒇࡵஉᆘဟ‫ݣ‬ख႙DSDቅዩ൩ăᎌਈ
ည߅DSDቅዩ൩ࡼৎࣶቧᇦ༿‫ݬ‬ఠ።፿‫܊‬଑38ă
`````````````````````````````````````````````````````` ௥ᄏෘഎ2.Xjsfᄰቧ቏ፇ—९੓‫ܭ‬
SYMBOL
RST
PD
Select
WS
1-Wire reset pulse generated by master.
1-Wire presence pulse generated by slave.
Command and data to satisfy the ROM function protocol.
Command "Write Scratchpad."
RS
Command "Read Scratchpad."
CPS
Command "Copy Scratchpad."
RM
Command "Read Memory."
TA
TA-E/S
<8–T[2:0] bytes>
<Data to EOM>
Target address TA1, TA2.
Target address TA1, TA2 with E/S byte.
Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address.
Transfer of as many data bytes as are needed to reach the end of the memory.
CRC-16
Transfer of an inverted CRC-16.
FF Loop
Indefinite loop where the master reads FF bytes.
AA Loop
Indefinite loop where the master reads AA bytes.
Programming
20
DESCRIPTION
Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.
______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
Master to Slave
Slave to Master
Programming
````````````````````````````````````````````````````````````````````` 2.Xjsfᄰቧာಿ
Write Scratchpad (Cannot Fail)
RST PD Select WS TA <8–T[2:0] bytes> CRC-16 FF Loop
Read Scratchpad (Cannot Fail)
RST PD Select RS TA-E/S <8–T[2:0] bytes> CRC-16 FF Loop
Copy Scratchpad (Success)
RST PD Select CPS TA-E/S Programming AA Loop
Copy Scratchpad (Invalid Address or PF = 1 or Copy Protected)
RST PD Select CPS TA-E/S FF Loop
Read Memory (Success)
RST PD Select RM TA <Data to EOM> FF Loop
Read Memory (Invalid Address)
RST PD Select RM TA FF Loop
______________________________________________________________________________________
21
ET3542
`````````````````````````````````````````````````` ௥ᄏෘഎ2.Xjsfᄰቧ቏ፇ—‫ܠྻݨ‬൩
ET3542
2135ᆡ2.Xjsf! FFQSPN
````````````````````````` ࡀ߼໭৖ถာಿ
ቖྜྷࡀ߼໭࢒2጑ࡼ༄9ৈᔊஂăࣗᑳৈࡀ߼໭ă
MASTER MODE
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Rx
Tx
Rx
Tx
Tx
Rx
Rx
Rx
Rx
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Tx
—
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Rx
Tx
Rx
22
DATA (LSB FIRST)
(Reset)
(Presence)
CCh
0Fh
20h
00h
<8 Data Bytes>
<2 Bytes CRC-16>
(Reset)
(Presence)
CCh
AAh
20h
00h
07h
<8 Data Bytes>
<2 Bytes CRC-16>
(Reset)
(Presence)
CCh
55h
20h
00h
07h
<1-Wire Idle High>
AAh
(Reset)
(Presence)
CCh
F0h
00h
00h
<144 Data Bytes>
(Reset)
(Presence)
ᔐሣ࿟ᒑᎌ࡝ৈET3542Ꭷᓍ૦ೌ୻ǈᄰቧਭ߈ྙሆჅာǖ
COMMENTS
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Write Scratchpad” command
TA1, beginning offset = 20h
TA2, address = 0020h
Write 8 bytes of data to scratchpad
Read CRC to check for data integrity
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Read Scratchpad” command
Read TA1, beginning offset = 20h
Read TA2, address = 0020h
Read E/S, ending offset = 111b, AA, PF = 0
Read scratchpad data and verify
Read CRC to check for data integrity
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Copy Scratchpad” command
TA1
(AUTHORIZATION CODE)
TA2
E/S
Wait t PROGMAX for the copy function to complete
Read copy status, AAh = success
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Read Memory” command
TA1, beginning offset = 00h
TA2, address = 0000h
Read the entire memory
Reset pulse
Presence pulse
______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
SIDE VIEW
FRONT VIEW
GND
1
1
IO
2
2
N.C.
3
3
FRONT VIEW (T&R VERSION)
TO-92
1
2
3
TOP VIEW
TOP VIEW
GND
N.C.
N.C.
A1
A2
A3
+
GND
1
IO
2
N.C.
3
6 N.C.
DS2431
5
N.C.
4
N.C.
DS2431
TSOC
C1
C2
C3
IO
N.C.
N.C.
UCSPR
TOP VIEW
BOTTOM VIEW
DS2431
+
1
IO
2
GND
3
*EXPOSED PAD
2431
ymrrF
N.C.
*EP
TDFN-EP
(3mm × 3mm)
6
N.C.
5
N.C.
4
N.C.
SIDE VIEW
1
2
IO
GND
SFN
(6mm × 6mm × 0.9mm)
NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL
CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE
INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT
METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE.
______________________________________________________________________________________
23
ET3542
```````````````````````````````````````````````````````````````````````````` ፛୭๼ᒙ
ET3542
2135ᆡ2.Xjsf! FFQSPN
``````````````````````````````````````````````````````````````` TGOॖᓤᏴ௳ࡒ࿟ࡼᆡᒙ
USER DIRECTION OF FEED
LEADS FACE UP IN ORIENTATION SHOWN ABOVE.
```````````````````````````````````````````````````````````````````````````` ॖᓤቧᇦ
ྙኊᔢதࡼॖᓤᅪተቧᇦਜ਼੆๤‫ݚ‬௜ǈ༿‫އ‬ኯ china.maxim-ic.com/packagesă༿ᓖፀǈॖᓤ‫ܠ‬൩ᒦࡼĐ,đĂĐ$đ૞Đ.đஞ‫ܭ‬ာSpITᓨზă
ॖᓤᅄᒦభถ۞਺‫ݙ‬ᄴࡼᆘᓮᔊ९ǈࡣॖᓤᅄᒑᎧॖᓤᎌਈǈᎧSpITᓨზᇄਈă
24
ॖᓤಢቯ
ॖᓤ‫ܠ‬൩
ᅪተ‫ܠ‬੓
੆๤‫ݚ‬௜‫ܠ‬੓
3 TO-92 (ྲᓤ)
Q3+1
21-0248
—
3 TO-92 (T&R)
Q3+4
21-0250
—
6 TSOC
D6+1
21-0382
90-0321
2 SFN
G266+1
21-0390
—
6 TDFN-EP
T633+2
21-0137
90-0058
6 UCSPR
BR622+1
21-0376
༿‫ݬ‬ఠ
።፿‫܊‬଑29:2
______________________________________________________________________________________
2135ᆡ2.Xjsf! FFQSPN
ኀࢿ੓
ኀࢿ྇໐
0
050704
ᔢ߱‫۾ۈ‬ă
ᄐધ፛୭๼ᒙă
1
081604
ᏴFmfdusjdbm! Dibsbdufsjtujdt‫ܭ‬ᒦǈWUM)NJO*ᎅ1/6Wখᆐ1/57W༦WUM)NBY*ᎅ5/2Wখᆐ5/5WǗ
WIZ)NJO*ᎅ1/33Wখᆐ1/32Wă
2
Ᏼ Dpqz! Tdsbudiqbe! \66i^ᒦǈআᒜဟମᎅ24ntৎᑵᆐ23/6ntă
14
1
ႁී
ᐐଝTGOॖᓤǈ݀ৎቤࢾ৪ቧᇦ‫ܭ‬ă
Ᏼ፛୭๼ᒙᒦǈᐐଝጙᄟਈ᎖DTQॖᓤᅪተࡼᓖျǖĐ*Tff! qbdlbhf! sfmjbcjmjuz! sfqpsu! gps
jnqpsubou! hvjefmjoft! po! rvbmjgjfe! vtbhf! dpoejujpot/đ
ă
2
3
4
5
6
090506
122106
102207
032008
8/08
Ᏼ Fmfdusjdbm! Dibsbdufsjtujdt ‫ܭ‬ᒦǈB3‫۾ۈ‬ሆࡼFD‫ܭ‬ᒦ‫ݬ‬ၫuQSPH )‫߈ܠ‬ဟମ*ᎅ23/6ntখᆐ
21nt! )થ༿‫ݬ‬ఠ࢒2጑ਜ਼࢒24጑*ă࿎߹uGQEǈ݀ሤ።࢐ৎቤuQEIĂuNTQ ਜ਼uX1Mă୓JQSPH
ᔢࡍᒋখᆐ1/9nBǈጲປ๼HCEă
ኀখ጑
——
1, 24
1
1, 2, 3, 13
ৎቤࡀ߼໭৖ถာಿ‫ܭ‬ă
23
Ᏼ፛୭๼ᒙᒦᐐଝDTQॖᓤᅪተᅄᒓ‫ܠ‬੓ă
1
Ᏼ Fmfdusjdbm! Dibsbdufsjtujdt ‫ܭ‬ᒦǈ୓WUM)NJO*ᎅ1/57Wখᆐ1/6Wă
2
Ᏼ Bctpmvuf! Nbyjnvn! Sbujoht ᒦǈࡀ߼ᆨࣞৎখᆐ.66°Dᒗ,236°DǗᏴ Fmfdusjdbm
Dibsbdufsjtujdt ‫ܭ‬ᒦǈো௣WQVQ খ‫ܤ‬WUIĂWUMǈ༦Ᏼ96°Dሆၫ௣భۣߒᒗ࿩51ฤǗ
ᐐଝၫ௣ۣߒਖपࡼႁීǖ
ĐFFQSPN! xsjuft! dbo! cfdpnf! opogvodujpobm! bgufs! uif! ebub.
sfufoujpo! ujnf! jt! fydffefe/! Mpoh.ufsn! tupsbhf! bu! fmfwbufe! ufnqfsbuvsft! jt! opu! sfdpnnfoefe<
uif! efwjdf! dbo! mptf! jut! xsjuf! dbqbcjmjuz! bgufs! 21! zfbst! bu! ,236°D! ps! 51! zfbst! bu! ,96°D/đ
1, 2, 3
ࢾ৪ቧᇦ‫ܭ‬ᒦǈ࿎߹೫Ⴥᎌᎌ໺໭ୈቯ੓݀ᐐଝ೫UEGO.FQॖᓤă
1, 24
Ᏼ Fmfdusjdbm! Dibsbdufsjtujdt ᒦǈWJM)NBY*ਖৃᎅ1/4Wখᆐ1/6WǗ࠭uX2M)NBY*ਖৃᒦ࿎߹ ε Ǘ
࣪uX1M ਖৃᐐଝᓖျ28ǗৎቤFD‫ܭ‬ᓖျ28ਜ਼29Ǘኀᑵᓖျ31ă
2, 3
Ᏼ፛୭ႁීᒦᐐଝFQ৖ถă
3
Ᏼᅄ22ቖ1ဟᇺᒦᐐଝ εă
19
Ᏼ፛୭๼ᒙᒦǈᐐଝॖᓤᅄᒓቧᇦ0ᆀ൥೔୻ጲૺᐐଝጙᄟਈ᎖ளਭTGOॖᓤ࢟໮.૦቗
ೌ୻ዩᑺࡼᓖျǈ‫ݙ‬း੝੆୻ăᐐଝ TGOॖᓤᏴ௳ࡒ࿟ࡼᆡᒙ‫ݝ‬ॊăᏴࢾ৪ቧᇦᒦǈ
ᐐଝᎌਈVDTQSॖᓤࡼ৙ૡቧᇦ༿Ꭷ৔‫ޣ‬ೊᇹࡼᓖျăᐐଝ࣪௳ࡒᒦUP.:3ॖᓤࡼ፛୭
ମ৆Ꮦᆐ211njmࡼᓖျă
24
ᏴTGO ፛୭๼ᒙᒦǈᐐଝ‫ݬ‬ఠ።፿‫܊‬଑5243ă
24
ᐐଝॖᓤቧᇦ‫ܭ‬ă
25
ည߅ቤ‫ࡼ۾ۈ‬ၫ௣ᓾ೯ă
Ⴥᎌ጑
______________________________________________________________________________________
25
ET3542
```````````````````````````````````````````````````````````````````````````` ኀࢿ಼ဥ
ET3542
2135ᆡ2.Xjsf! FFQSPN
``````````````````````````````````````````````````````````````````````````````````` ኀࢿ಼ဥ)ኚ*
ኀࢿ੓
ኀࢿ྇໐
ႁී
ኀখ጑
7
6/09
8
10/09
ኀᑵ೫ࢾ৪ቧᇦ‫ܭ‬ᒦࡼ໭ୈቯ੓ă
1
9
12/10
࠭ᄂቶ‫ݝ‬ॊᒦ࿎߹໱‫଀ޱ‬໭ୈࡼሤਈቧᇦă
1
• ࿎߹೫ࢾ৪ቧᇦᒦĐೊᇹ৔‫ޣ‬đࡼᓖျă
• ৎቤ೫፛୭ႁීਜ਼፛୭๼ᒙǈጲ࣪።VDTQSॖᓤ፛୭๝೰ࡼ‫ܤ‬છă
1, 5, 23
Nbyjn ۱ய‫ࠀူێ‬
۱ய 9439ቧረ ᎆᑶ‫ܠ‬൩ 211194
඾ॅ࢟જǖ911!921!1421
࢟જǖ121.7322 62::
ࠅᑞǖ121.7322 63::
Nbyjn‫࣪ݙ‬Nbyjn‫ޘ‬ອጲᅪࡼྀੜ࢟വဧ፿ঌᐊǈጐ‫ݙ‬ᄋ৙໚ᓜಽ኏భăNbyjnۣഔᏴྀੜဟମĂ඗ᎌྀੜᄰۨࡼ༄ᄋሆኀখ‫ޘ‬ອᓾ೯ਜ਼ਖৃࡼཚಽă
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Nbyjn ဵ Nbyjn!Joufhsbufe!Qspevdut-!Jod/ ࡼᓖ‫ݿ‬࿜‫ܪ‬ă
19-4675; Rev 13; 3/12
1024-Bit, 1-Wire EEPROM
The DS2431 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each. Data is
written to an 8-byte scratchpad, verified, and then
copied to the EEPROM memory. As a special feature, the
four memory pages can individually be write protected or
put in EPROM-emulation mode, where bits can only be
changed from a 1 to a 0 state. The DS2431 communicates over the single-conductor 1-Wire bus. The communication follows the standard 1-Wire protocol. Each
device has its own unalterable and unique 64-bit ROM
registration number that is factory lasered into the chip.
The registration number is used to address the device in
a multidrop, 1-Wire net environment.
Applications
Accessory/PCB Identification
Medical Sensor Calibration Data Storage
Analog Sensor Calibration Including IEEE
P1451.4 Smart Sensors
Features
o 1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 Bits
o Individual Memory Pages Can Be Permanently
Write Protected or Put in EPROM-Emulation Mode
(“Write to 0”)
o Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
o IEC 1000-4-2 Level 4 ESD Protection (±8kV
Contact, ±15kV Air, Typical)
o Reads and Writes Over a Wide Voltage Range
from 2.8V to 5.25V from -40°C to +85°C
o Communicates to Host with a Single Digital
Signal at 15.4kbps or 125kbps Using 1-Wire
Protocol
o Also Available as Automotive Version Meeting
AEC-Q100 Grade 1 Qualification Requirements
(DS2431-A1; Refer to the IC Data Sheet for
Details)
Ink and Toner Print Cartridge Identification
Ordering Information
After-Market Management of Consumables
PART
Typical Operating Circuit
VCC
RPUP
IO
µC
TEMP RANGE
PIN-PACKAGE
DS2431+
-40°C to +85°C
3 TO-92
DS2431+T&R
-40°C to +85°C
3 TO-92
DS2431P+
-40°C to +85°C
6 TSOC
DS2431P+T&R
-40°C to +85°C
6 TSOC
DS2431G+U
-40°C to +85°C
2 SFN (6mm x 6mm)
DS2431G+T&R
-40°C to +85°C
2 SFN (6mm x 6mm)
(2.5k pcs)
DS2431GA+U
-40°C to +85°C
2 SFN (3.5mm x 6.5mm)
DS2431GA+T&R
-40°C to +85°C
2 SFN (3.5mm x 6.5mm)
(2.5k pcs)
DS2431Q+T&R
-40°C to +85°C
6 TDFN-EP* (2.5k pcs)
DS2431X-S+
-40°C to +85°C
3x3 UCSPR (2.5k pcs)
DS2431X+
-40°C to +85°C
3x3 UCSPR (10k pcs)
DS2431
GND
Pin Configurations appear at end of data sheet.
Note: The leads of TO-92 packages on tape and reel are
formed to approximately 100-mil (2.54mm) spacing. For
details, refer to the package outline drawing.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS2431
General Description
DS2431
1024-Bit, 1-Wire EEPROM
ABSOLUTE MAXIMUM RATINGS
IO Voltage Range to GND .......................................-0.5V to +6V
IO Sink Current ...................................................................20mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (excluding UCSP, soldering, 10s).....+300°C
Soldering Temperature (reflow)
TO-92 ............................................................................+250°C
AIl other packages, excluding SFN ..............................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
VPUP
(Note 2)
2.8
5.25
V
1-Wire Pullup Resistance
RPUP
(Notes 2, 3)
0.3
2.2
k
Input Capacitance
CIO
(Notes 4, 5)
1000
pF
Input Load Current
IL
0.05
6.7
µA
0.5
VPUP 1.8
V
0.5
V
IO pin at VPUP
High-to-Low Switching Threshold
VTL
(Notes 5, 6, 7)
Input Low Voltage
VIL
(Notes 2, 8)
Low-to-High Switching Threshold
VTH
(Notes 5, 6, 9)
1.0
VPUP 1.0
V
Switching Hysteresis
VHY
(Notes 5, 6, 10)
0.21
1.70
V
Output Low Voltage
VOL
At 4mA (Note 11)
0.4
V
Recovery Time
(Notes 2,12)
tREC
Rising-Edge Hold-Off Time
(Notes 5, 13)
tREH
Time Slot Duration
(Notes 2, 14)
t SLOT
Standard speed, RPUP = 2.2k
5
Overdrive speed, RPUP = 2.2k
2
Overdrive speed, directly prior to reset
pulse; RPUP = 2.2k
5
Standard speed
Overdrive speed
0.5
µs
5.0
Not applicable (0)
Standard speed
65
Overdrive speed
8
µs
µs
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time (Note 2)
tRSTL
Presence-Detect High Time
t PDH
Presence-Detect Low Time
t PDL
Presence-Detect Sample Time
(Notes 2, 15)
tMSP
2
Standard speed
480
640
Overdrive speed
48
80
Standard speed
15
60
Overdrive speed
2
6
Standard speed
60
240
Overdrive speed
8
24
Standard speed
60
75
Overdrive speed
6
10
_______________________________________________________________________________________
µs
µs
µs
µs
1024-Bit, 1-Wire EEPROM
(TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 2, 16, 17)
Write-One Low Time
(Notes 2, 17)
tW0L
tW1L
Standard speed
60
120
Overdrive speed, VPUP > 4.5V
5
15.5
Overdrive speed
6
15.5
Standard speed
1
15
Overdrive speed
1
2
Standard speed
5
15 - Overdrive speed
1
2-
Standard speed
tRL + 15
Overdrive speed
tRL + 2
µs
µs
IO PIN: 1-Wire READ
Read Low Time
(Notes 2, 18)
tRL
Read Sample Time
(Notes 2, 18)
tMSR
µs
µs
EEPROM
Programming Current
I PROG
(Notes 5, 19)
0.8
mA
Programming Time
t PROG
(Notes 20, 21)
10
ms
Write/Erase Cycles (Endurance)
(Notes 22, 23)
NCY
Data Retention
(Notes 24, 25, 26)
tDR
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
At +25°C
200k
At +85°C (worst case)
50k
At +85°C (worst case)
40
Years
Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Maximum value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Guaranteed by design, characterization, and/or simulation only. Not production tested.
VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of
VTL, VTH, and VHY.
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.
The I-V characteristic is linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to tW0LMIN + tRECMIN.
Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS2431 present. The power-up presencedetect pulse could be outside this interval, but will be complete within 2ms after power-up.
Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table.
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
_______________________________________________________________________________________
3
DS2431
ELECTRICAL CHARACTERISTICS (continued)
DS2431
1024-Bit, 1-Wire EEPROM
Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval
should be such that the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, a lowimpedance bypass of RPUP, which can be activated during programming, may need to be added.
Note 20: Interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by
the device has returned from IPROG to IL.
Note 21: tPROG for units branded version “A1” is 12.5ms. tPROG for units branded version “A2” and later is 10ms.
Note 22: Write-cycle endurance is degraded as TA increases.
Note 23: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 24: Data retention is degraded as TA increases.
Note 25: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 26: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
COMPARISON TABLE
LEGACY VALUES
PARAMETER
STANDARD SPEED
(µs)
DS2431 VALUES
OVERDRIVE SPEED
(µs)
STANDARD SPEED
(µs)
OVERDRIVE SPEED
(µs)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
61
(undefined)
7
(undefined)
65*
(undefined)
8*
(undefined)
tRSTL
480
(undefined)
48
80
480
640
48
80
t PDH
15
60
2
6
15
60
2
6
t PDL
60
240
8
24
60
240
8
24
tW0L
60
120
6
16
60
120
6
15.5
t SLOT (including tREC)
*Intentional change; longer recovery time requirement due to modified 1-Wire front-end.
Note: Numbers in bold are not in compliance with legacy 1-Wire product standards.
4
_______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
PIN
NAME
TSOC
TO-92
TDFN-EP
SFN
UCSPR
3, 4, 5, 6
3
1, 4, 5, 6
—
A2, A3, C2,
C3
N.C.
2
2
2
1
C1
IO
1
1
3
2
A1
GND
—
—
—
—
—
EP
FUNCTION
Not Connected
1-Wire Bus Interface. Open-drain signal
that requires an external pullup resistor.
Ground Reference
Exposed Pad (TDFN only). Solder
evenly to the board’s ground plane for
proper operation. Refer to Application
Note 3273: Exposed Pads: A Brief
Introduction for additional information.
Detailed Description
The DS2431 combines 1024 bits of EEPROM, an
8-byte register/control page with up to 7 user read/write
bytes, and a fully featured 1-Wire interface in a single
chip. Each DS2431 has its own 64-bit ROM registration
number that is factory lasered into the chip to provide a
guaranteed unique identity for absolute traceability.
Data is transferred serially through the
1-Wire protocol, which requires only a single data lead
and a ground return. The DS2431 has an additional
memory area called the scratchpad that acts as a
buffer when writing to the main memory or the register
page. Data is first written to the scratchpad from which
it can be read back. After the data has been verified, a
Copy Scratchpad command transfers the data to its
final memory location. The DS2431 applications include
accessory/PCB identification, medical sensor calibration data storage, analog sensor calibration including
IEEE P1451.4 smart sensors, ink and toner print cartridge identification, and after-market management of
consumables.
PARASITE POWER
IO
1-Wire
FUNCTION CONTROL
64-BIT
LASERED ROM
DS2431
MEMORY
FUNCTION
CONTROL UNIT
CRC-16
GENERATOR
DATA MEMORY
4 PAGES OF
256 BITS EACH
64-BIT
SCRATCHPAD
Overview
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS2431. The DS2431 has four main data components:
64-bit lasered ROM, 64-bit scratchpad, four 32-byte
pages of EEPROM, and a 64-bit register page.
REGISTER PAGE
64 BITS
Figure 1. Block Diagram
_______________________________________________________________________________________
5
DS2431
Pin Description
DS2431
1024-Bit, 1-Wire EEPROM
DS2431 COMMAND LEVEL:
1-Wire ROM FUNCTION COMMANDS
(SEE FIGURE 9)
DS2431-SPECIFIC
MEMORY FUNCTION COMMANDS
(SEE FIGURE 7)
AVAILABLE COMMANDS:
DATA FIELD AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT REG. #, RC-FLAG, OD-FLAG
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
READ MEMORY
64-BIT SCRATCHPAD, FLAGS
64-BIT SCRATCHPAD
DATA MEMORY, REGISTER PAGE
DATA MEMORY, REGISTER PAGE
Figure 2. Hierarchical Structure for 1-Wire Protocol
MSB
LSB
8-BIT
CRC CODE
MSB
8-BIT FAMILY CODE
(2Dh)
48-BIT SERIAL NUMBER
LSB MSB
LSB MSB
LSB
Figure 3. 64-Bit Lasered ROM
The hierarchical structure of the 1-Wire protocol is
shown in Figure 2. The bus master must first provide
one of the seven ROM function commands: Read ROM,
Match ROM, Search ROM, Skip ROM, Resume,
Overdrive-Skip ROM, or Overdrive-Match ROM. Upon
completion of an Overdrive-Skip ROM or OverdriveMatch ROM command byte executed at standard
speed, the device enters overdrive mode where all
subsequent communication occurs at a higher speed.
The protocol required for these ROM function commands is described in Figure 9. After a ROM function
command is successfully executed, the memory functions become accessible and the master can provide
any one of the four memory function commands. The
protocol for these memory function commands is
described in Figure 7. All data is read and written
least significant bit first.
64-Bit Lasered ROM
Each DS2431 contains a unique ROM code that is 64
bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits
are a cyclic redundancy check (CRC) of the first 56 bits.
See Figure 3 for details. The 1-Wire CRC is generated
using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial
is X8 + X5 + X4 + 1. Additional information about the
1-Wire CRC is available in Application Note 27:
Understanding and Using Cyclic Redundancy Checks
with Maxim iButton® Products.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the last bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of the CRC returns the shift register to all 0s.
iButton is a registered trademark of Maxim Integrated Products, Inc.
6
_______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
POLYNOMIAL = X8 + X5 + X4 + 1
1ST
STAGE
X0
2ND
STAGE
X1
3RD
STAGE
X2
4TH
STAGE
5TH
STAGE
X3
6TH
STAGE
X4
X5
7TH
STAGE
X6
8TH
STAGE
X7
X8
INPUT DATA
Figure 4. 1-Wire CRC Generator
Memory Access
Data memory and registers are located in a linear
address space, as shown in Figure 5. The data memory and the registers have unrestricted read access.
The DS2431 EEPROM array consists of 18 rows of 8
bytes each. The first 16 rows are divided equally into
four memory pages (32 bytes each). These four pages
are the primary data memory. Each page can be individually set to open (unprotected), write protected, or
EPROM mode by setting the associated protection
byte in the register row. As a factory default, the entire
data memory is unprotected and its contents are undefined. The last two rows contain protection registers
and reserved bytes. The register row consists of 4 protection control bytes, a copy-protection byte, the factory byte, and 2 user byte/manufacture ID bytes. The
manufacturer ID can be a customer-supplied identification code that assists the application software in
identifying the product the DS2431 is associated with.
ADDRESS RANGE
TYPE
0000h to 001Fh
R/(W)
Data Memory Page 0
DESCRIPTION
—
PROTECTION CODES
0020h to 003Fh
R/(W)
Data Memory Page 1
—
0040h to 005Fh
R/(W)
Data Memory Page 2
—
0060h to 007Fh
R/(W)
Data Memory Page 3
—
0080h*
R/(W)
Protection Control Byte Page 0
55h: Write Protect P0; AAh: EPROM Mode P0;
55h or AAh: Write Protect 80h
0081h*
R/(W)
Protection Control Byte Page 1
55h: Write Protect P1; AAh: EPROM Mode P1;
55h or AAh: Write Protect 81h
0082h*
R/(W)
Protection Control Byte Page 2
55h: Write Protect P2; AAh: EPROM Mode P2;
55h or AAh: Write Protect 82h
0083h*
R/(W)
Protection Control Byte Page 3
55h: Write Protect P3; AAh: EPROM Mode P3;
55h or AAh: Write Protect 83h
0084h*
R/(W)
Copy Protection Byte
55h or AAh: Copy Protect 0080h:008Fh, and Any
Write-Protected Pages
0085h
R
Factory Byte. Set at Factory.
AAh: Write Protect 85h, 86h, 87h;
55h: Write Protect 85h; Unprotect 86h, 87h
0086h
R/(W)
User Byte/Manufacturer ID
—
0087h
R/(W)
User Byte/Manufacturer ID
—
0088h to 008Fh
—
Reserved
—
*Once programmed to AAh or 55h this address becomes read only. All other codes can be stored, but neither write protect the
address nor activate any function.
Figure 5. Memory Map
_______________________________________________________________________________________
7
DS2431
1024-Bit, 1-Wire EEPROM
Contact the factory to set up and register a custom
manufacturer ID. The last row is reserved for future
use. It is undefined in terms of R/W functionality and
should not be used.
In addition to the main EEPROM array, an 8-byte
volatile scratchpad is included. Writes to the EEPROM
array are a two-step process. First, data is written to the
scratchpad and then copied into the main array. This
allows the user to first verify the data written to the
scratchpad prior to copying into the main array. The
device only supports full row (8-byte) copy operations.
For data in the scratchpad to be valid for a copy operation, the address supplied with a Write Scratchpad
command must start on a row boundary, and 8 full
bytes must be written into the scratchpad.
The protection control registers determine how incoming data on a Write Scratchpad command is loaded
into the scratchpad. A protection setting of 55h (write
protect) causes the incoming data to be ignored and
the target address main memory data to be loaded into
the scratchpad. A protection setting of AAh (EPROM
mode) causes the logical AND of incoming data and
target address main memory data to be loaded into the
scratchpad. Any other protection control register setting leaves the associated memory page open for unrestricted write access. Note: For the EPROM mode to
function, the entire affected memory page must first be
programmed to FFh. Protection-control byte settings of
55h or AAh also write protect the protection-control
byte. The protection-control byte setting of 55h does
not block the copy. This allows write-protected data to
be refreshed (i.e., reprogrammed with the current data)
in the device.
The copy-protection byte is used for a higher level of
security and should only be used after all other protection control bytes, user bytes, and write-protected
pages are set to their final value. If the copy-protection
byte is set to 55h or AAh, all copy attempts to the register row and user-byte row are blocked. In addition, all
copy attempts to write-protected main memory pages
(i.e., refresh) are blocked.
Address Registers and Transfer Status
The DS2431 employs three address registers: TA1,
TA2, and E/S (Figure 6). These registers are common to
many other 1-Wire devices but operate slightly differently with the DS2431. Registers TA1 and TA2 must be
loaded with the target address to which the data is written or from which data is read. Register E/S is a readonly transfer-status register used to verify data integrity
with write commands. E/S bits E[2:0] are loaded with
the incoming T[2:0] on a Write Scratchpad command
and increment on each subsequent data byte. This is,
in effect, a byte-ending offset counter within the 8-byte
scratchpad. Bit 5 of the E/S register, called PF, is a
logic 1 if the data in the scratchpad is not valid due to a
loss of power or if the master sends fewer bytes than
needed to reach the end of the scratchpad. For a valid
write to the scratchpad, T[2:0] must be 0 and the master must have sent 8 data bytes. Bits 3, 4, and 6 have
no function; they always read 0. The highest valued bit
of the E/S register, called authorization accepted (AA),
acts as a flag to indicate that the data stored in the
scratchpad has already been copied to the target
memory address. Writing data to the scratchpad clears
this flag.
BIT #
7
6
5
4
3
2
1
0
TARGET ADDRESS (TA1)
T7
T6
T5
T4
T3
T2
T1
T0
TARGET ADDRESS (TA2)
T15
T14
T13
T12
T11
T10
T9
T8
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
AA
0
PF
0
0
E2
E1
E0
Figure 6. Address Registers
8
_______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
Memory Function Commands
The Memory Function Flowchart (Figure 7) describes
the protocols necessary for accessing the memory of
the DS2431. An example on how to use these functions
to write to and read from the device is in the Memory
Function Example section. The communication
between the master and the DS2431 takes place either
at standard speed (default, OD = 0) or at overdrive
speed (OD = 1). If not explicitly set into overdrive
mode, the DS2431 assumes standard speed.
Write Scratchpad [0Fh]
The Write Scratchpad command applies to the data
memory and the writable addresses in the register
page. For the scratchpad data to be valid for copying
to the array, the user must perform a Write Scratchpad
command of 8 bytes starting at a valid row boundary.
The Write Scratchpad command accepts invalid
addresses and partial rows, but subsequent Copy
Scratchpad commands are blocked.
After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The
data is written to the scratchpad starting at the byte offset of T[2:0]. The E/S bits E[2:0] are loaded with the
starting byte offset and increment with each subsequent byte. Effectively, E[2:0] is the byte offset of the
last full byte written to the scratchpad. Only full data
bytes are accepted.
When executing the Write Scratchpad command, the
CRC generator inside the DS2431 (Figure 13) calculates a CRC of the entire data stream, starting at the
command code and ending at the last data byte as
sent by the master. This CRC is generated using the
CRC-16 polynomial by first clearing the CRC generator
and then shifting in the command code (0Fh) of the
Write Scratchpad command, the target addresses (TA1
and TA2), and all the data bytes. Note that the CRC-16
calculation is performed with the actual TA1 and TA2
and data sent by the master. The master can end the
Write Scratchpad command at any time. However, if
the end of the scratchpad is reached (E[2:0] = 111b),
the master can send 16 read time slots and receive the
CRC generated by the DS2431.
If a Write Scratchpad command is attempted to a writeprotected location, the scratchpad is loaded with the
data already existing in memory rather than the data
transmitted. Similarly, if the target address page is in
EPROM mode, the scratchpad is loaded with the bitwise logical AND of the transmitted data and data
already existing in memory.
_______________________________________________________________________________________
9
DS2431
Writing with Verification
To write data to the DS2431, the scratchpad must be
used as intermediate storage. First, the master issues
the Write Scratchpad command to specify the desired
target address, followed by the data to be written to the
scratchpad. Note that Copy Scratchpad commands
must be performed on 8-byte boundaries, i.e., the three
LSBs of the target address (T2, T1, T0) must be equal
to 000b. If T[2:0] are sent with nonzero values, the copy
function is blocked. Under certain conditions (see the
Write Scratchpad [0Fh] section) the master receives an
inverted CRC-16 of the command, address (actual
address sent), and data at the end of the Write
Scratchpad command sequence. Knowing this CRC
value, the master can compare it to the value it has calculated to decide if the communication was successful
and proceed to the Copy Scratchpad command. If the
master could not receive the CRC-16, it should send
the Read Scratchpad command to verify data integrity.
As a preamble to the scratchpad data, the DS2431
repeats the target address TA1 and TA2 and sends the
contents of the E/S register. If the PF flag is set, data
did not arrive correctly in the scratchpad, or there was
a loss of power since data was last written to the
scratchpad. The master does not need to continue
reading; it can start a new trial to write data to the
scratchpad. Similarly, a set AA flag together with a
cleared PF flag indicates that the device did not recognize the Write command.
If everything went correctly, both flags are cleared.
Now the master can continue reading and verifying
every data byte. After the master has verified the data,
it can send the Copy Scratchpad command, for example. This command must be followed exactly by the
data of the three address registers, TA1, TA2, and E/S.
The master should obtain the contents of these registers by reading the scratchpad.
DS2431
1024-Bit, 1-Wire EEPROM
FROM ROM FUNCTIONS
FLOWCHART (FIGURE 9)
BUS MASTER Tx MEMORY
FUNCTION COMMAND
0Fh
WRITE SCRATCHPAD?
AAh
READ SCRATCHPAD?
N
Y
Y
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
BUS MASTER Rx
TA1 (T[7:0]), TA2 (T[15:8]),
AND E/S BYTE
DS2431
SETS PF = 1
CLEARS AA = 0
SETS E[2:0] = T[2:0]
DS2431 SETS
SCRATCHPAD
BYTE COUNTER = T[2:0]
MASTER Tx DATA BYTE
TO SCRATCHPAD
DS2431
INCREMENTS
E[2:0]
MASTER Tx RESET?
APPLIES ONLY
IF THE MEMORY
AREA IS NOT
PROTECTED.
Y
N
N
Y
BUS MASTER Rx
DATA BYTE FROM
SCRATCHPAD
DS2431
INCREMENTS
BYTE COUNTER
IF WRITE PROTECTED,
THE DS2431 COPIES
THE DATE BYTE FROM
THE TARGET ADDRESS
INTO THE SCRATCHPAD.
IF IN EPROM MODE,
THE DS2431 LOADS
THE BITWISE LOGICAL
AND OF THE TRANSMITTED
BYTE AND THE DATA
BYTE FROM THE TARGETED
ADDRESS INTO THE
SCRATCHPAD.
E[2:0] = 7?
T[2:0] = 0?
TO FIGURE 7b
N
MASTER Tx RESET?
Y
N
N
BYTE COUNTER
= E[2:0]?
Y
N
BUS MASTER Rx CRC-16
OF COMMAND, ADDRESS,
E/S BYTE, AND DATA BYTES
AS SENT BY THE DS2431
Y
PF = 0
BUS MASTER
Rx "1"s
DS2431 Tx CRC-16 OF
COMMAND, ADDRESS,
AND DATA BYTES AS THEY
WERE SENT BY THE BUS
MASTER
BUS MASTER
Rx "1"s
N
N
MASTER Tx RESET?
Y
MASTER Tx RESET?
Y
FROM FIGURE 7b
TO ROM FUNCTIONS
FLOWCHART (FIGURE 9)
Figure 7a. Memory Function Flowchart
10
______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
55h
COPY SCRATCHPAD?
Y
Y
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
ADDRESS < 90h?
Y
T[15:0] < 0090h?
N
Y
APPLICABLE TO ALL R/W
MEMORY LOCATIONS.
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
AND E/S BYTE
AUTH. CODE
MATCH?
F0h
READ MEMORY?
N
DS2431
FROM FIGURE 7a
Y
N
N
DS2431 SETS MEMORY
ADDRESS = (T[15:0])
N
N
PF = 0?
Y
BUS MASTER Rx
DATA BYTE FROM
MEMORY ADDRESS
DS2431
INCREMENTS
ADDRESS
COUNTER
Y
COPY PROTECTED?
MASTER Tx RESET?
Y
BUS MASTER
Rx "1"s
N
N
AA = 1
N
Y
DURATION: tPROG
DS2431 COPIES
SCRATCHPAD
DATA TO ADDRESS
BUS MASTER
Rx "1"s
MASTER Tx RESET?
ADDRESS < 8Fh?
*
Y
N
DS2431 Tx "0"
BUS MASTER
Rx "1"s
N
MASTER Tx RESET?
Y
MASTER Tx RESET?
N
Y
MASTER Tx RESET?
Y
N
DS2431 Tx "1"
MASTER Tx RESET?
N
Y
TO FIGURE 7a
* 1-Wire IDLE HIGH FOR POWER.
Figure 7b. Memory Function Flowchart (continued)
______________________________________________________________________________________
11
DS2431
1024-Bit, 1-Wire EEPROM
Read Scratchpad [AAh]
The Read Scratchpad command allows verifying the
target address and the integrity of the scratchpad data.
After issuing the command code, the master begins
reading. The first two bytes are the target address. The
next byte is the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different
from what the master originally sent. This is of particular
importance if the target address is within the register
page or a page in either write-protection mode or
EPROM mode. See the Write Scratchpad [0Fh] section
for details. The master should read through the scratchpad (E[2:0] - T[2:0] + 1 bytes), after which it receives
the inverted CRC based on data as it was sent by the
DS2431. If the master continues reading after the CRC,
all data is logic 1.
Copy Scratchpad [55h]
The Copy Scratchpad command is used to copy data
from the scratchpad to writable memory sections. After
issuing the Copy Scratchpad command, the master
must provide a 3-byte authorization pattern, which
should have been obtained by an immediately preceding Read Scratchpad command. This 3-byte pattern
must exactly match the data contained in the three
address registers (TA1, TA2, E/S, in that order). If the
pattern matches, the target address is valid, the PF flag
is not set, and the target memory is not copy protected,
then the AA flag is set and the copy begins. All 8 bytes
of scratchpad contents are copied to the target memory location. The duration of the device’s internal data
transfer is tPROG during which the voltage on the 1-Wire
bus must not fall below 2.8V. A pattern of alternating 0s
and 1s are transmitted after the data has been copied
until the master issues a reset pulse. If the PF flag is set
or the target memory is copy protected, the copy does
not begin and the AA flag is not set.
Read Memory [F0h]
The Read Memory command is the general function to
read data from the DS2431. After issuing the command, the master must provide the 2-byte target
address. After these 2 bytes, the master reads data
beginning from the target address and can continue
until address 008Fh. If the master continues reading,
the result is logic 1s. The device’s internal TA1, TA2,
E/S, and scratchpad contents are not affected by a
Read Memory command.
12
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS2431
is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken
down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types
and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots,
which are initiated on the falling edge of sync pulses
from the bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS2431 is
open drain with an internal circuit equivalent to that
shown in Figure 8.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS2431 supports both a standard
and overdrive communication speed of 15.4kbps (max)
and 125kbps (max), respectively. Note that legacy
1-Wire products support a standard communication
speed of 16.3kbps and overdrive of 142kbps. The
slightly reduced rates for the DS2431 are a result of
additional recovery times, which in turn were driven by
a 1-Wire physical interface enhancement to improve
noise immunity. The value of the pullup resistor primarily depends on the network size and load conditions.
The DS2431 requires a pullup resistor of 2.2kΩ (max) at
any speed.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
must be left in the idle state if the transaction is to
resume. If this does not occur and the bus is left low for
more than 16µs (overdrive speed) or more than 120µs
(standard speed), one or more devices on the bus
could be reset.
Transaction Sequence
The protocol for accessing the DS2431 through the
1-Wire port is as follows:
• Initialization
• ROM Function Command
• Memory Function Command
• Transaction/Data
______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
VPUP
BUS MASTER
DS2431 1-Wire PORT
RPUP
DATA
Rx
Tx
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
PORT PIN
Rx
IL
Tx
100Ω MOSFET
Figure 8. Hardware Configuration
Initialization
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by presence pulse(s) transmitted by the slave(s). The
presence pulse lets the bus master know that the
DS2431 is on the bus and is ready to operate. For more
details, see the 1-Wire Signaling section.
1-Wire ROM Function
Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that
the DS2431 supports. All ROM function commands are
8 bits long. A list of these commands follows (see the
flowchart in Figure 9).
Read ROM [33h]
The Read ROM command allows the bus master to read
the DS2431’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if
there is a single slave on the bus. If more than one slave
is present on the bus, a data collision occurs when all
slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and
48-bit serial number result in a mismatch of the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS2431 on a multidrop bus. Only the DS2431 that exactly matches the 64-bit ROM sequence responds to the
subsequent memory function command. All other slaves
wait for a reset pulse. This command can be used with a
single device or multiple devices on the bus.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire
bus or their registration numbers. By taking advantage
of the wired-AND property of the bus, the master can
use a process of elimination to identify the registration
numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the
bus master issues a triplet of time slots. On the first slot,
each slave device participating in the search outputs
the true value of its registration number bit. On the second slot, each slave device participating in the search
outputs the complemented value of its registration number bit. On the third slot, the master writes the true
value of the bit to be selected. All slave devices that do
not match the bit written by the master stop participating in the search. If both of the read bits are zero, the
master knows that slave devices exist with both states
of the bit. By choosing which state to write, the bus
master branches in the ROM code tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the
registration numbers of the remaining devices. Refer to
Application Note 187: 1-Wire Search Algorithm for a
detailed discussion, including an example.
Skip ROM [CCh]
This command can save time in a single-drop bus system by allowing the bus master to access the memory
functions without providing the 64-bit ROM code. If
more than one slave is present on the bus and, for
example, a read command is issued following the Skip
ROM command, data collision occurs on the bus as
multiple slaves transmit simultaneously (open-drain
pulldowns produce a wired-AND result).
______________________________________________________________________________________
13
DS2431
1024-Bit, 1-Wire EEPROM
BUS MASTER Tx
RESET PULSE
FROM FIGURE 9b
FROM MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)
OD
RESET PULSE?
N
OD = 0
Y
BUS MASTER Tx ROM
FUNCTION COMMAND
33h
READ ROM
COMMAND?
DS2431 Tx
PRESENCE PULSE
N
55h
MATCH ROM
COMMAND?
F0h
SEARCH ROM
COMMAND?
N
N
CCh
SKIP ROM
COMMAND?
Y
Y
Y
Y
RC = 0
RC = 0
RC = 0
RC = 0
DS2431 Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
TO FIGURE 9b
DS2431 Tx BIT 0
DS2431 Tx BIT 0
MASTER Tx BIT 0
BIT 0 MATCH?
N
N
BIT 0 MATCH?
Y
Y
DS2431 Tx
SERIAL NUMBER
(6 BYTES)
N
DS2431 Tx BIT 1
MASTER Tx BIT 1
DS2431 Tx BIT 1
MASTER Tx BIT 1
BIT 1 MATCH?
N
N
BIT 1 MATCH?
Y
Y
DS2431 Tx BIT 63
DS2431 Tx
CRC BYTE
MASTER Tx BIT 63
DS2431 Tx BIT 63
MASTER Tx BIT 63
BIT 63 MATCH?
N
N
BIT 63 MATCH?
Y
Y
RC = 1
RC = 1
TO FIGURE 9b
FROM FIGURE 9b
TO MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)
Figure 9a. ROM Functions Flowchart
14
______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
TO FIGURE 9a
FROM FIGURE 9a
A5h
RESUME
COMMAND?
3Ch
OVERDRIVESKIP ROM?
N
Y
N
Y
69h
OVERDRIVEMATCH ROM?
N
Y
RC = 0; OD = 1
RC = 0; OD = 1
N
RC = 1?
Y
MASTER Tx BIT 0
MASTER Tx
RESET?
N
Y
BIT 0 MATCH?
N
OD = 0
Y
MASTER Tx BIT 1
MASTER Tx
RESET?
N
Y
BIT 1 MATCH?
N
OD = 0
Y
MASTER Tx BIT 63
BIT 63 MATCH?
N
OD = 0
Y
FROM FIGURE 9a
RC = 1
TO FIGURE 9a
Figure 9b. ROM Functions Flowchart (continued)
______________________________________________________________________________________
15
DS2431
1024-Bit, 1-Wire EEPROM
Resume [A5h]
To maximize the data throughput in a multidrop environment, the Resume command is available. This command checks the status of the RC bit and, if it is set,
directly transfers control to the memory function commands, similar to a Skip ROM command. The only way
to set the RC bit is through successfully executing the
Match ROM, Search ROM, or Overdrive-Match ROM
command. Once the RC bit is set, the device can
repeatedly be accessed through the Resume command. Accessing another device on the bus clears the
RC bit, preventing two or more devices from simultaneously responding to the Resume command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the
normal Skip ROM command, the Overdrive-Skip ROM
command sets the DS2431 into the overdrive mode
(OD = 1). All communication following this command
must occur at overdrive speed until a reset pulse of
minimum 480µs duration resets all devices on the bus
to standard speed (OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be
issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the
search process. If more than one slave supporting
overdrive is present on the bus and the Overdrive-Skip
ROM command is followed by a read command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wiredAND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64bit ROM sequence transmitted at overdrive speed
allows the bus master to address a specific DS2431 on
a multidrop bus and to simultaneously set it in overdrive
mode. Only the DS2431 that exactly matches the 64-bit
ROM sequence responds to the subsequent memory
function command. Slaves already in overdrive mode
from a previous Overdrive-Skip ROM or successful
Overdrive-Match ROM command remain in overdrive
mode. All overdrive-capable slaves return to standard
speed at the next reset pulse of minimum 480µs duration. The Overdrive-Match ROM command can be used
with a single device or multiple devices on the bus.
16
1-Wire Signaling
The DS2431 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling on one line: reset sequence with reset pulse and
presence pulse, write-zero, write-one, and read-data.
Except for the presence pulse, the bus master initiates
all falling edges. The DS2431 can communicate at two
different speeds: standard speed and overdrive speed.
If not explicitly set into the overdrive mode, the DS2431
communicates at standard speed. While in overdrive
mode, the fast timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from VPUP below the threshold VTL. To get
from active to idle, the voltage needs to rise from
VILMAX past the threshold VTH. The time it takes for the
voltage to make this rise is seen in Figure 10 as ε, and
its duration depends on the pullup resistor (RPUP) used
and the capacitance of the 1-Wire network attached.
The voltage VILMAX is relevant for the DS2431 when
determining a logical level, not triggering any events.
Figure 10 shows the initialization sequence required to
begin any communication with the DS2431. A reset
pulse followed by a presence pulse indicates that the
DS2431 is ready to receive data, given the correct ROM
and memory function command. If the bus master uses
slew-rate control on the falling edge, it must pull down
the line for tRSTL + tF to compensate for the edge. A
tRSTL duration of 480µs or longer exits the overdrive
mode, returning the device to standard speed. If the
DS2431 is in overdrive mode and tRSTL is no longer
than 80µs, the device remains in overdrive mode. If the
device is in overdrive mode and tRSTL is between 80µs
and 480µs, the device resets, but the communication
speed is undetermined.
After the bus master has released the line it goes into
receive mode. Now the 1-Wire bus is pulled to VPUP
through the pullup resistor or, in the case of a DS2482x00 or DS2480B driver, through the active circuitry.
When the threshold VTH is crossed, the DS2431 waits
for tPDH and then transmits a presence pulse by pulling
the line low for tPDL. To detect a presence pulse, the
master must test the logical state of the 1-Wire line at
tMSP.
The t RSTH window must be at least the sum of
t PDHMAX , t PDLMAX , and t RECMIN . Immediately after
tRSTH is expired, the DS2431 is ready for data communication. In a mixed population network, tRSTH should
be extended to minimum 480µs at standard speed and
48µs at overdrive speed to accommodate other 1-Wire
devices.
______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
DS2431
MASTER Tx "RESET PULSE"
MASTER Rx "PRESENCE PULSE"
ε
tMSP
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tRSTL
tPDH
tF
tPDL
tREC
tRSTH
RESISTOR
MASTER
DS2431
Figure 10. Initialization Procedure: Reset and Presence Pulse
Read/Write Time Slots
Data communication with the DS2431 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time
slots transfer data from slave to master. Figure 11 illustrates the definitions of the write and read time slots.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold VTL, the DS2431 starts its internal
timing generator that determines when the data line is
sampled during a write time slot and how long data is
valid during a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the VTH threshold before the writeone low time tW1LMAX is expired. For a write-zero time
slot, the voltage on the data line must stay below the
VTH threshold until the write-zero low time tW0LMIN is
expired. For the most reliable communication, the voltage on the data line should not exceed VILMAX during
the entire tW0L or tW1L window. After the VTH threshold
has been crossed, the DS2431 needs a recovery time
tREC before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below VTL
until the read low time tRL is expired. During the tRL
window, when responding with a 0, the DS2431 starts
pulling the data line low; its internal timing generator
determines when this pulldown ends and the voltage
starts rising again. When responding with a 1, the
DS2431 does not hold the data line low at all, and the
voltage starts rising as soon as tRL is over.
The sum of tRL + δ (rise time) on one side and the internal timing generator of the DS2431 on the other side
define the master sampling window (t MSRMIN to
tMSRMAX), in which the master must perform a read
from the data line. For the most reliable communication,
tRL should be as short as permissible, and the master
should read close to but no later than tMSRMAX. After
reading from the data line, the master must wait until
tSLOT is expired. This guarantees sufficient recovery
time tREC for the DS2431 to get ready for the next time
slot. Note that tREC specified herein applies only to a
single DS2431 attached to a 1-Wire line. For multidevice configurations, tREC must be extended to accommodate the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup
during the 1-Wire recovery time such as the DS2482x00 or DS2480B 1-Wire line drivers can be used.
______________________________________________________________________________________
17
DS2431
1024-Bit, 1-Wire EEPROM
WRITE-ONE TIME SLOT
tW1L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tSLOT
RESISTOR
MASTER
WRITE-ZERO TIME SLOT
tW0L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tREC
tSLOT
RESISTOR
MASTER
READ-DATA TIME SLOT
tMSR
tRL
VPUP
VIHMASTER
VTH
MASTER
SAMPLING
WINDOW
VTL
VILMAX
0V
δ
tF
tREC
tSLOT
RESISTOR
MASTER
DS2431
Figure 11. Read/Write Timing Diagrams
18
______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
In a 1-Wire environment, line termination is possible
only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the
physical size and topology of the network, reflections
from end points and branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication
line. Noise coupled onto the 1-Wire line from external
sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave
device to lose synchronization with the master and,
consequently, result in a Search ROM command coming to a dead end or cause a device-specific function
command to abort. For better performance in network
applications, the DS2431 uses a new 1-Wire front-end,
which makes it less sensitive to noise.
The DS2431’s 1-Wire front-end differs from traditional
slave devices in three characteristics.
1) There is additional lowpass filtering in the circuit that
detects the falling edge at the beginning of a time
slot. This reduces the sensitivity to high-frequency
noise. This additional filtering does not apply at
overdrive speed.
2) There is a hysteresis at the low-to-high switching
threshold VTH. If a negative glitch crosses VTH but
does not go below VTH - VHY, it is not recognized
(Figure 12, Case A). The hysteresis is effective at
any 1-Wire speed.
3) There is a time window specified by the rising edge
hold-off time tREH during which glitches are ignored,
even if they extend below the VTH - VHY threshold
tREH
(Figure 12, Case B, tGL < tREH). Deep voltage drops
or glitches that appear late after crossing the VTH
threshold and extend beyond the tREH window cannot be filtered out and are taken as the beginning of a
new time slot (Figure 12, Case C, tGL ≥ tREH).
Devices that have the parameters VHY and tREH specified in their electrical characteristics use the improved
1-Wire front-end.
CRC Generation
The DS2431 uses two different types of CRCs. One
CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit
ROM and compare it to the value stored within the
DS2431 to determine if the ROM data has been
received error-free. The equivalent polynomial function
of this CRC is X 8 + X 5 + X 4 + 1. This 8-bit CRC is
received in the true (noninverted) form. It is computed
at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to
the standardized CRC-16 polynomial function X16 + X15
+ X2 + 1. This CRC is used for fast verification of a data
transfer when writing to or reading from the scratchpad.
In contrast to the 8-bit CRC, the 16-bit CRC is always
communicated in the inverted form. A CRC generator
inside the DS2431 chip (Figure 13) calculates a new 16bit CRC, as shown in the command flowchart (Figure 7).
The bus master compares the CRC value read from the
device to the one it calculates from the data and
decides whether to continue with an operation or to
reread the portion of the data with the CRC error.
With the Write Scratchpad command, the CRC is generated by first clearing the CRC generator and then
shifting in the command code, the target addresses
TA1 and TA2, and all the data bytes as they were sent
tREH
VPUP
VTH
VHY
CASE A
CASE B
CASE C
0V
tGL
tGL
Figure 12. Noise Suppression Scheme
______________________________________________________________________________________
19
DS2431
Improved Network Behavior
(Switchpoint Hysteresis)
DS2431
1024-Bit, 1-Wire EEPROM
POLYNOMIAL = X16 + X15 + X2 + 1
1ST
STAGE
3RD
STAGE
2ND
STAGE
X0
X2
X1
9TH
STAGE
X8
4TH
STAGE
10TH
STAGE
X9
11TH
STAGE
X10
X3
12TH
STAGE
X11
5TH
STAGE
6TH
STAGE
X4
13TH
STAGE
X12
X5
14TH
STAGE
X13
7TH
STAGE
X6
8TH
STAGE
X7
15TH
STAGE
X14
16TH
STAGE
X15
X16
CRC OUTPUT
INPUT DATA
Figure 13. CRC-16 Hardware Description and Polynomial
by the bus master. The DS2431 transmits this CRC only
if E[2:0] = 111b.
With the Read Scratchpad command, the CRC is generated by first clearing the CRC generator and then
shifting in the command code, the target addresses
TA1 and TA2, the E/S byte, and the scratchpad data as
they were sent by the DS2431. The DS2431 transmits
this CRC only if the reading continues through the end
of the scratchpad. For more information on generating
CRC values, refer to Application Note 27.
Command-Specific 1-Wire Communication Protocol—Legend
SYMBOL
RST
1-Wire reset pulse generated by master.
PD
1-Wire presence pulse generated by slave.
Select
Command and data to satisfy the ROM function protocol.
WS
Command "Write Scratchpad."
RS
Command "Read Scratchpad."
CPS
Command "Copy Scratchpad."
RM
Command "Read Memory."
TA
Target address TA1, TA2.
TA-E/S
<8–T[2:0] bytes>
<Data to EOM>
Target address TA1, TA2 with E/S byte.
Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address.
Transfer of as many data bytes as are needed to reach the end of the memory.
CRC-16
Transfer of an inverted CRC-16.
FF Loop
Indefinite loop where the master reads FF bytes.
AA Loop
Indefinite loop where the master reads AA bytes.
Programming
20
DESCRIPTION
Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.
______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
Master to Slave
Slave to Master
Programming
1-Wire Communication Examples
Write Scratchpad (Cannot Fail)
RST PD Select WS TA <8–T[2:0] bytes> CRC-16 FF Loop
Read Scratchpad (Cannot Fail)
RST PD Select RS TA-E/S <8–T[2:0] bytes> CRC-16 FF Loop
Copy Scratchpad (Success)
RST PD Select CPS TA-E/S Programming AA Loop
Copy Scratchpad (Invalid Address or PF = 1 or Copy Protected)
RST PD Select CPS TA-E/S FF Loop
Read Memory (Success)
RST PD Select RM TA <Data to EOM> FF Loop
Read Memory (Invalid Address)
RST PD Select RM TA FF Loop
______________________________________________________________________________________
21
DS2431
Command-Specific 1-Wire Communication Protocol—Color Codes
DS2431
1024-Bit, 1-Wire EEPROM
Memory Function Example
Write to the first 8 bytes of memory page 1. Read the
entire memory.
MASTER MODE
Tx
Rx
Tx
Tx
Tx
Tx
Tx
Rx
Tx
Rx
Tx
Tx
Rx
Rx
Rx
Rx
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Tx
—
Rx
Tx
Rx
Tx
Tx
Tx
Tx
Rx
Tx
Rx
22
DATA (LSB FIRST)
(Reset)
(Presence)
CCh
0Fh
20h
00h
<8 Data Bytes>
<2 Bytes CRC-16>
(Reset)
(Presence)
CCh
AAh
20h
00h
07h
<8 Data Bytes>
<2 Bytes CRC-16>
(Reset)
(Presence)
CCh
55h
20h
00h
07h
<1-Wire Idle High>
AAh
(Reset)
(Presence)
CCh
F0h
00h
00h
<144 Data Bytes>
(Reset)
(Presence)
With only a single DS2431 connected to the bus master, the communication looks like this:
COMMENTS
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Write Scratchpad” command
TA1, beginning offset = 20h
TA2, address = 0020h
Write 8 bytes of data to scratchpad
Read CRC to check for data integrity
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Read Scratchpad” command
Read TA1, beginning offset = 20h
Read TA2, address = 0020h
Read E/S, ending offset = 111b, AA, PF = 0
Read scratchpad data and verify
Read CRC to check for data integrity
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Copy Scratchpad” command
TA1
(AUTHORIZATION CODE)
TA2
E/S
Wait t PROGMAX for the copy function to complete
Read copy status, AAh = success
Reset pulse
Presence pulse
Issue “Skip ROM” command
Issue “Read Memory” command
TA1, beginning offset = 00h
TA2, address = 0000h
Read the entire memory
Reset pulse
Presence pulse
______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
SIDE VIEW
FRONT VIEW
GND
1
1
IO
2
2
N.C.
3
3
FRONT VIEW (T&R VERSION)
TO-92
1
2
3
TOP VIEW
TOP VIEW
TOP VIEW
DS2431
N.C.
N.C.
A1
A2
A3
+
GND
1
IO
2
N.C.
3
6 N.C.
DS2431
5
N.C.
4
N.C.
+
N.C.
1
IO
2
GND
3
2431
ymrrF
GND
6
N.C.
5
N.C.
4
N.C.
DS2431
TSOC
C1
C2
C3
IO
N.C.
N.C.
*EP
UCSPR
TDFN
(3mm × 3mm)
*EXPOSED PAD
BOTTOM VIEW
BOTTOM VIEW
1
2
GND
2
IO
1
DS2431GA
DS2431G
IO
GND
SFN
(6mm × 6mm × 0.9mm)
SFN
(3.5mm × 6.5mm × 0.75mm)
NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR
MORE INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE.
______________________________________________________________________________________
23
DS2431
Pin Configurations
1024-Bit, 1-Wire EEPROM
DS2431
SFN Package Orientation on Tape and Reel
USER DIRECTION OF FEED
LEADS FACE UP IN ORIENTATION SHOWN ABOVE.
SFN
(6mm × 6mm × 0.9mm)
USER DIRECTION OF FEED
LEADS FACE UP IN ORIENTATION SHOWN ABOVE.
SFN
(3.5mm × 6.5mm × 0.75mm)
24
______________________________________________________________________________________
1024-Bit, 1-Wire EEPROM
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
3 TO-92 (Bulk)
Q3+1
21-0248
—
3 TO-92 (T&R)
Q3+4
21-0250
—
6 TSOC
D6+1
21-0382
90-0321
2 SFN (6mm x 6mm)
G266N+1
21-0390
—
2 SFN (3.5mm x 6.5mm)
T23A6N+1
21-0575
—
6 TDFN-EP
T633+2
21-0137
90-0058
6 UCSPR
BR622+1
21-0376
Refer to
Application Note 1891
______________________________________________________________________________________
25
DS2431
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
DS2431
1024-Bit, 1-Wire EEPROM
Revision History
REVISION
NUMBER
REVISION
DATE
0
050704
1
081604
DESCRIPTION
Initial release
1
In the Electrical Characteristics table, changed VTL(MIN) from 0.5V to 0.46V and
VTL(MAX) from 4.1V to 4.4V; changed VHY(MIN) from 0.22V to 0.21V
2
In the Copy Scratchpad [55h] section, corrected the copy time from 13ms to 12.5ms
090506
4
26
122106
102207
14
1, 24
In the Pin Configuration, added a note to the CSP package outline “*See package
reliability report for important guidelines on qualified usage conditions.”
1
In the Electrical Characteristics table, changed the t PROG (programming time) EC
table parameter from 12.5ms to 10ms for version A2 (see also pages 1, 13).
Removed tFPD and updated tPDH, tMSP, tW0L accordingly. Changed IPROG max to
0.8mA to match GBD
1, 2, 3, 13
Updated Memory Function Example table
3
——
Replaced Pin Configuration
Added the SFN package and updated the Ordering Information table
2
PAGES
CHANGED
23
Added CSP package outline drawing number to Pin Configuration
1
Changed VTL(MIN) from 0.46V to 0.5V in the Electrical Characteristics table
2
In the Absolute Maximum Ratings, changed storage temp to -55°C to +125°C; in the
Electrical Characteristics table, changed VTH, VTL based on VPUP and data retention
to 40 years min at 85°C; added note to retention spec: “EEPROM writes can become
nonfunctional after the data-retention time is exceeded. Long-term storage at
elevated temperatures is not recommended; the device can lose its write capability
after 10 years at +125°C or 40 years at +85°C.”
1, 2, 3
In the Ordering Information table, removed all leaded part numbers and added the
TDFN-EP package
1, 24
In the Electrical Characteristics table, changed the VIL(MAX) spec from 0.3V to 0.5V;
removed from the tW1L(MAX) spec; added Note 17 to tW0L spec; updated EC table
Notes 17 and 18; corrected Note 20
2, 3
Added EP function to the Pin Description table
3
Added to Figure 11 Write-Zero Time Slot
19
In the Pin Configuration, added the package drawing information/weblink and a note
that the SFN package is qualified for electro-mechanical contact applications only,
not for soldering. Added the SFN Package Orientation on Tape-and-Reel section. In
the Ordering Information, added note to contact factory for availability of the UCSPR
package. Added note that TO-92 T&R leads are formed to approximately 100-mil
spacing
24
In the SFN Pin Configuration, added reference to Application Note 4132
24
5
032008
Added Package Information table
25
6
8/08
Created newer template-style data sheet
All
7
6/09
Deleted “contact factory” note in Ordering Information; updated Pin Description and
Pin Configurations to reflect changes in pin assignment of UCSPR package
8
10/09
Corrected part number in Ordering Information table
1
9
12/10
Deleted the automotive version reference in the Features section
1
10
3/11
Added the automotive version reference to the Features section
1
______________________________________________________________________________________
1, 5, 23
1024-Bit, 1-Wire EEPROM
REVISION
NUMBER
REVISION
DATE
11
1/12
Updated Note 1 in the Electrical Characteristics section; specified the data memory
default status and added a note that the memory must be programmed to FFh for the
EPROM mode to function to the Memory Access section
12
2/12
Added the 3.5mm x 6.5mm SFN package information to the Ordering Information
table, Pin Configurations, and Package Information table
13
3/12
Revised the Electrical Characteristics table Notes 4 and 15
DESCRIPTION
PAGES
CHANGED
3, 7, 8
1, 23, 24, 25
3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
DS2431
Revision History (continued)

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