ETC IRS2500S

October 17, 2011
IRS2500S
TRANSITION MODE PFC CONTROL IC
Features
•
•
•
•
•
•
•
•
•
•
•
•
PFC Control IC
Boost or Flyback Converter Modes
Critical-conduction / Transition mode
operation
Over-current protection
Static and Dynamic DC bus overvoltage
protection
Micropower startup (<50μA)
Low quiescent current (2.5mA)
Latch immunity and ESD protection
Wide range PFC for universal AC line input
Low THD
Open load Over voltage protection
Noise immunity
Typical Applications
•
•
•
Product Summary
Topology
Boost / Flyback
Io+ & I o- (typical)
500 / 500mA
tON & tOFF (typical)
60 / 30nS
Packages
8-LeadSOIC
Switched Mode Power Supplies
Electronic Ballasts
LED Drivers
Typical Connection Diagram
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© 2011 International Rectifier
IRS2500S
Table of Contents
Page
Description
3
Qualification Information
5
Absolute Maximum Ratings
6
Recommended Operating Conditions
6
Electrical Characteristics
7
Functional Block Diagram
9
Input/Output Pin Equivalent Circuit Diagram
10
Lead Definitions
11
Lead Assignments
11
Application Information and Additional Details
12
Package Details
18
Tape and Reel Details
19
Part Marking Information
20
Ordering Information
21
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© 2011 International Rectifier
2
IRS2500S
Description
The IRS2500 is a fully integrated, fully protected PFC SMPS control IC designed to drive Boost or Flyback
switching regulators providing high power factor. Typical applications are PFC pre-regulators for SMPS and
electronic ballasts for fluorescent or HID lighting as well as single stage Flyback converters widely used in
low power LED drivers. The IRS2500 is pin compatible with most industry standard critical counduction or
transition mode PFC control IC with additional improvements to increase performance. The PFC circuitry
provides high PF, low THD and stable DC bus regulation over a wide line/load range. The IRS2500
protection features include cycle by cycle over-current protection and output over voltage protection.
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3
IRS2500S
Typical Application Diagram
DBUS
DIN
RPU
RSH
RS
DVCC
IC2
VREG
T1
OUT+
+5V
CVCC
RIN
RV1
RZX
CIN
RFB1
INV
1
COMP
CCOMP
AC
Line
Input
CVREG
IC1
VDC
OC
2
3
4
8
IRS2500
BR1
7
6
5
VCC
CVOUT
OUT
RD1
COM
ZX
RPFC
RPD
IC3A
RFB2
RD2
RVFB
CVFB
MPFC
CF
RDC
OUTRV2
RF
RII
IC3B
ROC
RI
CF
RD3
RIFB
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CIFB
© 2011 International Rectifier
4
IRS2500S
†
Qualification Information
Qualification Level
Moisture Sensitivity Level
Machine Model
ESD
IC Latch-Up Test
RoHS Compliant
Human Body Model
Industrial††
Comments: This family of ICs has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by
extension of the higher Industrial level.
MSL2††† 260°C
(per IPC/JEDEC J-STD-020)
Class B
(per JEDEC standard JESD22-A115)
Class 2
(per EIA/JEDEC standard EIA/JESD22-A114)
Class I, Level A
(per JESD78)
Yes
†
††
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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© 2011 International Rectifier
5
IRS2500S
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead.
The thermal resistance and power dissipation ratings are measured under board mounted and still air
conditions.
Symbol
VOUT
Definition
Gate Driver Output Voltage
IOMAX
Maximum allowable output current (OUT) due to external
power transistor miller effect
ICC
VCOMP
VOC
VVBUS
VZX
ICOMP
Min.
Max.
Unit
s
-0.3
VCC + 0.3
V
-500
500
mA
0
25
mA
-0.3
VCC + 0.3
VCC current
COMP Pin Voltage
OC Pin Voltage
V
VBUS Pin Voltage
ZX Pin Voltage
-0.3
7.0
-5
5
mA
COMP Pin Current
IZX
ZX Pin Current
IOC
OC Pin Current
PD
Package Power Dissipation @ TA ≤ +25ºC
---
0.625
W
Thermal Resistance, Junction to Ambient
---
128
ºC/W
TJ
Junction Temperature
-55
150
TS
Storage Temperature
-55
150
TL
Lead Temperature (soldering, 10 seconds)
---
300
RθJA
ºC
Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal
breakdown voltage of 25V. This supply pin should not be driven by a DC, low impedance power source
greater than the VCLAMP specified in the Electrical Characteristics section.
Recommended Operating Conditions
For proper operation the device should be used within recommended conditions.
Definition
Symbol
††:
VCC
Supply Voltage
ICC
VCC Supply Current
IOC
OC Pin Current
IZX
ZX Pin Current
TJ
Junction Temperature
Min.
Max.
Units
VCCUV+
VCLAMP
V
Note 2
10
-1
1
-25
125
mA
ºC
This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 25V. This
supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical
Characteristics section.
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© 2011 International Rectifier
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IRS2500S
Electrical Characteristics
VCC = 14 V +/- 0.25 V, COUT=1000 pF, CVCC=0.1 μF, TA=25 °C unless otherwise specified.
Symbol
Supply Characteristics
Definition
Min
Typ
Max
11.5
12.5
13.5
9.5
10.5
11.5
1.5
2.0
3.0
Units
Test Conditions
VUVHYS
VCC Supply Undervoltage Positive Going
Threshold
VCC Supply Undervoltage Negative Going
Threshold
VCC Supply Undervoltage Lockout
Hysteresis
IQCCUV
UVLO Mode VCC Quiescent Current
---
30
---
uA
VCC Supply Current
---
2.3
5.0
mA
VCC Zener Clamp Voltage
---
20.0
---
V
---
10
---
---
-23
---
---
6.0
---
---
0.25
---
---
0
---
Input bias current
---
---
-1
uA
VBUS=0 to 3V
Voltage gain
60
80
---
dB
Open loop
---
1
---
MHz
2.46
2.5
2.54
VCCUV+
VCCUV-
ICC
VCLAMP
VCC = 8V
VBUS=2.5V
PFC off time =
5us
ICC = 10mA
Error Amplifier Characteristics
ICOMP
SOURCE
ICOMP
SINK
COMP Pin Error Amplifier Output Current
Sourcing
COMP Pin Error Amplifier Output Current
Sinking
Error Amplifier Output Voltage Swing (high
VCOMPOH
state)
Error Amplifier Output Voltage Swing (low
VCOMPOL
state)
VCOMPFL Error Amplifier Output Voltage in Fault
T
Mode
IVBUS
Gv
GB
mA
V
VVBUS = 2.4V
VCOMP=4.0V
VVBUS = 2.6V
VCOMP=4.0V
VBUS=2.0V
ICOMP=-0.5mA
VBUS=3.0V
ICOMP=+0.5mA
VBUS=3.0V
Control Characteristics
VVBUS
VBUS Internal Reference Voltage
V
VCOMP = 4.0V
---
V
320
---
ns
---
400
---
us
PFC Minimum ON time
---
0.3
---
us
PFC Maximum ON Time
10
50
---
us
IZX = 1mA
VBUS=2.5V
VCOMP=4.0V
ZX = 0,VCOMP =
4.0V
ZX = 0,VCOMP =
0.25V
ZX = 0,VCOMP =
6.0V,
VDC = 2V
VZX+
ZX Pin Threshold Voltage (Arm)
---
1.6
---
VZX-
ZX Pin Threshold Voltage (Trigger)
---
0.7
---
---
5.2
OC pin current-sensing blank time
---
PFC Watch-dog Pulse Interval
tONMIN
tONMAX
VZXclamp ZX pin Clamp Voltage (high state)
tBLANK
tWD
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© 2011 International Rectifier
7
IRS2500S
Electrical Characteristics (cont’d)
VCC = 14V +/- 0.25V, COUT = 1000pF,
VCOMP = VOC = VBUS = VZX = 0V, TA=25C unless otherwise specified.
Protection Circuitry Characteristics
VOCTH
VVBUSOV
VVBUSOV
HYS
ICOMPOV+
ICOMPOV-
OC Pin Over-current Sense Threshold
VBUS Over-voltage Comparator
Threshold
VBUS Over-voltage Comparator
Hysteresis
Dynamic Over-voltage detection
threshold
0.93
1.1
1.22
V
2.7
50
100
150
30
Dynamic Over-voltage detection reset
mV
Guaranteed by
design
Guaranteed by
design
uA
8
Gate Driver Output Characteristics
VOL
Low-Level Output Voltage
---
0
100
mV
IO = 0
VOH
High-Level Output Voltage
---
0
11
V
IO = 0
tr
Turn-On Rise Time
---
60
110
tf
Turn-Off Fall Time
---
30
70
I0+
Source Current
---
500
---
I0-
Sink Current
---
500
---
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nsec
mA
© 2011 International Rectifier
8
IRS2500S
Functional Block Diagram
VCC
OC 4
VOCTH
COM
6
8
200 ns
Blank Time
UVLO
VBUS 1
VCLAMP
OVP
VVBUS
VCC
VVBUSOV
7
COMP 2
VDC
ON TIME
MODULATOR
3
S
S
Q
R
Q
Q
OUT
300us
Watchdog
Timer
R1
R2 Q
ZX 5
VZXCLAMP
VZX
Note: Values in block diagram are typical values
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9
IRS2500S
Input/Output Pin Equivalent Circuit Diagrams
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10
IRS2500S
Lead Definitions
Symbol
VBUS
COMP
VDC
OC
ZX
COM
OUT
VCC
Description
DC Bus Sensing Input
PFC Error Amplifier Compensation
Full Wave Voltage Input
PFC Current Sensing Input
PFC Zero-Crossing Detection
IC Power & Signal Ground
Gate Drive Output
Logic & Low-Side Gate Driver Supply
VBUS
COMP
VDC
OC
1
2
3
4
IRS2500
Lead Assignments
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8
7
6
5
VCC
OUT
COM
ZX
© 2011 International Rectifier
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IRS2500S
When the switch MPFC is turned on, the inductor
LPFC is connected between the rectified line input
(+) and (-) causing the current in LPFC to increase
linearly. When MPFC is turned off, LPFC is
connected between the rectified line input (+) and
the DC bus capacitor CBUS through diode DPFC.
The stored energy in LPFC is transferred to the
output, supplying a current into CBUS. MPFC is
turned on and off at a high frequency and the
voltage on CBUS charges up to a specified voltage.
The voltage feedback loop of the IRS2500
regulates the output to the desired voltage by
continuously monitoring the DC output and
adjusting the on-time of MPFC accordingly. If the
output voltage is too high the on-time is decreased
and if it is too low the on-time is increased. This
negative feedback control loop operates with a slow
loop speed and a low loop gain such that the
average inductor current smoothly follows the lowfrequency line input voltage to obtain high power
factor and low THD.
The loop speed is intentionally slow with repect to
the AC line frequency so that there is no
appreciable change in the on time during a single
line half cycle. This allows the current to follow
shape of the sinusoidal voltage.
Application Information and Additional
Details
Power factor correction is required in many
electrical appliances in order to minimize reactive
current losses in AC power transmission lines. The
degree to which an electronic circuit matches an
ideal purely resistive load is measured by the phase
shift (displacement) between the input voltage and
input current and the amount of current waveform
distortion. In other words how well the shape of the
input current waveform matches the shape of the
sinusoidal input voltage.
The power factor (PF) is defined as the ratio
between real power and apparent power with the
maximum value of 1.0 representing a totally
resistive load where the current waveform shape
matches the voltage waveform shape exactly. The
distortion of the input current waveform is quantified
by the total harmonic distortion (THD), which is the
sum of all harmonic content of the waveform
expressed as a percentage.
An ideal power factor of 1.0 corresponds to zero
phase shift and a THD of 0% representing a purely
sinusoidal input current waveform in phase with the
line voltage. The lower the power factor the more
current is needed to supply the same power to the
load, which results is higher conduction losses in
transmission lines. For this reason it is desirable to
have a high PF and a low THD. To achieve this the
IRS2500 implements an active power factor
correction (PFC) circuit.
The control method implemented in the IRS2500
may be used in a Boost converter (Figure 8) or a
low poer single stage Flyback converter for small
power supplies or LED drivers. The IRS2500
operates in critical-conduction mode (CCM), also
known as transition mode. This means that during
each switching cycle of the PFC MOSFET, the
circuit waits until the inductor current discharges to
zero before turning the PFC MOSFET on again.
The PFC MOSFET is turned on and off at a much
higher frequency (>10KHz) than the line input
frequency (50 to 60Hz).
LPFC
(+)
DPFC
V, I
t
Figure 9: Sinusoidal line input voltage (solid line),
triangular PFC Inductor current and smoothed
sinusoidal line input current (dashed line) over one
half-cycle of the AC line input voltage.
Corrections to the output voltage therefore require
several line cycles. With a fixed on-time, and an offtime determined by the inductor current discharging
to zero, the result is a system where the switching
frequency is free-running and constantly changing
from a high frequency near the zero crossing of the
AC input line voltage, to a lower frequency at the
peaks (Figure 9).
When the line input voltage is low (near the zero
crossing), the inductor current will increase only a
small amount and the discharge time will be short
resulting in a high switching frequency. When the
input line voltage is high (near the peak), the
inductor current will charge up to a much higher
DC Bus
+
MPFC
CBUS
(-)
Figure 8: Boost converter circuit.
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© 2011 International Rectifier
12
IRS2500S
level and the discharge time will be longer giving a
lower switching frequency.
The PFC control circuit of the IRS2500 (Figure
10) includes six control pins: VBUS, COMP, ZX,
OUT, VDC and OC. The VBUS pin measures the
DC bus voltage through an external resistor voltage
divider. The COMP pin voltage determines the ontime of MPFC and sets the feedback loop response
speed with an external RC integrator. The ZX pin
detects when the inductor current discharges to
zero each switching cycle using a secondary
winding from the PFC inductor. The OUT pin is the
low-side gate driver output for the external
MOSFET, MPFC. The VDC pin senses the line
input cycle providing phase information to control
the on time modulation described in the next
section. The OC pin senses the current flowing
through MPFC and performs cycle-by-cycle overcurrent protection.
VBUS 1
VCC
2.75
5.1V
RZX
CBUS
MPFC
OC
COM
ROC
RVBUS
RDC
(-)
Figure 10:
RS4
2.0V
The off-time of MPFC is determined by the time it
takes the LPFC current to discharge to zero. The
zero current level is detected by a secondary
winding on LPFC that is connected to the ZX pin
through an external current limiting resistor RZX. A
positive-going edge exceeding the internal
threshold VZX+ signals the beginning of the offtime. A negative-going edge on the ZX pin falling
below VZX- will occur when the LPFC current
discharges to zero, which signals the end of the offtime and MPFC is turned on again (Figure 12). The
ZX pin is internally biased to ensure that the voltage
detected from the inductor drops fully to zero before
triggering the next PWM cycle. A wide hysteresis
prevents false triggering by ringing oscillations.
The cycle repeats itself indefinitely until the
IRS2500 is disabled through an over-voltage
condition on the DC bus or if the negative transition
of ZX pin voltage does not occur. Should the
negative edge on the ZX pin not occur, MPFC will
remain off until the watch-dog timer forces a turn-on
of MPFC for an on-time duration programmed by
the voltage on the COMP pin. The watch-dog
pulses occur every 300-400us (tW) indefinitely until
a correct positive and negative-going signal is
detected at the ZX pin and normal operation is
resumed. Should the OC pin voltage exceed the
VOCTH over-current threshold during the on-time
the gate drive output will turn off. The circuit will
then wait for a negative-going transition on the ZX
pin or a forced turn-on from the watch-dog timer to
turn the output on again.
ZX
COMP
OC
1.2V
Figure 11: IRS2500 detailed PFC control circuit.
RVBUS2
RPFC
4
WATCH
DOG
TIMER
M2
COMP3
ZX 5
RIN
OUT
OUT
R Q
S Q
R1
R2 Q
RVBUS1
PFC
Control
7
Q
On Time
Modulator
C1
DFPC
VDC
S
M1
VDC 3
LPFC
CCOMP
RS3
COMP5
COMP 2
(+)
VBUS
COMP4
2.5V
IRS2500 simplified PFC control
circuit.
The VBUS pin is compared with a fixed internal
2.5V reference voltage for regulating the DC output
voltage (Figure 11). The feedback loop error
amplifier increases or decreases the COMP pin
voltage. The resulting voltage on the COMP pin
sets the threshold for the charging of the internal
timing capacitor (C1, Figure 11) and therefore
determines the on-time of MPFC.
The error amplifier operates at a slow loop speed
preventing rapid changes in PWM duty cycle during
a single input line cycle. This prevents distortion
achieving high power factor and low THD.
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13
IRS2500S
ILPFC
ILPFC
...
OUT
0
...
OUT
pin
0
ZX
near peak region of
rectified AC line
...
VOCTH
OC
near zero-crossing region
of rectified AC line
Figure 13: On-time modulation circuit timing
diagram.
...
Output Over-voltage Protection
The IRS2500 incorporates both static and dynamic
overvoltage protection. Static over voltage
protection monitors the feedback voltage at the
VBUS pin and disables the gate drive output if this
voltage exceeds the target voltage by 8%. This is
activated by an internal comparator set to detect a
threshold of 2.7V, which is 8% above the regulation
threshold of 2.5V.
However, under startup condition or when a load is
removed from the output the error amplifier output
voltage at the COMP pin swings low. Since the
compensation capacitor CCOMP is connected from
this output back to the VBUS input a current will
flow during the COMP voltage transition. This pulls
down the VBUS voltage, which allows the output
voltage to exceed the desired regulation level
during the transition and results in an overshoot
before the voltage at the VBUS input exceeds the
regulation threshold.
In order to compensate for this effect, the IRS2500
includes dynamic detection of the error amplifier
output current. During a swing in the negative
direction the error amplifier output current peaks at
a much high level than the level during steady state
operation. This higher current is internally detected
and triggers the overvoltage protection circuitry
disabling the PWM output until the error amplifier
output has settled to a new level. This prevents the
output voltage from overshooting the desired level
by a significant amount under the transient
conditions described. For this reason the loop
should be designed such that voltage ripple at
COMP is minimized during steady state operation.
Figure 12: Inductor current, OUT pin, ZX pin and
OC pin timing diagram.
On-time Modulation Circuit
A fixed on-time of MPFC over an entire cycle of the
line input voltage produces a peak inductor current
which naturally follows the sinusoidal shape of the
line input voltage. The smoothed, averaged line
input current is in phase with the line input voltage
for high power factor but a high total harmonic
distortion (THD), as well as individual higher
harmonics, of the current are still possible. This is
mostly due to cross-over distortion of the line
current near the zero-crossings of the line input
voltage. To achieve low harmonics that are
acceptable for compliance with international
standards and general market requirements, an
additional on-time modulation circuit has been
added to the PFC control. This circuit dynamically
increases the on-time of MPFC as the line input
voltage nears the zero-crossings (Figure 13). This
causes the peak LPFC current, and therefore the
smoothed line input current, to increase near the
zero-crossings of the line input voltage. This
reduces the amount of cross-over distortion in the
line input current which reduces the THD and
higher harmonics.
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© 2011 International Rectifier
14
IRS2500S
PFC Design Equations (for Boost Converter)
Step1: Calculate PFC inductor value:
LPFC =
2
(VBUS − 2 ⋅ VACMIN ) ⋅VAC MIN
⋅η
2 ⋅ f MIN ⋅ POUT ⋅VBUS
[Henries]
(1)
where,
VBUS
VAC MIN
η
f MIN
POUT
=
=
=
=
=
DC bus voltage
Minimum rms AC input voltage
PFC efficiency (typically 0.95)
Minimum PFC switching frequency at minimum AC input voltage
Ballast output power
Step 2: Calculate peak PFC inductor current:
i PK =
2 ⋅ 2 ⋅ POUT
VAC MIN ⋅η
[Amps Peak]
(2)
Note: The PFC inductor must not saturate at i PK over the specified ballast operating temperature range. Proper core sizing
and air-gapping should be considered in the inductor design.
Step 3: Calculate PFC over-current resistor ROC value:
ROC =
VOCTH
i PK
[Ohms]
where VOCTH = 1.1V
(3)
Step 4: Calculate start-up resistor RVCC value:
RVCC =
VAC MIN
+ 10
PK
[Ohms]
IQCCUV
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(4)
© 2011 International Rectifier
15
IRS2500S
14
2.5
VCCUV+
12
2
VCCUV‐
ICC ( mA)
VCCUV (+/‐)
10
8
6
4
1.5
1
0.5
2
0
0
‐25
‐25
0
25
50
75
100
0
25
50
75
100
125
125
TEMP C
TEMP C
Graph 2: ICC vs. Temperature
Graph 1: VCCUV+ vs. Temperature
22
120
21.8
21.6
100
VCLAMP (V)
IQCCUV (uA)
21.4
80
60
40
21.2
21
20.8
20.6
20.4
20
20.2
0
20
‐25
0
25
50
75
100
125
‐25
0
25
50
75
100
125
TEMP C
TEMP C
Graph 4: VCLAMP vs. Temperature
Graph 3: IQCCUV vs. Temperature
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© 2011 International Rectifier
16
IRS2500S
500
450
WATCH DOG INTERVAL (us)
3
2.9
2.8
VBUS (V)
2.7
2.6
2.5
2.4
2.3
2.2
2.1
400
350
300
250
200
150
100
50
2
0
‐25
0
25
50
75
100
125
‐25
0
25
50
75
100
125
TEMP C
TEMP C
Graph 6: Watch dog interval vs. Temperature
Graph 5: VBUS reference vs. Temperature
50
49
PFC Ton max (US)
48
47
46
45
44
43
42
41
40
‐25
0
25
50
75
100
125
TEMP C
Graph 7: PFC Ton max (us)
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© 2011 International Rectifier
17
IRS2500S
Package Details
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18
IRS2500S
Tape and Reel Details
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
7.90
8.10
B
3.90
4.10
C
11.70
12.30
D
5.45
5.55
E
6.30
6.50
F
5.10
5.30
G
1.50
n/a
H
1.50
1.60
8SOICN
Imperial
Min
Max
0.311
0.318
0.153
0.161
0.46
0.484
0.214
0.218
0.248
0.255
0.200
0.208
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
18.40
G
14.50
17.10
H
12.40
14.40
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Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
0.724
0.570
0.673
0.488
0.566
© 2011 International Rectifier
19
IRS2500S
Part Marking Information
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© 2011 International Rectifier
20
IRS2500S
Ordering Information
Standard Pack
Base Part Number
Package Type
Complete Part Number
Form
IRS2500
SOIC8
Quantity
Tube/Bulk
95
IRS2500SPBF
Tape and Reel
2500
IRS2500STRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no
responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement
of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or
otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to
change without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
www.irf.com
© 2011 International Rectifier
21
Application Note AN-1173
Power Factor Correction using the IRS2500
By Peter B. Green
Table of Contents
Page
1. Introduction ......................................................................................2
2. Power Factor and THD.....................................................................3
3. PFC Boost Pre-regulator ..................................................................5
4. Design Equations .............................................................................11
5. Factors affecting PF and THD..........................................................12
6. PCB Layout Considerations .............................................................14
7. Example Schematic .........................................................................15
8. Bill of Materials.................................................................................16
9. Test Results .....................................................................................17
10. Replacing Alternative Controllers ...................................................19
Safety Warning!
The IRS2500 based power factor correction pre-regulator is based on a non-isolated Boost
SMPS circuit topology. The output typically ranges from 400 to 500VDC. When operating the
output produces potentially dangerous voltages!The IRS2500 and associated circuitry should be
handled by qualified electrical engineers only!
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AN-1173
1
IRS2500 PFC Pre-regulator
1. Introduction
Many offline applications require power factor correction circuitry in order to
minimize transmission line losses and stress on electrical generators and
transformers created by high harmonic content and phase shift. Appliances often
incorporate switching power supplies (SMPS) which include capacitive filter
circuitry followed by a bridge rectifier and bulk capacitor supplying a load.
Without power factor correction circuitry a SMPS draws a high peak current close
to the line voltage peak and almost no current over much of the cycle, resulting in
a power factor of around 0.5 and a high total harmonic distortion.
Power factor correction circuitry is added which enables the appliance to draw a
sinusoidal current from the AC line with negligible phase shift and very low
harmonic distortion. This allows optimization of the load seen by the power grid
such that power can be supplied without creating additional conductive losses in
transmission lines or additional burden on transformers and generators. Costs to
electricity providers are therefore reduced, which are hopefully passed on to the
consumer.
Although not explicitly specified in standards such as IEC 61000-3-2 relating to
power factor and line current harmonics, it is generally a requirement for the total
harmonic distortion (THD) of the line input current supplying a PFC pre-regulator
to be as low as possible. As is normally the case a tradeoff exists between cost
and performance where more expensive high end products rated at higher power
typically incorporate active power factor correction circuits, while low cost passive
circuits often suffice in cheaper consumer products.
This is a market trend in power supplies used in a variety of appliances as well
as electronic lighting ballasts for Fluorescent, high intensity discharge (HID)
lamps and LED lighting.
For a product incorporating active power factor correction a THD of less than
20% over a wide input voltage range, normally 100VAC to 305VAC is expected.
In many cases THD can be less than 10% over much or all of this voltage range.
Important Safety Information
The IRS2500 based PFCpre-regulator does not provide galvanic isolation of the
output from the line input. Therefore if the system is supplied directly from a
non-isolated input, an electrical shock hazard exists.The DC output voltage is
highenough to produce a potentially lethal electrical shock!
It is recommended that for laboratory evaluation that the IRS2500PFC board be
used with an isolated AC or DC input supply. The IRS2500 series Boost
topology is suitable only for front end applications where isolation is either not
necessary or provided elsewhere in the system.
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AN-1173
2
2. Power Factor and THD
THD is the RMS of harmonic distortion from all components of an AC signal
excluding the fundamental, expressed as a percentage of the RMS of the
fundamental. In other words it quantifies the amount by which the signal deviates
from a pure sinusoid.
∞
THD =
∑ An
n =2
A1
2
=
( ARMS − A1
2
A1
where, A1 is the RMS amplitude of the fundamental and ARMS is the total RMS
value of the complete signal.
It should be noted that THD is not directly related to power factor (PF) since
phase shift between current and voltage inputs are not factored into the THD
calculation. Power factor is defined as the ratio of the real power, which is utilized
by the load, to the apparent power which also includes energy stored in the load
and returned to the source as well as current harmonics created by non-resistive
loads. In an off line AC system real power is derived from the voltage and the
fundamental component of the current only as a function of the phase shift
between them. Distortion power is derived from all other harmonics of the
current.
It is therefore possible for a circuit to obtain a very low THD without a high power
factor if a phase shift exists. The European standard IEC 61000-3-2 class C
limits (applicable to lighting ballasts rated above 25W) specifies maximum
allowable levels for individual odd harmonics up to the 39th. A THD of less than
10% will normally provide compliance to these limits.
Figure 1. Power Vector Diagram
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AN-1173
3
A general formula for power factor is:
PF =
PRMS
V RMS ⋅ I RMS
where PRMS is the real power consumed by the load.
The displacement power factor is given the formula:
PF = COS(φ )
where Ф is the phase shift between the voltage and sinusoidal current.
The following formula gives the distortion power factor:
DF =
1
1 + THD 2
The following formula combines these to give the total power factor:
PF =
COS (φ1 )
1 + THD 2
where Ф1 refers to the phase shift between the voltage and the fundamental
component of the current and THD is expressed as a fraction.
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AN-1173
4
3. PFC Boost Pre-regulator
Figure 1 shows the schematic for a PFC pre-regulator based on a critical
conduction mode Boost circuit. The IRS2500 pinout conforms to most industry
standard power factor controllers and can be used as a drop in replacement for
alternative parts in many applications.
The Boost PFC pre-regulator circuit consists of an EMI filter followed by a bridge
rectifier which provides a full wave rectified voltage at the input to the Boost
inductor LPFC. CIN provides an essential path for the circulating high frequency
switching current. Both CF and CIN are critical to prevent excessive conducted
emissions back onto the AC line, however CF produces a phase leading
component of input current and CIN contributes to cross over distortion since it
never fully discharges at the line zero crossing.
In critical conduction mode (also known as transition or boundary mode) the
PWM gate drive signal to MPFC maintains a constant on time during the line
cycle apart except where additional on time is added near the zero crossing and
a variable off time. Each new cycle starts when the energy stored in LPFC has
been fully transferred to the output.
LPFC
DPFC
DC Bus (+)
RBUS1
RS
DVCC
IC1
RBUS2
VBUS
COMP
2
RDC2
VDC
3
LF
AC Line CF
Input
OC
CIN
4
CDC
8
IRS2500
CCOMP
RDC1
BR
VCC
1
OUT
7
6
COM
CVCC
CBUS +
LOAD
ZX
5
RZX
ROUT
MPFC
ROC1
COC
ROC
DC Bus (-)
Figure 2: PFC Pre-regulator Schematic
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AN-1173
5
The on and off times not taking into account the additional on time modulation
can be calculated by the following formulae:
L.IL ( pk )
2 .Vin ( rms )
L.IL ( pk ). sin θ
=
Vout − 2 .Vin ( rms ). sin θ
TON =
TOFF
A feedback loop regulates the output voltage by adjusting the PWM on time
gradually over many line cycles so that the input current follows the shape of the
input voltage and remains sinusoidal.
When the switch MPFC is turned on, the inductor LPFC is connected between
the rectified line input (+) and (-) causing the current in LPFC to increase linearly.
When MPFC is turned off, LPFC is connected between the rectified line input (+)
and the DC bus capacitor CBUS through diode DPFC. The stored energy in
LPFC is transferred to the output, supplying a current into CBUS. MPFC is
turned on and off at a high frequency and the voltage on CBUS charges up to a
specified voltage. The voltage feedback loop of the IRS2500 regulates the output
to the desired voltage by continuously monitoring the DC output and adjusting
the on-time of MPFC accordingly. If the output voltage is too high the on-time is
decreased and if it is too low the on-time is increased. This negative feedback
control loop operates with a slow loop speed and a low loop gain such that the
average inductor current smoothly follows the low-frequency line input voltage to
obtain high power factor and low THD.
The loop speed is intentionally slow with respect to the AC line frequency so that
there is no appreciable change in the on time during a single line half cycle. This
allows the current to follow shape of the sinusoidal voltage.
V, I
t
Figure 3: Sinusoidal line input voltage (solid line), triangular PFC Inductor
current and smoothed sinusoidal line input current (dashed line) over one halfcycle of the AC line input voltage.
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AN-1173
6
Corrections to the output voltage therefore require several line cycles. With a
fixed on-time, and an off-time determined by the inductor current discharging to
zero, the result is a system where the switching frequency is free-running and
constantly changing from a high frequency near the zero crossing of the AC input
line voltage, to a lower frequency at the peaks (Figure 3).
When the line input voltage is low (near the zero crossing), the inductor current
will increase only a small amount and the discharge time will be short resulting in
a high switching frequency. When the input line voltage is high (near the peak),
theinductor current will charge up to a much higher level and the discharge time
will be longer giving a lower switching frequency.
The PFC control circuit of the IRS2500 (Figure 4) includes six control pins:
VBUS, COMP, ZX, OUT, VDC and OC. The VBUS pin measures the DC bus
voltage through an external resistor voltage divider. The COMP pin voltage
determines the on-time of MPFC and sets the feedback loop response speed
with an external RC integrator. The ZX pin detects when the inductor current
discharges to zero each switching cycle using a secondary winding from the PFC
inductor. The OUT pin is the low-side gate driver output for the external
MOSFET, MPFC. The VDC pin senses the line input cycle providing phase
information to control the on time modulation described in the next section. The
OC pin senses the current flowing through MPFC and performs cycle-by-cycle
over-current protection.
Figure 4: IRS2500 simplified PFC control circuit.
The VBUS pin is compared with a fixed internal 2.5V reference voltage for
regulating the DC output voltage. The feedback loop error amplifier increases or
decreases the COMP pin voltage. The resulting voltage on the COMP pin sets
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AN-1173
7
the threshold for the charging of the internal timing capacitor shown in Figure 5
and therefore determines the on-time of MPFC.
The error amplifier operates at a slow loop speed preventing rapid changes in
PWM duty cycle during a single input line cycle. This prevents distortion
achieving high power factor and low THD.
VCC
OC 4
VOCTH
COM
6
8
200 ns
Blank Time
UVLO
VBUS 1
VCLAMP
OVP
VVBUS
VCC
VVBUSOV
7
COMP 2
VDC
ON TIME
MODULATOR
3
S
Q
R
Q
CT
S
Q
OUT
Watchdog
Timer
R1
R2 Q
ZX
5
VZXCLAMP
VZX
Figure 5: IRS2500 Internal Block Diagram.
The off-time of MPFC is determined by the time it takes the LPFC current to
discharge to zero. The zero current level is detected by a secondary winding on
LPFC that is connected to the ZX pin through an external current limiting resistor
RZX. This winding normally has close to a 1:10 turns ratio relative to the main
winding. A positive-going edge exceeding the internal threshold VZX+ signals the
beginning of the off-time. A negative-going edge on the ZX pin falling below VZXwill occur when the LPFC current discharges to zero, which signals the end of
the off-time and MPFC is turned on again (Figure 12). The ZX pin is internally
biased to ensure that the voltage detected from the inductor drops fully to zero
before triggering the next PWM cycle. A wide hysteresis prevents false triggering
by ringing oscillations. The ZX pin current should not exceed 0.5mA as excessive
current can cause incorrect triggering and possible damage to the IRS2500.
The cycle repeats itself indefinitely until the IRS2500 is disabled through an overvoltage condition on the DC bus or if the negative transition of ZX pin voltage
does not occur. Should the negative edge on the ZX pin not occur, MPFC will
remain off until the watch-dog timer forces a turn-on of MPFC for an on-time
duration programmed by the voltage on the COMP pin. The watch-dog pulses
occur every 300-400us (tW) indefinitely until a correct positive and negativegoing signal is detected at the ZX pin and normal operation is resumed. Should
the OC pin voltage exceed the VOCTH over-current threshold during the on-time
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AN-1173
8
the gate drive output will turn off. The circuit will then wait for a negative-going
transition on the ZX pin or a forced turn-on from the watch-dog timer to turn the
output on again.
ILPFC
...
OUT
...
ZX
...
VOCTH
OC
...
Figure 6: Inductor current, OUT pin, ZX pin and OC pin timing diagram.
A fixed on-time of MPFC over an entire cycle of the line input voltage produces a
peak inductor current which naturally follows the sinusoidal shape of the line
input voltage. The smoothed, averaged line input current is in phase with the line
input voltage for high power factor but a high total harmonic distortion (THD), as
well as individual higher harmonics of the current are still possible. This is mostly
due to cross-over distortion of the line current near the zero-crossings of the line
input voltage. To achieve low harmonics that are acceptable for compliance with
international standards and general market requirements, an additional on-time
modulation circuit has been added to the PFC control. This circuitdynamically
increases the on-time of MPFC as the line input voltage nears the zero-crossings
(Figure 7). This causes the peak LPFC current, and therefore the smoothed line
input current, to increase near the zero-crossings of the line input voltage. This
reduces the amount of cross-over distortion in the line input current which
reduces the THD and higher harmonics.
On time modulation is controlled by sensing the full wave rectified voltage at the
bridge rectifier output through a resistor divider (RDC1, RDC2). This is scaled
such that the peak voltage will be close to 1V at 120VAC and 3V at 265VAC.
This function can be disabled by connecting a resistor from pin 3 to VCC in place
of the input signal.
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AN-1173
9
ILPFC
0
OUT
pin
0
near peak region of
rectified AC line
near zero-crossing region
of rectified AC line
Figure 7: On-time modulation circuit timing diagram.
The IRS2500 incorporates both static and dynamic overvoltage protection. Static
over voltage protection monitors the feedback voltage at the VBUS pin and
disables the gate drive output if this voltage exceeds the target voltage by 8%.
This is activated by an internal comparator set to detect a threshold of 2.7V,
which is 8% above the regulation threshold of 2.5V.
However, under startup condition or when a load is removed from the output the
error amplifier output voltage at the COMP pin swings low. Since the
compensation capacitor CCOMP is connected from this output back to the VBUS
input a current will flow during the COMP voltage transition. This pulls down the
VBUS voltage, which allows the output voltage to exceed the desired regulation
level during the transition and results in an overshoot before the voltage at the
VBUS input exceeds the regulation threshold.
In order to compensate for this effect, the IRS2500 includes dynamic detection of
the error amplifier output current. During a swing in the negative direction the
error amplifier output current peaks at a much high level than the level during
steady state operation. This higher current is internally detected and triggers the
overvoltage protection circuitry disabling the PWM output until the error amplifier
output has settled to a new level. This prevents the output voltage from
overshooting the desired level by a significant amount under the transient
conditions described. For this reason the loop should be designed such that
voltage ripple at COMP is minimized during steady state operation.
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AN-1173
10
4. Design Equations
Step1: CalculatePFC inductor value:
LPFC =
2
(VBUS − 2 ⋅ VAC MIN ) ⋅ VAC MIN
⋅η
2 ⋅ f MIN ⋅ POUT ⋅ VBUS
[Henries]
where,
VBUS = DC bus voltage
VAC MIN = Minimum RMS AC input voltage
= PFC efficiency (typically 0.95)
η
f MIN
= Minimum PFC switching frequency at minimum AC input voltage
POUT
= Output power
Step 2: Calculate peak PFC inductor current:
iPK =
2 ⋅ 2 ⋅ POUT
VACMIN ⋅η
[Amps Peak]
Note: The PFC inductor must not saturate at i PK over the specified ballast
operating temperature range. Proper core sizing and air-gapping should
be considered in the inductor design.
Step 3: Calculate PFC over-current resistor ROC value:
ROC =
VOCTH
i PK
where VOCTH = 1.1V
[Ohms]
ROC power rating can be approximated:
2
PROC
⎛ POUT ⎞
⎟⎟ × ROC
≥ ⎜⎜
⎝ VAC MIN .η ⎠
[Watts]
Step 4: Calculate start-up resistor RVCC value:
RVCC <
VAC MIN
IQCCUV
PRVCC >
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[Ohms]
2
V ACMAX
RVCC
[Watts]
AN-1173
11
RVCC is often comprised of two series resistors (RBUS1A and RBUS1B)
in order to withstand the high voltage.
In this case choose RVCC1 and RVCC2 to be the next preferred value
down from RVCC/2 with power rating greater than PRVCC/2.
Step 5: Calculate VBUS feedback resistor divider network:
RBUS1 is often comprised of two series resistors (RBUS1A and RBUS1B)
in order to withstand the high voltage.
Select an initial value of 10K for RBUS2
RBUS1 = (VBUS − 2.5) ×
RBUS 1 A = RBUS 1B =
10000
2.5
[Ohms]
RBUS 1
2
[Ohms]
Choose the nearest preferred value for RBUS1A and RBUS1B.
Then re-calculate RBUS2:
RBUS 2 =
2.5 × ( RBUS 1 A + RBUS 1B )
VBUS − 2.5
[Ohms]
Then choose the nearest E96 1% tolerance value for RBUS2.
Step 6: Calculate VDC resistor divider network:
RDC1 is often comprised of two series resistors (RDC1A and RDC1B) in
order to withstand the high voltage.
Select an initial value of 10K for RDC2
R DC 1 = ( 2.V ACMIN − 1) × 10000
[Ohms]
Choose the nearest preferred value for RDC1A and RDC1B.
Then re-calculate RDC2:
RDC 2 =
RDC1 A + RDC1B
[Ohms]
2.V ACMIN − 1
Then choose the nearest E96 1% tolerance value for RDC2.
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AN-1173
12
Step 7: Calculate COMP capacitor:
CCOMP should be selected to roll off the gain of the error amplifier at
approximately 20Hz.
CCOMP =
1
2π × 20 Hz × RBUS 2
[Farads]
Choose the nearest preferred value for CCOMP.
Step 8: Calculate RZX resistor:
Choose Izx as 0.5mA and assume ZX winding maximum voltage VZX of
20V at the ZX winding as an approximation. If the actual VZX is higher
than 20V use the true value.
RZX ≤
VZX
I ZX
[Ohms]
Choose the next lowest preferred resistor value for RZX.
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AN-1173
13
5. Factors affecting PF and THD
The PFC pre-regulator circuit described above draws a current from the line input
which follows the shape of the voltage, however the following limitations exist:
1. Phase shift produced by CF.
The capacitance of CF draws current from the line input, which leads the voltage
by 90º. The magnitude of this reactive current is dependent on the size of CF and
the AC line input voltage. This is one reason why the power factor always drops
as line input voltage increases. For this reason CF should be kept as small as
possible while making sure the input filter is adequate for EMC compliance. This
does not produce distortion and affects only the power factor.
2. Phase shift produced by CIN.
CIN also causes some phase shift since the voltage across it is full wave
rectified.
This should also be kept to a minimum though it must be sufficient to provide a
high frequency AC current source for the switching regulator. This is also
essential for EMC compliance.
3. Cross over distortion produced by CIN.
CIN also contributes to cross over distortion while CF does not. The circuit can
be considered as a resistive load and therefore it is clear that as the AC line input
voltage passes through each zero crossing, CIN will need to discharge through
the load. Depending on the magnitude of CIN and the load the voltage on CIN
never discharges completely to zero at each zero crossing always maintaining a
residual voltage. This problem becomes worse in systems where the load is
variable such as a dimmable electronic lighting ballast. As the load is reduced the
residual voltage on CIN increases.
Since the voltage at CIN does not reach zero, when the AC line input voltage
drops below the minimum voltage at CIN there is no current drawn from the line
input, which results in the characteristic dead band shown on the input current
waveform in figure 7.
It should be noted that the bridge rectifier (BR) also contributes to the cross over
distortion to a small extent due to the forward voltage drop of two series diodes
that always appears between the AC line voltage and the rectified voltage,
therefore there will always be some cross over distortion no matter how small
CIN is.
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AN-1173
14
Power Factor = 0.99
THD < 10%
Traces:
Green – Line Input Voltage
Blue – Line Current
Figure 8: Line input and current in a typical PFC pre-regulator
4. Minimal energy transfer at the zero crossing.
At low line input voltage levels there may be insufficient energy stored in the
Boost inductor LPFC to provide enough voltage at the drain of MPFC to forward
bias the output diode DPFC. This is due to parasitic capacitances in the windings
of LPFC as well as the drain to source capacitance of the MOSFET switch. This
being the case it is necessary for the control IC to compensate for this by
increasing the MOSFET on time when the voltage approaches zero in order to
draw more current. Many PFC control ICs including the IRS2500 include circuitry
that gradually increases the on time when the input voltage is close to a zero
crossing. This functionality is referred to as on time modulation. The line input
voltage is generally detected through the divided input signal provided at pin 3. It
should be noted here that the residual voltage across CIN will be divided down
through RDC1 and RDC2 so that it also appears at pin 3, which prevents the IC
from detecting the input voltage below the level of the residual voltage. In order
to limit this problem, the IRS2500 must produce sufficient on time modulation to
discharge CIN as low as possible and introduce this before the residual voltage
level is reached.
5. Ripple at the error amplifier output (COMP)
The output bus voltage from the PFC pre-regulator circuit will always contain
some ripple at twice the line frequency, ∆VOUT superimposed on top of the
regulated DC output. The magnitude of ∆VOUT depends on the magnitude of the
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AN-1173
15
output storage capacitor CBUS. Since the output voltage is divided and fed back
to the inverting input of the error amplifier, a component of ripple will also be fed
to the input and compared with the internal 2.5V reference of the IRS2500. This
may result in a component of ripple appearing at the error amplifier output
(COMP) which determines the PWM on time. It is necessary for the
compensation capacitor CCOMP to be large enough to roll off the error amplifier
gain at a frequency well below twice the line frequency in order to eliminate this
ripple as much as possible. Ripple at the COMP output results in modulation of
the on time which causes distortion of the current waveform and should therefore
be eliminated as far as possible.
6. Delay before next switching cycle
In critical conduction mode an auxiliary wining on the Boost inductor provides a
signal to the ZX (zero crossing) pin of the controller. This indicates when all of
the energy from the inductor has been transferred to the output by transitioning
from high to low. When this transition is detected the PWM output drive goes
high to start the next cycle, however if there is delay then the converter is actually
operating in discontinuous mode due to the dead time. This can cause some
distortions in the current waveform.
6. PCB Layout Considerations
For correct operation the following guidelines should be followed:
1. CVCC must be as close to IC1 as possible with short direct traces.
2. The feedback path should be kept to a minimum length and separated as
much as possible from high frequency switching traces to minimize noise
at the VBUS input.
3. The current sense filter components ROC and COC should be located
close to the IRS2500 with short direct traces.
4. It is essential that all signal and power grounds should be kept separated
from each other to prevent noise from entering the control environment.
Signal and power grounds should be connected together at one point only,
which must be at the COM pin of the IRS2500. The IRS2500 may not
operate in a stable manner if these guidelines are not followed!
All components associated with the IR2500 should be connected to the IC
signal ground (COM) with the shortest path possible.
5. All traces carrying the load current need to be sized accordingly.
6. Gate drive traces should also be kept to a minimum length.
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AN-1173
16
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AC Line CF
Input
LF
BR
CIN
LPFC
DBP
MPFC
ROC
RDC1
DPFC
RDC2
AN-1173
ROUT
RZX
ROC1
DOUT
CDC
RDC3
RBUS3
OC
VDC
4
3
2
COMP
1
VBUS
COC
CCOMP
RBUS2
RBUS1
IC1
DVCC
5
6
7
8
ZX
COM
OUT
VCC
CVCC1
DZVCC
RVCC
CVCC2
Q1
RS2
RS1
+
+
DC Output (-)
CBUS2
CBUS1
DC Output (+)
7. Example Schematic
IRS2500
Figure 9: 80W PFC Schematic
17
8. Bill of Materials
Item
Description
Part #
Manufacturer
Qty
Reference
1
2
Diode, 75V, 150mA, MiniMELF
Diode, 1000V, 1A
DL4148
1N4007
Diodes Inc
Diodes Inc
2
1
DVCC, DOUT
DBP
3
20V, ZenerDiode, 500mW,
MiniMELF
ZMM5250B-7
Diodes Inc
1
DZVCC
4
5
6
7
Diode, 600V, 3A, 250nS, SMB
Bridge, 1000V, 1.5A, 4SDIP
MOSFET, 650V, 0.38 Ohm, TO220
NPN Transistor, SOT23, 40V
RS3JB-13-F
DF10S
SPP11N60C3
MMBT2222A-TP
1
1
1
1
DPFC
BR1
MPFC
Q1
8
IC, PFC Controller
IRS2500SPBF
Diodes Inc
Fairchild
Infineon
Micro Com
International
Rectifier
1
IC1
9
Inductor CM Line Filter,
250V,0.70A
ELF-15N007A
Panasonic
1
LF
10
Inductor, 520uH, 4.2Apk
SRW2620PQX22V102
TDK
1
LPFC
11
Capacitor, 0.10uF, 275VAC,
X2/Y2,TH,.591”
ECQ-U2A104ML
Panasonic
1
CF
12
Capacitor, 0.10uF, 400VDC, 0.295”
MKS4-.1/400/10 PCM
7.5
Wima
1
CIN
13
14
Capacitor, 100uF, 250V
Capacitor, 1.0uF, 25V,X7R, 1206
C3216X7R1E105K
TDK
2
1
CBUS1, CBUS2
CCOMP
15
Capacitor, 10nF, 1206
12061C103K4T2A
AVX
1
CDC
16
Capacitor, 1nF, 50V, 1206
12065C102KAT2A
AVX
1
COC
17
Capacitor, 10µF, 50V, 1210
GRM32DF51H106ZA
01L
Murata
1
CVCC1
18
Capacitor, 2.2uF, 25V, X7R, 1206
C3216X7R1E225K
TDK
1
CVCC2
19
Resistor, 0.33 Ohm, 0.5W, 2010
MCR50JZHFLR330
Rohm
1
ROC
20
Resistor, 470K, 5%, 1206
ERJ-8GEYJ474V
Panasonic
2
RDC1, RDC2
21
Resistor, 5.6K, 5%, 1206
ERJ-8GEYJ562V
Panasonic
1
RDC3
22
23
24
25
26
27
28
29
Resistor, 787K, 1%, 1206
Resistor, 9.1K, 1%, 1206
Resistor, 100K, 5%, 1206
Resistor, 18K, 5%, 1206
Resistor, 1.0K, 5%, 1206
Resistor, 3.3K, 5%, 1206
CONNECTOR, 2 POSITION
PCB
ERJ-8SENF7873V
ERJ-8ENF9101V
ERJ-8GEYJ104V
ERJ-8GEYJ183V
ERJ-8GEYJ102V
ERJ-8GEYJ332V
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
2
1
2
1
1
1
2
1
RBUS1, RBUS2
RBUS3
RS1, RS2
RZX
ROC1
RVCC
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9. Test Results
Figure 10: 80W ExampleWaveforms
AC Input Voltage
AC Current
VDC Pin Input
MPFC Gate Drive
: Yellow
: Green
: Blue
: Red
Results for power factor and THD were measured over the input voltage range
90VAC to 260VAC (see table 1). In order for the THD results to be accurately
measured an electronic AC source was used which produces a pure sinusoidal
voltage supply to the board under test. Without using an electronic AC source the
input voltage may be distorted as a result of auto-transformers and safety
isolating transformers combined with the effects of other loads connected to the
AC line. These effects can make THD results appear worse than they actually
are.
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VAC
VDCmax
VDCmin
P.F.
T.H.D.i
Vout
Pout
(W)
90
1
0
0.998
6.4%
440
83.5
100
1.2
0
0.998
5.5%
440
82.7
110
1.4
0
0.998
4.9%
440
82.1
120
1.6
0
0.999
4.4%
440
81.9
140
1.8
0
0.998
4.0%
440
80.9
160
2.0
0
0.998
4.4%
440
80.6
180
2.2
0
0.997
5.4%
440
80.6
200
2.4
0
0.995
6.8%
440
80.6
220
2.6
0
0.993
8.3%
440
80.6
240
2.8
0
0.99
9.8%
440
80.4
260
3
0
0.986
11.3%
440
80.4
Table 1: 80W Example PF and THD Results
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10. Replacing Alternative Controllers
Competitor
Part
Number
Manufacturer
IR Direct
Cross
L6561(A)
L6562(A)
MC33262
UCC28810
UCC28811
FAN7527B
STM
STM
On Semi
TI
TI
Fairchild
IRS2500
IRS2500
IR Close
Cross
IR Cross
Possible
IRS2500
IRS2500
IRS2500
IRS2500
Competitor
Package
SO8/DIP8
SO8/DIP8
SO8/DIP8
SO8/DIP8
SO8/DIP8
SO8/DIP8
IR Package
SO8
SO8
SO8
SO8
SO8
SO8
Table 2: Alternative controllers
The IRS2500 can be used as a direct drop in replacement for the controllers
listed in table 2 indicated as a direct cross. In the case of controllers listed as
close cross some minor modifications to the application circuit will be necessary
in order to replace the existing controller with the IRS2500.
Some controllers such as the MC33262 use a trans-conductance error amplifier
where the compensation capacitor is connected from the output to 0V instead of
back to the input as in the standard integrating configuration. When replacing this
part with the IRS2500 the compensation capacitor must be disconnected from 0V
and connected to pin 1.
IR WORLD HEADQUARTERS: 101 N. SepulvedaBlvd., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 8/17/2011
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