NCP1650 Power Factor Controller The NCP1650 is an active, power factor correction controller that can operate over a wide range of input voltages, and output power levels. It is designed to operate on 50/60 Hz power systems. This controller offers several different protection methods to assure safe, reliable operation under any conditions. The PWM is a fixed frequency, average current mode controller with a wide complement of features. These features allow for both flexibility as well as precision in it’s application to a circuit. Critical components of the internal circuitry are designed for high accuracy, which allows for precise power and current limiting, therefore minimizing the amount of overdesign necessary for the power stage components. The NCP1650 is designed with a true power limiting circuit that will maintain excellent power factor even in constant power mode. It also contains features that allow for fast transient response to changing load currents and line voltages. http://onsemi.com SO--16 D SUFFIX CASE 751B 16 1 MARKING DIAGRAM 16 Features Fixed Frequency Operation Average Current Mode PWM Continuous or Discontinuous Mode Operation Fast Line/Load Transient Compensation True Power Limiting Circuit High Accuracy Multipliers Undervoltage Lockout Overvoltage Limiting Comparator Brown Out Protection Ramp Compensation Does Not Affect Oscillator Accuracy Operation from 25 to 250 kHz This is a Pb--Free Device Typical Applications NCP1260G AWLYWW 1 A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb--Free Package PIN CONNECTIONS Vin 1 16 OUTPUT Vref 2 15 GND 14 CT AC COMP 3 AC REF 4 Server Power Converters Front End for Distributed Power Systems 13 RAMP COMP AC INPUT 5 12 IS-- FB/SD 6 11 Iavg--fltr LOOP COMP 7 10 Iavg PCOMP 8 9 Pmax (Top View) ORDERING INFORMATION Device NCP1650DR2G Package Shipping† SOIC--16 (Pb--Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2010 December, 2010 -- Rev. 12 1 Publication Order Number: NCP1650/D NCP1650 PIN FUNCTION DESCRIPTION Pin # Function 1 VCC Provides power to the device. This pin is monitored for undervoltage and the unit will not operate if the VCC voltage is not within the UVLO range. Description 2 Vref 6.5 V regulated reference output. This reference voltage is disabled when the chip is in the shutdown mode. 3 AC Compensation 4 AC REF This pin accommodates a capacitor to ground for filtering and stability of the AC error amplifier. The AC error amplifier is a transconductance amplifier and is terminated with an internal high impedance load. 5 AC Input The rectified input AC rectified sinewave is connected to this pin. This information is used for the reference comparator, maximum power circuit, and the average current compensation circuit. 6 Feedback/ Shutdown 7 Loop Compensation 8 PCOMP 9 PMAX 10 Iavg 11 Iavgfltr 12 IS-- 13 Ramp Compensation 14 CT 15 Ground Ground reference for the circuit. 16 Output Drive output for power FET or IGBT. Capable of driving small devices, or can be connected to an external driver for larger transistors. Provides pole for the AC Reference Amplifier. This amplifier compares the sum of the AC input voltage and the low frequency component of the input current to the reference signal. The response must be slow enough to filter out most of the high frequency content of the current signal that is injected from the current sense amplifier, but fast enough to cause minimal distortion to the line frequency information. The DC output of the converter is reduced through a resistive voltage divider, to a level of 4.0 V, and connected to this pin to provide feedback for the voltage regulation loop. This pin also provides an input undervoltage lockout feature by disabling the chip until the divided output voltage exceeds 0.75 V. It can also be used as a shutdown pin by shorting it to ground with an open collector comparator, or a small signal transistor. A compensation network for the voltage regulation loop, is connected to the output of the voltage error amplifier at this pin. A compensation network for the maximum power loop, is connected to the output of the power error amplifier at this pin. This pin allows the output of the power multiplier to be scaled for the desired maximum power limit level. This multiplier is a proprietary switching design and requires both a resistor and capacitor to ground. The value of this resistor is determined in conjunction with R10. An external resistor with a low temperature coefficient is connected from this terminal to ground, to set and stabilize the gain of the Current Sense Amplifier output that drives the Power Multiplier and the AC error amplifier. This resistor should be of the same type as that used on pin 9. The value of this resistor will determine the maximum average current that the unit will allow before limiting will occur. A capacitor connected to this pin filters the high frequency component from the instantaneous current waveform, to create a waveform that resembles the average line current. Negative current sense input. Designed to connect to the negative side of the current shunt. This pin biases the ramp compensation circuit, to adjust the amount of compensation that is added to the instantaneous current and AC error amp outputs. Timing capacitor for the internal oscillator. This capacitor adjusts the oscillator frequency. http://onsemi.com 2 NCP1650 MAXIMUM RATINGS (Maximum ratings are those that, if exceeded, may cause damage to the device. Electrical Characteristics are not guaranteed over this range.) Rating Power Supply Voltage (Operating) Output (Pin 16) Current Sense Inverting Input (Pin 12) Reference Voltage (Pin 2) Reference Filter (Pin 4) Symbol Value Unit VCC --0.3 to 20 V V(IS --) --0.5 to 1.0 V Vref --0.3 to 7.5 V Ref fltr --0.3 to 5.0 V --0.3 to 6.5 V All Other Inputs Thermal Resistance, Junction--to--Air 0.1 in2 Copper 0.5 in2 Copper θJA Thermal Resistance, Junction--to--Lead (Pin 1) (Note 1) θJL Maximum Power Dissipation @ TA = 25C C/W 130 110 50 C/W Pmax 0.77 W Operating Temperature Range TJ --40 to 125 C Non--operating Temperature Range TJ --55 to 150 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. θJL is equivalent to PsiJL ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 14 volts, CT = 470 pF, C2 = 0.1 mF, TJ = 25C for typical values. For min/max values TJ is the applicable junction temperature.) Symbol Min Typ Max Unit Frequency Fosc 90 100 110 kHz Max Duty Cycle dmax 0.95 0.97 -- -- Min Duty Cycle (Note 2) dmin -- 0 5.0 % Ramp Peak (Note 2) VRpeak -- 4.0 -- V Ramp Valley (Note 2) VRvalley -- 0.100 -- V Ramp Compensation Peak Voltage (Pin 13) (Note 2) -- -- 4.0 -- V Ramp Compensation Current (Pin 13) (Note 2) -- -- 400 -- mA Input Bias Current (Note 2) Ibias -- 0.2 0.6 mA Input Offset Voltage (Note 2) VIO -- 10 -- mV Characteristic OSCILLATOR VOLTAGE ERROR AMPLIFIER Transconductance (TJ = --40C to + 125C) gm 90 120 150 umho IOsource 10 20 -- mA IOsink --10 --20 -- mA Source Boost Current Threshold (Vpin6/Vref) Vfb(boost+) -- 1.06 -- V/V Sink Boost Current Threshold (Vpin6/Vref) Vfb(boost--) -- 0.920 -- V/V Output Source (Vref + 0.2 V) Output Sink (Vref -- 0.2 V) Boost Current (Vref = 4.0 volts nominal) Source Boost Current (Vref + 0.4 V) I(boost+) 150 230 -- mA Sink Boost Current (Vref -- 0.4 V) I(boost--) --150 --260 -- mA 2. Verified by design. http://onsemi.com 3 NCP1650 ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise noted: VCC = 14 volts, CT = 470 pF, C2 = 0.1 mF, TJ = 25C for typical values. For min/max values TJ is the applicable junction temperature.) Symbol Min Typ Max Unit Input Offset Voltage (Note 3) VIO -- 20 -- mV Transconductance gm 60 100 150 umho IOsource 10 20 -- mA IOsink --10 --20 -- mA Source Boost Current Threshold Vfb(boost+) -- 1.175 -- V/V Sink Boost Current Threshold Vfb(boost--) -- 0.825 -- V/V Source Boost Current (1.3 X Vref) I(boost+) 150 250 -- mA Sink Boost Current I(boost--) --150 --285 -- mA Input Offset Voltage (Note 3) VIO -- 20 -- mV Transconductance gm 60 100 150 umho IOsource 25 70 -- mA Output Sink (Pin 4 = 0 V, Pin 5 = 4 V) IOsink --25 --70 -- mA AC Inverting Input Clamp Voltage (250 mA) (TJ = 25C) Vclamp 4.30 4.45 4.60 V AC Inverting Input Clamp Voltage (250 mA) (TJ = --40C to +125C) Vclamp 3.70 -- 4.60 V AV -- 2.0 -- V/V Input Bias Current (Pin 11) Ibias --40 --50 --80 mA Differential Input Voltage Range (Note 3) VIdiff -- --0.20 -- V Input Offset Voltage VIO 0 2.5 5.0 mV Output Gain (150 mA/0.150 V) (Voltage Loop Outputs) (Note 3) Av -- 1000 -- umho Output Gain (150 mA/0.150 V) (Max Pwr Output) (R10 = 15 kΩ) (Note 3) Av -- 1000 -- umho funity -- 1.5 -- MHz PWM Output Voltage Gain (k = VPWM+ / Vsense-- ) (Pin 13 = Open) (TJ = --40C to + 125C) Av 12.9 15 17 V/V Current Limit Voltage Gain (k = Vace/a / Vsense-- ) (Vpin5 = 0, R10 = 15 k) Av 13 15 17 V/V k 13.4 15 17 V/V Current Limit Threshold (Vpin5 = 0, Pin 13 = Open) ILIMthr 225 270 315 mV Current Limit Delay (0 to –450 mV Step) (Note 3) ILIMdelay -- 300 -- nS ---- 3.75 -1.0 ---- -- 8.0 -- Characteristic POWER ERROR AMPLIFIER (Vcomp = 2.0 V, Vref = 2.5 V) Output Source (Vref + 0.2 V) Output Sink (Vref -- 0.2 V) Boost Current (Vref = 2.5 V nominal) AC ERROR AMPLIFIER Output Source (Pin 4 = 4 V, Pin 5 = 0 V) Gain from ACcomp to PWM+ (Av = VPWM+ / (VACcomp – Voffset)) (Note 3) CURRENT SENSE AMPLIFIER Bandwidth (Note 3) Power Output Voltage Gain (k = Vpin10 / Vsense-- ) (TJ = --40C to + 125C) REFERENCE MULTIPLIER Dynamic Input Voltage Range Ac Input (p--input) (Note 3) Compensation Input (a--input) (Note 3) Offset Voltage (a--input) Multiplier Gain k= (Note 3) Vmax k Vmult out (VAC∕Vramp pk) × (VLOOPcomp − Voffset) 3. Verified by design. http://onsemi.com 4 V 1.0/V NCP1650 ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise noted: VCC = 14 volts, CT = 470 pF, C2 = 0.1 mF, TJ = 25C for typical values. For min/max values TJ is the applicable junction temperature.) Symbol Min Typ Max 12.1 11.8 12.8 12.8 13.3 13.3 Vmax -- 3.75 -- V IINbias -- 0.01 -- mA Rsource 4.0 8.0 15 Ω Rsink 3.0 8.0 15 Ω Rise Time (CL = 1.0 nF, 20% to 80%) tr -- 50 -- ns Fall Time (CL = 1.0 nF, 20% to 80%) tf -- 50 -- ns VO(UV) -- 1.0 10 mV 4.0 Volt Reference (Pin 6) (TJ = 25C) Vref 3.94 4.00 4.06 V 4.0 Volt Regulation (TJ = --55C to 125C) Vref 3.92 4.00 4.08 V 2.5 Volt Reference (Pmax, Pin 9) Vref2.5 2.40 2.50 2.60 V Buffered Output (Iload = 0 mA) VrefOUT 6.24 6.50 6.76 V DVrefOUT 0 4.0 40 mV UVLO Startup Threshold (VCC Increasing) VSU 10 10.5 11 V UVLO Hysteresis (Shutdown Voltage = VSU – VH) VH 0.3 0.5 0.7 V Shutdown Startup Threshold (Pin 6) (Vout Increasing) VSD 0.50 0.85 1.00 V Shutdown Hysteresis (Pin 6) VH 0.10 0.18 0.3 V VOV 106.5 108 109.5 V/V VOVdiff -- 50 -- mV IBIAS -- 4.0 5.0 mA IBshutdown -- 0.6 1.0 mA Characteristic Unit MAXIMUM POWER MULTIPLIER Multiplier Gain Vpin9 4.0 × R9 K= ≈ (--Vpin12) × Vpin5 R10 R9 = 47 k, R10 = 15 k (TJ = 25C) (TJ = --40C to +125C) Dynamic Input Voltage Range Ac Input (p--input) (Note 4) k 1.0/V AC INPUT (Pin 5) Input Bias Current (Total bias current for both multipliers and current compensation amplifier) DRIVE OUTPUT Source Resistance (80 mA Load) Sink Resistance (--80 mA Load) Output Voltage in UVLO Condition VOLTAGE REFERENCE Load Regulation (Buffered Output, Io = 0 to 10 mA, VCC > 10 V) UNDERVOLTAGE LOCKOUT/SHUTDOWN OVERVOLTAGE PROTECTION Overvoltage Voltage Trip Point (Vpin6/Vref) Overvoltage Voltage Differential (VOV -- Vboost+) TOTAL DEVICE Operational Bias Current (CL(Driver) = 1.0 nF, 100 kHz) Bias Current in Undervoltage Mode 4. Verified by design. http://onsemi.com 5 NCP1650 VCC LOOP COMP 4.24 V 200 mA -+ FB/SD 4V 3.68 V ERROR AMP 20 mA + -+ -- REFERENCE REGULATOR VOLTAGE/POWER ORing NETWORK 200 mA 0.85 V PCOMP POWER MULTIPLIER AC INPUT REFERENCE MULTIPLIER 2.5 V POWER AMP + -- -+ 1.08 Vref UVLO SHUTDOWN -+ OVERVOLTAGE COMPARATOR CURRENT SHAPING NETWORK CONTROL LOGIC OUT + OSCILLATOR CURRENT SENSE AMPLIFIER GND RAMP COMP CT Figure 1. Simplified Block Diagram http://onsemi.com 6 -- IS-- NCP1650 UVLO or SHUTDOWN OVERVOLTAGE COMPARATOR DRIVE LATCH Q AC Error Amp + Ramp Comp + Inductor Current PWM 4V GND OSCILLATOR RAMP OSCILLATOR BLANKING PULSE Figure 2. Timing Diagram Typical Performance Characteristics (Test circuits are located in the document TND307/D) 130 125 θJA (C/W) 120 115 110 105 100 95 90 0 100 200 300 400 500 600 COPPER AREA (mm2) Figure 3. θJA as a Function of the Pad Copper Area (1 oz. Cu Thickness) for a JEDEC Test PCB http://onsemi.com 7 NCP1650 Typical Performance Characteristics (Test circuits are located in the document TND307/D) 102 100 k FREQUENCY (Hz) 101 CT (pF) 10 k 1k 100 99 98 97 100 1.0 10 100 96 --50 1000 0 25 50 75 100 TEMPERATURE (C) Figure 4. CT versus Frequency Figure 5. Frequency versus Temperature 125 4.12 4.40 NOTE: Ramp Valley Voltage is Zero for all Frequencies 4.35 NOTE: Valley Voltage is Zero 4.30 4.10 RAMP PEAK (V) PEAK RAMP VOLTAGE (V) --25 FREQUENCY (kHz) 4.25 4.20 4.08 4.15 4.10 4.06 4.05 4.00 0 50 100 150 200 250 4.04 --50 300 0 25 50 75 100 TEMPERATURE (C) Figure 6. Ramp Peak versus Frequency Figure 7. Peak Ramp Voltage versus Temperature 99 6 98 5 97 96 95 94 93 --25 FREQUENCY (kHz) DUTY CYCLE (%) DUTY CYCLE (%) 3.95 125 4 3 2 1 0 50 100 150 200 250 0 300 0 50 100 150 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 8. Max Duty Cycle versus Frequency Figure 9. Minimum Duty Cycle versus Frequency http://onsemi.com 8 250 NCP1650 300 30 200 20 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) Typical Performance Characteristics (Test circuits are located in the document TND307/D) 100 0 --100 --200 --300 --0.6 --0.4 --0.2 0 0.2 0.4 10 0 --10 --20 --30 --0.3 0.6 PIN 6 VOLTAGE RELATIVE TO 4.0 V REF--BOOST CIRCUIT --0.2 Figure 10. Voltage Amplifier Gain 0.1 0.2 0.3 40 30 300 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) 0 Figure 11. Voltage Amplifier Gain 400 200 100 0 --100 --200 --300 --1.5 --0.1 PIN 6 VOLTAGE RELATIVE TO 4.0 V REF--LINEAR REGION 20 10 0 --10 --20 --30 --40 --1.0 --0.5 0 0.5 1.0 --50 --0.6 1.5 PIN 9 VOLTAGE RELATIVE TO 2.5 V REF--BOOST CIRCUIT --0.4 --0.2 0 0.2 0.4 0.6 PIN 9 VOLTAGE RELATIVE TO 2.5 V REF--LINEAR REGION Figure 12. Power Amplifier Gain Figure 13. Power Amplifier Gain 5.0 PIN 11 4.5 OUTPUT (V) 4.0 PIN 10 3.5 IS-- (pin 12) 100 mV/div 3.0 2.5 GND 2.0 1.5 Iavg fltr (pin 11) 200 mV/div 1.0 0.5 0 --50 0 50 100 150 200 250 300 350 Ch 1 200 mV GND C11 = 1 nF BW Ch 4 VIS-- (mV) M 1.00 ms 100 mVΩ BW Ch 4 --58 mV Figure 15. Current Sense Amplifier High Frequency Response Figure 14. Current Sense Amplifier Gain http://onsemi.com 9 NCP1650 Typical Performance Characteristics (Test circuits are located in the document TND307/D) 5.0 PIN 7 = 0 V 1.5 V 6.0 2V 2.5 V Pmax, PIN 9 (V) Vref, PIN 4 (V) IS-- = --0.2 5.0 4.0 3.0 2.0 3V 1.0 --0.15 4.0 --0.1 3.0 2.0 --0.05 1.0 --0.02 0 0 1.0 2.0 3.0 4.0 0 5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VAC, PIN 5 (V) Figure 16. Reference Multiplier Transfer Function Figure 17. Power Multiplier Transfer Function 10 k 4.01 FALL TIME C, PIN 16 CAPACITANCE (pF) 0 VAC, PIN 5 (V) RISE TIME 4.0 Vref (V) 4.00 1k 3.99 3.98 3.97 100 0 50 100 150 200 250 300 3.96 350 --50 --25 0 25 50 75 100 RISE/FALL TIME (ns) TEMPERATURE (C) Figure 18. Capacitance versus 10--90% Drive Rise and Fall Times Figure 19. 4.0 Volt Reference versus Temperature 2.51 125 6.51 25C 6.50 --40C Vref (V) 2.5 Vref (V) 2.50 2.49 6.49 6.48 125C 6.47 2.48 --50 --25 0 25 50 75 100 6.46 125 10 12 14 16 18 TEMPERATURE (C) VCC, VOLTAGE (V) Figure 20. 2.5 Volt Reference versus Temperature Figure 21. Vref Line Regulation http://onsemi.com 10 20 NCP1650 Typical Performance Characteristics (Test circuits are located in the document TND307/D) 6.52 25C 6.50 Vref 50 mV/div Vref (V) --40C 10 mA 6.48 Vref Load 6.46 6.44 0 mA 125C 2 0 4 6 8 10 2.0 ms/div LOAD CURRENT (mA) Figure 23. Vref Transient Response Figure 22. Vref Load Regulation 7 TURN ON 10.5 10.4 10.3 10.2 10.1 TURN OFF 10.0 9.9 --50 --25 0 25 50 75 --40C 6 INPUT CURRENT (mA) TURN ON/OFF VOLTAGE (V) 10.6 5 25C 4 125C 3 2 100 0 125 25C 125C --40C 1 0 2 4 6 8 10 12 14 16 18 TEMPERATURE (C) INPUT VOLTAGE (V) Figure 24. UVLO versus Temperature Figure 25. Input Current versus Input Voltage http://onsemi.com 11 20 NCP1650 Vout Vout R1 FB/SD R1 6 FB/SD Vref 6 2 NCP1650 Vref R2 2 4.7 V NCP1650 R2 R2 R2 ZENER DIODE RESISTOR--DIODE NETWORK Figure 26. Shutdown Override Circuit Figure 27. Shutdown Override Circuit (This circuit will not override the shutdown until the chip has achieved it’s initial enable state) 5 V -- Shutdown 0 V -- Normal Operation Vout Vref 2 20 k R1 33 k BAS16LT1 AC COMP FB/SD 6 NCP1650 3 MMBT2907AL 2N3904 R2 R3 4.7 k 0.33 mF Figure 28. External Shutdown Circuit NCP1650 C3 Figure 29. Soft--Start Circuit http://onsemi.com 12 NCP1650 LOOP COMP 7 1 4.24 V VCC 200 mA -+ 4V ERROR AMP 20 mA + FB/SD 6 4V 3.68 V 200 mA + -- Pmax 0.85 V 9 PCOMP a POWER MULTIPLIER 2.5 V + -- POWER AMP 2 UVLO -+ SHUTDOWN -+ 1.08 Vref 8 Vref REFERENCE REGULATOR VOLTAGE/POWER ORing NETWORK -- 6.5 V OVERVOLTAGE COMPARATOR p AC INPUT 5 AC REF AC REFERENCE BUFFER a REFERENCE MULTIPLIER 0.75 Vline + k Iin = Vref + p 4 25 k V--I S -+ -- 4.5 V 4V AC ERROR AMP 16 k S Q PWM R DRIVER AC COMP RAMP COMPENSATION 3 + -- OUTPUT 16 20 k + OSCILLATOR 60 k AVERAGE CURRENT COMPENSATION CURRENT SENSE AMPLIFIER -- GND IS-12 15 RAMP COMP 13 14 CT Figure 30. Detailed Block Diagram http://onsemi.com 13 Iavg 10 11 Iavg fltr NCP1650 THEORY OF OPERATION Introduction Optimizing the power factor of units operating off of AC lines is becoming more and more important. There are a number of reasons for this. There are a growing number of government regulations requiring Power Factor Correction (PFC). Many of these are originating in Europe. Regulations such as IEC1000--3--2 are forcing equipment to utilize input stages with topologies other than a simple off--line front end which contains a bridge rectifier and capacitor. There are also system requirements that dictate the use of PFC. In order to obtain the maximum power from an existing circuit in a building, the power factor is very critical. The real power available from such a circuit is: Unity power factor is defined as the current waveform being in phase with the voltage, and undistorted. Therefore, there are two causes of power factor degradation – phase shift and distortion. Phase shift is normally caused by reactive loads such as motors which are inductive, or electroluminescent lighting which is highly capacitive. In such a case the power factor is relatively simple to analyze, and is determined by the phase shift. PF = cos θ Where θ is the phase angle between the voltage and the current. Reduced power factor due to distortion is more complicated to analyze and is normally measured with AC analyzers, although most circuit simulation programs can also calculate power factor. One of the major causes of distortion is rectification of the line into a capacitive filter. This causes current spikes that do not follow the input voltage waveform. An example of this type of waveform is shown in the upper diagram in Figure 2. A power converter with PFC forces the current to follow the input waveform. This reduces the peak current, the rms current and eliminates any phase shift. The NCP1650 accomplishes this for both continuous and discontinuous mode power converters. Preal = Vrms × Irms × PF A typical off--line converter will have a power factor of 0.5 to 0.6, which means that for a given circuit breaker rating only 50% to 60% of the maximum power is available. If the power factor is increased to unity, the maximum available power can be obtained. There is a similar situation in aircraft systems, where a limited supply of power is available from the on--board generators. Increasing the power factor will increase the load on the aircraft without the need for a larger generator. PFC Operation The basic PWM function of the NCP1650 is controlled by a small block of circuitry, which comprises the DC regulation loop and the PFC circuit. These components are shown in Figure 26. There are three inputs to this loop. They are the fullwave rectified input sinewave, the instantaneous input current and the DC output voltage. The input current is forced to maintain a near unity power factor due to the control of the AC error amplifier. This amplifier uses information from the AC input voltage and the AC input current to control the power switch in a manner that provides good DC regulation as well as an excellent power factor. The reference multiplier sets a reference level for the input fullwave rectified sinewave waveform. One of its inputs is connected to the scaled down fullwave rectified sinewave, and the other is connected to the output of the DC error amplifier. The signal from the DC error amplifier adjusts the level of the fullwave rectified sinewave on its output without distorting it. To accomplish this, it is necessary for the bandwidth of the DC error amp to be less than twice the lowest line frequency. Typically it is set at a factor of ten less than the rectified frequency (e.g. for a 60 Hz input, the bandwidth would be 12 Hz). V I v, i t OFF--LINE CONVERTER V I v, i t PFC CONVERTER Figure 31. Voltage and Current Waveforms http://onsemi.com 14 NCP1650 +Bus FB/SD LOOP COMP Verror(dc) -4V + VOLTAGE ERROR AMP 4V -+ REFERENCE MULTIPLIER Vref + -- .75 Vline PWM Logic PWM Rac1 DRIVE 1 Rac2 Verror(ac) AC ERROR AMP + -- AC INPUT DRIVER Verror(ac) V--I Verror(ac) AC REFERENCE BUFFER k Iin CURRENT SENSE AMPLIFIER IS-- AVERAGE CURRENT COMPENSATION --Bus REF FILTER Figure 32. Simplified Block Diagram of Basic PFC Control Circuit output so that the signal can be summed with the instantaneous input switching current (Iin). The output of the buffer is still Verrorac. The key to understanding how the input current is shaped into a high quality sine wave is the operation of the AC error amplifier. The inputs of an operational amplifier operating in its linear range, must be equal. There are several secondary effects, that create small differences between the inverting and non--inverting inputs, but for the purpose of this analysis they can be considered to be equal. The fullwave rectified sinewave output of the reference multiplier is fed into the non--inverting input of the AC error amplifier. The inverting input to the AC error amplifier receives a signal that is comprised of the input fullwave rectified sinewave (which is not modified by the reference multiplier), and summed with the filtered input current. Since the two inputs to this amplifier will be at the same potential, the complex signal at the inverting input will have the same wave shape as the AC reference signal. The AC reference signal (Vref) is a fullwave rectified sinewave, and the AC input signal (Vline) is also a fullwave rectified sinewave, therefore, the AC current signal (Iin), must also be a fullwave rectified sinewave. This relationship gives the formula: AC Input Vref Vline OSC k Iin Vref Vline + k Iin 4 V ref Verror(ac) Vref = .75 · Vline + (k · Iin) The Iin signal has a wide bandwidth, and its instantaneous value will not follow the low frequency fullwave rectified sinewave exactly, however, the output of the AC error amplifier has a low frequency pole that allows the average value of the .75 Vline + (k x Iin) to follow Vref. Since the AC error amplifier is a transconductance amplifier, it is followed by an inverting unity gain buffer stage with a low impedance GND 4 V ref Verror(ac) Verror(ac) GND Figure 33. Typical Signals for PFC Circuit http://onsemi.com 15 NCP1650 The difference between Verror(ac) and the 4.0 volt reference, sets the window that the instantaneous current will modulate in, to determine when to turn the power switch off. The switch is turned on by the oscillator, which makes this a fixed frequency controller. Under normal operation, the switch will remain on until the instantaneous value of Verror(ac) reaches the 4.0 volt reference level, at which time the switch will turn off. Since the input current has a fundamental frequency that is twice that of the line, the output filter must have poles lower than the input current to create a reasonable DC waveform. The output DC voltage is divided down via. an external divider and fed back to the DC error amplifier. Instantaneous Current Limit Protection Features The NCP1650 contains a number of features to protect the device and circuit from overload and stressful conditions. These include: Output voltage overshoot protection Low line input protection Instantaneous current limit Line frequency current limit Maximum power limit Line Frequency Current Limit The fastest protection available is a cycle--by--cycle current limit feature. The current sense amplifier has three outputs. One is the instantaneous current in the inductor, and the other two are average current waveforms. The instantaneous current signal goes directly to the PWM and is terminated by an internal 16 kΩ resistor. This current signal is added to the output of the AC error amplifier and the ramp compensation signal. The switch will conduct current until the sum of these three signals reaches the 4.0 V reference of the inverting input to the PWM comparator. The peak current is determined by the value of the ramp compensation resistor (R13) and the current shunt. The output of the reference multiplier determines the current that will be required for the unit to regulate. The sum of the input voltage from the Average Current Compensation amplifier and the averaged current signal from the current sense amplifier must add to the level of the reference multiplier. The output of this multiplier is clamped to a 4.5 maximum level. The maximum average current is set by R10. This form of protection is slower than the cycle--by--cycle current limiting, but faster than the maximum power limit circuit. Output Voltage Overshoot Protection An overshoot comparator has been provided to monitor the output voltage. Due to the slow transient response of a PFC controller, a fast load dump can cause a large output voltage transient to occur. The overshoot comparator uses the same input as the feedback and shutdown signals. Its reference is set 8% higher than the reference used by the error amplifier. This comparator will shutdown the output stage if the output voltage exceeds the set level by 8%. The circuit will resume operation once the voltage is reduced to within 8% of the set level. Maximum Power Limit The NCP1650 can limit the output power to protect against nuisance tripping of circuit breakers or other input power restrictions. It should be understood that boost regulators by design, can not be short circuit limited. Operation of the power limiting circuit will reduce the output voltage only to the level where it is equal to the peak of the input line voltage. At this point, the rectified line voltage will continue to provide output voltage through line frequency rectification by means of the series rectifier diode. The input power of the converter is calculated by the power multiplier. By multiplying the instantaneous input voltage (AC input signal, pin 5) and the instantaneous input current (averaged current sense amplifier output), the actual input power is accurately calculated. The power multiplier has a very low frequency pole which converts the power to a filtered DC level. The power error amplifier has a reference set at 2.5 volts. If the output of the power multiplier reaches 2.5 volts, the power error amplifier takes control of the loop via the ORing network and will regulate a constant power output within the limits of the power stage. It should be understood that once the output voltage is reduced to a level equal to the peak of the input voltage, the converter can no longer control the output power. The output power level is set by combination of the Iavg resistor at pin 10 and the Pmax resistor at pin 9. Low Line Input Protection This feature uses the shutdown circuitry to assure that the unit does not start under low line condition. PFC converters typically are designed with an output voltage of 400 VDC. To reduce this to the level of the 4.0 volt reference, a 100:1 ratio is required for the voltage divider to the FB/SD pin. When the converter is energized, the output voltage will be the peak line voltage. If the peak line voltage does not exceed 75 volts (0.75 volts at the FB/SD pin) the unit will not start. This corresponds to a line voltage of 53 volts rms. Application circuits have been provided in Figures 33 and 34 to override this feature if desired. http://onsemi.com 16 NCP1650 OPERATING DESCRIPTION DC Reference and Buffer The internal DC reference is a precision bandgap design with a nominal output voltage of 4.0 volts. It is temperature compensated, and trimmed for a ±1% tolerance of its nominal voltage, with an overall tolerance over line and temperature of ±2%. To assure maximum stability, this is only used as a reference so there is minimal loading on this source. The DC reference is fed into a buffer with a gain of 1.625 which creates a 6.5 volt supply. This is used as an internal voltage to power many of the blocks inside of the NCP1650 and is also available for external use. The 6.5 volt reference is designed to be terminated with at 0.1 mF capacitor for stability reasons. There is no buffer between the internal and external 6.5 V supply, so care should be used when connecting external loads. A short or overload on this voltage output will inhibit the operation of the chip. There is also a 2.5 volt reference on the power amplifier. This is derived by a resistive voltage divider off of the 4.0 V reference. by the RC network on the output. This network creates a low pass filter, and removes the high frequency content from the original waveform. INPUT A V to I CONVERTER INPUT P RAMP + -- Inverting Input NI Input Undervoltage Lockout An Undervoltage Lockout circuit (UVLO) is provided to assure that the unit does not exhibit undesirable behavior at low Vcc levels. It also reduces power consumption to a level that allows rapid charging of the Vcc cap. When the Vcc cap is originally charging, the UVLO will hold the unit off, and in a low bias current mode until the Vcc voltage reaches a nominal 10.5 volt level. At this point the unit will begin operation, and the UVLO will no longer be active. If the Vcc voltage falls to a level that is 0.5 volts below the turn--on point, the UVLO circuit will again become active. When in the shutdown state, the UVLO circuit removes power from all internal circuitry by shutting off the 6.5 volt supply. The 4.0 volt reference remains active, and the UVLO and Shutdown comparators are also active. OUTPUT Figure 34. Simplified Multiplier Schematic The multiplier ramp is generated by the internal oscillator, and is the same signal as is used in the PWM. It will therefore have the same frequency as the power stage. It is not necessary for Input P (into the PWM comparator) to be a DC signal, low frequency AC signals (relative to the ramp frequency) work well also. The gain of the multiplier is determined by the current--to--voltage ratio of the V--I converter, the load resistor of the output filter and the peak and valley points of the sawtooth ramp. When the P input signal is at the peak of the ramp waveform, the comparator will allow the A input signal to pass without chopping it at all. This gives an output voltage of the A current multiplied by the output filter resistance. When the P input signal is at the ramp valley voltage, the comparator is held low and no current is passed into the output filter. Between these two extremes, the duty cycle (and therefore, the output signal) is proportional to the level of the P input signal. The output filter is a parallel RC network. The pole for this network needs to be greater than twice the highest line frequency (120 Hz for a 60 Hz line), and less than the switching frequency. Reference Multiplier The two multipliers have different rules for designing their filters. The reference multiplier contains an internal loading resistor, with a nominal value of 25 kΩ. This is because the resistor that converts the A input voltage into a current is internal. Making both of these resistors internal, allows for good accuracy and good temperature performance. Only a capacitor needs to added externally to properly compensate this multiplier. It is not Multipliers The NCP1650 uses a new proprietary concept for the Power and Reference multipliers. This innovative design allows greatly improved accuracy compared to a conventional linear analog multiplier. The multipliers use a PWM switching circuit to create a scalable output signal, with a very well defined gain. One input (A) to the multiplier is a voltage--to--current (V--I) converter. By converting the input voltage into a current, an overall multiplier gain can be accomplished. In addition, there will be no error in the output signal due to the series rectifier. The other signal (Input P) is inputted into the PWM comparator. This selects a pulse width for the comparator output. The current signal from the V--I converter is factored by the duty cycle of the PWM comparator, and then filtered http://onsemi.com 17 NCP1650 recommended that an external resistor be used at the “Ref Gain” pin, due to tolerance variations of the internal resistances. The voltage--to--current conversion is performed in the Voltage/Power ORing network. This circuit also limits the maximum input signal (from the error amplifier) to 3 volts. Power Multiplier/Current Sense Amplifier There is no voltage--to--current converter on the power multiplier. The current output of the current sense amplifier is used for the analog input with no scaling. The power multiplier requires an external resistor as well as an external capacitor. The value of the resistor at pin 9 (max power) will depend on the value of the resistor used at pin 10 for the current gain and the maximum desired output power of the converter. These resistors should be the same style of resistor and have the same temperature coefficients for best performance. The gain of the power multiplier is based on the values of external components on this multiplier as well as the current sense amplifier. The current sense amplifier output that drives the power multiplier has its gain controlled by R9 and R10, and is filtered by a capacitor on pin 11 which removes the high frequency content from the inductor current signal. The gain for the power multiplier can be calculated as follows: Multiplier AC Ref + -25 k 4.5 V AC Error Amplifier Figure 35. Reference Multiplier Clamp Circuit There is a 1 k resistor between the AC Ref pin and the AC Error Amplifier for ESD protection. Due to this resistor, the voltage on pin 4 will exceed 4.5 volts under some conditions, but the maximum voltage at the non--inverting AC Error Amplifier input will be clamped at 4.5 volts. Feedback/Shutdown The FB/SD pin is a multiple function pin. Its primary function is to provide an input to the error amplifier for sensing of the output voltage. The signal at this pin is also sensed by an internal comparator that will shutdown the unit if the voltage falls below 0.75 volts. The feedback circuit applies the signal to the non--inverting input of the voltage loop error amp. The other input of the error amp is connected to the internal 4.0 volt reference. The output of a voltage divider from the high voltage DC output to ground, feeds this pin. The shutdown function can be used for multiple purposes including overvoltage, undervoltage or hot--swap control. An external transistor, open collector or open drain gate, connected to this pin can be used to pull it low, which will inhibit the operation of the chip, and change the operating state to a low power standby mode. An example of a shutdown circuit is shown in Figure 36. The shutdown circuit is designed such that under normal line conditions the unit will be on. At startup, the AC line is rectified and charges up the output capacitor. Under normal line conditions, the output voltage will be great enough to apply more than 1.0 volt to this pin and the circuit will commence switching. If the unit is turned on into a low line condition, the voltage at this pin will not allow the unit to start. Figures 33 and 34 shown circuits that can be used to disable the shutdown function. Both of these circuits limit the minimum voltage that can appear at the FB/SD input when the chip is properly biased, while not interfering with the 4.0 volt level that pin 6 sees when the unit is operating properly. (1.) V9 = ICS × R9 × (Vac∕Vramp) Where: ICS is the rms value of the average current out of the current sense amplifier R9 is the resistor value at pin 9 (Ohms) Vac is the rms voltage at pin 5 Vramp is the sawtooth p--p ramp voltage (4.0 volts) and, (2.) ICS = VCS × 15∕R10 Since the pole at pin 12 is much greater than twice the line frequency we can ignore the effects of the capacitor on this pin. VCS is the differential current sense rms input voltage. Equations 1 and 2 can be rearranged to give the gain of the multiplier: (3.) V9 = 1k 3.75 ⋅ R9 ⋅ VCS ⋅ Vac R10 This gain equation gives the output voltage of the multiplier, where the inputs are the AC fullwave rectified sinewave and the current sense input signal. Ramp Compensation The Ramp Compensation pin allows the amount of ramp compensation to be adjusted for optimum performance. Ramp compensation is necessary in a current mode http://onsemi.com 18 NCP1650 converter to stabilize the units operation when the duty cycle is greater than 50%. The amount of compensation required is dependent on several variables, including the boost inductor value, and the desires of the designer. The value should be based on the falling di/dt of the inductor current. For a boost inductor with a variable input voltage, this will vary over the AC input cycle, and with changes in the input line. A di/dt chart is included in the design spreadsheet that is available for the NCP1650. This pin is a buffered output of the oscillator, which provides a voltage equal to the ramp on the oscillator CT pin. A resistor from this pin to ground, programs a current that is transformed via a current mirror to the non--inverting input of the PWM comparator. The ramp voltage due to the inductor di/dt at the input to the PWM comparator is the current shunt voltage at pin 11 multiplied by 15, which is the gain of the current amplifier output that feeds the PWM. Current Sense Amp i Where CT is in pF and f is in kHz. It is important not to load the capacitor on this pin, since this could affect the accuracy of the frequency as well as that of the multipliers which use the ramp signal. Any use of this signal should incorporate a high impedance buffer. Due to the required accuracy of the peak and valley ramp voltages, the NCP1650 is not designed to be synchronized to the frequency of another oscillator. Average Current Compensation The Peak Current Compensation circuit adjusts the maximum current that can occur before the controller limits the current. This allows for higher levels of current under low line conditions than at high line. The input signal to this amplifier is the input fullwave rectified sinewave. The amplifier is a unity gain amplifier, with a voltage divider on the output that attenuates the signal by a factor of 0.75. This scaled down fullwave rectified sinewave is summed with the low frequency current signal out of the current sense amplifier. The sum of these signals must equal the signal at the inverting input to the AC error amplifier, which is the output of the reference multiplier. Since there is a hard limit of 4.5 volts at the inverting input, the sum of the line voltage plus the current cannot exceed this level. A typical universal input design operates from 85 to 265 vac, which is a range of 3.1:1. The output of the Average Current Compensation amplifier will change by this amount to allow the maximum current to vary inversely to the line voltage. + -- + -- 13 CT = 47, 000∕f AC Ref Buffer 1.6i 16 k Oscillator pin with a saturated transistor. A hysteretic comparator monitors that ramp signal and is used to switch between the current source and discharge transistor. While the cap is charging, the comparator has a reference voltage of 4.0 volts. When the ramp reaches that voltage, the comparator switches from the charging circuit to the discharge circuit, and its reference changes from 4.0 to ~0.5 volts (overshoot and delays will allow the valley voltage to reach 0 volts). The relationship between the frequency and timing capacitor is: PWM Comparator Ramp Compensation RRC Figure 36. Ramp Compensation Circuit The current mirror is designed with a 1:1.6 current ratio. The ramp signal injected can be calculated by the following formula: VRcomp = 1.6 Voscpk 16 k RRC = 102 RRC Where: VRcomp = Peak injected ramp signal (v) Driver The output driver can be used to directly drive a FET, for low and medium power applications, or a larger driver for high power applications. It is a complementary MOS, totem pole design, and is capable of sourcing and sinking over 1.5 amps, with typical rise and fall times of 30 ns with a 1.0 nF load. The totem pole output has been optimized to minimize cross conduction current during high speed operation. Additional internal circuitry has been added to keep the Driver in its low state whenever the Undervoltage Lockout is active. This characteristic eliminates the need for an external gate pulldown resistor. RRC = Ramp compensation resistor (kΩ) Oscillator The oscillator generates the sawtooth ramp signal that sets the switching frequency, as well as sets the gain for the multipliers. Both the frequency and the peak--to--peak amplitude are important parameters. The oscillator uses a current source for charging the capacitor on the CT pin. The charge rate is approximately 200 mA and is trimmed to maintain an accurate, repeatable frequency. Discharge is accomplished by grounding the CT http://onsemi.com 19 NCP1650 Error Amplifiers The NCP1650 has three error amplifiers. These amplifiers regulate the DC output voltage, the maximum output power, and shape the AC reference fullwave rectified sinewave signal. All three of these are transconductance amplifiers. Transconductance amplifiers differ from voltage amplifiers in that the output is a high impedance with a controlled voltage--to--current gain (i.e. the output current is proportional to the differential input voltage). The gain of a transconductance amplifier is determined by the equation: amplifier does not contain a boost circuit, and has a constant transconductance across its operating range. Voltage and Power ORing Network The ORing network for the voltage and power amplifiers are inverting transconductance amplifiers. The network uses an internal reference of approximately 3.0 volts. Its gain is: Iout = (Vref − Vin) · 4 = 3 V − Vin 3,125 12.5 k Where the 12.5 k is the internal resistor, and 4 is the gain of the current mirror. Av = gm RL Voltage Error Amplifier The voltage loop has a low bandwidth amplifier, which is referred to simply as “Error Amp” on the block diagram. This amplifier compares the output DC voltage to the 4.0 volt reference and generates an error signal which is used to adjust the AC reference voltage from the reference multiplier. The voltage error amplifier has a nominal gain of 100 umhos (or 0.0001 amps/volt). This means that an input voltage differential of 10 mv would cause the output current to change by 1.0 mA. The maximum output current for this amplifier in its normal operating range is 50 mA. This amplifier is a switched gain transconductance amplifier, that increases the output current (or gain) when the differential input voltage exceeds the reference voltage by +6% or --8% the output current is increased to 250 or –300 mA respectively. This boost circuit allows for rapid changes to line or load transients by increasing the dv/dt of the output capacitance of the amplifier. Power Error Amplifier The power loop has a low bandwidth error amplifier which is referred to as the “Power Amp”. This amplifier performs a similar function to the Error Amp, only it generates an error signal that holds the power to a constant level. The power error amplifier has a nominal gain of 100 umhos (or 0.0001 amps/volts). The maximum output current for this amplifier in its normal operating range is 20 mA. It is also a switched gain transconductance amplifier similar to the voltage error amplifier, however, the thresholds are different. AC Error Amplifier The third error amplifier, is the “AC error amp”. It requires a higher bandwidth than the voltage or power error amplifiers. This amplifier forces a signal which is the sum of the current and input voltage to equal the AC reference signal from the reference multiplier. The AC error amplifier has a nominal gain of 100 umhos (or 0.0001 amps/volt). The maximum output current for this amplifier in its normal operating range is 20 mA. This FB/SD 6 VOLTAGE + AMP CURRENT MIRROR i -- 3.0 V Vin + -8 4i POWER AMP 12.5 k To Reference Multiplier, Input a COMP Figure 37. Voltage/Power ORing Network The amplifier (voltage or power) with the highest output voltage will control the loop, as the buffer transistor from the other amplifier will be in cutoff. As the output voltage of an amplifier increases, it’s contribution to the current sink will increase, and the current driving the current mirror will decrease, thus the output of the current mirror will decrease. The current mirror output feeds the analog (a) input to the reference multiplier. Overvoltage Comparator For a load transient, in which the current is suddenly reduced, the output voltage will overshoot. This circuit, will minimize the overshoot, and effectively decrease the response time of the loop. A comparator is provided to monitor the feedback voltage and shut down the PWM in the event that the output exceeds 8% of the designed output voltage. The feedback voltage is supplied to this comparator from pin 6, which is the same signal that the voltage error amplifier uses to regulate the DC voltage loop. http://onsemi.com 20 NCP1650 Current Sense Amplifier The current sense amplifier is a wide bandwidth amplifier with a differential input. It consists of a differential input stage, a high frequency current mirror and a low frequency current mirror, for a total of three current outputs. Two of them (AC Error Amplifier and Power Multiplier) are generated from the i2 mirror, and their waveforms have been filtered to resemble the average value of the input current. The third output is the instantaneous inductor current and is generated from the i1 mirror which directly feeds the input of the PWM. CURRENT MIRROR i1 i1 across an internal 15 kW resistor, and filtered by a capacitor at pin 11. This signal, when properly filtered, will be the 2x line frequency fullwave rectified sinewave. The filter pole on pin 11 should be far enough below the switching frequency to remove most of the high frequency component, but high enough above the line frequency so as not to cause significant distortion to the input fullwave rectified sinewave waveform. For a 100 kHz switching frequency and a 60 Hz line frequency, a 10 kHz pole will normally work well. The capacitor at pin 11 can be calculated knowing the desired pole frequency by the equation: C11 = 10.5 f CURRENT MIRROR i1 i2 i2 Where: C11 = Pin 11 capacitance (nF) f = pole frequency (kHz) i2 PWM Pwr Mult 1k 1k 12 + -- 15 k IS-- 11 Iavg fltr or, for a 10 kHz pole, C11 would be 1.0 nF. AC Error Amp 10 C11 The gain of the low frequency current buffer is set by the value of the resistor at pin 10. The value of R10 affects the operation of the AC error amplifier as well as the maximum power level. Power multiplier gain calculations are included in the description of that circuit. Iavg R10 PWM and Logic The PWM and logic circuits are comprised of a PWM comparator, an RS flip--flop (latch) and an OR gate. The latch has two Set inputs and one Reset input. The Reset input is dominant over the PWM Set input, but the Overshoot Comparator Set input is dominant over the Reset input. The two Set Inputs are effectively OR’ed together although their dominance varies. The NCP1650 uses a standard Pulse Width Modulation scheme based on a fixed frequency oscillator. The oscillator outputs a ramp waveform as well as a pulse which is coincident with the falling edge of the ramp. The pulse is fed into the PWM latch and AND gate that follows. During the pulse, the latch is reset, and the output drive is in it’s low state. On the falling edge of the pulse, the output drive goes high and the power switch begins conduction. The instantaneous inductor current is summed with the AC error amplifier voltage and the ramp compensation signal to create a complex waveform that is compared to the 4.0 volt reference signal on the inverting input to the PWM comparator. When the signal at the non--inverting input to the PWM comparator exceeds 4.0 volts, the output of the PWM comparator changes to a high state which drives one of the Set inputs to the latch and turns the power switch off until the next oscillator cycle. Figure 40 shows the relationships of the oscillator and logic signals. There are two override signals to the normal cycle--by--cycle PWM operation. The UVLO circuit feeds directly into the AND gate and will inhibit operation until the input voltage is in a valid range. The Overshoot Figure 38. Current Sense Amplifier The input to the current sense amplifier is a common base configuration. The voltage developed across the current shunt is sensed at the Is-- input. The amplifier input is designed for negative going voltages only; the power stage should resemble the configuration of the circuit in Figure 39. Caution should be exercised when designing a filter between the shunt resistor and this input, due to the low impedance of this amplifier. Any series resistance due to a filter, will create an offset of: VOS = 50 mA × Rexternal which will add a negative offset to the current signal. The effect of this is that current information will be lost when the current signal is below the offset level. This will be a problem mainly at light loads and near the zero crossings. The voltage across the current shunt resistor is converted into a current (i1), which drives a current mirror. The output of the i1 current mirror is a high frequency signal that is a replica of the instantaneous current in the inductor. The conversion of the current sense signal to current i1 is: i1 = Vis-- ∕1 k The PWM output sends that information directly to the PWM input where it is added to the AC error amp signal and the ramp compensation signal. The other output of the i1 mirror provides a voltage signal to a buffer amplifier. This signal is the result of i1 dropped http://onsemi.com 21 NCP1650 Comparator monitors the output voltage and will shutdown operation of the PWM circuit if the output voltage exceeds 8% above the normal regulation level. The Overshoot Comparator signal is fed into the second Set input to the latch. The buffer amplifier, converts the input voltage to a current by creating a current equal to the voltage difference between the AC error amplifier output and the 2.9 volt reference dropped across the 14 kΩ resistor. The bipolar transistor level shifts the voltage and maintains the proper current into the current mirror. The current mirror has a 1:2 ratio and delivers the output current to the PWM input. This current is summed with the currents of the ramp compensation signal and the instantaneous current signal to determine the turn--off point in the switching cycle. AC Reference Buffer The AC reference buffer converts the voltage generated by the AC error amplifier to be converted into a current to be summed with the ramp compensation signal and the instantaneous current signal. Soft--Start Circuit The AC error amplifier has been configured such that a low output level will cause the output duty cycle to go to zero. This will have the effect of soft--starting the unit at turn--on, since the output is coupled to ground through a capacitor. There will be an initial offset of the output voltage due to the output current and the resistor at pin 3. For example, if the output is saturated in the high state at turn on, it will source 50 mA. If pin 3 is terminated with a 2.2 kΩ resistor and a 0.01 F capacitor, the initial step will be: CURRENT MIRROR 2.9 V AC Comp 3 AC ERROR AMP i1 2 X i1 + -- 14 k + -- 16 k PWM, Ramp Comp Current Sense Amp 50 mA × 2.2 k = 0.11 volts and the rate of rise will be: Unity Gain Amplifier 50 mA∕0.01 mF = 5 mv∕ms Figure 39. AC Reference Buffer Schematic or, 560 ms until the output is at 2.9 volts, which corresponds to full duty cycle. An external soft--start circuit can be added, as shown in Figure 29, if additional time is desired. The buffer’s transfer function is: iout = (2.9 V − Vac)∕7 k http://onsemi.com 22 NCP1650 DESIGN GUIDELINES D1 VCC LOOP COMP Vin D2 7 Cin D3 R7 D4 4.24 V + -- 4V ERROR AMP FB/SD C7 1 6 4V PCOMP 3.68 V + -- -+ 0.85 V 9 C8 POWER AMP a POWER MULTIPLIER C9 2.5 V + -- 1.08 Vref Cref UVLO SHUTDOWN INRUSH LIMITER (OPTIONAL) -+ 4V Pmax R9 Vref VOLTAGE/POWER ORing NETWORK + -- 0.1 mF 2 REFERENCE REGULATOR 8 R8 6.5 V OVERVOLTAGE COMPARATOR p Rac1 a REFERENCE MULTIPLIER AC INPUT 5 AC REF p 4 25 k AC REFERENCE BUFFER AC ERROR AMP + -- V--I 0.75 Vline + k Iin = Vref 16 k L1 S 4V -+ S Q PWM R D5 4.5 V RDC1 Rac2 Cac DRIVER AC COMP RAMP COMPENSATION 3 C4 R3 C3 GND + -- OUT 16 20 k Q1 Cout to FB RDC2 + OSCILLATOR 60 k AVERAGE CURRENT COMPENSATION CURRENT SENSE AMPLIFIER Rshunt 15 -- IS-12 13 RAMP COMP 14 R13 CT CT Iavg 10 11 Iavg fltr R10 C11 Note: This is a theoretical design, and it is not implied that a circuit designed by this procedure will operate properly without normal troubleshooting and adjustments as are common with any power conversion circuit. ON Semiconductor provides a spread sheet that incorporates the following equations, and will calculate the bias components for a circuit using the above schematic. Figure 40. Typical Application Schematic Basic Specifications The design of any power converter begins with a basic set of specifications. As a minimum, the following parameters should be known before beginning: Pomax (Maximum rated output power) Vrmsmin (Minimum operational line voltage) Vrmsmax (Maximum operational line voltage) fswitch (Nominal switching frequency) Vout (Nominal regulated output voltage) Most of these parameters will be dictated by system requirements. The output voltage may not be defined. In general, it should be slightly greater than the peak of the line waveform at high line. For a 265 vrms input, the peak line voltage would be 375 volts, and 400 volts is a standard output voltage. In no case should it be less than the peak input line voltage. Inductor For an average current mode, fixed frequency PFC converter, there is no magic formula to determine the optimum value of the inductor. There are several trade--off’s that should be considered. These include peak current vs. average current, and switching losses vs. core losses. All of these are a function of inductance, line and load. These parameters determine when the converter is operating in the continuous conduction mode and when it is operating in the discontinuous conduction mode. http://onsemi.com 23 NCP1650 For a first approach, the following formula will give the inductance value that will cause the peak current to be a fraction of the peak line frequency current. L= T · Vin2 2 · I% · Pout 1− Using the ON Semiconductor spreadsheet, a value of 250 mH allows for continuous mode operation at full load and most input voltages. At the high line value of 265 vac, the unit will operate in the continuous mode from 30 to 150, and discontinuous when the input voltage is near zero. Using information from the ON Semiconductor spreadsheet the inductor can either be specified to a magnetics company to design, or can be designed by the Magnetics Inc. software. In either case, the critical information for the inductor design, (inductance, maximum average current, peak--to--peak ripple current, and switching frequency) can be obtained from the spreadsheet. If a secondary winding is desired to provide a bias supply, it should provide a minimum of 11.8 volts (to exceed the UVLO spec) and a maximum of 18 volts. The secondary should be connected such that it conducts when the power switch is off. This will create an output voltage that varies with the input voltage, and near the zero crossings of the line frequency will have a peak voltage equal to the regulated output voltage divided by the turns ratio. The filter cap on the Vcc pin needs to be of sufficient size to hold the voltage up over between the zero crossings. 2 · V in Vout Where: L is the inductance (mH) T is the switching period (ms) Vin is the minimum rms line voltage (v) I% is the percent switching current ripple relative to the line current (.xx) Pout is the maximum output power (w) Vout is the output voltage (v) So for the following unit: Vin = 85 vrms Vout = 400 VDC Pmax = 1000 watts T = 10 ms (100 kHz) I% = .30 Oscillator The relationship between the frequency and timing capacitor is: the inductance would be 84 mH. I max = CT = 47, 000∕f 2 · P out Where CT is in pF and f is in kHz. Vin The maximum low frequency line current would be determined at full load and low line, or: where the definitions of Pout and Vin are as in the above equation. For the above conditions, Imax would be 16.6 amps. The peak current in the inductor at full load and low line would be 30% greater than this, or 21.6 amps. For thermal calculations the transformer will have to pass 11.8 amps rms, and not saturate with a peak current of 21.6 amps. There are several options available for the design of inductors. You can contact a magnetics manufacturer, such as Coiltronics (cooperet.com) or inductor designs can be made simply with the use of programs such as the DC inductor design program from Magnetics Inc. This software is free at their website, www.mag--inc.com. Using the equation provided, and the following variables: AC Voltage Divider The voltage divider from the input rectifiers to ground is a simple but important calculation. For this calculation it is necessary to know the maximum line that the unit can operate at. The peak input voltage will be: Vinpeak = 1.414 × Vrms max The maximum voltage at the AC input (pin 5) is 3.75 volts (this is true for both multipliers). If the maximum line voltage is 265 vac, the peak input voltage is: Vinpeak = 1.414 × 265 Vrms = 375 Vpk To keep the power dissipation reasonable for a ½ watt resistor (Rac1), it should dissipate no more than ¼ watt. Depending on environmental conditions, further derating may be required. The power in this resistor is: T = 10 ms (f = 100 kHz) Vrms = 265 v Vo = 400 VDC Pmax = 1000 watts I% = 30 PRac1 = (375 v − 3.75 v)2∕Rac1 = .25 watts so : Rac1 = 551 kOhms To minimize dissipation, use the next largest standard value, or 560 kOhms. Then, Rac2 = 3.75 v∕((375 v − 3.75 v)∕560 k) = 5.6 kOhms the inductance would be 74 mH. http://onsemi.com 24 NCP1650 Current Sense Resistor/Ramp Compensation The combination of the voltage developed across the current sense resistor and ramp compensation signal, will determine the peak instantaneous current that the power switch will be allowed to conduct before it is turned off. The vector sum of the three signals that combine to create the signal at the non--inverting input to the PWM comparator must add up to 4.0 volts in order to terminate the switch cycle. These signals are the error signal from the AC error amp, the ramp compensation signal, and the instantaneous current. For a worst case condition, the output of the AC error amp could be zero (current), which would require that the sum of the ramp compensation signal and current signal be 4.0 volts. This must be evaluated under full load and low line conditions. RS = Shunt resistance (Ω) L = Inductance (H) Vout = Output voltage (V) Equation 1) RRC = Ramp comp resistor (kΩ) VRCOMP = Ramp Compensation: Equation 3) Vrefpwm = Vinst + VRCOMP Where: Vrefpwm = 3.8 V 3.8 = (ipk * RS * 16 + RRC = 1.6 * Voscpk * 16 k Current Shunt: Equation 4) Combining equations 2 and 3: RRC 1.6 * 4 * 16 k 102, 400 = RRC RRC RS = For proper ramp compensation, the ramp signal should match the falling di/dt (which has been converted to a dv/dt) of the inductor at 50% duty cycle. 50% duty cycle will occur when the input voltage is 50% of the output voltage. Thus the following equations must be satisfied: RS = di * T * R * High Frequency Current Gain S dt Vo * T * RS * 16 102, 400 = RRC L * 2 RS = Shunt resistance (Ω) PO = Output power (W) L = Inductance (H) 2 · Vin LL Vout 3.8 + 16 * ipk 8 * Vo * ton L Current Scaling Resistor and Filter Capacitor R10 sets the gain of the averaged current signal out of the current sense amplifier. This signal is fed into the AC error amplifier and is also used in the power multiplier. R10 is used to scale the current to the appropriate level for protection purposes in the AC error amplifier circuit. The power multiplier has an external resistor, R9 that will adjust the gain of that circuit. R10 should be calculated to limit the maximum current signal at the input to the AC error amplifier to less than 4.5 volts at low line and full load. 4.5 volts is the clamp voltage at the output of the reference amplifier and limits the maximum averaged current that the unit can process. The equation for R10 is: 12800 * L RS = Vo * T * RRC (3.8 − 16 * ipk * RS) 12800 * L * T * t Vo * T * RRC 102, 400 on Solve for RS and then RRC, using the above equations. It should be understood that these equations do not take into account tolerances of the inductor, switching frequency, etc The shunt should be a non--wirewound (low inductance) type of resistor. There are several types of metal film resistors available for shunt applications. Equation 2) ton = T 1 − t 102, 400 * on T (3.8 − (16 * ipk * RS)) Where: Where: Voscpk = 4.0 V VRCOMP = t 102, 400 ) * on T RRC Where: ton = Switch on time (s) T = Period (s) VinLL = Low line input voltage (Vrms) Vout = DC output voltage (V) R10 = 2 ⋅ P in VinLL ⋅ ton ipk = + 2 ⋅ L VinLL 318, 200 · Pin · RS∕VinLL 4.5 − (1.06 · VinLL · ACratio) Where: Pin = rated input power (w) RS = Shunt resistance (W) VinLL = min. operating rms input voltage (v) ACratio = AC attenuation factor at pin 5 http://onsemi.com 25 NCP1650 Reference Multiplier The output of the reference multiplier is a pulse width modulated representation of the analog input. The multiplier is internally loaded with a resistor to ground which will set the DC gain. An external capacitor is required to filter the signal back into one that resembles the input fullwave rectified sinewave. The pole for this circuit should be greater than the line frequency and lower than the switching frequency. 1/15th of the switching frequency is a recommended starting value for a 60 Hz line frequency. The filter capacitor for pin 4 can be determined by the following equation: This equation does not allow for tolerances, and it would be advisable to increase the input power to assure operation at maximum power over production tolerance variations. The current sense filter capacitor should be selected to set it’s pole about a factor of 10 below the switching frequency. C11 = 10.6 f Where: C11 = Pin 11 capacitance (nF) f = pole frequency (kHz) so, for a 100 kHz switching frequency, a 10 kHz pole is desirable, and C11 would be 1.0 nF. C4 = Maximum Power Circuit The power multiplier multiplies the input voltage, current and a scale factor, to output a value that is proportional to the input power. This voltage is filtered to remove the line frequency components. The resulting output is compared to the 2.5 volt reference on the power error amplifier. When the output of the multiplier reaches 2.5 volts the power loop takes control and will reduce the output voltage as necessary, but can not reduce it to less than the peak of the line voltage. For proper operation, resistor R9 should be chosen such that the unit will power limit at a value slightly greater than the maximum power desired. R9 can be calculated by the formula: R9 = C4 = Pin 4 capacitance (F) fpole = Ref gain pole freq (Hz) AC Error Amplifier The AC error amplifier is a transconductance amplifier that is terminated with a series RC impedance. This creates a pole--zero pair. To determine the values of R3 and C3, it is necessary to look at the two signals that reach the PWM inputs. The non--inverting input is a slow loop using the averaged current signal. It’s gain is: 15 k 15 k Alf = ⋅ ⋅ (gm ⋅ R3) ⋅ 2.3 1 k R10 V9 R10 ACratio Pin RS 3.75 Where the first two terms are the gains in the current sense amplifier averaging circuit. The next term is the gain of the transconductance amplifier and the constant is the gain of the AC Reference Buffer. The high frequency path is that of the instantaneous current signal to the PWM non--inverting input. This gain is simply 16, since the input signal is converted to a current through a 1 k resistor, and then terminated by the 16 k resistor at the PWM input. For stability, the gain of the low frequency path must be less than the gain of the high frequency path. This can be written as: Where: V9 = Power reference voltage (2.5 v nom) R10 = Current scaling resistor (Ω) ACratio = AC attenuation factor at pin 5 Pin = rated input power (w) RS = Shunt resistance (W) The NCP1650 has been designed such that with a 2% current shunt and a 1% AC divider, the RSS error will be 7% maximum, or a worst case error of 14%. In order to assure maximum power output the reference voltage (V9) should be reduced by the error factor. The output signal from the power multiplier should be close to a DC level, so a filter cap needs to be added with a high frequency pole relative to the line frequency. For a 60 Hz line, a 0.6 Hz pole would allow 40 dB of attenuation, or .01 which would reduce a 5.0 volt p--p signal to a DC level of 2.5 volts, with 50 mv of ripple. The chosen frequency will be a tradeoff of response time vs. ripple. For a pole of 0.6 Hz: C9 = 1 = 6.366E − 6 fpole 2 ⋅ π ⋅ 25 k ⋅ fpole 517, 500 ⋅ gm ⋅ R3 R10 < 16 The suggested resistor and capacitor values are: R3 = R10 56, 000 gm and for a zero at 1/10th of the switching frequency C3 = 1.59 fsw R3 1 = 0.265 2 ⋅ π ⋅ R9 ⋅ 0.6 R9 Where: Where: C9 = Pin 9 capacitance (F) R3 and R10 are in units of Ω gm is in units of mhos C3 is in Farads fsw is in Hz R9 = Pin 9 resistance (Ω) http://onsemi.com 26 NCP1650 Loop Compensation Rac2 Rac1 Vac Vline Vo Rdc1 V FB/SD 6 Rdc2 4V + -- Ve/a ORing NET --0.32 mA/V REFERENCE MULTIPLIER AC ERROR AMP Vref 4V -- RL -- OUT LOGIC + + ERROR AMP PWM 16 25 k RS 12 C.S. Amp LOOP COMP C Q1 Iavg 7 IS-RECTIFIER 10 R10 R7 C7 DIVIDER Rdc2 V′ = Rdc1 + Rdc2 Vo ERROR AMP funity = fz = Gm 2 π C7 1 2 π C7 R7 REFERENCE SIGNAL MODULATOR AND OUTPUT STAGE RL R10 ΔVo = ΔVref 225k RS Vref = --2 Vac Ve∕a Vac = R Vline Rac2 fp = ac1 + Rac2 1 2πRC Av = Gm R7 (High Frequency Gain, Past Zero) Figure 41. Voltage Loop Model Voltage Loop Block Diagram 20 GAIN (dB) The block diagram for the voltage loop has been broken down into four sections. These are the voltage divider, voltage error amplifier, reference signal and modulator and output stage. The modulator and output stage circuitry is greatly simplified based on the assumption that that poles and zeros in the current feedback loop are considerably greater than the bandwidth of the overall loop. This should be a good assumption, because a bandwidth in the kilohertz is necessary for a good current waveform, and the voltage error amplifier needs to have a bandwidth of less than the lowest line frequency that will be used. There are two poles in this circuit. The output filter has a pole that varies with the load. The pole on the voltage error amplifier will be determined by this analysis. 0 UNITY GAIN Av --20 FREQUENCY Figure 42. Pole--Zero Bode Plot Reference Signal The voltage divider is a simple resistive divider that reduces the output voltage to the 4.0 volt level required by the internal reference on the voltage error amplifier. The output of the error amplifier is modified by the ORing network, which has a negative gain, and is then used as an input to the reference multiplier. The gain of this block is dependent on the AC input voltage, because of the multiplier which requires two inputs for one output. Voltage Error Amplifier Modulator and Output Stage Voltage Divider The AC error amplifier receives an input from the reference multiplier and forces the current to follow the shape and amplitude of the reference signal. The current shaping circuit is an internal loop within this section due to the current sense amplifier. Based on the assumptions listed The voltage error amplifier is constrained by the three equations. When this amplifier is compensated with a pole--zero pair, there will be a unity gain pole which will be cancelled by the zero at frequency fZ. The corresponding bode plot would be: http://onsemi.com 27 NCP1650 Plot the sum of these three values. Figure 43 shows a gain of 35.5 dB until the pole of the output filter is reached at 0.3 Hz. After that, the gain is reduced at a rate of 20 dB/decade. in the introduction to this analysis, this is not analyzed separately. The equation for the gain is good for frequencies below the pole. There is a single pole due to the output filter. Since the NCP1650 is a current mode converter, the inductor is not part of the output pole as can be seen in that equation. 40 LOOP GAIN WITHOUT ERROR AMP 30 Calculating the Loop Gain At this point in the design process, all of the parameters involved in this calculation have been determined with the exception of the pole--zero pair on the output of the voltage error amplifier. All equations give gains in absolute numbers. It is necessary to convert these to the decibel format using the following formula: GAIN (dB) 20 10 0 --10 --20 A(dB) = 20 Log10 (A) --30 For example, the voltage divider would be: --40 5.6 k A= = .0099 560 k + 5.6 k 0.01 0.1 1 10 FREQUENCY (Hz) 100 1000 Figure 43. Open Loop Gain Less Error Amp A(dB) = 20 Log10 .0099 = − 40 dB The gain of the loop will vary as the input voltage changes. It is recommended that the compensation for the voltage error amplifier be calculated under high line, full load conditions. This should be the greatest bandwidth that the unit will see. By necessity, the unity gain (OdB) loop bandwidth for a PFC unit, must be less than the line frequency. If the bandwidth approaches or exceeds the line frequency, the voltage error amplifier signal will have frequency components in its output that are greater than the line frequency. These components will cause distortion in the output of the reference amplifier, which is used to shape the current waveform. This in turn will cause distortion in the current and reduce the power factor. Typically the maximum bandwidth for a 60 Hz PFC converter is 10 Hz, and slightly less for a 50 Hz system. This can be adjusted to meet the particular requirements of a system. The unity gain bandwidth is determined by the frequency at which the loop gain passes through the 0 dB level. For stability purposes, the gain should pass through 0 dB with a slope of –20 dB/decade for approximately one decade on either side of the unity gain frequency. This assures a phase margin of greater than 45. The gain can be calculated graphically using the equations of Figure 43 as follows: Divider: Calculate V’/Vo in dB, this value is constant so it will not change with frequency. Reference Signal: Calculate Vref/Ve/a using the peak level of the AC input signal at high line that will be seen on pin 5. Convert this to dB. This is also a constant value. Modulator and Output Stage: Calculate the gain in dB for DVo/DVref. Calculate the pole frequency. The gain will be constant for all frequencies less than fp. Starting at the pole frequency, this gain will drop off at a rate of 20 dB/decade. A typical error amplifier bode plot is shown in Figure 44. The zero is used to offset the pole of the output filter. The output filter pole will typically be lower than the unity gain loop bandwidth, so the zero will be necessary. This plot shows a forward gain of 7.0 dB at 10 Hz. To compensate for this the error amplifier should have a gain of –7.0 dB (0.45) at 10 Hz, and a zero at 0.4 Hz. The gain at 10 Hz is determined by the resistor since it is well past the zero. The resistor can be calculated by the equation: R7 = Av∕Gm = .45∕.0001 = 4.5 kΩ 4.7 kW is the closest standard value. Using this, the capacitor can be calculated based on the zero frequency of 0.4 Hz. This would give a value for C7 of: C= 1 = 85 mF 2 ⋅ π ⋅ 4.7 k ⋅ 0.4 Hz Using these values (4.7 kΩ and 86 mF), the open loop gain plot would be: 80 VOLTAGE LOOP BODE PLOT 60 GAIN (dB) 40 20 0 --20 --40 0.01 0.1 1 10 FREQUENCY (Hz) 100 Figure 44. Open Loop Gain of Voltage Loop http://onsemi.com 28 1000 NCP1650 Vline Rac1 AC INPUT Vac 5 Rac2 POWER MULTIPLIER Vpm Pmax 9 2.5 V R9 C9 + -- Vpa ORing NET --0.32 mA/V REFERENCE MULTIPLIER Vref AC ERROR AMP -+ POWER AMP Q1 4V -- OUT LOGIC + PWM 16 25 k C.S. Amp 12 IS-IO LOOP COMP Iavg 8 10 R10 R8 RS C8 POWER MULTIPLIER Vpm io = 3.75 R9 Vac RS Vac = R fp = R10 Vline Rac2 ac1 + Rac2 1 2 π C9 R9 POWER AMP REFERENCE SIGNAL Gm Av = 2πfC Vref = --2 Vac Vpa fz = 8 1 2 π C8 R8 Vac = R MODULATOR AND OUTPUT STAGE io R10 = Vref 225k RS Vline Rac2 ac1 + Rac2 Av = Gm R8 (High Frequency Gain, Past Zero) Figure 45. Power Loop Model Power Loop Power Multiplier The power multiplier’s gain is a function of the input voltage. This multiplier has a very low frequency pole that must be considerably lower than the line frequency, so that the power signal is essentially a DC level. Block Diagram The block diagram for the power loop has been broken down into four sections. These are the power multiplier, power amplifier, reference signal and modulator and output stage. Similar to the voltage loop, the modulator and output stage circuitry has been greatly simplified due to the location of the associated poles and zeros. There are two significant poles in this circuit. The first is on the power multiplier and the second is due to the power error amplifier. Because the pole on the power multiplier is very low, it will normally be necessary to include the resistor (R8) for the zero on this amplifier. Reference Signal The reference signal block is unchanged from the voltage loop model. Modulator and Output Stage For the power circuit, the transfer function of the modulator and output circuitry follows the path from the AC reference voltage (Vref) to the output current. Since this circuit regulates the power, and the input and output voltages are the two basic components of the power, the output current is the output variable for this block. There is no pole associated with this function. http://onsemi.com 29 NCP1650 Power Amplifier For this example it can be seen that for a bandwidth of 1.0 Hz, the power amplifier needs a gain of –27 dB (0.045 v/v) at 1.0 Hz, with a zero at 0.7 Hz. The zero frequency is chosen to match the pole frequency. Although it is not essential to do this, it is a safe method of assuring a stable system. Since the frequency that we are interested in is greater than the zero frequency, the gain of the amplifier is: The compensation for this amplifier will be determined similar to the network for the voltage error amplifier. The series RC on pin 8 will create a pole--zero pair based on the equations given. Calculating the Loop Gain The power loop gain should be calculated using high line conditions. At lower lines the bandwidth will decrease. Similar to the voltage loop, calculate the gains and power multiplier pole. Make sure that they are converted to dB’s. Begin with all stages except the power amplifier, and determine what the gain of the power amplifier needs to be at the unity gain frequency. This loop is normally slower than the voltage loop and will generally be a factor of 5 to 10 lower in bandwidth. The loop gain without the amplifier should resemble the following plot: Av = Gm R8 or, R8 = Av∕Gm = 0.045∕.0001 = 446 Ohms a 470 Ohm resistor would be a good choice, and for a zero at 0.7 Hz: C8 = and a 470 mF cap would be a good choice. Using these two values, the resulting open loop plot would be: 30 60 POWER LOOP GAIN LESS POWER AMP 20 40 20 GAIN (dB) GAIN (dB) 10 0 --10 0 --20 --20 --40 --30 --60 --40 1 = 483 mF 2 ⋅ π ⋅ 470 Ω ⋅ 0.7 Hz 0.01 0.1 1 10 FREQUENCY (Hz) 100 --80 1000 0.01 Figure 46. Power Loop without Power Amp 0.1 1 10 FREQUENCY (Hz) 100 1000 Figure 47. Power Circuit Open Loop Gain As stated previously, these are calculated values, and may require adjustment in actual circuit conditions. http://onsemi.com 30 NCP1650 PACKAGE DIMENSIONS SOIC--16 CASE 751B--05 ISSUE K --A-16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 --B-1 P 8 PL 0.25 (0.010) 8 B M S DIM A B C D F G J K M P R G R K F X 45 _ C --T-- SEATING PLANE J M D MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303--675--2175 or 800--344--3860 Toll Free USA/Canada Fax: 303--675--2176 or 800--344--3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800--282--9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81--3--5773--3850 http://onsemi.com 31 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP1650/D AND8084/D NCP1650 Benchtop Assistance Prepared by: Alan Ball ON Semiconductor Applications Engineer http://onsemi.com APPLICATION NOTE 3. Low Output Voltage If the output voltage is less than the designed output level, check the values in the output voltage divider that connects to pin 6 of the IC. If the voltage divider values are correct, check the output of the power error amplifier at pin 8. If this voltage level is higher than the output of the voltage error amplifier (pin 7), the power circuit is limiting the output. Check to make sure that the load is within the rated range, and that the values of R10, R9, and the current shunt are correct. The NCP1650 is a high–performance, Power Factor Correction IC. It is capable of producing a high power factor input current waveform under continuous and discontinuous modes of operation. It is also a highly integrated device, and as such, requires fine tuning for optimum performance. The purpose of this application note is to assist in troubleshooting and fine tuning this circuit. Troubleshooting When troubleshooting this circuit, always use an oscilloscope. DVM readings will not show oscillations, spikes or other waveforms that may be helpful in determining the cause of the problem. Be aware that this is a non–isolated power converter that is connected to a high–voltage, AC line. The ground of this circuit will be at an AC potential and could pose a shock hazard. Use an approved isolation transformer before connecting oscilloscopes or other test equipment to this circuit. Unit Does Not Start 1. Typically, the inability of this unit to start–up is due to inadequate Vcc. The NCP1650 requires a minimum of 10.5 volts to turn on, and 9.5 to maintain operation. If the Vcc voltage drops below 9.5 volts, the chip will shut down. When the chip begins operation, the bias current will increase from a level of 0.5 mA to about 5.0 mA. Depending on the start–up circuit used, there may not be enough energy available to get the unit started before the Vcc drops below 9.5 volts. In this case, a higher value Vcc cap may solve the problem, and/or a higher current start–up circuit. If the start–up circuit is operating properly, check the voltage on pin 6. This pin has a shutdown feature that requires a voltage of greater than 0.75 volts for the chip to come out of its shutdown mode and commence operation. Output Does Not Regulate 1. High Output Voltage If the output voltage is greater than 8% of the level of the designed output voltage, check the voltage divider from the output to pin 6. Make sure that the resistor values are correct, and that the resistors are connected properly. 2. High Output Voltage If the output voltage is approximately 8% above the designed output level, the overvoltage comparator is controlling the loop. The switching will be erratic as the overvoltage comparator inhibits the operation of the loop. The input to the error amplifier (pin 6) should be 4.3 volts under this condition. The output of the error amplifier (pin 7) should be high (approximately 6.0 volts). If it is not high, check connections to this node. The voltage/power OR’ing network inverts this signal, which should cause the output of the reference multiplier (pin 4) to be approximately zero volts. The averaged current signal on pin 10 of the current sense amplifier should be less than the output of the reference multiplier on pin 4. Semiconductor Components Industries, LLC, 2002 May, 2002 – Rev. 0 Failure of Power Switch or High Voltage Diode Overheating is the main cause of failures of these devices. The rectifier diode will experience significant heating due to the reverse recovery spike (unless a special circuit is used to reduce this effect). Measure the temperature of the package of both of these devices with a thermocouple and assure that they do not exceed the manufacturers ratings. Additional heatsinking and/or alternative parts may be required to keep the temperature in a safe range. The power switch has several protection circuits within the NCP1650 controller. The main one being the instantaneous current limit. If peak current is a concern, check the values per the Excel spreadsheet or review the design equations in the data sheet. 1 Publication Order Number: AND8084/D AND8084/D The voltage on the power switch will exceed the output voltage by a diode drop plus any spikes that may occur. A good layout will keep these spikes to a minimum. Observe the drain pin of the power switch with a wide bandwidth oscilloscope to look for spikes. Spikes can be reduced by adding snubbers or modifying the layout to reduce path lengths between the inductor, drain and rectifier anode. Possible causes are: 1. Poor grounding. In general, one of two grounding schemes should be used. • Single Point Ground – This is sometimes referred to as a “star ground”. All major power traces should be routed as closes as possible to a single point, and routed directly to that point. This includes the shunt resistor, FET source, output capacitor, input bypass capacitor, and one trace going to all signal circuitry. The chip ground should be as close as possible to the ground side of the shunt resistor. • Ground Plane – One layer of the printed circuit board is left as a solid copper plane and all grounds are connected to this plane. Even with a ground plane, it is recommended to keep the high power grounds (as described in the above paragraph) close to each other, as well as keeping the chip ground close to the current shunt resistor ground. 2. Reduce rise and fall times of the power device. Increasing the resistance in the gate lead of the power FET will reduce the speed of its transitions. This will result in increased switching losses in the power switch. Snubber circuits can be added across the FET and/or diode to reduce noise levels. There are several types of snubbers including RC and RCD configurations. 3. Noise can also be radiated from various sources. The node of the FET drain, output rectifier, and boost inductor is a very noisy source, with both high voltages and high dv/dt’s. Sensitive components, which include most bias components of the NCP1650, should be kept away from this node. Traces between these components should be kept as short as possible to reduce these emissions. Noise Problems Noise issues can be identified by abrupt changes in the current waveform. Instabilities will cause smooth oscillations, but noise will cause sharp edges as the current steps from one level to another. Figure 1. Example of Input Current Waveform Distortion Due to Noise Issues Performance Figure 2. AC Ref with Phase Delay Figure 3. AC Ref with Minimal Phase Delay http://onsemi.com 2 AND8084/D How to Improve Harmonics and Distortion Low harmonic content and distortion are achieved by forcing the input current to exactly replicate the waveshape of the input voltage. To do this the output of the reference multiplier must be an accurate copy of the input haversine waveform. It is the function of the AC error amplifier loop to force the input current to copy this waveform. This loop includes the current sense amplifier averaged output, the AC error amplifier, and the output of the reference multiplier. 1. Check output of reference multiplier. With an oscilloscope, view the waveshape on pins 4 and 5. Pin 4 should copy the waveshape of pin 5. If not, confirm that the AC input (pin 5) does not exceed 4 volts peak, and check the output of the voltage error amplifier per the next step. The waveform on pin 5 (AC input) should be a scaled version of the input haversine after the rectifiers. If it is shifted in phase or does not go to zero, the cap on pin 5 should be reduced in value. Decreasing the value on pin 5 will reduce errors in the reference signal, but also increase the AC ripple (see Figures 2 and 3). 2. Check output of voltage error amplifier. It should be a DC signal. If there is much ripple on it, recheck calculations and components for the compensation network of C7 and R7. If the ripple is random, it could be a noise problem. Check grounding and proximity to high frequency, high voltage/current nodes. If the ripple is at the line frequency reduce loop bandwidth by modifying compensation components on pin 7. It is often helpful to add a small bypass capacitor to this point. Start with a value that is 1/100th of the value of C7. 3. Check average current signal on pins 10 and 11. There should be a small amount of switching frequency ripple (up to several hundred millivolts). If other frequencies are noted determine if it is a constant frequency. Random spacing of peaks indicates noise, repeatable spacing indicates an oscillation. If circuit is oscillating, reduce value of R3 and increase C3 by the same percentage. 4. If the voltage error amplifier and average current signal are both good, harmonics may be reduced by increasing the bandwidth of the AC error amplifier. To do this decrease the value of C3. Be cautious when doing so, to maintain loop stability. If there are oscillations on pins 10 and 11 (see Figure 4), reduce the gain of the current shaping loop by decreasing the value of R3 and increasing the value of C3 by the same percentage. Figure 4. Current Shaping Loop Oscillations Poor Power Factor Poor power factor is caused by two phenomena. One is the distortion of the input current waveform, relative to the input voltage waveform. The other is the phase shift of the input current waveform. Improving the harmonics and THD will improve the power factor due to distortion issues. The input EMI filter can cause poor power factor due to its capacitance, especially at high line. The reason that the power factor suffers at high line is the phase shift due to the combination of the input current to the converter, and the current in the EMI capacitors. The input current to the converter reduces at high line, due to the fact that the unit is essentially a constant power device and as the line voltage increases, the line current must decrease proportionally. The capacitor current increases at high line due to the increased voltage on the capacitors. The following example illustrates this point. For a 1000 watt unit, with an efficiency of 95%, and an input voltage range of 85 to 265 volts, the input current would be: Iinlow = 1000 w/(85 v x .95) = 12.4 amps Iinhigh = 1000 w/(265 v x .95) = 3.97 amps This current is in phase with the input voltage. If we assume a total input capacitance of 8.0 F, and a line frequency of 60 Hz, the reactive current is: Izlow = 85 v x 2 x p x 60 Hz x 8.0 F = .26 amps http://onsemi.com 3 AND8084/D Izhigh = 265 v x 2 x p x 60 Hz x 8.0 F = .80 amps I pk The power factor due to the phase displacement is: IC Qlow = arctan (.26/12.4) = 1.20° t off t on PFlow = cos Q = 1.00 I min T Qhigh = arctan (.80/3.97) = 11.4° VC PFhigh = cos Q = .980 It is recommended that the AC caps be kept as small as possible, while still assuring proper operation, as well as meeting the EMI specifications. One criteria to consider is the value of the capacitance on the AC side of the line vs. the value on the rectified side. The capacitor on the rectified side of the line, will have a DC component associated with it. It should also carry the majority of the high frequency switching current, as opposed to requiring it to flow through the rectifiers. A good starting point is to calculate the allowable high–frequency voltage ripple for this capacitor. The input current will normally be in the continuous conduction mode of operation at low line and full load. The ripple on the input filter capacitor due to this waveform is: Figure 5. Input Capacitor Voltage and Current Waveforms Vc I T 8·C Where: Vc is the capacitor peak–to–peak voltage in volts I is the peak–to–peak ripple current. This can be found on sheet 1 of the NCP1650 design spreadsheet in the “P–P Ripple Current vs. Angle” graph. T is the switching period in seconds C is the capacitance in Farads The capacitor on the AC side of the line should be at least a factor of 2 greater than the capacitor on the rectified side of the line and typically a factor of 5 or more. The capacitor on the rectified side of the line will tend to hold up the voltage at zero crossings, and will contribute to the distortion in the current waveform, whereas, the capacitor on the AC side of the line will help to filter any distortion at the zero crossings, but will cause phase shift. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 4 AND8084/D AND8106/D 100 Watt, Universal Input, PFC Converter ON Semiconductor http://onsemi.com APPLICATION NOTE General Description This 100 watt converter demonstrates the wide range of features found on the NCP1650. This chip is capable of controlling PFC converters well into the kilowatt range. In addition to excellent power factor, this chip offers fixed frequency operation in continuous and discontinuous modes of operation. It has a wide variety of protection features, including instantaneous current limiting, average current limiting, and true power limiting. This unit will provide 400 V of well regulated power from an input source with a frequency range from 50 Hz to 60 Hz, and a voltage range of 85 Vrms to 265 Vrms. It is fully self contained and includes a high voltage start-up circuit, and bias supply that operates off of the boost inductor. Vout 10 k FQP1N60 Vbias 1 F MMSZ5248BT1 Vin Figure 1. Start-Up Circuit Schematic This circuit will provide current as long as the FET is enhanced. For this to occur, the gate to source voltage must be greater than the gate threshold voltage. For this device that value is nominally, 4.0 V. The zener breakdown voltage is 18 V, so the FET will turn off at: Circuit Description Start-Up Circuit The start-up circuit allows the unit to use power from the input line to begin operation, and then shuts down to allow operation off of the bias winding, which reduces losses in the circuit. The start-up circuit has three modes of operation. One is used for starting the NCP1650 when the chip is functional, one is for bias power during shutdown operation, and the third is the off state. When power is initially applied to the unit, the gate of the pass transistor will be high, and the FET will be fully enhanced. The current into the VCC capacitance at pin 1 will be limited by the three 10 k resistors in series with the FET. February, 2003 - Rev. 2 1 NCP1650 Fixed Frequency Operation Shutdown Circuit Operation Over the Universal Input Range Multiple Protection Schemes True Power Limiting Start-Up and Bias Circuits Included Semiconductor Components Industries, LLC, 2003 10 k 1.2 M Features • • • • • • 10 k Vchg max 18 V 4.0 V 14 Volts As the output capacitor is charged up during the turn-on sequence, the bias supply voltage will also increase until the source of the FET exceeds 14 V. At this point, the FET will cease conduction, and all of the VCC power will be supplied via the bias circuit from the power inductor. If the unit is commanded into the shutdown mode, the chip will reduce its bias current to 0.5 mA and the start-up circuit will then maintain a regulated voltage of approximately 14 V on the VCC pin until the device becomes operational. 1 Publication Order Number: AND8106/D 1N5406 L2 D1 F1 470 H D2 0.47 F Vin R4 178 k C7 0.1 F D3 L3 D4 R7 Loop Comp R8 6 PCOMP C26 4V + − Error Amp R22 FQP1N60 Vin Reference Regulator Power + Amp − 2 Reference Multiplier BAS16LT1 D6 1.08 Vref − + Current Shaping Network L1 MUR460 Q1 FQP12N60 R16 4.7 Out Current + Sense Amplifier - Oscillator 12 IS- Gnd 15 Ramp Comp 14 R13 51 k CT 10 Iavg 11 Iavgfltr C14 470 pF C11 R10 8.25 k 470 pF R27 453 k R28 453 k C25 100 F 16 3 C3 13 C23 100 F D7 Control Logic R3 0 V - ON 5 V - OFF 0.1 F UVLO 1 mH AC Comp 810 R25 4.7 k Overshoot Comparator 4 .012 F R26 Vref 0.75 V Power Multiplier 1.0 nF Shutdown C2 − + 5 AC Ref 0.022 F MMBT2222ALT1 12 k 1 Shutdown 9 C9 10 F R23 1.2 M D5 MMSZ5248BT1 Voltage/Power ORing Network AC Input C4 R21 Q2 2.5 V R5 3.57 k R20 1.0 F U1 PMAX 10 F C5 10 k Q3 8 8.2 k R9 56.2 k 10 k 0.07 1/2 W R30 R29 9.09 k AND8106/D 2 http://onsemi.com Figure 1. Applications Circuit Schematic 0.1 F FB/SD C8 10 k 7 C22 22 F R6 178 k C21 C20 470 H 3.3 k SPECIFICATIONS: Line - 85 Vac to 265 Vac Power - 100 Watts Output Voltage - 400 VDC AND8106/D Voltage Regulation Loop If the load is increased to a level that exceeds the maximum power limit of the circuit, the output of the power multiplier will reach 2.5 V and the output of the power error amplifier will go to some level above ground. This signal will then override the signal from the voltage error amplifier (labeled “error amp” on the schematic), and will dominate the OR’ing network. This signal then determines the level of the reference signal out of the reference multiplier, and determines the input current to the power converter. It should be noted that as this is a boost converter, the power limit circuit will only fold back the output voltage until it reaches the level of the peak line voltage. At this point the converter will shut down, but the input voltage will continue to charge the output capacitors through the rectifier. The output voltage is sensed and reduced to the reference level by the resistive divider consisting of R27, R28 and R29. The output voltage of this divider is sensed by the non-inverting input of the error amplifier and compared to the internal 4.0 V reference. Assuming that the unit in not in a power limit condition, the voltage error signal will dominate the loop and be fed through the OR’ing network to provide one of the inputs to the reference multiplier. The other reference multiplier input is the divided down rectified AC input signal. The output of this multiplier is a haversine signal that is an accurate replica of the input AC signal. The current shaping network compares the average current from the current sense amplifier to the reference voltage and forces this current to follow the AC reference voltage. The current out of the current sense amplifier is filtered at a frequency that is less than the switching frequency, but greater than the rectified line frequency. This current is fed into the output filter capacitor(s) that filter it to a DC level. Shutdown Circuit The shutdown circuit will inhibit the operation of the power converter and put the NCP1650 into a low power shutdown mode. To activate this circuit, apply 5.0 V to the red test point, with the black jack being “ground”. Be aware that the black jack is actually hot as it is connected to the output of the input bridge rectifiers. An isolated 5.0 V supply should be used. If this circuit is not being used, the terminals can be left open, as there is enough resistance built in to the circuit to keep the transistor (Q2) in it’s off state. Power Regulation Loop The power multiplier generates the product of the input current (from the current sense amplifier) and the AC rectified input voltage, to generate a signal that represents the input power of the unit. This signal is filtered to a frequency of less than the line frequency, so that it’s output is a DC level. PCB The printed circuit board Gerber files are located on the ON Semiconductor website under the name NCP650- PCB1. D3 D4 Q1 D1 D2 Input 400 Vdc 0.25 amps NCP1650 Demo Board C20 C21 R4 Q3 + ON Semiconductor R20 R21 R22 C23 + R6 D7 L1 R27 R28 R23 L3 R5 L2 R29 Gnd Shutdown 0 V/5 V http://onsemi.com 3 85 - 265 Vac C25 AND8106/D Table 1. Ref Des Part Number Manufacturer C2 Cap, Ceramic, Chip, 0.1 F, 50 V C1608X7R1H104KT TDK C3 Cap, Ceramic, Chip, .012 F, 50 V C1608X7R1H123KT TDK C4 Cap, Ceramic, Chip, 1.0 nF, 50 V C1608X7R1H102K TDK C5 Cap, Ceramic, Chip, 0.022 F, 50 V C1608X7R1H223K TDK C7 Cap, Ceramic, Chip, 22 F, 6.3 V C3225X5R0J226MT TDK C8 Cap, Ceramic, Chip, 10 F, 10 V C3225X5R1A106MT TDK C9 Cap, Ceramic, Chip, 4.7 F, 10 V C3216X5R1A475KT TDK C11 Cap, Ceramic, Chip, 470 pF, 50 V C1608C0G1H471JT TDK C14 Cap, Ceramic, Chip, 470 pF, 50 V C1608C0G1H471JT TDK C20 0.47 F, 275 Vac, X Cap ECQ-U2A474ML Panasonic C21 Cap, Polyprop, 0.1 F, 400 Vdc MKP1841-410-405 Vishay-Sprague C22 Cap, Ceramic, Chip, 0.1 F, 50 V C1608X7R1H104KT TDK C23 100 F, Alum Elect, 25 V ECA-1EM101I Panasonic C25 100 F, Alum Elect, 450 V ECO-S2WP100EX Panasonic C26 Cap, Ceramic, Chip, 1.0 F, 25 V C3216X7R1E105KT TDK 1N5406 ON Semiconductor MMSZ5248BT1 ON Semiconductor D1-D4 Description Diode, Rectifier, 600 V, 3.0 A D5 Diode, Zener, 18 V, Axial Lead D6 Diode, Signal, 75 V, 200 mA, SOT-23 D7 Diode, Ultra-Fast, 600 V, 8.0 A F1 Fuse, 2.0 A, 250 Vac L1 Inductor, 1000 H, 2.4 A Max L2 BAS19LT1 ON Semiconductor MURHF860CT ON Semiconductor 1025TD2A Bussman CTX22-15557 Coiltronics 2.5 A Sat, 100 H Inductor, Diff Mode TSL1315S-101K2R5 TDK L3 2.5 A Sat, 100 H Inductor, Diff Mode TSL1315S-101K2R5 TDK Q1 FET, 10.5 A, 0.7 , 600 V, N-chl FQP12N60 Fairchild Q2 Bipolar Transistor, 50 V MMBT2222ALT1 ON Semiconductor Q3 FET, 1.0 A, 600 V, N-chl FQP1N60 Fairchild R3 Resistor, SMT, 810 CRCW1206810JNTA Vishay R4 Resistor, Axial Lead, 178 k, _ Watt, 1% CMF-55-178K00FKRE Vishay R5 Resistor, Axial Lead, 3.57 k, _ Watt, 1% CMF-55-3K5700FKBF Vishay R6 Resistor, Axial Lead, 178 k, _ Watt, 1% CMF-55-178K00FKRE Vishay R7 Resistor, SMT, 8.6 k CRCW12068K60JNTA Vishay R8 Resistor, SMT, 9.1 k CRCW12069K10JNTA Vishay R9 Resistor, SMT, 56.2 k, 1% CRCW120656K2FKTA Vishay R10 Resistor, SMT, 8.25 k, 1% CRCW12068K2FKTA Vishay R13 Resistor, SMT, 51 k CRCW120651K0JNTA Vishay R16 Resistor, SMT, 10 CRCW1206100JRE4 Vishay R20 Resistor, Axial Lead, 10 k, _ Watt CCF-07-103J Vishay R21 Resistor, Axial Lead, 10 k, _ Watt CCF-07-103J Vishay R22 Resistor, Axial Lead, 10 k, _ Watt CCF-07-103J Vishay R23 Resistor, Axial Lead, 1.2 M, _ Watt CCF-07-125J Vishay R25 Resistor, SMT, 4.7 k CRCW12064K70JNTA Vishay http://onsemi.com 4 AND8106/D Table 1. (continued) Ref Des Description Part Number Manufacturer R26 Resistor, SMT, 12 k CRCW120612K0JNTA Vishay R27 Resistor, Axial Lead, 453 k, _ Watt, 1% CMF-55-453K00FKBF Vishay R28 Resistor, Axial Lead, 453 k, _ Watt, 1% CMF-55-4533F Vishay R29 Resistor, Axial Lead, 9.09 k, _ Watt, 1% CCF-55-9K09FHR362 Vishay R30 1.0 W, 0.07 , 1% Resistor WSL2512R0700FTB Vishay U1 PFC Controller NCP1650 ON Semiconductor NCP1650-PWB1 www.onsemi.com Hardware H1 Printed Circuit Board H2 Connector 171602 Weidmuller H3 Connector 171602 Weidmuller H4 Test Point, Red 5005 Keystone H5 Test Point, Black 5006 Keystone H6 Standoff, 4-40, Alum, Hex, .500 Inches 8403 HH Smith H7 Standoff, 4-40, Alum, Hex, .500 Inches 8403 HH Smith H8 Standoff, 4-40, Alum, Hex, .500 Inches 8403 HH Smith H9 Standoff, 4-40, Alum, Hex, .500 Inches 8403 HH Smith H10 Heatsink, TO-220 590302B03600 Aavid Thermalloy H11 Heatsink, TO-220 590302B03600 Aavid Thermalloy Performance Data Table 2. Vendor Contacts Vendor ON Semiconductor Table 3. Regulation U.S. Phone/Internet 1-800-282-9855 www.onsemi.com/ Line/Load No Load 50 Watts 100 Watts 85 Vrms 405.5 405.1 403.9 115 Vrms 405.6 405.2 404.3 TDK 1-847-803-6100 www.component.tdk.com/ 220 Vrms 405.4 405.5 404.9 Vishay www.vishay.com/ 265 Vrms 438.4 405.5 405 Bussman (Cooper Ind.) 1-888-414-2645 www.cooperet.com/ Coiltronics (Cooper Ind.) 1-888-414-2645 www.cooperet.com/ Fairchild www.fairchildsemi.com/ Panasonic www.eddieray.com/panasonic/ Weidmuller www.weidmuller.com/ Keystone 1-800-221-5510 www.keyelco.com/ HH Smith 1-888-847-6484 www.hhsmith.com/ Aavid Thermalloy www.aavid.com/ http://onsemi.com 5 AND8106/D Table 4. Harmonics and Distortion 115 Vac, 100 Watts 230 Vac, 100 Watts V harmon A harm. % V harmon A harm. % 2nd 0.084 0.03 0.169 0.12 3rd 0.505 2.8 0.722 2.6 5th 0.482 1.3 0.132 4.4 7th 0.168 0.5 0.075 0.17 9th 0.074 0.17 0.133 0.23 11th 0.088 0.13 0.134 0.17 13th 0.212 0.27 0.073 0.15 15th 0.324 0.37 0.265 0.28 17th 0.413 0.35 0.488 0.32 19th 0.632 0.31 1.12 0.44 PF - 0.998 - 0.9928 THD (A) - 3.68 - 6.2 Ifund - 0.919 - 0.451 85 Vrms 115 Vrms 230 Vrms 265 Vrms Pin @ No Load 2.87 4.06 5.07 5.11 Pin 108.8 106.9 103.2 103.7 Vo 403.2 404.3 404.9 405 Io 0.246 0.246 0.243 0.244 Efficiency 0.912 0.930 0.953 0.953 Table 5. Efficiency http://onsemi.com 6 AND8106/D Notes http://onsemi.com 7 AND8106/D ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 8 AND8106/D AND8123/D Power Factor Correction Stages Operating in Critical Conduction Mode Prepared by: Joel Turchi ON Semiconductor http://onsemi.com APPLICATION NOTE Basics of the Critical Conduction Mode Critical conduction mode (or border line conduction mode) operation is the most popular solution for low power applications. Characterized by a variable frequency control scheme in which the inductor current ramps to twice the desired average value, ramps down to zero, then immediately ramps positive again (refer to Figures 2 and 4), this control method has the following advantages: • Simple Control Scheme: The application requires few external components. • Ease of Stabilization: The boost keeps a first order converter and there is no need for ramp compensation. • Zero Current Turn On: One major benefit of critical conduction mode is the MOSFET turn on when the diode current reaches zero. Therefore the MOSFET switch on is lossless and soft and there is no need for a low trr diode. On the other hand, the critical conduction mode has some disadvantages: • Large peak currents that result in high dl/dt and rms currents conducted throughout the PFC stage. • Large switching frequency variations as detailed in the paper. This paper proposes a detailed and mathematical analysis of the operation of a critical conduction mode Power factor Corrector (PFC), with the goal of easing the PFC stage dimensioning. After some words on the PFC specification and a brief presentation of the main critical conduction schemes, this application note gives the equations necessary for computing the magnitude of the currents and voltages that are critical in the choice of the power components. INTRODUCTION The IEC1000−3−2 specification, usually named Power Factor Correction (PFC) standard, has been issued with the goal of minimizing the Total Harmonic Distortion (THD) of the current that is drawn from the mains. In practice, the legislation requests the current to be nearly sinusoidal and in phase with the AC line voltage. Active solutions are the most effective means to meet the legislation. A PFC pre−regulator is inserted between the input bridge and the bulk capacitor. This intermediate stage is designed to output a constant voltage while drawing a sinusoidal current from the line. In practice, the step−up (or boost) configuration is adopted, as this type of converter is easy to implement. One can just notice that this topology requires the output to be higher than the input voltage. That is why the output regulation level is generally set to around 400 V in universal mains conditions. Diode Bridge PFC Stage Power Supply + AC Line + Bulk Capacitor Controller IN LOAD − Figure 1. Power Factor Corrected Power Converter PFC boost pre−converters typically require a coil, a diode and a Power Switch. This stage also needs a Power Factor Correction controller that is a circuit specially designed to drive PFC pre−regulators. ON Semiconductor has developed three controllers (MC33262, MC33368 and MC33260) that operate in critical mode and the NCP1650 for continuous mode applications. One generally devotes critical conduction mode to power factor control circuits below 300 W. Semiconductor Components Industries, LLC, 2003 September, 2003 − Rev. 1 1 Publication Order Number: AND8123/D AND8123/D Diode Bridge Diode Bridge + L Icoil + Icoil L Vin + Vin IN Vout IN − − The power switch is ON The power switch is OFF The coil current flows through the diode. The coil voltage is (Vout −Vin ) and the coil current linearly decays with a (Vout −Vin )/L slope. The power switch being about zero, the input voltage is applied across the coil. The coil current linearly increases with a (Vin /L) slope. Coil Current Vin/L (Vout−Vin)/L Critical Conduction Mode: Next current cycle starts as soon as the core is reset. Icoil_pk Figure 2. Switching Sequences of the PFC Stage levels of the output voltage. The error amplifier bandwidth is set low so that the error amplifier output reacts very slowly and can be considered as a constant within an AC line period. • The controller multiplies the shaping information by the error amplifier output voltage. The resulting product is the desired envelope that as wished, is sinusoidal, in phase with the AC line and whose amplitude depends on the amount of power to be delivered. • The controller monitors the power switch current. When this current exceeds the envelope level, the PWM latch is reset to turn off the power switch. • Some circuitry detects the core reset to set the PWM latch and initialize a new MOSFET conduction phase as soon as the coil current has reached zero. Consequently, when the power switch is ON, the current ramps up from zero up to the envelope level. At that moment, the power switch turns off and the current ramps down to zero (refer to Figures 2 and 4). For simplicity of the drawing, Figure 4 only shows 8 “current triangles”. Actually, their frequency is very high compared to the AC line one. The input filtering capacitor and the EMI filter averages the “triangles” of the coil current, to give: In critical discontinuous mode, a boost converter presents two phases (refer to Figure 2): • The on−time during which the power switch is on. The inductor current grows up linearly according to a slope (Vin/L) where Vin is the instantaneous input voltage and L the inductor value. • The off time during which the power switch is off. The inductor current decreases linearly according to the slope (Vout−Vin)/L where Vout is the output voltage. This sequence terminates when the current equals zero. Consequently, a triangular current flows through the coil. The PFC stage adjusts the amplitude of these triangles so that in average, the coil current is a (rectified) sinusoid (refer to Figure 4). The EMI filter (helped by the 100 nF to 1.0 F input capacitor generally placed across the diodes bridge output), performs the filtering function. The more popular scheme to control the triangles magnitude and shape the current, forces the inductor peak current to follow a sinusoidal envelope. Figure 3 diagrammatically portrays its operation mode that could be summarized as follows: • The diode bridge output being slightly filtered, the input voltage (Vin) is a rectified sinusoid. One pin of the PFC controller receives a portion of Vin. The voltage of this terminal is the shaping information necessary to build the current envelope. • An error amplifier evaluates the power need in response to the error it senses between the actual and wished Icoil T Icoil_pk 2 (eq. 1) where <Icoil>T is the average of one current triangle (period T) and Icoil_pk is the peak current of this triangle. http://onsemi.com 2 AND8123/D As Icoil_pk is forced to follow a sinusoidal envelop (k*Vin), where k is a constant modulated by the error amplifier, <Icoil> T is also sinusoidal Icoil T k * Vin 2 k * 2 * Vac * sin(t) . 2 As a result, this scheme makes the AC line current sinusoidal. PFC Stage Vin L1 D1 Bulk Capacitor Input Filtering Capacitor AC Line + C1 X1 R7 Current Sensing Resistor PWM Latch Zero Current Detection S Output Buffer + − Current Envelope Q R Current Sense Comparator R1 R2 C2 Multiplier Error Amplifier − + R3 Vref R4 Figure 3. Switching Sequences of the PFC Stage The controller monitors the input and output voltages and using this information and a multiplier, builds a sinusoidal envelope. When the sensed current exceeds the envelope level, the Current Sense Comparator resets the PWM latch and the power switch turns off. Once the core has reset, a dedicated block sets the PWM latch and a new MOSFET conduction time starts. http://onsemi.com 3 AND8123/D Peak Icoil_pk Average (<Icoil>T) Inductor Current (Icoil) Tac/2 T (Tac is the AC line period) MOSFET DRIVE Figure 4. Coil Current During the power switch conduction time, the current ramps up from zero up to the envelope level. At that moment, the power switch turns off and the current ramps down to zero. For simplicity of the drawing, only 8 “current triangles” are shown. Actually, their frequency is very high compared to the AC line one. One can note that a simple calculation would show that the on−time is constant over the sinusoid: ton 2 * L * Pin and Vac2 that the switching frequency modulation is brought by the off−time that equals: toff 2 * 2 * L * 2 * Vac * sin(t) Pin * sin(t) ton * Vac * (Vout 2 * Vac * sin(t)) Vout 2 * Vac * sin(t) (eq. 2) That is why the MC33260 developed by ON Semiconductor does not incorporate a multiplier inputting a portion of the rectified AC line to shape the coil current. Instead, this part forces a constant on−time to achieve in a simplest manner, the power factor correction. Main Equations • The power switch off time (toff). During this second phase, the coil current flows through the output diode and feeds the output capacitor and the load. The diode voltage being considered as null when on, the voltage across the coil becomes negative and equal to (Vin−Vout). The coil current decreases then linearly with the slope ((Vout−Vin)/L) from (Icoil_pk) to zero, as follows: Switching Frequency As already stated, the coil current consists of two phases: • The power switch conduction time (ton). During this time, the input voltage applies across the coil and the current increases linearly through the coil with a (Vin/L) slope: Icoil(t) Vin * t L (eq. 3) This phase ends when the conduction time (ton) is complete that is when the coil current has reached its peak value (Icoil_pk). Thus: Icoil_pk Vin * ton L L * Icoil_pk Vin (eq. 6) This phase ends when Icoil reaches zero, then the off−time is given by the following equation: toff (eq. 4) The conduction time is then given by: ton Icoil(t) Icoil_pk Vout Vin * t L L * Icoil_pk Vout Vin (eq. 7) The total current cycle (and then the switching period, T) is the sum of ton and toff. Thus: (eq. 5) T ton toff L * Icoil_pk * http://onsemi.com 4 Vout (eq. 8) Vin * (Vout Vin) AND8123/D 20 As shown in the next paragraph (equation 15), the coil peak current can be expressed as a function of the input power and the AC line rms voltage as follows: Icoil_pk 2 * 2 * Pin * sin(t) , where is the AC Vac T 2 * 2 * L * Pin * sin(t) Vac Vout * 2 * Vac * sin(t) * (Vout Vin) f / f(200W) line angular frequency. Replacing Icoil_pk by this expression in equation (8) leads to: (eq. 9) This equation simplifies: 0 T 2 * L * Pin * Vout Vac2 * (Vout Vin) (eq. 10) 2 * Vac * sin(t) Vac2 1 Vout 2 * L * Pin 2 working point (load and AC line rms voltage). 1 2 * Vac * sin(t) Vout 100 150 200 This plot sketches the switching frequency variations versus the input power in a normalized form where f(200 W) = 1. The switching frequency is multiplied by 20 when the power is 10 W. In practice, the PFC stage propagation delays clamp the switching frequency that could theoretically exceed several megaHertz in very light load conditions. The MC33260 minimum off−time limits the no load frequency to around 400 kHz. (eq. 11) that only varies versus the • One term 2 * L Vac * Pin 50 Figure 6. Switching Frequency vs. the Input Power (at the Sinusoid top) This equation shows that the switching frequency consists of: • A modulation factor 0 Pin (W) The switching frequency is the inverse of the switching period. Consequently: f 10 1.5 that makes the switching frequency vary within the AC line sinusoid. The following figure illustrates the switching frequency variations versus the AC line amplitude, the power and within the sinusoid. 1.0 sin (t) 0.5 2.50 f 2.00 0 0 1.0 2.0 3.0 f / f(90) t Figure 7. Switching Frequency Over the AC Line Sinusoid @ 230 Vac 1.50 This plot gives the switching variations over the AC line sinusoid at Vac = 230 V and Vout = 400 V, in a normalized form where f is taken equal to 1 at the AC line zero crossing. The switching frequency is approximately divided by 5 at the top of the sinusoid. 1.00 0.50 80 110 140 170 200 Vac, (V) 230 260 290 Figure 5. Switching Frequency Over the AC Line RMS Voltage (at the Sinusoid top) The figure represents the switching frequency variations versus the line rms voltage, in a normalized form where f(90) = 1. The plot drawn for Vout = 400 V, shows large variations (200% at Vac = 180 V, 60% at Vac = 270 V). The shape of the curve tends to flatten if Vout is higher. However, the minimum of the switching frequency is always obtained at one of the AC line extremes (VacLL or VacHL where VacLL and VacHL are respectively, the lowest and highest Vac levels). http://onsemi.com 5 AND8123/D 1.5 Provided that the AC line current results from the averaging of the coil current, one can deduct the following equation: 1.0 lin(t) Icoil T sin (t) Icoil_pk 2 * 2 * lac * sin(t) 0 0 1.0 (eq. 13) where <Icoil>T is the average of the considered coil current triangle over the switching period T and Icoil_pk is the corresponding peak. Thus, the peak value of the coil current triangles follows a sinusoidal envelope and equals: f 0.5 Icoil_pk 2 2.0 Since the PFC stage forces the power factor close to 1, one can use the well known relationship linking the average input power to the AC line rms current and rms voltage ( Pin Vac * lac) and the precedent equation leads to: 3.0 t Figure 8. Switching Frequency Over the AC Line Sinusoid @ 90 Vac Icoil_pk 2 * 2 * Pin * sin(t) Vac This plot shows the same characteristic but for Vac = 90 V. Similarly to what was observed in Figure 5 (f versus Vac), the higher the difference between the output and input voltages, the flatter the switching frequency shape. (eq. 15) The coil current peak is maximum at the top of the sinusoid where sin( t) 1. This maximum value, (Icoil_pk)H, is then: Finally, the switching frequency dramatically varies within the AC line and versus the power. This is probably the major inconvenience of the critical conduction mode operation. This behavior often makes tougher the EMI filtering. It also can increase the risk of generating interference that disturb the systems powered by the PFC stage (for instance, it may produce some visible noise on the screen of a monitor). In addition, the variations of the frequency and the high values it can reach (up to 500 kHz) practically prevent the use of effective tools to damp EMI and reduce noise like snubbing networks that would generate too high losses. One can also note that the frequency increases when the power diminishes and when the input voltage increases. In light load conditions, the switching period can become as low as 2.0 s (500 kHz). All the propagation delays within the control circuitry or the power switch reaction times are no more negligible, what generally distorts the current shape. The power factor is then degraded. The switching frequency variation is a major limitation of the system that should be reserved to application where the load does not vary drastically. (Icoil_pk)H 2 * 2 * Pin Vac (eq. 16) From this equation, one can easily deduct that the peak coil current is maximum when the required power is maximum and the AC line at its minimum voltage: Icoil_max 2 * 2 * Pin max VacLL (eq. 17) where <Pin>max is the maximum input power of the application and VacLL the lowest level of the AC line voltage. Coil RMS Current The rms value of a current is the magnitude that squared, gives the dissipation produced by this current within a 1.0 resistor. One must then compute the rms coil current by: • First calculating the “rms current” within a switching period in such a way that once squared, it would give the power dissipated in a 1.0 resistor during the considered switching period. • Then the switching period being small compared to the input voltage cycle, regarding the obtained expression as the instantaneous square of the coil current and averaging it over the rectified sinusoid cycle, to have the squared coil rms current. This method will be used in this section. As above explained, the current flowing through the coil is: • (IM(t) Vin * tL Icoil_pk * tton) during the MOSFET on−time, when 0<t<ton. Coil Peak and RMS Currents Coil Peak Current As the PFC stage makes the AC line current sinusoidal and in phase with the AC line voltage, one can write: lin(t) 2 * lac * sin(t) (eq. 14) (eq. 12) where Iin(t) is the instantaneous AC line current and Iac its rms value. • (ID(t) Icoil_pk−(Vout−Vin) * tL Icoil_pk * (T t) (T ton) ) during the diode conduction time, that is, when ton<t<T. http://onsemi.com 6 AND8123/D Therefore, the rms value of any coil current triangle over the corresponding switching period T, is given by the following equation: (Icoil)rms T 1* T 2 T 2 Icoil_pk * t * dt Icoil_pk * T t * dt ton T ton ton 0 ton (eq. 18) Solving the integrals, it becomes: (Icoil)rms T (eq. 19) 1* T The precedent simplifies as follows: (Icoil)rms T 1 * Icoil_pk2 * ton (T ton) * ( Icoil_pk3) 3 T 3 * Icoil_pk Rearrangement of the terms leads to: (Icoil)rms T Icoil_pk * 1 * ton T ton 3 3 T (Icoil)rms T Icoil_pk 3 (eq. 22) Replacing the coil peak current by its expression as a function of the average input power and the AC line rms voltage (equation 15), one can write the following equation: Pin * sin(t) 23 * Vac (eq. 20) gives the resistive losses at this given Vin. Now to have the rms current over the rectified AC line period, one must not integrate <(Icoil)rms>T but the square of it, as we would have proceeded to deduct the average resistive losses from the dissipation over one switching period. However, one must not forget to extract the root square of the result to obtain the rms value. As the consequence, the coil rms current is: (eq. 21) Calculating the term under the root square sign, the following expression is obtained: (Icoil)rms T 2 * 3 Icoil_pk * TTtonT 3 Icoil_pk * TT ton ton Icoil_pk2 ton3 (T ton) * * 3 3 * Icoil_pk ton2 (Icoil)rms (eq. 24) 2 * Tac Tac2 0 (Icoil)rms T 2 * dt where Tac = 2*/ is the AC line period (20 ms in Europe, 16.66 ms in USA). The PFC stage being fed by the rectified AC line voltage, it operates at twice the AC line frequency. That is why, one integrates over half the AC line period (Tac/2). (eq. 23) This equation gives the equivalent rms current of the coil over one switching period, that is, at a given Vin. As already stated, multiplying the square of it by the coil resistance, Substitution of equation (23) into the precedent equation leads to: (Icoil)rms 2 * Tac Tac2 0 2* Pin * sin(t), 23 * Vac 2 * dt Icoil(rms) 2 * Pin 3 Vac that is, the rms value of a sinusoidal current whose magnitude is (2 * (eq. 25) Therefore: This equation shows that the coil rms current is the rms value of: 2 * 2 * Pin * sin(t) 3 Vac Pin ). The rms value of such a sinusoidal 23 * Vac current is well known (the amplitude divided by 2). http://onsemi.com 7 (eq. 26) AND8123/D • The output voltage is considered as a constant. The Switching Losses The switching losses are difficult to determine with accuracy. They depend of the MOSFET type and in particular of the gate charge, of the controller driver capability and obviously of the switching frequency that varies dramatically in a critical conduction mode operation. However, one can make a rough estimation if one assumes the following: • output voltage ripple being generally less than 5% the nominal voltage, this assumption seems reasonable. The switching times (t and tFR, as defined in Figure 9), are considered as constant over the sinusoid. Dissipated Power: (IMOSFET * Vdrain) tFR IMOSFET Vdrain t Figure 9. Turn Off Waveforms (eq. 27) Figure 9 represents a turn off sequence. One can observe three phases: • During approximately the second half of the gate voltage Miller plateau, the drain−source voltage increases linearly till it reaches the output voltage. • During a short time that is part of the diode forward recovery time, the MOSFET faces both maximum voltage and current. • The gate voltage drops (from the Miller plateau) below the gate threshold and the drain current ramps down to zero. psw Vout * 2Icoil_pk * t−tTFR Vout * Icoil_pk * tFRT where: t and tFR are the switching times portrayed by Figure 9 and T is the switching period. Equation (8) gives an expression linking the coil peak current and the switching period of the considered current cycle (triangle): T L * Icoil_pk Vout * . Vin Vout Vin Substitution of equation (8) into the equation (27) leads to: “t” of Figure 9 represents the total time of the three phases, “tFR’’ the second phase duration. Therefore, one can write: psw http://onsemi.com 8 Vin * (Vout Vin) * (t tFR) 2*L (eq. 28) AND8123/D (eq. 29) This equation shows that the switching losses over a switching period depend of the instantaneous input voltage, the difference between the instantaneous output and input voltages, the switching time and the coil value. Let’s calculate the average losses (<psw>) by integrating psw over half the AC line period: Rearranging the terms, one obtains: psw t tFR * 2*L 2 * Tac psw 2 * Tac Tac2 Vin * Vout * dt 0 Vout being considered as a constant, one can easily solve this equation if one remembers that the input voltage average value is (2 * 2 * Vac) and that (Vac2 2 * Tac Tac2 Vin2 * dt). Applying this, it becomes: • 0 (eq. 31) 2 * Tac Tac2 Vin2 * dt 0 (eq. 30) Q3 being not always specified, instead, one can take the sum of Q1 with half the Miller plateau gate charge (Q2/2). Knowing the drive capability of the circuit, one can deduct the turn off time (t = Q3/Idrive or t = [Q1 + (Q2/2)]/Idrive). In a first approach, tFR can be taken equal to the diode forward recovery time. VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0 Vin * (Vout Vin) * (t tFR) * dt 2*L 12 Or in a simpler manner: 2 * (t tFR) * Vac2 Vout psw * 2 * Vac 4 *L (eq. 32) The coil inductance (L) plays an important role: the losses are inversely proportional to this value. It is simply because the switching frequency is also inversely proportional to L. This equation also shows that the switching losses are independent of the power level. One could have easily predict this result by simply noting that the switching frequency increased when power diminished. Equation (32) also shows that the lower the ratio (Vout/Vac), the smaller the MOSFET switching losses. That is because the “Follower Boost” mode that reduces the difference between the output and input voltages, lowers the switching frequency. In other words, this technique enables the use of a smaller coil for the same switching frequency range and the same switching losses. For instance, the MC33260 features the “Follower Boost” operation where the pre−converter output voltage stabilizes at a level that varies linearly versus the AC line amplitude. This technique aims at reducing the gap between the output and input voltages to optimize the boost efficiency and minimize the cost of the PFC stage 1. How to extract t and tFR? • The best is to measure them. • One can approximate t as the time necessary to extract the gate charge Q3 of the MOSFET (refer to Figure 10). QT VDS 9 VGS 6 Q2 Q1 3 ID = 2.3 A TJ = 25°C Q3 0 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) t tFR 2 * 2 * Vac * Vout psw * Vac2 2*L Tac2 QT, TOTAL GATE CHARGE (nC) Figure 10. Typical Total Gate Charge Specification of a MOSFET One must note that the calculation does not take into account: • The energy consumed by the controller to drive the MOSFET (Qcc*Vcc*f), where Qcc is the MOSFET gate charge necessary to charge the gate voltage to Vcc, Vcc the driver supply voltage and f the switching frequency. • The energy dissipated because of the parasitic capacitors of the PFC stage. Each turn on produces an abrupt voltage change across the parasitic capacitors of the MOSFET drain−source, the diode and the coil. This results in some extra dissipation across the MOSFET (1/2*Cparasitic*V2*f), where Cparasitic is the http://onsemi.com 9 AND8123/D considered parasitic capacitor and V the voltage change across it. 1 Power MOSFET Conduction Losses As portrayed by Figure 4, the coil current is formed by high frequency triangles. The input capacitor together with the input RFI filter integrates the coil current ripple so that the resulting AC line current is sinusoidal. During the on−time, the current rises linearly through the power switch as follows: Refer to MC33260 data sheet for more details at http://www.onsemi.com/. However, equation (32) should give a sufficient first approach approximation in most applications where the two listed sources of losses play a minor role. Nevertheless, the losses produced by the parasitic capacitors may become significant in light load conditions where the switching frequency gets high. As always, bench validation is key. Icoil(t) Vin * t L (eq. 33) where Vin is the input voltage (Vin 2 * Vac * sin(t) ), L is the coil inductance and t is the time. During the rest of the switching period, the power switch is off. The conduction losses resulting from the power dissipated by Icoil during the on−time, one can calculate the power during the switching period T as follows: ton pT 1 * T ton Ron * Icoil(t)2 * dt 1 * T 0 where Ron is the MOSFET on−time drain source resistor, ton is the on−time. Solving the integral, equation (34) simplifies as follows: (eq. 34) One can calculate the duty cycle (d = ton/T) by: • 2 ton 2 3 pT Ron * Vin * t2 * dt 1 * Ron * Vin * ton 3 T L L T 0 As the coil current reaches its peak value at the end of the on−time, Icoil_pk Vin * tonL and the precedent equation can be rewritten as follows: pT 1 * Ron * Icoil_pk2 * ton 3 T • Either noting that the off−time (toff) can be expressed as (eq. 35) 0 2 Ron * Vin * t * dt L a function of ton (refer to equation 2) and substituting this equation into (T = ton + Toff), Or considering that the critical conduction mode being at the border of the continuous conduction mode (CCM), the expression giving the duty−cycle in a CCM boost converter applies. Both methods lead to the same following result: d ton 1 Vin T Vout (eq. 36) (eq. 37) Substitution of equation (37) into equation (36) leads to: One can recognize the traditional equation permitting to calculate the MOSFET conduction losses in a boost or a pT 1 * Ron * Icoil_pk2 * 1 Vin 3 Vout flyback ( 1 * Ron * Ipk2 * d, where Ipk is the peak current and 3 (eq. 38) One can note that the coil peak current (Icoil_pk) that follows a sinusoidal envelop, can be written as follows: d, the MOSFET duty cycle). Icoil_pk 2 * 2 * Pin * sin(t) (refer to equation 15). Vac Replacing Vin and Icoil_pk by their sinusoidal expression, respectively (2 * Vac * sin(t) ) and (2 * 2 * Pin * sin(t) ), Vac equation (38) becomes: 2 * Vac * sin(t) 2 pT 1 * Ron * 2 * 2 * Pin * sin(t) * 1 3 Vout Vac That is in a more compact form: 2 * Vac 2 pT 8 * Ron * Pin * sin 2(t) * sin 3(t) 3 Vout Vac (eq. 39) (eq. 40) Equation (40) gives the conduction losses at a given Vin voltage. This equation must be integrated over the rectified AC line sinusoid to obtain the average losses: 2 p Tac 8 * Ron * Pin * 2 * 3 Vac Tac Tac2 0 sin 2(t) http://onsemi.com 10 2 * Vac * sin 3(t) Vout * dt (eq. 41) AND8123/D If the average value of sin2(t) is well known (0.5), the calculation of <sin3(t)> requires few trigonometry remembers: • sin 2() • sin() * cos() sin( ) sin( ) 2 Combining the two precedent formulas, one can obtain: 1 cos(2) 2 sin 3(t) 3 * sin(t) sin(3t) 4 4 (eq. 42) Substitution of equation 42) into equation (41) leads: 2 p Tac 8 * Ron * Pin * 2 * 3 Tac Vac Tac2 0 sin(t)2 Solving the integral, it becomes: 2 * Vac 3 * 2 * Vac * sin(t) * sin(3t) 4 * Vout 4 * Vout 2 * Vac 2 2 3 * 2 * Vac 2 p Tac 8 * Ron * Pin * 1 * * 2 3 Vac 4 * Vout 4 * Vout 3 Equation (44) simplifies as follows: 2 8 * 2 * Vac p Tac 4 * Ron * Pin * 1 3 3 * Vout Vac This formula shows that the higher the ratio (Vac/Vout), the smaller the MOSFET conduction losses. That is why the “Follower Boost” mode that reduces the difference between the output and input voltages, enables to reduce the MOSFET size. For instance, the MC33260 features the “Follower Boost” operation where the pre−converter output voltage stabilizes at a level that varies linearly versus the AC line amplitude. This technique aims at reducing the gap between the output and input voltages to optimize the boost efficiency and minimize the cost of the PFC stage2. By the way, one can deduct from this equation the rms current ((IM)rms) flowing through the power switch knowing that p Tac Ron * (IM)2rms : (IM)rms 2 * Pin * 3 Vac 1 8 * 2 * Vac 3 * Vout * dt (eq. 44) (eq. 45) The MC33260 monitors the whole coil current by monitoring the voltage across a resistor inserted between ground and the diodes bridge (negative sensing – refer to Figure 15). The circuit utilizes the current information for both the overcurrent protection and the core reset detection (also named zero current detection). This technique brings two major benefits: • No need for an auxiliary winding to detect the core reset. A simple coil is sufficient in the PFC stage. • The MC33260 detects the in−rush currents that may flow at start−up or during some overload conditions and prevents the power switch from turning on in that stressful condition. The PFC stage is significantly safer. Some increase of the power dissipated by the current sense resistor is the counter part since the whole current is sensed while circuits like the MC33262 only monitor the power switch current. (eq. 46) Dissipation of the Current Sense Resistor in MC33262 Like Circuits Dissipation within the Current Sense Resistor PFC controllers monitor the power switch current either to perform the shaping function or simply to prevent it from being excessive. That is why a resistor is traditionally placed between the MOSFET source and ground to sense the power switch current. 2 (eq. 43) Since the same current flows through the current sense resistor and the power switch, the calculation is rather easy. One must just square the rms value of the power switch current (IM)rms calculated in the previous section and multiply the result by the current sense resistance. Refer to MC33260 data sheet for more details at http://www.onsemi.com/. http://onsemi.com 11 AND8123/D Doing this, one obtains: 2 8 * 2 * Vac pRs 262 4 * Rs * Pin * 1 3 3 * Vout Vac (eq. 47) where <pRs>262 is the power dissipated by the current sense resistor Rs. Dissipation of the Current Sense Resistor in MC33260 Like Circuits current at the switching period level and then to integrate the obtained result over the AC line sinusoid. As portrayed by Figure 4, the coil discharges during the off time. More specifically, the current decays linearly through the diode from its peak value (Icoil_pk) down to zero that is reached at the end of the off−time. Taking the beginning of the off−time as the time origin, one can then write: In this case, the current sense resistor Rs derives the whole coil current. Consequently, the product of Rs by the square of the rms coil current gives the dissipation of the current sense resistor: pRs 260 Rs * (Icoil(rms) )2 (eq. 48) where Icoil(rms) is the coil rms current that as expressed by Icoil(t) Icoil_pk * toff−t toff equation (26), equals: Icoil(rms) 2 * Pin . 3 Vac Similarly to the calculation done to compute the coil rms current, one can calculate the “diode rms current over one switching period”: Consequently: 2 (eq. 49) pRs 260 4 * Rs * Pin 3 Vac (eq. 50) Id(rms)T Id(rms)T 2 * pRs 262 pRs 260 1 0.85 * Vm (eq. 51) Vout (eq. 57) Pin * toff * sin(t) 23 * Vac T (eq. 58) In addition, one can easily show that toff and T are linked by the following equation: where Vm is the AC line amplitude. 2 * Vac * sin(t) toff T * Vin T * Vout Vout Average and RMS Current through the Diode The diode average current can be easily computed if one notes that it is the sum of the load and output capacitor currents: (eq. 59) Consequently, equation (58) can be changed into: (eq. 52) Id(rms)T Then, in average: 3 2 * 2 * 2 Pin * * sin(t) (eq. 60) 3 Vac * Vout This equation gives the equivalent rms current of the diode over one switching period, that is, at a given Vin. As already stated in the Coil Peak and RMS Currents section, the square of this expression must be integrated over a rectified sinusoid period to obtain the square of the diode rms current. Therefore: (eq. 53) Id Iload ICout Iload ICout At the equilibrium, the average current of the output capacitor must be 0 (otherwise the capacitor voltage will be infinite). Thus: Id Iload Pout Vout 3toff* T * Icoil_pk Substitution of equation (15) that expresses Icoil_pk, into the precedent equation leads to: If one considers that (8/3 ) approximately equals 0.85, the precedent equation simplifies: Id Iload ICout (eq. 56) Solving the integral, one obtains the expression of the “rms diode current over one switching period”: One obtains: toff 2 Id(rms)2T 1 * Icoil_pk * toff−t * dt T 0 toff Comparison of the Losses Amount in the Two Cases Let’s calculate the ratios: pRs 262 pRs 260 . 8 * 2 * Vac pRs 262 pRs 260 1 3 * Vout (eq. 55) (eq. 54) The rms diode current is more difficult to calculate. Similarly to the computation of the rms coil current for instance, it is necessary to first compute the squared rms Tac2 Id(rms)2 2 * Tac http://onsemi.com 12 0 (eq. 61) 8 * 2 Pin 2 * * sin 3(t) * dt 3 Vac * Vout AND8123/D Similarly to the Power MOSFET Conduction Losses section, the integration of (sin3 (t)) requires some preliminary trigonometric manipulations: sin 3(t) sin(t) * sin 2(t) sin(t) * 1 cos(2t) 12 * sin(t) 12 * sin(t) * cos(2t) 2 And : sin(t) * cos(2t) 1 * (sin(−t) sin(4t) ) 2 Then : sin 3(t) 3 * sin(t) 1 * sin(3t) 4 4 Consequently, equation (61) can change into: Tac2 Id(rms)2 2 * Tac One can now solve the integral and write: 0 3 * sin(t) sin(3t) 8 * 2 Pin2 * * * dt 4 3 4 Vac * Vout (eq. 62) 16 * 2 Pin 2 3 * (cos(0) cos(Tac2) ) cos(3Tac2) cos(30) Id(rms)2 * * 12 4 3 * Tac Vac * Vout As ( * Tac 2), we have: cos()−1 3 * (1− cos() ) 16 * 2 Pin2 Id(rms)2 * * 3 Vac * Vout 12 * Tac 4 * Tac One can simplify the equation replacing the cosine elements by their value: (eq. 63) (eq. 64) Thus: (eq. 71) 16 * 2 Pin 2 (eq. 65) Id(rms)2 * * 6 1 3 Vac * Vout 8 * 12 * Ic(rms)2 I1(rms)2 I2(rms)2 4 * Tac Tac2 I1 * I2 * dt 0 The square of the diode rms current simplifies as follows: 32 * 2 Pin 2 Id(rms)2 * 9 * Vac * Vout PFC Stage (eq. 66) L Finally, the diode rms current is given by: Id(rms) 4 * 3 2 * 2 * Pin Vac * Vout Vin I1 Load DRV As shown by Figure 11, the capacitor current results from the difference between the diode current (I1) and the current absorbed by the load (I2): One knows the first term (I1(rms)2). This is the diode rms current calculated in the previous section. The second and third terms are dependent of the load. One cannot compute them without knowing the characteristic of this load. Anyway, the second term (I2(rms)2) is generally easy to calculate once the load is known. Typically, this is the rms current absorbed by a downstream converter. On the other hand, the third term is more difficult to determine as it depends on the relative occurrence of the I1 and I2 currents. As the PFC stage and the load (generally a switching mode power supply) are not synchronized, this term even seems impossible to predict. One can simply note that this term tends to decrease the capacitor rms current and consequently, one can deduct that: (eq. 68) Tac2 (I1 I2)2 * dt (eq. 69) 0 Rearranging (I1−I2)2 leads to: Ic(rms)2 2 * Tac Tac2 Power Switch Figure 11. Output Capacitor Current Thus, the capacitor rms current over the rectified AC line period, is the rms value of the difference between I1 and I2 during this period. As a consequence: Ic(rms)2 2 * Tac I2 Ic (eq. 67) Output Capacitor RMS Current Ic(t) I1(t) I2(t) Vout D (eq. 70) [I12 I22 (2 * I1 * I2)] * dt 0 Ic(rms) I1(rms)2 I2(rms)2 http://onsemi.com 13 (eq. 72) AND8123/D Substitution of equation (67) that gives the diode rms current into the precedent equation leads to: Ic(rms) Pin 2 329 ** 2* * I2(rms)2 Vac * Vout where I2(rms) is the load rms current. (eq. 73) If the load is resistive, I2 = Vout/R where R is the load resistance and equation (71) changes into: 2 Ic(rms)2 1(rms)2 Vout 4 * Tac R Tac2 0 1 * Vout * dt R (eq. 74) Thus, the capacitor squared rms current is: 2 2 * Vout Ic(rms)2 Id(rms)2 Vout * Id R R (eq. 75) 2 32 * 2 Pin 2 * Vout 2 * Vout * Pout Ic(rms)2 Vout R R 9 * Vac * Vout (eq. 76) As Pout = Vout2/R, the precedent equation simplifies as follows: Ic(rms) 2 32 * 2 Pin 2 * Vout 9 * Vac * Vout R You may find a more friendly expression in the literature: (eq. 77) This explanation assumes that the energy that is fed by the PFC stage perfectly matches the energy drawn by the load over each switching period so that one can consider that the capacitive part of the bulk has a constant voltage and that only the ESR creates some ripple. In fact, there is an additional low frequency ripple which is inherent to the Power Factor Correction. The input current and voltage being sinusoidal, the power fed by the PFC stage has a squared sinusoid shape. On the other hand, the load generally draws a constant power. As a consequence, the PFC pre−converter delivers an amount of power that matches the load demand in average only. The output capacitor compensates the lack (excess) of input power by supplying (storing) the part of energy necessary for the instantaneous matching. Figures 13 and 14 sketch this behavior. Ic(rms) I2 , where I2 is the load current. This equation is 2 an approximate formula that does not take into account the switching frequency ripple of the diode current. Only the low frequency current that generates the low frequency ripple of the bulk capacitor (refer to the next section) is considered (this expression can easily be found by using equation (88) and computing Ibulk Cbulk * dVoutdt ). Equation (77) takes into account both high and low frequency ripples. Output Voltage Ripple The output voltage (or bulk capacitor voltage) exhibits two ripples. The first one is traditional to Switch Mode Power Supplies. This ripple results from the way the output is fed by current pulses at the switching frequency pace. As bulk capacitors exhibit a parasitic series resistor (ESR – refer to Figure 12), they cannot fully filter this pulsed energy source. More specifically: • During the on−time, the PFC MOSFET conducts and no energy is provided to the output. The bulk capacitor feeds the load with the current it needs. The current together with the ESR resistor of the bulk capacitor form a negative voltage –(ESR*I2), where I2 is the instantaneous load current, • During the off−time, the diode derives the coil current towards the output and the current across the ESR becomes ESR*(Id−I2), where Id is the instantaneous diode current. PFC Stage Id Vin I2 Load Ic Driver ESR Bulk Capacitor Figure 12. ESR of the Output Capacitor http://onsemi.com 14 AND8123/D 400 V Vout (5 V/div) *Pin (40 W/div) Load Power (100 W) Vin (100 V/div) 0V Figure 13. Output Voltage Ripple The dashed black line represents the power that is absorbed by the load. The PFC stage delivers a power that has a squared sinusoid shape. As long as this power is lower than the load demand, the bulk capacitor compensates by supplying part of the energy it stores. Consequently the output voltage decreases. When the power fed by the PFC pre−converter exceeds the load consumption, the bulk capacitor recharges. The peak of the PFC power is twice the load demand. Vout (5 V/div) 400 V Ic (200 mA/div) 0A Vin (100 V/div) 0V Figure 14. Output Voltage Ripple The output voltage equals its average value when the input voltage is minimum and maximum. The output voltage is lower than its average value during the rising phase of the input voltage and higher during the input voltage decay. Similarly to the input power and voltage, the frequency of the capacitor current (represented in the case of a resistive load) is twice the AC line one. http://onsemi.com 15 AND8123/D In this calculation, one does not consider the switching ripple that is generally small compared to the low frequency ripple. In addition, the switching ripple depends on the load current shape that cannot be predicted in a general manner. As already discussed, the average coil current over a switching period is: lin 2 * Pin * sin(t) Vac The instantaneous input power (averaged over the switching period) is the product of the input voltage (2 * Vac * sin( t) ) by Iin. Consequently: Pin 2 * Pin * sin 2(t) (eq. 79) In average over the switching period, the bulk capacitor receives a charge current ( * PinVout) , where is the PFC stage efficiency, and supplies the averaged load current I2 * Pin Vout. Applying the famous “capacitor formula” I C * dVdt, it becomes: (eq. 78) * Pin I2 Cbulk * dVout Vout dt Substitution of equation (79) into equation (80) leads to: (eq. 81) 2 * Pin * sin(2t) Vout 1 Vout Cbulk * * Vout 2 (eq. 84) dVout 1 * 2 * * Pin * sin 2(t) * Pin Vout Vout dt Cbulk Rearranging the terms of this equation, one can obtain: * Pin Vout * dVout * 2 * sin 2(t) 1 (eq. 82) dt Cbulk d(Vout2) 2 * Vout * dVout and that Noting that dt dt cos(2t) 1−2 * sin 2(t), one can deduct the square of the (eq. 80) Thus: (eq. 85) Vout Vout Vout output voltage from the precedent equation: * Pin * sin(2t) 1 Cbulk * * Vout 2 Where Vout is the instantaneous output voltage ripple. Equation (85) can be rearranged as follows: − * Pin Vout2 Vout 2 * sin(2t) (eq. 83) Cbulk * where <Vout> is the average output voltage. Dividing the terms of the precedent equations by the square of the average output voltage, it becomes: Vout Vout * 1 (eq. 86) * Pin * sin(2t) 1 Cbulk * * Vout 2 One can simplify this equation considering that the output voltage ripple is small compared to the average output voltage (fortunately, it is generally true). This leads to say that the term words, that 1 * Pin * sin(2t) Cbulk is small compared to 1. Thus, one can write that: * * Vout 2 * Pin * sin(2t) Pin * sin(2t) 1 Cbulk 11* 2 2 * * Vout Cbulk * * Vout 2 http://onsemi.com 16 * Pin * sin(2t) 1 Cbulk * * Vout 2 is nearly zero or in other (eq. 87) AND8123/D Conclusion Substitution of equation (86) into equation (87), leads to the simplified ripple expression that one can generally find in the literature: Compared to traditional switch mode power supplies, one faces an additional difficulty when trying to predict the currents and voltages within a PFC stage: the sinusoid modulation. This is particularly true in critical conduction mode where the switching ripple cannot be neglected. As proposed in this paper, one can overcome this difficulty by: • First calculating their value within a switching period, • Then the switching period being considered as very small compared to the AC line cycle, integrating the result over the sinusoid period. The proposed theoretical analysis helps predict the stress faced by the main elements of the PFC stages: coil, MOSFET, diode and bulk capacitor, with the goal of easing the selection of the power components and therefore, the PFC implementation. Nevertheless, as always, it cannot replace the bench work and the reliability tests necessary to ensure the application proper operation. − * Pin * sin(2t) (eq. 88) 2 * Cbulk * * Vout The maximum ripple is obtained when (sin(2 t) −1) and minimum when (sin(2t) 1) . Thus, the peak−to−peak Vout ripple that is the difference of these two values is: (Vout)pk−pk * Pin (eq. 89) Cbulk * * Vout And: Vout Vout (Vout)pk−pk * sin(2t) (eq. 90) 2 http://onsemi.com 17 AND8123/D Peak Coil Current: Icoil_pk 2 * 2 * Pin * sin(t) Vac Switching Frequency: f Maximum Peak Current: Icoil_max 2 * 2 * Pin max VacLL 2 * Vac * sin(t) Vac2 1 Vout 2 * L * Pin Switching Losses: psw RMS Coil Current: Icoil(rms) 2 * Pin 3 Vac 2 * (t tFR) * Vac2 Vout * 2 * Vac 4 *L Conduction Losses: 2 Pon 4 * Ron * Pin * 3 Vac 1 8 * 2 * Vac 3 * Vout Average Diode Current: Id Iload Pout Vout RMS Diode Current: Id(rms) 4 * 3 2 *2 * Pin Vac * Vout L1 D6 CONTROLLER M1 AC Line Iload Vout + C1 LOAD R7 R5 Capacitor Low Frequency Ripple: (Vout)pk−pk MC33260 like Current Sense Resistor (Rs = R5) Dissipation: RMS Capacitor Current: 2 pRs 260 4 * Rs * Pin 3 Vac Ic(rms) MC33262 like Current Sense Resistor (Rs = R7) Dissipation: 2 pRs 262 4 * Rs * Pin * 3 Vac Vac: AC line rms voltage VacLL: Vac lowest level : AC line angular frequency <Pin>: Average input power <Pin>max: Maximum pin level * Pin Cbulk * * Vout 8 * 2 * Vac 1 3 * Vout 32 * 2 * Pin 2 Iload(rms) 2 9 * * Vac * Vout If load is resistive: Vout: Output voltage Pout: Output power Iload: Load current Iload(rms): RMS load current : Efficiency Figure 15. Summary http://onsemi.com 18 Ic(rms) 2 32 * 2 Pin 2 * Vout R 9 * Vac * Vout Ron: MOSFET on resistance t, tFR: Switching times (see Switching Losses section and Figure 10) Cbulk = C1: Bulk capacitor value Rs: Current sense resistance L: Coil inductance AND8123/D Notes http://onsemi.com 19 AND8123/D ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 20 For additional information, please contact your local Sales Representative. AND8123/D

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