PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Product Description The KXSD9 is a tri-axis silicon micromachined accelerometer with a user selectable full-scale output range of ±2g, ±4g, ±6g or ±8g. The sense element is fabricated using Kionix’s proprietary plasma micromachining process technology. Acceleration sensing is based on the principle of a differential capacitance arising from acceleration-induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process variation, temperature, and environmental stress. The sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. A separate ASIC device packaged with the sense element provides signal conditioning, self-test, and temperature compensation. The accelerometer is delivered in a 3 x 3 x 0.9 mm LGA plastic package operating from a 1.8 – 3.6V DC supply. Either I2C or SPI interfaces can be used to communicate to the chip to trigger A/D conversions or manage power consumption. Functional Diagram X Sensor Y Sensor Charge Amp Z Sensor Temp Sensor LPF Vdd 5 A/D SPI/I 2C Motion Detection IO Vdd 1 3 AUX IN GND 4 6 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] 8 9 10 7 © 2009 Kionix – All Rights Reserved 091012-01 Page 1 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Product Specifications Table 1. Mechanical (specifications are for operation at 3.3V and T = 25C unless stated otherwise) Parameters Min Typical ºC -40 - 85 Zero-g Offset counts 1843 2048 2253 Zero-g Offset Variation from RT over Temp. mg/ºC Operating Temperature Range 1 Sensitivity Units Max 0.5 (xy) 3 (z) FS1=1, FS0=1 (± 2g) 794 819 844 FS1=1, FS0=0 (± 4g) 390 410 430 257 273 289 189 205 221 FS1=0, FS0=1 (± 6g) counts/g FS1=0, FS0=0 (± 8g) Sensitivity Variation from RT over Temp. Offset Ratiometric Error (Vdd = 3.3V ± 5%) 0.01 (xy) 0.04 (z) %/ºC % 0.3 Sensitivity Ratiometric Error (Vdd = 3.3V ± 5%) % 1.1 (xy) 0.6 (z) Self Test Output change on Activation g Mechanical Resonance (-3dB)2 Non-Linearity Cross Axis Sensitivity Noise Density (on filter pins) 1.1 0.03 1.5 (xy) 0.5 (z) Hz 4000 (xy) 2000 (z) % of FS 0.1 % 2 µg / √Hz 750 1.9 1.1 Notes: 1. User selectable from CTRL_REGC 2. Resonance as defined by the dampened mechanical sensor. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 2 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Table 2. Electrical (specifications are for operation at 3.3V and T = 25C unless stated otherwise) Parameters Supply Voltage (Vdd) Operating Units Min Typical Max V 1.8 1.7 3.3 3.6 Vdd 120 220 320 0.9 * Vio 0.8 * Vio 0.1 0 15.9 8.0 1.6 0.8 0.4 200 I/O Pads Supply Voltage (VIO) V Operating (full power) Current Consumption Operating (15Hz) Standby µA Output Low Voltage1 Output High Voltage Input Low Voltage Input High Voltage Input Pull-down Current LPF (-3dB) = 50Hz LPF (-3dB) = 100Hz 2 Power Up Time LPF (-3dB) = 500Hz LPF (-3dB) = 1,000Hz LPF (-3dB) = 2,000Hz A/D Conversion time SPI Communication Rate3 2 I C Communication Rate Bandwidth (-3dB) 4 V V V V µA ms µs MHz 1 400 KHz Hz 0.3 * Vio 0.2 * Vio - 40 50 60 Notes: 1. Assuming I2C communication and minimum 1.5Kohm pull-up resistor on SCL and SDA. 2. Power up time is determined after the enabling of the part and is determined by the low-pass filter (LPF) set in CTRL_REGC. 3. SPI Communication Rate can be optimized for faster communication per the SPI timing diagram below. 4. Factory programmable to have a switched capacitor low pass filter at 2kHz, 1kHz, 500Hz, 100Hz, 50Hz or no low pass filter. Optionally, the user can define with in CTRL_REGC. Maximum defined by the frequency response of the sensors. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 3 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 KXSD9 SPI Timing Diagram t1 t2 t3 t4 t5 t6 t7 nCS SCLK SDI bit 7 bit 6 bit 1 bit 0 SDO bit 7 bit 7 t8 bit 6 bit 1 bit 0 bit 6 bit 1 bit 0 t10 t9 t11 Table 3. SPI Timing Number Description MIN MAX Units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Enable transition from low to high after Vdd above 1.6V nCS low to first SCLK setup time SCLK pulse width: high (Does not apply to the last bit of a byte.) SCLK pulse width: low (Does not apply to the last bit of a byte.) SCLK pulse width: high (Only on last bit of a byte.) SCLK pulse width: low (Only on last bit of a byte.) nCS low after the final SCLK falling edge nCS pulse width: high SDI valid to SCLK rising edge SCLK rising edge to SDI invalid SCLK falling edge to SDO valid SCLK falling edge to SDO invalid Recommended SPI SCLK A/D conversion SCLK hold (t5) 1 130 130 130 200 350 350 130 10 100 0 1 200 130 - ms ns ns ns ns ns ns ns ns ns ns ns us us Notes 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 4 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Table 4. Environmental Units Min Typical Max Supply Voltage (Vdd) Absolute Limits Operating Temperature Range Storage Temperature Range Parameters V ºC ºC -0.3 -40 -55 - Mech. Shock (powered and unpowered) g - - ESD V - - 6.0 85 150 5000 for 0.5ms 10000 for 0.2ms 2000 HBM Caution: ESD Sensitive and Mechanical Shock Sensitive Component, improper handling can cause permanent damage to the device. This product conforms to Directive 2002/95/EC of the European Parliament and of the Council of the European Union (RoHS). Specifically, this product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or polybrominated diphenyl ethers (PBDE) above the maximum concentration values (MCV) by weight in any of its homogenous materials. Homogenous materials are "of uniform composition throughout." HF This product is halogen-free per IEC 61249-2-21. Specifically, the materials used in this product contain a maximum total halogen content of 1500 ppm with less than 900-ppm bromine and less than 900-ppm chlorine. Soldering Soldering recommendations are available upon request or from www.kionix.com. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 5 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Application Schematic SDA/SDO 10 IO Vdd 1 9 SCL/SCLK 2 8 ADDR/SDI 7 MOT 6 CS KXSD9 AUX IN 3 4 5 C1 Vdd Table 5. KXSD9 Pin Descriptions Pin Name Description 1 IO Vdd The power supply input for the digital communication bus 2 DNC 3 AUX IN 4 GND 5 Vdd The power supply input. Decouple this pin to ground with a 0.1uF ceramic capacitor. 6 nCS SPI Enable I2C/SPI mode selection (1 = I2C mode, 0 = SPI mode) 7 MOT Motion Wakeup Interrupt 8 ADDR/SDI I2C programmable address bit/SPI Serial Data Input 9 SCL/SCLK I2C Serial Clock/SPI Serial Clock 10 SDA/SD0 I2C Serial Data/SPI Serial Data Output 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] Reserved – Do Not Connect Auxiliary Input for analog/digital conversion Ground © 2009 Kionix – All Rights Reserved 091012-01 Page 6 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Test Specifications ! Special Characteristics: These characteristics have been identified as being critical to the customer. Every part is tested to verify its conformance to specification prior to shipment. Table 6. Test Specifications Parameter Zero-g Offset @ RT Sensitivity @ RT Current Consumption -- Operating 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] Specification 2048 +/- 205 counts 819 +/- 25 counts/g 120 <= Idd <= 320 uA Test Conditions 25C, Vdd = 3.3 V 25C, Vdd = 3.3 V 25C, Vdd = 3.3 V © 2009 Kionix – All Rights Reserved 091012-01 Page 7 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Package Dimensions and Orientation 3 x 3 x 0.9 mm LGA All dimensions and tolerances conform to ASME Y14.5M-1994 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 8 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Orientation +Y Pin 1 +X +Z When device is accelerated in +X, +Y or +Z direction, the corresponding output will increase. Static X/Y/Z Output Response versus Orientation to Earth’s surface (1-g): FS1=1, FS0=1 (± 2g) Position Diagram 1 2 3 4 5 Top 6 Bottom Bottom Top X 2048 counts 2867 counts 2048 counts 1229 counts 2048 counts 2048 counts Y 2867 counts 2048 counts 1229 counts 2048 counts 2048 counts 2048 counts Z 2048 counts 2048 counts 2048 counts 2048 counts 2867 counts 1229 counts 0 + 0 + 0 0 0 0 0 0 0 0 + 0 0 - X-Polarity Y-Polarity Z-Polarity (1-g) Earth’s Surface 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 9 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 KXSD9 Digital Interfaces The Kionix KXSD9 digital accelerometer has the ability to communicate on both I2C and SPI digital serial interface busses. This flexibility allows for easy system integration by eliminating analog-to-digital converter requirements and by providing direct communication with system micro-controllers. In doing so, all of the digital communication pins have shared responsibilities. The serial interface terms and descriptions as indicated in Table 7 below will be observed throughout this document. Term Transmitter Receiver Master Slave Description The device that transmits data to the bus. The device that receives data from the bus. The device that initiates a transfer, generates clock signals and terminates a transfer. The device addressed by the Master. Table 7. Serial Interface Terminologies I2C Serial Interface The KXSD9 has the ability to communicate on an I2C bus. I2C is primarily used for synchronous serial communication between a Master device and one or more Slave devices. The Master, typically a micro controller, provides the serial clock signal and addresses Slave devices on the bus. The KXSD9 always operates as a Slave device during standard Master-Slave I2C operation as shown in Figure 1 on the following page. I2C is a two-wire serial interface that contains a Serial Clock (SCL) line and a Serial Data (SDA) line. SCL is a serial clock that is provided by the Master, but can be held low by any Slave device, putting the Master into a wait condition. SDA is a bi-directional line used to transmit and receive data to and from the interface. Data is transmitted MSB (Most Significant Bit) first in 8-bit per byte format, and the number of bytes transmitted per transfer is unlimited. The I2C bus is considered free when both lines are high. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 10 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications SDA SCL KXSD9-2050 Rev. 2 Jul-2009 Vdd SDA MCU SCL SDA KXSD9 SCL ADDR SDA KXSD9 SCL ADDR Figure 1 Multiple KXSD9 I2C Connection I2C Operation Transactions on the I2C bus begin after the Master transmits a start condition (S), which is defined as a high-to-low transition on the data line while the SCL line is held high. The bus is considered busy after this condition. The next byte of data transmitted after the start condition contains the Slave Address (SAD) in the seven MSBs (Most Significant Bits), and the LSB (Least Significant Bit) tells whether the Master will be receiving data ‘1’ from the Slave or transmitting data ‘0’ to the Slave. When a Slave Address is sent, each device on the bus compares the seven MSBs with its internally-stored address. If they match, the device considers itself addressed by the Master. The KXSD9’s Slave Address is comprised of a programmable part and a fixed part, which allows for connection of multiple KXSD9's to the same I2C bus. The Slave Address associated with the KXSD9 is 001100X, where the programmable bit, X, is determined by the assignment of ADDR (pin 8) to GND or Vdd. Figure 1 above shows how two KXSD9's would be implemented on an I2C bus. It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter must release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it remains stable low during the high period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or Slave, is obliged to generate an ACK after each byte of data has been received. To conclude a transaction, the Master must transmit a stop condition (P) by transitioning the SDA line from low to high while SCL is high. The I2C bus is now free. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 11 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Writing to a KXSD9 8-bit Register Upon power up, the Master must write to the KXSD9’s control registers to set its operational mode. Therefore, when writing to a control register on the I2C bus, as shown Sequence 1 on the following page, the following protocol must be observed: After a start condition, SAD+W transmission, and the KXSD9 ACK has been returned, an 8-bit Register Address (RA) command is transmitted by the Master. This command is telling the KXSD9 to which 8-bit register the Master will be writing the data. Since this is I2C mode, the MSB of the RA command should always be zero (0). The KXSD9 acknowledges the RA and the Master transmits the data to be stored in the 8-bit register. The KXSD9 acknowledges that it has received the data and the Master transmits a stop condition (P) to end the data transfer. The data sent to the KXSD9 is now stored in the appropriate register. The KXSD9 automatically increments the received RA commands and, therefore, multiple bytes of data can be written to sequential registers after each Slave ACK as shown in Sequence 2 on the following page. Reading from a KXSD9 8-bit Register When reading data from a KXSD9 8-bit register on the I2C bus, as shown in Sequence 3 on the next page, the following protocol must be observed: The Master first transmits a start condition (S) and the appropriate Slave Address (SAD) with the LSB set at ‘0’ to write. The KXSD9 acknowledges and the Master transmits the 8-bit RA of the register it wants to read. The KXSD9 again acknowledges, and the Master transmits a repeated start condition (Sr). After the repeated start condition, the Master addresses the KXSD9 with a ‘1’ in the LSB (SAD+R) to read from the previously selected register. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NACK) it received the transmitted data, but transmits a stop condition to end the data transfer. Note that the KXSD9 automatically increments through its sequential registers, allowing data reads from multiple registers following a single SAD+R command as shown below in Sequence 4 on the following page. If a receiver cannot transmit or receive another complete byte of data until it has performed some other function, it can hold SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases SCL. For instance, after the Master has requested to read acceleration data from the KXSD9, the KXSD9 can hold SCL low to force the Master into a wait state while it completes the A/D conversion. After the A/D conversion, the KXSD9 will release SCL and transmit the acceleration data to the Master. Note that the KXSD9 will hold for A/D conversions only if the CLKhld bit is set in CTRL_REGB. Data Transfer Sequences The following information clearly illustrates the variety of data transfers that can occur on the I2C bus and how the Master and Slave interact during these transfers. Table 8 on the following page defines the I2C terms used during the data transfers. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 12 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications Term S Sr SAD W R ACK NACK RA Data P KXSD9-2050 Rev. 2 Jul-2009 Definition Start Condition Repeated Start Condition Slave Address Write Bit Read Bit Acknowledge Not Acknowledge Register Address Transmitted/Received Data Stop Condition Table 8. I2C Terms Sequence 1. The Master is writing one byte to the Slave. Master Slave S SAD + W RA ACK DATA P ACK ACK Sequence 2. The Master is writing multiple bytes to the Slave. Master Slave S SAD + W RA ACK DATA DATA ACK ACK P ACK Sequence 3. The Master is receiving one byte of data from the Slave. Master Slave S SAD + W RA ACK Sr SAD + R ACK NACK ACK P DATA Sequence 4. The Master is receiving multiple bytes of data from the Slave. Master Slave S SAD + W RA ACK Sr SAD + R ACK ACK ACK DATA NACK DATA Sequence 5. The Master is receiving acceleration bytes from the Slave (ADDR = 0, CLKhld = 1). Master Slave S 0x30h 0x00h ACK 200µS ACK CLKhld Sr 0x31h ACK ACK XOUT_H Master ACK ACK ACK ACK NACK Slave YOUT_H YOUT_L ZOUT_H ZOUT_L 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] XOUT_L P © 2009 Kionix – All Rights Reserved 091012-01 Page 13 of 25 P PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 SPI Interface The KXSD9 also utilizes an integrated Serial Peripheral Interface (SPI) for digital communication. The SPI interface is primarily used for synchronous serial communication between one Master device and one or more Slave devices. The Master, typically a micro controller, provides the SPI clock signal (SCLK) and determines the state of Chip Select (nCS). The KXSD9 always operates as a Slave device during standard Master-Slave SPI operation. SPI is a 4-wire synchronous serial interface that uses two control and two data lines. With respect to the Master, the Serial Clock output (SCLK), the Data Output (SDI or MOSI) and the Data Input (SDO or MISO) are shared among the Slave devices. The Master generates an independent Chip Select (nCS) for each Slave device that goes low at the start of transmission and goes back high at the end. The Slave Data Output (SDO) line, remains in a high-impedance (hi-z) state when the device is not selected, so it does not interfere with any active devices. This allows multiple Slave devices to share a master SPI port as shown in Figure 2 below. Master Serial Clock CS0 CS1 Slave 0 SCLK CS KXSD9 MCU SDI MOSI (Data Out) MISO (Data In) SDO Slave 1 SCLK CS KXSD9 SDI SDO Figure 2 KXSD9 SPI Connections Read and Write Control Registers The control registers embedded in the KXSD9 have 8-bit addresses. Upon power up, the Master must write to the accelerometer’s control registers to set its operational mode. On the falling edge of nCS,, a 2byte command is written to the appropriate control register. The first byte initiates the write to the appropriate register, and is followed by the user-defined, operational-mode byte. The MSB (Most Significant Bit) of the control register address byte will indicate “0” when writing to the register and “1” when reading from the register. This operation occurs over 16 clock cycles. All commands are sent MSB first, 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 14 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 and the host must return nCS high for at least 130nS before the next data request. Figure 3 below shows the timing diagram for carrying out the 8-bit control register write operation. SCLK SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) SDO (MSB) HI-Z HI-Z CS Figure 3 Timing Diagram for 8-Bit Control Register Write Operation In order to read an 8-bit control register, an 8-bit read command must be written to the accelerometer to initiate the read. The MSB of this control register address byte will indicate “0” when writing to the register and “1” when reading from the register. Upon receiving the command, the accelerometer returns the 8-bit operational-mode data stored in the appropriate control register. This operation also occurs over 16 clock cycles. All returned data is sent MSB first, and the host must return nCS high for at least 130nS before the next data request. Figure 4 shows the timing diagram for an 8-bit control register read operation. SCLK SDI A7 A6 A5 A4 A3 A2 A1 A0 (MSB) SDO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 HI-Z (MSB) CS Figure 4 Timing Diagram for 8-Bit Control Register Read Operation Accelerometer Read Back Operation The KXSD9 has an onboard 12-bit ADC that can sample, convert and read back sensor data at any time. Transmission of an 8-bit axis-conversion command (see Table 10) begins on the falling edge of nCS. The MSB of this command indicates if you are writing to (0) or reading from (1) the register. After the eight clock cycles used to send the command, the host must hold SCLK low for at least 200µs during the A/D conversion time. Note that all returned data is sent MSB first. Once the data is received, nCS must be returned high for at least 130nS before the next data request. Figure 5 on the following page shows the timing and diagram for the accelerometer 12-bit ADC read operation. The Read Back Operation is a 3-byte SPI command. The first byte of SDI contains the command to convert one of the axes. The second and third bytes of SDO contain the 12 bits of the A/D result plus four bits of padding in the LSB to make a total of 16 bits. See Figure 6 below. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 15 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 200µs SCLK SDI A7 A6 A5 A4 A3 A2 A1 A0 (MSB) SDO HI Z D7 D6 D5 D4 D3 D2 D1 (MSB) D0 D7 D6 D5 D4 D3 D2 D1 HI Z D0 (MSB) CS Figure 5 Timing Diagram for an A/D conversion and 12-Bit data read operation. Axis Conversion Command SDI SDO A7 A6 A5 A4 A3 A2 A1 A0 MSB X X X X X X X X X X X X X X X X MSB D11 D10 D9 D8 D7 D6 D5 D4 X X X X X X X X D3 D2 D1 D0 X X X X Conversion Read Back Data X = Don’t Care Bits Figure 6 Register Diagram for 12-Bit ADC Read Operation Digital Accelerometer SPI Sequence An example of a SPI sequence for reading sensor data using the auto-increment feature is as follows: Power up digital accelerometer nCS low to select Write operational mode commands to the 8-bit control registers CTRL_REGB and CTRL_REGC nCS high for at least 130nS nCS low to select Send convert axis command There should be a minimum of 200µs between the command byte and readback bytes in order to give the A/D conversion adequate time to complete. The 12-bit A/D data is read to the second and third SDO bytes. The KXSD9 auto-increments register transmits on SDO. Therefore, Y-axis, Z-axis, AuxOut, CTRL_REGC, CTRL_REGB, and CTRL_REGA will follow the two X-axis bytes automatically. After receiving the last byte of required data, return nCS high for at least 130nS to reset the autoincrement. Repeat data read cycle Recommend reading X-axis, Y-axis, Z-axis, and the three Control Registers for each read cycle to verify the mode selections and status 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 16 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 KXSD9 Embedded Registers The KXSD9 has 12 embedded 8-bit registers that are accessible by the user. This section contains the addresses and describes bit functions all embedded registers. Table 9 and Table 10 below list the accessible 8-bit registers and their addresses when in I2C mode and SPI Mode. Type Register Name XOUT_H XOUT_L YOUT_H YOUT_L ZOUT_H ZOUT_L AUXOUT_H AUXOUT_L Reset_write CTRL_REGC CTRL_REGB CTRL_REGA Read/Write R R R R R R R R W R/W R/W R Address Hex 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 xxxx xxxx 0x0A xxxx 0x0C 0x0D 0x0E Binary 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 xxxx xxxx xxxx xxxx 0000 1010 xxxx xxxx 0000 1100 0000 1101 0000 1110 Table 9. I2C Mode Register Map Type Register Name XOUT_H XOUT_L YOUT_H YOUT_L ZOUT_H ZOUT_L AUXOUT_H AUXOUT_L Reset_write CTRL_REGC CTRL_REGB CTRL_REGA Read/Write R R R R R R R R W R/W R/W R Read Address Hex 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 xxxx xxxx xxxx xxxx 0x8C 0x8D 0x8E Binary 1000 0000 1000 0001 1000 0010 1000 0011 1000 0100 1000 0101 1000 0110 1000 0111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1000 1100 1000 1101 1000 1110 Write Address Hex xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0x0A xxxx 0x0C 0x0D xxxx Binary xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 1010 xxxx xxxx 0000 1100 0000 1101 xxxx xxxx Table 10. SPI Mode Register Map 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 17 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Register Descriptions XOUT_H X-axis accelerometer output most significant byte R R R XOUTD11 XOUTD10 XOUTD9 Bit7 Bit6 Bit5 R XOUTD8 Bit4 R XOUTD7 Bit3 R R R XOUTD6 XOUTD5 XOUTD4 Bit2 Bit1 Bit0 I2C Address: 0x00h SPI Read Address: 0x80h XOUT_L X-axis accelerometer output least significant byte R XOUTD3 Bit7 R XOUTD2 Bit6 R XOUTD1 Bit5 R XOUTD0 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 I2C Address: 0x01h SPI Read Address: 0x81h YOUT_H Y-axis accelerometer output most significant byte R R R YOUTD11 YOUTD10 YOUTD9 Bit7 Bit6 Bit5 R YOUTD8 Bit4 R YOUTD7 Bit3 R R R YOUTD6 YOUTD5 YOUTD4 Bit2 Bit1 Bit0 2 I C Address: 0x02h SPI Read Address: 0x82h YOUT_L Y-axis accelerometer output least significant byte R YOUTD3 Bit7 R YOUTD2 Bit6 R YOUTD1 Bit5 R YOUTD0 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 I2C Address: 0x03h SPI Read Address: 0x83h ZOUT_H Z-axis accelerometer output most significant byte R R 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] R R R R R R © 2009 Kionix – All Rights Reserved 091012-01 Page 18 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications ZOUTD11 ZOUTD10 ZOUTD9 Bit7 Bit6 Bit5 ZOUTD8 Bit4 ZOUTD7 Bit3 KXSD9-2050 Rev. 2 Jul-2009 ZOUTD6 Bit2 ZOUTD5 ZOUTD4 Bit1 Bit0 2 I C Address: 0x04h SPI Read Address: 0x84h ZOUT_L Z-axis accelerometer output least significant byte R ZOUTD3 Bit7 R ZOUTD2 Bit6 R ZOUTD1 Bit5 R ZOUTD0 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 I2C Address: 0x05h SPI Read Address: 0x85h AUXOUT_H Auxiliary output most significant byte R R R R R R R R AUXOUTD11 AUXOUTD10 AUXOUTD9 AUXOUTD8 AUXOUTD7 AUXOUTD6 AUXOUTD5 AUXOUTD4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 2 I C Address: 0x06h SPI Read Address: 0x86h AUXOUT_L Auxiliary output least significant byte R R R R AUXOUTD3 AUXOUTD2 AUXOUTD1 AUXOUTD0 Bit7 Bit6 Bit5 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 I2C Address: 0x07h SPI Read Address: 0x87h Reset_write When the key (11001010) is written to this register the offset, sensitivity and temperature correction values will be loaded into RAM and used for all further measurements. This is also accomplished at power-up by an internal power-up reset circuit. W W W W W W W W 1 1 0 0 1 0 1 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] Bit1 Bit0 2 I C Address: 0x0Ah © 2009 Kionix – All Rights Reserved 091012-01 Page 19 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 SPI Write Address: 0x0Ah CTRL_REGC Read/write control register: Factory programmed power up/reset default value (0xE1h) R/W LP2 Bit7 R/W LP1 Bit6 R/W LP0 Bit5 R/W MOTLev Bit4 R/W MOTLat Bit3 SPI Read Address: 0x8Ch R/W 0 Bit2 R/W R/W FS1 FS0 Bit1 Bit0 2 I C Address: 0x0Ch SPI Write Address: 0x0Ch Reset Value 11100001 FS0 is the first of two bits used to select the full scale sensing range of the accelerometer. See Table 11 below. FS1 is the second of two bits used to select the full scale sensing range of the accelerometer. See Table 11 below. FS1 FS0 0 0 1 1 0 1 0 1 Full Scale 12-bit Sensitivity Range +/-8 g +/-6 g +/-4 g +/-2 g 205 counts/g 273 counts/g 410 counts/g 819 counts/g Table 11. Full Scale Range MOTLat switches the motion wake up response function between latching and non-latching. MOTLat = 1 - If MOTIen in CTRL_REGB is “1” and a motion event happens, the MOTI bit in CTRL_REGA will be set to “1” and the MOT pin (7) will be pulled high. The part will clear the MOTIen bit in CTRL_REGB and enter full-power mode. To re-enter low power motion wakeup mode, reset the MOTIen bit to “1”. Figure 7 shows the response of the KXSD9 as described above. MOTLat = 0 – If MOTIen in CTRL_REGB is “1” and a motion event happens, the MOTI bit in CTRL_REGA will be set to “1” and the MOT pin (7) will be pulled high. The part will remain in low power motion wakeup mode. The MOT pin (7) can be cleared by reading CTRL_REGA. Figure 8 shows the response of the KXSD9 as described above. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 20 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Typical Motion Wake Up Interrupt Example (MOTLat = 1) MOTLev Threshold Input Acceleration 0g MOTLev Threshold Accelerometer Output MOT Figure 7 Latched Motion Wake Up Response 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 21 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Typical Motion Wake Up Interrupt Example (MOTLat = 0) MOTLev Threshold Input Acceleration 0g MOTLev Threshold Accelerometer Output MOT CRTL_REGA Read Figure 8 Unlatched Motion Wake Up Response MOTLev sets the motion wakeup threshold to an acceleration level as defined in Table 12. MOTLev FS1 FS0 Motion Wake Up Threshold 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 +/-6 g +/-4.5 g +/-3 g +/-1.5 g +/-4 g +/-3 g +/-2 g +/-1 g Table 12. Motion Wake Up Acceleration Threshold LP0 is the first of three bits used to select the operational bandwidth of the accelerometer. See Table 13 below. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 22 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 LP1 is the second of three bits used to select the operational bandwidth of the accelerometer. See Table 13 below. LP2 is the third of three bits used to select the operational bandwidth of the accelerometer. See Table 13 below. LP2 LP1 LP0 Filter Corner Frequency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 No Filter 2000 Hz 2000 Hz 2000 Hz 1000 Hz 500 Hz 100 Hz 50 Hz Table 13. Operational Bandwidth CTRL_REGB Read/write control register: Factory programmed power up/reset default value (0x40h) R/W CLKhld Bit7 R/W ENABLE Bit6 R/W ST Bit5 R/W 0 Bit4 R/W 0 Bit3 SPI Read Address: 0x8Dh R/W MOTIen Bit2 R/W R/W 0 0 Bit1 Bit0 I2C Address: 0x0Dh SPI Write Address: 0x0Dh Reset Value 01000000 MOTIen enables the motion wakeup feature. MOTIen = 1 – the KXSD9 will run in a low power mode until a motion event occurs that causes MOTI in CTRL_REGA and the MOT pin (7) to go high. The part then enters normal operation if MOTLat = 1 or remains in low power mode if MOTLat = 0. MOTIen = 0 – the KXSD9 is in normal operating mode ST activates the self-test function for the sensor elements on all three axes. A correctly functioning KXSD9 will increase all channel outputs when Self test = 1 and Enable = 1. This bit can be read or written. Enable powers up the KXSD9 for operation. Enable = 1 – normal operation Enable = 0 – low-power standby CLKhld allows the KXSD9 to hold the serial clock, SCL, low in I2C mode to force the transmitter into a wait state during A/D conversions. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 23 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 CLKhld = 1 – SCL held low during A/D conversions CLKhld = 0 – SCL unaffected CLKhld should be set to 0 when Enable is set to 0 (disabled) to prevent potential holding of the CLK line. CTRL_REGA Read-only status register R X Bit7 R X Bit6 R X Bit5 R X Bit4 R X Bit3 SPI Read Address: 0x8Eh R X Bit2 R R MOTI X Bit1 Bit0 I2C Address: 0x0Eh SPI Write Address: 0x0Eh MOTI reports the status of the motion wakeup interrupt. Reading CTRL_REGA clears the MOTI bit and MOT pin (7). MOTI = 1 - a motion wake up event has occurred and the MOT pin (7) is high. MOTI = 0 - a motion wake up event has not occurred and the MOT pin (7) is low. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 24 of 25 PART NUMBER: ± 2g Tri-axis Digital Accelerometer Specifications KXSD9-2050 Rev. 2 Jul-2009 Revision History REVISION 1 2 DESCRIPTION Initial release Changed to new format & revisioning. DATE 16-May-2008 17-Jul-2009 "Kionix" is a registered trademark of Kionix, Inc. Products described herein are protected by patents issued or pending. No license is granted by implication or otherwise under any patent or other rights of Kionix. The information contained herein is believed to be accurate and reliable but is not guaranteed. Kionix does not assume responsibility for its use or distribution. Kionix also reserves the right to change product specifications or discontinue this product at any time without prior notice. This publication supersedes and replaces all information previously supplied. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2009 Kionix – All Rights Reserved 091012-01 Page 25 of 25