PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Product Description The KXSS5-4457 is a Tri-axis, silicon micromachined accelerometer with a full-scale output range of +/-3g (29.4 m/s/s). The sense element is fabricated using Kionix’s proprietary plasma micromachining process technology. Acceleration sensing is based on the principle of a differential capacitance arising from acceleration-induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process variation, temperature, and environmental stress. The sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. A separate ASIC device packaged with the sense element provides signal conditioning, selftest, and temperature compensation. The accelerometer is delivered in a 5 x 3 x 0.9 mm LGA plastic package operating from a 1.8 – 3.6V DC supply. The ASIC will trigger interrupt signals if an acceleration threshold is exceeded in any axis (motion interrupt), or if the total acceleration falls below a threshold (freefall interrupt). The thresholds can be set by the customer or default to factory calibrated values. Either I2C or SPI interfaces can be used to communicate to the chip to trigger A/D conversions, set thresholds or threshold delays, or manage power consumption. Functional Diagram X Sensor Y Sensor Charge Amp Z Sensor 7 8 9 Temp Sensor Vdd 14 A/D SPI/I2C/Logic Enable6 Interrupt Logic GND 10 2 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] 32K 32K 32K 1kHz LPF 3 4 11 12 5 © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 1 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Product Specifications Table 1. Mechanical (specifications are for operation at 1.8V and T = 25C unless stated otherwise) Parameters Units Min Operating Temperature Range Zero-g Offset (analog) Zero-g Offset (digital) Zero-g Offset Variation from RT over Temp. Sensitivity (analog) Sensitivity (digital) Sensitivity Variation from RT over Temp. ºC V counts mg/ ºC mV/g counts/g %/ ºC Offset Ratiometric Error (Vdd = 1.8V ± 5%) % Sensitivity Ratiometric Error (Vdd = 1.8V ± 5%) % Self Test Output change on Activation g Non-Linearity Cross Axis Sensitivity Noise Density (on filter pins) Freefall threshold 1 Freefall delay Motion threshold 1 Motion delay Notes: 1 1 % of FS % g / √Hz g ms g ms -25 0.852 1939 233 530 Typical Max 0.9 2048 0.6 240 546 0.01 (xy) 0.03 (z) 0.3 0.6 (xy) 0.3 (z) 0.8 (xy) 0.6 (z) 0.1 2 175 70 0.948 2157 247 562 0.4 4 2.5 4 2 1. Factory default settings. User can adjust thresholds and delays using I C or SPI interface. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 2 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Table 2. Electrical (specifications are for operation at 1.8V and T = 25C unless stated otherwise) Parameters Units Min Typical Max Supply Voltage (Vdd) Operating V 1.7 1.8 3.6 Current Consumption Operating Standby A A V V A k Hz ms 400 700 0.0012 0 32 1000 0.8 200 1 400 1000 Input Low Voltage Input High Voltage Input Pull-down Current Analog Output Resistance(Rout) 1 Bandwidth (-3dB) 2 Power Up Time A/D Conversion time 3 SPI Communication Rate 2 I C Communication Rate s MHz kHz 0.8 * Vdd 24 800 0.2 * Vdd 40 1200 Notes: 1. Internal 1 kHz low pass filter. Lower frequencies are user definable with external capacitors. 2. Power up time is determined after the enabling of the part. The typical value reported is when using the internal 1kHz low pass filter only. When a user defined low pass filter is used, the power up time is 5 times the RC time constant of the filter. 3. SPI Communication Rate can be optimized for faster communication per the SPI timing diagram below. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 3 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 KXSS5 SPI Timing Diagram t1 t2 t3 t4 t5 t6 t7 nCS CLK SDI bit 7 bit 6 bit 1 5 bit 0 SDO bit 7 5 bit 7 5 t8 t9 bit 6 bit 1 5 bit 0 bit 6 bit 1 5 bit 0 t10 t11 Table 3. SPI Timing Number Description MIN t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Enable transition from low to high after Vdd above 1.6V nCS low to first CLK setup time CLK pulse width: high (Does not apply to the last bit of a byte.) CLK pulse width: low (Does not apply to the last bit of a byte.) CLK pulse width: high (Only on last bit of a byte.) CLK pulse width: low (Only on last bit of a byte.) nCS low after the final CLK falling edge nCS pulse width: high SDI valid to CLK rising edge CLK rising edge to SDI invalid CLK falling edge to SDO valid CLK falling edge to SDO invalid Recommended SPI CLK A/D conversion CLK hold (t5) 1 130 130 130 200 350 350 130 10 100 0 1 200 Notes 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] MAX Units 130 - ms ns ns ns ns ns ns ns ns ns ns ns us us © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 4 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Table 4. Environmental Parameters Units Min Typical Max V -0.3 - 7.0 ºC ºC -40 -55 - 85 150 Mech. Shock (powered and unpowered) g - - 5000 for 0.5ms ESD V - - 2000 Supply Voltage (Vdd) Absolute Limits Operating Temperature Range Storage Temperature Range HBM Caution: ESD Sensitive and Mechanical Shock Sensitive Component, improper handling can cause permanent damage to the device. This product conforms to Directive 2002/95/EC of the European Parliament and of the Council of the European Union (RoHS). Specifically, this product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or polybrominated diphenyl ethers (PBDE) above the maximum concentration values (MCV) by weight in any of its homogenous materials. Homogenous materials are "of uniform composition throughout." HF This product is halogen-free per IEC 61249-2-21. Specifically, the materials used in this product contain a maximum total halogen content of 1500 ppm with less than 900-ppm bromine and less than 900-ppm chlorine. Soldering Soldering recommendations are available upon request or from www.kionix.com. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 5 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Application Schematic 14 Vdd 1 13 CS 2 12 MOT Enable ADDR/SDI 3 11 FF/MOT SDA/SDO 4 10 SCL/SCLK 5 9 Z Enable 6 8 Y C1 KXSS5 7 X Table 5. KXSS5 Pin Descriptions Pin Name 1 Vdd 2 nCS 3 ADDR/SDI The power supply input. SPI Enable1 I2C/SPI mode selection (1 = I2C mode, 0 = SPI mode) I2C programmable address bit/SPI Serial Data Input1 4 SDA/SD0 I2C Serial Data/SPI Serial Data Output1 5 SCL/SCLK 6 Enable 7 X Output 8 Y Output 9 Z Output 10 GND 11 FF/MOT (output) I2C Serial Clock/SPI Serial Clock1 High - Normal operation Transition from low to high – Default values loaded into registers from eeprom, unlatched operation2 Low - Device is in standby, power down mode, I2C/SPI mode will not function The output of the x-channel. Optionally, a capacitor placed between this pin and ground will form a lowpass filter in addition to the internal 1kHz internal filter. The output of y-channel. Optionally, a capacitor placed between this pin and ground will form a lowpass filter in addition to the internal 1kHz internal filter. The output of z-channel. Optionally, a capacitor placed between this pin and ground will form a lowpass filter in addition to the internal 1kHz internal filter. Ground Low: no interrupts High: (all channels below Freefall threshold) OR (at least one channel above Motion threshold AND (MOT Enable=High)) Low – disable Motion interrupt High – enable Motion interrupt to “OR” with freefall interrupt onto the FF/MOT pin The power supply input. 13 MOT Enable (input) Vdd 14 Vdd 12 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] Description The power supply input. Decouple this pin to ground with a 0.1uF ceramic capacitor. © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 6 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Application Design Notes 1 When used without digital communications, make the following connections: 2 nCS = Vdd (puts the part into I C mode, disables pullups on SDA/SDO pad) SCL/SCLK = GND SDA/SDO = GND ADDR/SDI = GND or Vdd 14 Vdd 1 13 2 12 MOT Enable 3 11 FF/MOT C1 KXSS5 Enable 4 10 5 9 Z 6 8 Y 7 X In this mode, the interrupts operate in unlatched mode with the factory default settings for free-fall and motion thresholds and delays. 2 Enable cannot transition from low to high until a minimum of 1 ms after Vdd reaches 1.6V. Application Design Equations The bandwidth is determined by the filter capacitors connected from pins 7, 8 and 9 to ground. The response is single pole. Given a desired bandwidth, fBW, the filter capacitors are determined by: C2 C3 C4 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] 4.97 x106 f BW © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 7 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 KXSS5 Interrupt Features As shown in the application schematic, the KXSS5 features a free-fall interrupt (FF) with an optional high-g motion interrupt (MOT) on the same output pin (FF/MOT). Each interrupt features independent, user-definable thresholds, debounce times, and latch/unlatch capabilities that are customized through the KXSS5’s embedded 8-bit registers or default to factory calibrated values. Free-fall Detection Interrupt - The free-fall interrupt goes high when a free-fall event is detected. A free-fall event occurs when the acceleration on all three accelerometer axes simultaneously falls below the low acceleration threshold for a certain amount of time. The low acceleration threshold and debounce time is set by the user (or default to factory calibrated values) during power up through the embedded 8-bit registers. Also, the free-fall interrupt can be user-defined as latched or unlatched. High-g Motion Interrupt - The optional high-g motion interrupt goes high when a high-g event is detected. A high-g event occurs when the acceleration on any axis exceeds the high acceleration threshold for a certain amount of time. The high acceleration threshold and debounce time is set by the user (or default to factory calibrated values) during power up through the embedded 8-bit registers. The MOT Enable pin enables the Motion interrupt to logically “OR” with the free-fall interrupt onto the FF/MOT pin. Also, the high-g motion interrupt can be user-defined as latched or unlatched. Test Specifications ! Special Characteristics: These characteristics have been identified as being critical to the customer. Every part is tested to verify its conformance to specification prior to shipment. Table 6. Test Specifications Parameter Zero-g Offset @ RT Sensitivity @ RT Current Consumption -- Operating 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] Specification 0.9 +/- 0.048 V 240 +/- 7.2 mV/g 400 <= Idd <= 1000 uA Test Conditions 25C, Vdd = 1.8 V 25C, Vdd = 1.8 V 25C, Vdd = 1.8 V © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 8 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Package Dimensions and Orientation 3 x 5 x 0.9 mm LGA 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 9 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications Dimension A A1 A2 b D E K e L Min --0.66 0.45 0.75 mm Nom 0.91 0.21 REF 0.7 0.5 3 BSC 5 BSC 4 BSC 0.8 BSC 0.8 Max 1.0 Min --- 0.74 0.55 0.026 0.018 0.85 0.029 inch Nom 0.036 0.008 REF 0.028 0.020 0.118 BSC 0.197 BSC 0.157 BSC 0.031 BSC 0.031 KXSS5-4457 Rev. 3 Feb-2013 Max 0.039 0.029 0.022 0.033 All dimensions and tolerances conform to ASME Y14.5M-1994 Orientation Pin 1 +Y +X +Z When device is accelerated in +X, +Y or +Z direction, the corresponding output will increase. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 10 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Static X/Y/Z Output Response versus Orientation to Earth’s surface (1-g): Position Diagram X Y Z X-Polarity Y-Polarity Z-Polarity 1 2 3 4 5 Top 6 Bottom Bottom Top 0.9 V 1.14 V 0.9 V 1.14 V 0.9 V 0.9 V 0.9 V 0.66 V 0.9 V 0.66 V 0.9 V 0.9 V 0.9 V 0.9 V 1.14 V 0.9 V 0.9 V 0.66 V 0 + 0 + 0 0 0 0 0 0 0 0 + 0 0 - (1-g) Earth’s Surface 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 11 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 KXSS5 Digital Interfaces The Kionix KXSS5 digital accelerometer has the ability to communicate on both I2C and SPI digital serial interface busses. This flexibility allows for easy system integration by eliminating analog-to-digital converter requirements and by providing direct communication with system micro-controllers. In doing so, all of the digital communication pins have shared responsibilities. The serial interface terms and descriptions as indicated in Table 7 below will be observed throughout this document. Term Transmitter Receiver Master Slave Description The device that transmits data to the bus. The device that receives data from the bus. The device that initiates a transfer, generates clock signals and terminates a transfer. The device addressed by the Master. Table 7. Serial Interface Terminologies I2C Serial Interface The KXSS5 has the ability to communicate on an I2C bus. I2C is primarily used for synchronous serial communication between a Master device and one or more Slave devices. The Master, typically a micro controller, provides the serial clock signal and addresses Slave devices on the bus. The KXSS5 always operates as a Slave device during standard Master-Slave I2C operation as shown in Figure 1 on the following page. I2C is a two-wire serial interface that contains a Serial Clock (SCL) line and a Serial Data (SDA) line. SCL is a serial clock that is provided by the Master, but can be held low by any Slave device, putting the Master into a wait condition. SDA is a bi-directional line used to transmit and receive data to and from the interface. Data is transmitted MSB (Most Significant Bit) first in 8-bit per byte format, and the number of bytes transmitted per transfer is unlimited. The I2C bus is considered free when both lines are high. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 12 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications SDA SCL KXSS5-4457 Rev. 3 Feb-2013 Vdd SDA MCU SCL SDA KXSS5 SCL ADDR SDA KXSS5 SCL ADDR Figure 1 Multiple KXSS5 I2C Connection I2C Operation Transactions on the I2C bus begin after the Master transmits a start condition (S), which is defined as a highto-low transition on the data line while the SCL line is held high. The bus is considered busy after this condition. The next byte of data transmitted after the start condition contains the Slave Address (SAD) in the seven MSBs (Most Significant Bits), and the LSB (Least Significant Bit) tells whether the Master will be receiving data ‘1’ from the Slave or transmitting data ‘0’ to the Slave. When a Slave Address is sent, each device on the bus compares the seven MSBs with its internally-stored address. If they match, the device considers itself addressed by the Master. The KXSS5’s Slave Address is comprised of a programmable part and a fixed part, which allows for connection of multiple KXSS5's to the same I2C bus. The Slave Address associated with the KXSS5 is 001100X, where the programmable bit, X, is determined by the assignment of ADDR (pin 3) to GND or Vdd. Figure 1 above shows how two KXSS5's would be implemented on an I2C bus. It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter must release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it remains stable low during the high period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or Slave, is obliged to generate an ACK after each byte of data has been received. To conclude a transaction, the Master must transmit a stop condition (P) by transitioning the SDA line from low to high while SCL is high. The I2C bus is now free. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 13 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Writing to a KXSS5 8-bit Register Upon power up, the Master must write to the KXSS5’s control registers to set its operational mode. Therefore, when writing to a control register on the I2C bus, as shown Sequence 1 on the following page, the following protocol must be observed: After a start condition, SAD+W transmission, and the KXSS5 ACK has been returned, an 8-bit Register Address (RA) command is transmitted by the Master. This command is telling the KXSS5 to which 8-bit register the Master will be writing the data. Since this is I2C mode, the MSB of the RA command should always be zero (0). The KXSS5 acknowledges the RA and the Master transmits the data to be stored in the 8-bit register. The KXSS5 acknowledges that it has received the data and the Master transmits a stop condition (P) to end the data transfer. The data sent to the KXSS5 is now stored in the appropriate register. The KXSS5 automatically increments the received RA commands and, therefore, multiple bytes of data can be written to sequential registers after each Slave ACK as shown in Sequence 2 on the following page. Reading from a KXSS5 8-bit Register When reading data from a KXSS5 8-bit register on the I2C bus, as shown in Sequence 3 on the next page, the following protocol must be observed: The Master first transmits a start condition (S) and the appropriate Slave Address (SAD) with the LSB set at ‘0’ to write. The KXSS5 acknowledges and the Master transmits the 8-bit RA of the register it wants to read. The KXSS5 again acknowledges, and the Master transmits a repeated start condition (Sr). After the repeated start condition, the Master addresses the KXSS5 with a ‘1’ in the LSB (SAD+R) to read from the previously selected register. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NACK) it received the transmitted data, but transmits a stop condition to end the data transfer. Note that the KXSS5 automatically increments through its sequential registers, allowing data reads from multiple registers following a single SAD+R command as shown below in Sequence 4 on the following page. If a receiver cannot transmit or receive another complete byte of data until it has performed some other function, it can hold SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases SCL. For instance, after the Master has requested to read acceleration data from the KXSS5, the KXSS5 can hold SCL low to force the Master into a wait state while it completes the A/D conversion. After the A/D conversion, the KXSS5 will release SCL and transmit the acceleration data to the Master. Note that the KXSS5 will hold for A/D conversions only if the CLKhld bit is set in CTRL_REGB. Data Transfer Sequences The following information clearly illustrates the variety of data transfers that can occur on the I 2C bus and how the Master and Slave interact during these transfers. Table 8 on the following page defines the I2C terms used during the data transfers. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 14 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications Term S Sr SAD W R ACK NACK RA Data P KXSS5-4457 Rev. 3 Feb-2013 Definition Start Condition Repeated Start Condition Slave Address Write Bit Read Bit Acknowledge Not Acknowledge Register Address Transmitted/Received Data Stop Condition Table 8. I2C Terms Sequence 1. The Master is writing one byte to the Slave. Master Slave S SAD + W RA ACK DATA ACK P ACK Sequence 2. The Master is writing multiple bytes to the Slave. Master Slave S SAD + W RA ACK DATA ACK DATA ACK P ACK Sequence 3. The Master is receiving one byte of data from the Slave. Master Slave S SAD + W RA ACK Sr SAD + R ACK NACK ACK P DATA Sequence 4. The Master is receiving multiple bytes of data from the Slave. Master Slave S SAD + W 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] RA ACK Sr ACK SAD + R ACK ACK DATA NACK DATA © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 15 of 31 P PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 SPI Interface The KXSS5 also utilizes an integrated Serial Peripheral Interface (SPI) for digital communication. The SPI interface is primarily used for synchronous serial communication between one Master device and one or more Slave devices. The Master, typically a micro controller, provides the SPI clock signal (SCLK) and determines the state of Chip Select (nCS). The KXSS5 always operates as a Slave device during standard Master-Slave SPI operation. SPI is a 4-wire synchronous serial interface that uses two control and two data lines. With respect to the Master, the Serial Clock output (SCLK), the Data Output (MOSI) and the Data Input (MISO) are shared among the Slave devices. The Master generates an independent Chip Select (nCS) for each Slave device that goes low at the start of transmission and goes back high at the end. The Slave Data Output (SDO) line, remains in a high-impedance (hi-z) state when the device is not selected, so it does not interfere with any active devices. This allows multiple Slave devices to share a master SPI port as shown in Figure 2 below. Master Serial Clock CS0 CS1 MCU Slave 0 SCLK CS KXSS5 SDI MOSI (Data Out) MISO (Data In) SDO Slave 1 SCLK CS KXSS5 SDI SDO Figure 2 KXSS5 SPI Connections Read and Write Control Registers The control registers embedded in the KXSS5 have 8-bit addresses. Upon power up, the Master must write to the accelerometer’s control registers to set its operational mode. On the falling edge of nCS,, a 2-byte command is written to the appropriate control register. The first byte initiates the write to the appropriate register, and is followed by the user-defined, operational-mode byte. The MSB (Most Significant Bit) of the control register address byte will indicate “0” when writing to the register and “1” when reading from the register. This operation occurs over 16 clock cycles. All commands are sent MSB first, and the host must return nCS high for at least 130 ns before the next data request. Figure 3 below shows the timing diagram for carrying out the 8-bit control register write operation. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 16 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 CLK SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) SDO CS (MSB) HI-Z HI-Z Figure 3 Timing Diagram for 8-Bit Control Register Write Operation In order to read an 8-bit control register, an 8-bit read command must be written to the accelerometer to initiate the read. The MSB of this control register address byte will indicate “0” when writing to the register and “1” when reading from the register. Upon receiving the command, the accelerometer returns the 8-bit operationalmode data stored in the appropriate control register. This operation also occurs over 16 clock cycles. All returned data is sent MSB first, and the host must return nCS high for at least 130 ns before the next data request. Figure 4 shows the timing diagram for an 8-bit control register read operation. CLK SDI A7 A6 A5 A4 A3 A2 A1 A0 (MSB) SDO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 HI-Z (MSB) CS Figure 4 Timing Diagram for 8-Bit Control Register Read Operation Accelerometer Read Back Operation The KXSS5 has an onboard 12-bit ADC that can sample, convert and read back sensor data at any time. Transmission of an 8-bit axis-conversion command (see Table 10) begins on the falling edge of nCS. The MSB of this command indicates if you are writing to (0) or reading from (1) the register. After the eight clock cycles used to send the command, the host must hold SCLK low for at least 200µs during the A/D conversion time. Note that all returned data is sent MSB first. Once the data is received, nCS must be returned high for at least 130 ns before the next data request. Figure 5 on the following page shows the timing and diagram for the accelerometer 12-bit ADC read operation. The Read Back Operation is a 3-byte SPI command. The first byte of SDI contains the command to convert one of the axes. The second and third bytes of SDO contain the 12 bits of the A/D result plus four bits of padding in the LSB to make a total of 16 bits. See Figure 6 below. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 17 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 200μs CLK MOSI A7 A6 A5 A4 A3 A2 A1 A0 (MSB) HI Z MISO D7 D6 D5 D4 D3 D2 D1 D0 (MSB) D7 D6 D5 D4 D3 D2 D1 HI Z D0 (MSB) CS Figure 5 Timing Diagram for an A/D conversion and 12-Bit data read operation. Axis Conversion Command SDI SDO A7 A6 A5 A4 A3 A2 A1 A0 MSB X X X X X X X X X X X X X X X X MSB D11 D10 D9 D8 D7 D6 D5 D4 X X X X X X X X D3 D2 D1 D0 X X X X Conversion Read Back Data X = Don’t Care Bits Figure 6 Register Diagram for 12-Bit ADC Read Operation Digital Accelerometer SPI Sequence An example of a SPI sequence for reading sensor data is as follows: Power up digital accelerometer nCS low to select Write operational mode commands to the 8-bit control registers CTRL_REGB and CTRL_REGC nCS high for at least 130 ns nCS low to select Send convert axis command There should be a minimum of 200μs between the first and second bytes in order to give the A/D conversion adequate time to complete. The 12-bit A/D data is read to the second and third SDO bytes. The KXSS5 auto-increments register transmits on SDO. Therefore, Y-axis, Z-axis, CTRL_REGA, CTRL_REGB, and CTRL_REGC will follow the two X-axis bytes automatically. After receiving the last byte of required data, return nCS high for at least 130 ns to reset the autoincrement. Repeat data read cycle 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 18 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Recommend reading X-axis, Y-axis, Z-axis, and the three Control Registers for each read cycle to verify the mode selections and status KXSS5 Embedded Registers The KXSS5 has 14 embedded 8-bit registers that are accessible by the user. This section contains the addresses for all embedded registers and also describes bit functions of each register. Table 8 and Table 9 below provide a listing of the accessible 8-bit registers and their addresses when in I2C mode and SPI Mode. Type Register Name XOUT_H XOUT_L YOUT_H YOUT_L ZOUT_H ZOUT_L Reset_write FF_INT FF_DELAY MOT_INT MOT_DELAY CTRL_REGC CTRL_REGB CTRL_REGA Read/Write R R R R R R W R/W R/W R/W R/W R/W R/W R Address Hex 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E Binary 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 Table 9. I2C Mode Register Map 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 19 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications Type Register Name XOUT_H XOUT_L YOUT_H YOUT_L ZOUT_H ZOUT_L Reset_write FF_INT FF_DELAY MOT_INT MOT_DELAY CTRL_REGC CTRL_REGB CTRL_REGA Read/Write R R R R R R W R/W R/W R/W R/W R/W R/W R Read Address Hex 0x80 0x81 0x82 0x83 0x84 0x85 xxxx 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E KXSS5-4457 Rev. 3 Feb-2013 Write Address Binary 1000 0000 1000 0001 1000 0010 1000 0011 1000 0100 1000 0101 xxxx xxxx 1000 1000 1000 1001 1000 1010 1000 1011 1000 1100 1000 1101 1000 1110 Hex xxxx xxxx xxxx xxxx xxxx xxxx 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D xxxx Binary xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0110 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 xxxx xxxx Table 10. SPI Mode Register Map Register Descriptions XOUT_H X-axis accelerometer output most significant byte R R R XOUTD11 XOUTD10 XOUTD9 Bit7 Bit6 Bit5 R XOUTD8 Bit4 R XOUTD7 Bit3 R XOUTD6 Bit2 R XOUTD5 Bit1 R XOUTD4 Bit0 2 I C Address: 0x00h SPI Read Address: 0x80h XOUT_L X-axis accelerometer output least significant byte R XOUTD3 Bit7 R XOUTD2 Bit6 R XOUTD1 Bit5 R XOUTD0 Bit4 R X Bit3 R X Bit2 R X Bit1 R X Bit0 2 I C Address: 0x01h SPI Read Address: 0x81h 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 20 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 YOUT_H Y-axis accelerometer output most significant byte R R R YOUTD11 YOUTD10 YOUTD9 Bit7 Bit6 Bit5 R YOUTD8 Bit4 R YOUTD7 Bit3 R YOUTD6 Bit2 R YOUTD5 Bit1 R YOUTD4 Bit0 2 I C Address: 0x02h SPI Read Address: 0x82h YOUT_L Y-axis accelerometer output least significant byte R YOUTD3 Bit7 R YOUTD2 Bit6 R YOUTD1 Bit5 R YOUTD0 Bit4 R X Bit3 R X Bit2 R X Bit1 R X Bit0 2 I C Address: 0x03h SPI Read Address: 0x83h ZOUT_H Z-axis accelerometer output most significant byte R R R ZOUTD11 ZOUTD10 ZOUTD9 Bit7 Bit6 Bit5 R ZOUTD8 Bit4 R ZOUTD7 Bit3 R ZOUTD6 Bit2 R ZOUTD5 Bit1 R ZOUTD4 Bit0 2 I C Address: 0x04h SPI Read Address: 0x84h ZOUT_L Z-axis accelerometer output least significant byte R ZOUTD3 Bit7 R ZOUTD2 Bit6 R ZOUTD1 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] R ZOUTD0 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 I2C Address: 0x05h SPI Read Address: 0x85h © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 21 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Reset_write When the key (11001010) is written to this register the offset, sensitivity and temperature correction values will be loaded into RAM and used for all further measurements. This can also be accomplished by transitioning the Enable pin (6) from low to high. W W W W W W W W 1 1 0 0 1 0 1 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 2 I C Address: 0x06h SPI Write Address: 0x06h CTRL_REGA Read-only status register R X Bit7 R X Bit6 R X Bit5 R X Bit4 R X Bit3 R X Bit2 R MOTI Bit1 R FFI Bit0 2 SPI Read Address: 0x8Eh I C Address: 0x0Eh SPI Write Address: 0x0Eh FFI reflects the status of the free-fall interrupt. When FFI = 1, the free-fall interrupt pin is high. When FFI = 0, the free-fall interrupt pin is low. The free-fall interrupt is reset by setting FFI = 0. MOTI reflects the status of the motion interrupt. When MOTI = 1, the motion- interrupt pin is high. When MOTI = 0, the motion-interrupt pin is low. The motion interrupt is reset by setting MOTI = 0. CTRL_REGB Read/write control register: Hardwired power up/reset default value (0x42h) R/W CLKhld Bit7 R/W ENABLE Bit6 R/W ST Bit5 R/W 0 Bit4 R/W 0 Bit3 R/W X Bit2 R/W FFIen Bit1 R/W X Bit0 Reset Value 01000010 2 SPI Read Address: 0x8Dh I C Address: 0x0Dh SPI Write Address: 0x0Dh FFIen enables the freefall interrupt. FFIen = 1 - an interrupt will be generated when the KXSS5 is in a predetermined free-fall state FFIen = 0 – a free-fall interrupt is never generated 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 22 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 ST activates the self-test function for the sensor elements on all three axes. A correctly functioning KXSS5 will increase all channel outputs when Self test = 1 and Enable = 1. This bit can be read or written. Enable powers up the KXSS5 for operation. Enable = 1 – normal operation Enable = 0 – low-power standby CLKhld allows the KXSS5 to hold the serial clock, SCL, low in I2C mode to force the transmitter into a wait state during A/D conversions. CLKhld = 1 – SCL held low during A/D conversions CLKhld = 0 – SCL unaffected CLKhld should be set to 0 when Enable is set to 0 (disabled) to prevent potential holding of the CLK line. CTRL_REGC Read/write control register: Hardwired power up/reset default value (0x00h) R/W X Bit7 R/W X Bit6 R/W X Bit5 R/W FFLat Bit4 R/W MOTLat Bit3 R/W 0 Bit2 R/W IntSpd1 Bit1 R/W IntSpd0 Bit0 Reset Value 00000000 2 SPI Read Address: 0x8Ch I C Address: 0x0Ch SPI Write Address: 0x0Ch IntSpd0 is the first of two bits used to select the rate at which the accelerometer is sampled when debouncing a potential interrupt event. See Table 11 below. IntSpd1 is the second of two bits used to select the rate at which the accelerometer is sampled when debouncing a potential interrupt event. See Table 11 below. IntSpd1 0 0 1 1 IntSpd0 0 1 0 1 Interrupt Frequency 250 Hz 1 kHz 4 kHz 16 kHZ Table 11. Interrupt Frequencies 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 23 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 MOTLat switches the motion interrupt function between latching and non-latching as shown in Figures 7 and 8. MOTLat = 0 - The motion interrupt output will go high whenever the criterion for motion detection is met. The output will return low when the criterion is not met. MOTLat = 1 - The motion interrupt output will go high whenever the criterion for motion detection is met. The interrupt output will remain high until the user toggles the MOT Enable pin (12) low. Typical Motion Interrupt Example (nonLatching) 255 Pos. Motion limit 216 Pos. Freefall limit 0g Neg. Freefall limit 148 Neg. Motion limit 40 128 108 0 Motion debounce timer 10 Set to 10 counts. FF/MOT Interrupt Figure 7. Typical Motion Interrupt Example (MOTLat = 0, MOTen = 1) 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 24 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Typical Motion Interrupt Example (Latching) 255 Pos. Motion limit 216 Pos. Freefall limit 0g Neg. Freefall limit 148 Neg. Motion limit 40 128 108 0 Motion debounce timer 10 Set to 10 counts. FF/MOT Interrupt Figure 8. Typical Motion Interrupt Example (MOTLat = 1, MOTen = 1) 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 25 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 FFLat switches the free-fall interrupt function between latching and non-latching as shown in Figures 9 and 10. FFLat = 0 - The free-fall interrupt output will go high whenever the criterion for free-fall detection is met. The output will return low when the criterion is not met. FFLat = 1 - The free-fall interrupt output will go high whenever the criterion for free-fall detection is met. The output will remain high until FFIen bit in CTRL_REGB is cycled low. Typical Freefall Interrupt Example (nonLatching) 255 Pos. Motion limit 216 Pos. Freefall limit 0g Neg. Freefall limit 148 Neg. Motion limit 40 128 108 0 Freefall debounce timer 10 Set to 10 counts. FF/MOT Interrupt Figure 9. Typical Free-fall Interrupt Example (FFLat = 0, MOTen = 0) 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 26 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Typical Freefall Interrupt Example (Latching) 255 Pos. Motion limit 216 Pos. Freefall limit 0g Neg. Freefall limit 148 Neg. Motion limit 40 128 108 0 Freefall debounce timer 10 Set to 10 counts. FF/MOT Interrupt Figure 10. Typical Free-fall Interrupt Example (FFLat = 1, MOTen = 0) FF_INT Sets the free-fall interrupt threshold to this value R/W FFI7 Bit7 R/W FFI6 Bit6 R/W FFI5 Bit5 R/W FFI4 Bit4 R/W FFI3 Bit3 R/W FFI2 Bit2 R/W FFI1 Bit1 R/W FFI0 Bit0 Reset Value 00001110 2 SPI Read Address: 0x88h 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] I C Address: 0x08h SPI Write Address: 0x08h © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 27 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 FF_DELAY Sets the free-fall delay/debounce time to this value R/W FFD7 Bit7 R/W FFD6 Bit6 R/W FFD5 Bit5 R/W FFD4 Bit4 R/W FFD3 Bit3 R/W FFD2 Bit2 R/W FFD1 Bit1 R/W FFD0 Bit0 Reset Value 00000001 2 SPI Read Address: 0x89h I C Address: 0x09h SPI Write Address: 0x09h Free-fall Detect The KXSS5 features a free-fall interrupt that sends a flag through pin 11 when the accelerometer senses a free-fall event. A free-fall event is evident when all three accelerometer axes simultaneously fall below a certain acceleration threshold for a set amount of time. The KXSS5 gives the user the option to define the acceleration threshold value through the FF_INT 8-bit register where 256 counts cover the g range of the accelerometer. Equation 1 below shows how to calculate the FF_INT value needed for a desired acceleration threshold based on the Sensitivity. FF _ INT (counts ) Threshold ( g ) * Sensitivit y(counts / g ) 16 Equation 1. FF_INT Calculation Through the FF_DELAY 8-bit register, the user can set the amount of time all three accelerometer axes must simultaneously remain below the FF_INT acceleration threshold before the free-fall interrupt flag is sent through pin 11. This delay/debounce time is defined by the available 0 to 255 counts, which represent accelerometer samples taken at the rate defined by IntSpd0 and IntSpd1. Equation 2 below shows how to calculate FF_DELAY for a desired debounce time (Delay) based on the Interrupt Sampling Rate (IntSpd0 and IntSpd1). FF _ DELAY (counts ) Delay (sec) * Interrupt Sampling Rate ( Hz) Equation 2. FF_DELAY Calculation When the Free-fall interrupt is enabled the part must not be in a physical state that would trigger the free-fall interrupt or the delay will not be correct for the present free-fall. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 28 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 MOT_INT Sets the motion activated interrupt acceleration threshold R/W MOTI7 Bit7 R/W MOTI6 Bit6 R/W MOTI5 Bit5 R/W MOTI4 Bit4 R/W MOTI3 Bit3 R/W MOTI2 Bit2 R/W MOTI1 Bit1 R/W MOTI0 Bit0 Reset Value 01010101 2 SPI Read Address: 0x8Ah I C Address: 0x0Ah SPI Write Address: 0x0Ah MOT_DELAY Sets the motion activated delay/debounce time to this value R/W MOTD7 Bit7 R/W MOTD6 Bit6 R/W MOTD5 Bit5 R/W MOTD4 Bit4 R/W MOTD3 Bit3 R/W MOTD2 Bit2 R/W MOTD1 Bit1 R/W MOTD0 Bit0 Reset Value 00000001 2 SPI Read Address: 0x8Bh I C Address: 0x0Bh SPI Write Address: 0x0Bh Motion Detect The KXSS5 also features a high-g motion interrupt that sends a flag through pin 11 when the accelerometer senses a high-g acceleration. A high-g acceleration is evident when any of the three accelerometer axes sense acceleration above a certain threshold for a set amount of time. The KXSS5 gives the user the option to define the acceleration threshold value through the MOT_INT 8-bit register where 256 counts cover the g range of the accelerometer. Equation 3 shows how to calculate the MOT_INT value needed for a desired acceleration threshold based on the Sensitivity. MOT _ INT (counts ) Threshold ( g ) * Sensitivit y(counts / g ) 16 Equation 3. MOT_INT Calculation Through the MOT_DELAY 8-bit register, the user can set the amount of time that any of the three accelerometer axes has to sense acceleration above a certain threshold before the motion interrupt flag is sent through pin 11. This delay/debounce time is defined by the available 0 to 255 counts, which represent accelerometer samples taken at the rate defined by IntSpd0 and IntSpd1. Equation 4 below shows how to calculate MOT_DELAY for a desired debounce time (Delay) based on the Interrupt Sampling Rate (IntSpd0 and IntSpd1). 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 29 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 MOT _ DELAY (counts ) Delay (sec) * Interrupt Sampling Rate ( Hz) Equation 4. MOT_DELAY Calculation When the Motion interrupt is enabled the part must not be in a physical state that would trigger the motion interrupt or the delay will not be correct for the present motion. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 30 of 31 PART NUMBER: ± 3g Tri-axis Accelerometer Specifications KXSS5-4457 Rev. 3 Feb-2013 Revision History REVISION 1 2 3 DESCRIPTION Initial release Updated to new format and revision numbering Update max VDD from 5.25V to 3.6V DATE 31-Jul-2009 17-Dec-2009 25-Feb-2013 "Kionix" is a registered trademark of Kionix, Inc. Products described herein are protected by patents issued or pending. No license is granted by implication or otherwise under any patent or other rights of Kionix. The information contained herein is believed to be accurate and reliable but is not guaranteed. Kionix does not assume responsibility for its use or distribution. Kionix also reserves the right to change product specifications or discontinue this product at any time without prior notice. This publication supersedes and replaces all information previously supplied. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2013 Kionix – All Rights Reserved 584-4259-1302251530 Page 31 of 31