AD ADXL346BCCZ-RL7

3-Axis, ±2 g/±4 g/±8 g/±16 g
Ultralow Power Digital Accelerometer
ADXL346
Preliminary Technical Data
FEATURES
GENERAL DESCRIPTION
Ultralow power: as low as 35 µA in measurement mode and
1 µA in standby mode at VS = 2.5 V (typical)
Power consumption scales automatically with bandwidth
User-selectable resolution
Fixed 10-bit resolution
Full resolution, where resolution increases with g range,
up to 13-bit resolution at ±16 g (maintaining 4 mg/LSB
scale factor in all g ranges)
Patent pending, embedded memory management system
with FIFO technology minimizes host processor load
Single tap/double tap detection
Activity/inactivity monitoring
Free-fall detection
Concurrent four- and six-position orientation detection
Supply and I/O voltage range: 1.7 V to 2.75 V
SPI (3- and 4-wire) and I2C digital interfaces
Flexible interrupt modes mappable to either interrupt pin
Measurement ranges selectable via serial command
Bandwidth selectable via serial command
Wide temperature range (−40°C to +85°C)
10,000 g shock survival
Pb free/RoHS compliant
Small and thin: 3 mm × 3 mm × 0.95 mm LGA package
The ADXL346 is a small, thin, ultralow power, 3-axis accelerometer
with high resolution (13-bit) measurement at up to ±16 g. Digital
output data is formatted as 16-bit twos complement and is accessible through either a SPI (3- or 4-wire) or I2C digital interface.
The ADXL346 is well suited for mobile device applications. It
measures the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion
or shock. Its high resolution (4 mg/LSB) enables measurement
of inclination changes less than 1.0°.
Several special sensing functions are provided. Activity and
inactivity sensing detect the presence or lack of motion by
comparing the acceleration on any axis with user-set thresholds.
Tap sensing detects single and double taps in any direction. Freefall sensing detects if the device is falling. Orientation detection
is capable of concurrent four- and six-position sensing and a
user-selectable interrupt on orientation change for 2-D or 3-D
applications. These functions can be mapped individually to
either of two interrupt output pins. An integrated, patent pending
memory management system with 32-level first in, first out (FIFO)
buffer can be used to store data to minimize host processor activity
and lower overall system power consumption.
Low power modes enable intelligent motion-based power
management with threshold sensing and active acceleration
measurement at extremely low power dissipation.
APPLICATIONS
Handsets
Medical instrumentation
Gaming and pointing devices
Industrial instrumentation
Personal navigation devices
Hard disk drive (HDD) protection
The ADXL346 is supplied in a small, thin, 3 mm × 3 mm ×
0.95 mm, 16-lead, plastic package.
FUNCTIONAL BLOCK DIAGRAM
VS
ADXL346
3-AXIS
SENSOR
VDD I/O
POWER
MANAGEMENT
SENSE
ELECTRONICS
ADC
DIGITAL
FILTER
32 LEVEL
FIFO
CONTROL
AND
INTERRUPT
LOGIC
INT1
INT2
SDA/SDI/SDIO
SERIAL I/O
SDO/ALT
ADDRESS
CS
GND
08167-001
SCL/SCLK
Figure 1.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners. See the last
page for disclaimers.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADXL346
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Self-Test ....................................................................................... 17
Applications....................................................................................... 1
Register Map ................................................................................... 19
General Description ......................................................................... 1
Register Definitions ................................................................... 20
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 25
Revision History ............................................................................... 2
Power Supply Decoupling ......................................................... 25
Specifications..................................................................................... 3
Mechanical Considerations for Mounting.............................. 25
Absolute Maximum Ratings............................................................ 4
Tap Detection.............................................................................. 25
Thermal Resistance ...................................................................... 4
Improved Tap Detection............................................................ 26
ESD Caution.................................................................................. 4
Tap Sign ....................................................................................... 26
Pin Configuration and Function Descriptions............................. 5
Threshold .................................................................................... 27
Typical Performance Characteristics ............................................. 6
Link Mode ................................................................................... 27
Theory of Operation ...................................................................... 10
Sleep Mode vs. Low Power Mode............................................. 27
Power Sequencing ...................................................................... 10
Using Self-Test ............................................................................ 27
Power Savings.............................................................................. 10
Orientation Sensing ................................................................... 28
Serial Communications ................................................................. 12
Axes of Acceleration Sensitivity ............................................... 29
SPI................................................................................................. 12
Layout and Design Recommendations ................................... 30
I2C ................................................................................................. 14
Outline Dimensions ....................................................................... 31
Interrupts ..................................................................................... 16
Ordering Guide .......................................................................... 31
FIFO ............................................................................................. 16
REVISION HISTORY
6/09—Revision PrC: Updated Specifications and functional descriptions of Orientation, Tap Sign and Improved Tap.
4/09—Revision PrB: Updated Absolute Maximum Ratings table to reflect correct values for the ADXL346.
3/09—Revision PrA: Initial Version
Rev. PrC | Page 2 of 32
Preliminary Technical Data
ADXL346
SPECIFICATIONS
TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V, acceleration = 0 g, CS = 10 μF tantalum, CIO = 0.1 μF, ODR = 800 Hz, unless otherwise noted.
Table 1. Specifications1
Parameter
SENSOR INPUT
Measurement Range
Nonlinearity
Inter-Axis Alignment Error
Cross-Axis Sensitivity2
OUTPUT RESOLUTION
All g Ranges
±2 g Range
±4 g Range
±8 g Range
±16 g Range
SENSITIVITY
Sensitivity at XOUT, YOUT, ZOUT
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity at XOUT, YOUT, ZOUT
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity at XOUT, YOUT, ZOUT
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity at XOUT, YOUT, ZOUT
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity Change Due to Temperature
0 g OFFSET
0 g Output for XOUT, YOUT, ZOUT
0 g Offset vs. Temperature for x-, y-, z-Axes
NOISE
x-, y-Axes
z-Axis
OUTPUT DATA RATE AND BANDWIDTH
Output Data Rate (ODR)3
SELF-TEST4
Output Change in x-Axis
Output Change in y-Axis
Output Change in z-Axis
POWER SUPPLY
Operating Voltage Range (VS)
Interface Voltage Range (VDD I/O)
Supply Current
Standby Mode Leakage Current
Turn-On and Wake-Up Time5
TEMPERATURE
Operating Temperature Range
WEIGHT
Device Weight
Test Conditions
Each axis
User selectable
Percentage of full scale
Each axis
10-bit resolution
Full resolution
Full resolution
Full resolution
Full resolution
Each axis
±2 g, 10-bit or full resolution
±2 g, 10-bit or full resolution
±4 g, 10-bit resolution
±4 g, 10-bit resolution
±8 g, 10-bit resolution
±8 g, 10-bit resolution
±16 g, 10-bit resolution
±16 g, 10-bit resolution
Min
230
3.5
115
7.1
57
14.1
29
28.6
Typ
Max
Unit
±2, ±4, ±8, ±16
±0.5
±0.1
±1
g
%
Degrees
%
10
10
11
12
13
Bits
Bits
Bits
Bits
Bits
256
3.9
128
7.8
64
15.6
32
31.2
±0.01
282
4.3
141
8.7
71
17.5
35
34.5
LSB/g
mg/LSB
LSB/g
mg/LSB
LSB/g
mg/LSB
LSB/g
mg/LSB
%/°C
+150
<±1.0
mg
mg/°C
<1.0
LSB rms
<1.5
LSB rms
Each axis
−150
ODR = 100 Hz for ±2 g, 10-bit or
full resolution
ODR = 100 Hz for ±2 g, 10-bit or
full resolution
User selectable
6.25
3200
Hz
0.27
−1.55
0.40
1.55
−0.27
1.95
g
g
g
2.75
VS
V
V
µA
µA
µA
ms
1.7
1.7
ODR ≥ 100 Hz
ODR < 10 Hz
ODR = 3200 Hz
2.5
1.8
140
35
1
1.4
−40
+85
18
1
10
°C
mg
All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.
Cross-axis sensitivity is defined as coupling between any two axes.
Bandwidth is the −3 dB frequency and is half the output data rate, bandwidth = ODR/2.
4
Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register) minus the output (g) when the SELF_TEST bit = 0 (in the
DATA_FORMAT register). Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). The part
needs to be in normal power operation (LOW_POWER bit = 0 in BW_RATE register) for self-test to operate correctly.
5
Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For
other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate).
2
3
Rev. PrC | Page 3 of 32
ADXL346
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Acceleration
Any Axis, Unpowered
Any Axis, Powered
VS
VDD I/O
Digital Pins
All Other Pins
Output Short-Circuit Duration
(Any Pin to Ground)
Temperature Range
Powered
Storage
Rating
10,000 g
10,000 g
−0.3 V to +2.75 V
−0.3 V to +2.75 V
−0.3 V to VDD I/O + 0.3 V or
2.75 V, whichever is less
−0.3 V to +2.75 V
Indefinite
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 3. Package Characteristics
Package Type
16-Terminal LGA
−40°C to +105°C
−40°C to +105°C
ESD CAUTION
Rev. PrC | Page 4 of 32
θJA
150°C/W
θJC
85°C/W
Device Weight
18 mg
Preliminary Technical Data
ADXL346
VDD I/O
GND
RESERVED
VS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16
15
14
1
NC
2
ADXL346
13
GND
12
GND
11
INT1
10
NC
+X
5
NC = NO INTERNAL
CONNECTION
+Z
9
6
7
8
INT2
TOP VIEW
(Not to Scale)
08167-002
NC
+Y
CS
4
SDO/
ALT ADDRESS
3
SDA/SDI/SDIO
NC
SCL/SCLK
Figure 2. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
VDD I/O
NC
NC
SCL/SCLK
NC
SDA/SDI/SDIO
SDO/ALT ADDRESS
CS
INT2
NC
INT1
GND
GND
VS
Reserved
GND
Description
Digital Interface Supply Voltage.
Not Internally Connected.
Not Internally Connected.
Serial Communications Clock.
Not Internally Connected.
Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire).
Serial Data Output (SPI 4-Wire)/Alternate I2C Address Select (I2C).
Chip Select.
Interrupt 2 Output.
Not Internally Connected.
Interrupt 1 Output.
Must be connected to ground.
Must be connected to ground.
Supply Voltage.
Reserved. This pin must be connected to VS.
Must be connected to ground.
Rev. PrC | Page 5 of 32
ADXL346
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. X-Axis Zero g Offset at 25°C, VS = 2.5 V
Figure 6. X-Axis Self-Test Response at 25°C, VS = 2.5 V
Figure 4. Y-Axis Zero g Offset at 25°C, VS = 2.5 V
Figure 7. Y-Axis Self-Test Response at 25°C, VS = 2.5 V
Figure 5. Z-Axis Zero g Offset at 25°C, VS = 2.5 V
Figure 8. Z-Axis Self-Test Response at 25°C, VS = 2.5 V
Rev. PrC | Page 6 of 32
Preliminary Technical Data
ADXL346
Figure 9. X-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V
Figure 12. X-Axis Zero g Offset vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V
Figure 10. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V
Figure 13. Y-Axis Zero g Offset vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V
Figure 11. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V
Figure 14. Z-Axis Zero g Offset vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V
Rev. PrC | Page 7 of 32
ADXL346
Preliminary Technical Data
Figure 15. X-Axis Sensitivity at 25°C, VS = 2.5 V
Figure 18. Supply Current at 25°C, 100 Hz Output Data Rate,
VS = 2.5 V
Figure 16. Y-Axis Sensitivity at 25°C, VS = 2.5 V
Figure 19. Supply Current vs. Output Data Rate at 25°C—10 Parts, VS = 2.5 V
Figure 17. Z-Axis Sensitivity at 25°C, VS = 2.5 V
Figure 20. Supply Current vs. VS at 25°C
Rev. PrC | Page 8 of 32
Preliminary Technical Data
ADXL346
Figure 21. X-Axis Sensitivity Temperature Coefficient, VS = 2.5 V
Figure 24. X-Axis Sensitivity vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V
Figure 22. Y-Axis Sensitivity Temperature Coefficient, VS = 2.5 V
Figure 25. Y-Axis Sensitivity vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V
Figure 23. Z-Axis Sensitivity Temperature Coefficient, VS = 2.5 V
Figure 26. Z-Axis Sensitivity vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V
Rev. PrC | Page 9 of 32
ADXL346
Preliminary Technical Data
THEORY OF OPERATION
The ADXL346 is a complete 3-axis acceleration measurement
system with a selectable measurement range of ±2 g, ±4 g, ±8 g,
or ±16 g. It measures both dynamic acceleration resulting from
motion or shock and static acceleration, such as gravity, which
allows the device to be used as a tilt sensor.
The sensor is a polysilicon surface-micromachined structure
built on top of a silicon wafer. Polysilicon springs suspend the
structure over the surface of the wafer and provide a resistance
against forces due to applied acceleration.
Deflection of the structure is measured using differential capacitors
that consist of independent fixed plates and plates attached to the
moving mass. Acceleration deflects the proof mass and
unbalances the differential capacitor, resulting in a sensor output
whose amplitude is proportional to acceleration. Phase-sensitive
demodulation is used to determine the magnitude and polarity of
the acceleration.
POWER SEQUENCING
Power can be applied to VS or VDD I/O in any sequence without
damaging the ADXL346. All possible power-on modes are
summarized in Table 5. The interface voltage level is set with
the interface supply voltage, VDD I/O, which must be present to
ensure that the ADXL346 does not create a conflict on the
communication bus. For single-supply operation, VDD I/O can be
the same as the main supply, VS. In a dual-supply application,
however, VDD I/O can differ from VS to accommodate the desired
interface voltage, as long as VS is greater than or equal to VDD I/O.
After VS is applied, the device enters standby mode, where power
consumption is minimized and the device waits for VDD I/O to be
applied and for the command to enter measurement mode to be
received. (This command can be initiated by setting the measure
bit in the POWER_CTL register (Address 0x2D).) In addition, any
register can be written to or read from to configure the part while
the device is in standby mode. It is recommended to configure the
device in standby mode and then to enable measurement mode.
Clearing the measure bit returns the device to the standby mode.
Table 5. Power Sequencing
Condition
Power Off
VS
Off
VDD I/O
Off
Bus Disabled
On
Off
Bus Enabled
Off
On
Standby or
Measurement
On
On
Description
The device is completely off, but there is a
potential for a communication bus
conflict.
The device is on in standby mode, but
communication is unavailable and will
create a conflict on the communication
bus. The duration of this state should be
minimized during power-up to prevent a
conflict.
No functions are available, but the
device will not create a conflict on the
communication bus.
At power-up, the device is in standby
mode, awaiting a command to enter
measurement mode, and all sensor
functions are off. After the device is
instructed to enter measurement mode,
all sensor functions are available.
POWER SAVINGS
Power Modes
The ADXL346 automatically modulates its power consumption
in proportion to its output data rate, as outlined in Table 6. If
additional power savings is desired, a lower power mode is
available. In this mode, the internal sampling rate is reduced,
allowing for power savings in the 12.5 Hz to 400 Hz data rate
range at the expense of slightly greater noise. To enter low
power mode, set the LOW_POWER bit (Bit 4) in the BW_RATE
register (Address 0x2C). The current consumption in low power
mode is shown in Table 7 for cases where there is an advantage
to using low power mode. The current consumption values
shown in Table 6 and Table 7 are for a VS of 2.5 V.
Table 6. Typical Current Consumption vs. Data Rate
(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Output Data
Rate (Hz)
3200
1600
800
400
200
100
50
25
12.5
6.25
Bandwidth (Hz)
1600
800
400
200
100
50
25
12.5
6.25
3.125
Rate Code
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
IDD (µA)
140
90
140
140
140
140
90
60
45
35
Table 7. Typical Current Consumption vs. Data Rate, Low
Power Mode (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Output Data
Rate (Hz)
400
200
100
50
25
12.5
Rev. PrC | Page 10 of 32
Bandwidth (Hz)
200
100
50
25
12.5
6.25
Rate Code
1100
1011
1010
1001
1000
0111
IDD (µA)
90
60
45
35
35
35
Preliminary Technical Data
ADXL346
Auto Sleep Mode
Standby Mode
Additional power can be saved if the ADXL346 automatically
switches to sleep mode during periods of inactivity. To enable
this feature, set the THRESH_INACT register (Address 0x25)
and the TIME_INACT register (Address 0x26) each to a value
that signifies inactivity (the appropriate value depends on the
application), and then set the AUTO_SLEEP bit and the link bit in
the POWER_CTL register (Address 0x2D). Current consumption
at the sub-8 Hz data rates used in this mode is typically 35 µA
for a VS of 2.5 V.
For even lower power operation, standby mode can be used.
In standby mode, current consumption is reduced to 1 µA
(typical). In this mode, no measurements are made. Standby mode
is entered by clearing the measure bit (Bit 3) in the
POWER_CTL register (Address 0x2D). Placing the device into
standby mode preserves the contents of FIFO.
Rev. PrC | Page 11 of 32
ADXL346
Preliminary Technical Data
SERIAL COMMUNICATIONS
SPI
For SPI, either 3- or 4-wire configuration is possible, as shown
in the connection diagrams in Figure 27 and Figure 28. Clearing
the SPI bit in the DATA_FORMAT register (Address 0x31) selects
4-wire mode, whereas setting the SPI bit selects 3-wire mode.
The maximum SPI clock speed is 5 MHz with 100 pF maximum
loading, and the timing scheme follows clock polarity (CPOL) = 1
and clock phase (CPHA) = 1.
CS is the serial port enable line and is controlled by the SPI master.
This line must go low at the start of a transmission and high at
the end of a transmission, as shown in Figure 29. SCLK is the
serial port clock and is supplied by the SPI master. It is stopped
high when CS is high during a period of no transmission. SDI
and SDO are the serial data input and output, respectively. Data
should be sampled at the rising edge of SCLK.
ADXL346
PROCESSOR
D OUT
CS
D IN/OUT
SDO
SCLK
D OUT
PROCESSOR
CS
D OUT
SDI
D OUT
SDO
SCLK
D IN
D OUT
Figure 28. 4-Wire SPI Connection Diagram
To read or write multiple bytes in a single transmission, the
multiple-byte bit, located after the R/W bit in the first byte transfer
(MB in Figure 29 to Figure 31), must be set. After the register
addressing and the first byte of data, each subsequent set of
clock pulses (eight clock pulses) causes the ADXL346 to point
to the next register for a read or write. This shifting continues
until the clock pulses cease and CS is deasserted. To perform reads
or writes on different, nonsequential registers, CS must be
deasserted between transmissions and the new register must be
addressed separately.
The timing diagram for 3-wire SPI reads or writes is shown in
Figure 31. The 4-wire equivalents for SPI writes and reads are
shown in Figure 29 and Figure 30, respectively.
Table 8. SPI Digital Input/Output Voltage
Parameter
Digital Input Voltage
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Digital Output Voltage
Low Level Output Voltage (VOL)
High Level Output Voltage (VOH)
1
Limit1
Unit
0.3 × VDD I/O
0.7 × VDD I/O
V max
V min
0.2 × VDD I/O
0.8 × VDD I/O
V max
V min
Limits based on characterization results, not production tested.
08167-027
SDIO
ADXL346
08167-028
I2C and SPI digital communications are available. In both cases,
the ADXL346 operates as a slave. I2C mode is enabled if the CS pin
is tied high to VDD I/O. The CS pin should always be tied high to
VDD I/O or be driven by an external controller because there is no
default mode if the CS pin is left unconnected. Therefore, not
taking these precautions may result in an inability to communicate
with the part. In SPI mode, the CS pin is controlled by the bus
master. In both SPI and I2C modes of operation, data transmitted
from the ADXL346 to the master device should be ignored during
writes to the ADXL346.
Figure 27. 3-Wire SPI Connection Diagram
Table 9. SPI Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)1
Parameter
fSCLK
tSCLK
tDELAY
tQUIET
tDIS
tCS,DIS
tS
tM
tSDO
tSETUP
tHOLD
Min
Limit2, 3
Max
5
200
10
10
100
250
0.4 × tSCLK
0.4 × tSCLK
95
10
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
SPI clock frequency
1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
CS falling edge to SCLK falling edge
SCLK rising edge to CS rising edge
CS rising edge to SDO disabled
CS deassertion between SPI communications
SCLK low pulse width (space)
SCLK high pulse width (mark)
SCLK falling edge to SDO transition
SDI valid before SCLK rising edge
SDI valid after SCLK rising edge
The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
Limits based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested.
3
The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 8.
1
2
Rev. PrC | Page 12 of 32
Preliminary Technical Data
ADXL346
CS
tM
tSCLK
tDELAY
tS
tQUIET
tCS,DIS
SCLK
tHOLD
W
SDI
MB
A5
tSDO
X
SDO
A0
D7
ADDRESS BITS
X
D0
tDIS
DATA BITS
X
X
X
08167-029
tSETUP
X
Figure 29. SPI 4-Wire Write
CS
tSCLK
tDELAY
tM
tS
tCS,DIS
tQUIET
SCLK
tHOLD
R
SDI
MB
A5
tSDO
X
SDO
A0
X
X
tDIS
ADDRESS BITS
X
X
X
D7
D0
08167-030
tSETUP
DATA BITS
Figure 30. SPI 4-Wire Read
CS
tDELAY
tM
tSCLK
tS
tQUIET
tCS,DIS
SCLK
tSETUP
SDIO
tSDO
tHOLD
R/W
MB
A5
A0
ADDRESS BITS
D7
D0
DATA BITS
08167-031
SDO
NOTES
1. tSDO IS ONLY PRESENT DURING READS.
Figure 31. SPI 3-Wire Read/Write
Rev. PrC | Page 13 of 32
ADXL346
Preliminary Technical Data
I2C
If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed VDD I/O
by more than 0.3 V. External pull-up resistors, RP, are necessary
for proper I2C operation. Refer to the UM10204 I2C-Bus
Specification and User Manual, Rev. 03—19 June 2007, when
selecting pull-up resistor values to ensure proper operation.
With CS tied high to VDD I/O, the ADXL346 is in I2C mode,
requiring a simple 2-wire connection as shown in Figure 32.
The ADXL346 conforms to the UM10204 I2C-Bus Specification
and User Manual, Rev. 03—19 June 2007, available from NXP
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)
data transfer modes if the parameters given in Table 10 and
Table 11 are met. Single- or multiple-byte reads/writes are
supported, as shown in Figure 33. With the ALT ADDRESS pin
high, the 7-bit I2C address for the device is 0x1D, followed by the
R/W bit. This translates to 0x3A for a write and 0x3B for a read. An
alternate I2C address of 0x53 (followed by the R/W bit) can be
chosen by grounding the ALT ADDRESS pin (Pin 7). This
translates to 0xA6 for a write and 0xA7 for a read.
Table 10. I2C Digital Input/Output Voltage
Parameter
Digital Input Voltage
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Digital Output Voltage
Low Level Output Voltage (VOL)2
1
2
Limit1
Unit
0.3 × VDD I/O
0.7 × VDD I/O
V max
V min
0.2 × VDD I/O
V max
Limits based on characterization results; not production tested.
The limit given is only for VDD I/O < 2 V. When VDD I/O > 2 V, the limit is 0.4 V max.
VDD I/O
ADXL346
RP
RP
PROCESSOR
CS
SDA
D IN/OUT
ALT ADDRESS
D OUT
08167-032
SCL
Figure 32. I2C Connection Diagram (Address 0x53)
SINGLE-BYTE WRITE
MASTER START
SLAVE ADDRESS + WRITE
SLAVE
STOP
DATA
REGISTER ADDRESS
ACK
ACK
ACK
MULTIPLE-BYTE WRITE
MASTER START
SLAVE ADDRESS + WRITE
SLAVE
DATA
REGISTER ADDRESS
ACK
ACK
DATA
STOP
ACK
ACK
SINGLE-BYTE READ
MASTER START
SLAVE ADDRESS + WRITE
SLAVE
START1
REGISTER ADDRESS
ACK
SLAVE ADDRESS + READ
ACK
NACK
ACK
DATA
ACK
DATA
STOP
MULTIPLE-BYTE READ
SLAVE ADDRESS + WRITE
START1
REGISTER ADDRESS
ACK
ACK
SLAVE ADDRESS + READ
ACK
NOTES
1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.
2. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
Figure 33. I2C Device Addressing
Rev. PrC | Page 14 of 32
NACK
STOP
DATA
08167-033
MASTER START
SLAVE
Preliminary Technical Data
ADXL346
Table 11. I2C Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Parameter
fSCL
t1
t2
t3
t4
t5
t63, 4, 5, 6
t7
t8
t9
t10
Limit1, 2
Max
400
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
Unit
kHz
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
pF
0.9
300
0
t11
250
300
20 + 0.1 Cb7
Cb
400
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT, data hold time
tSU, STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus-free time between a stop condition and a start condition
tR, rise time of both SCL and SDA when receiving
tR, rise time of both SCL and SDA when receiving or transmitting
tF, fall time of SDA when receiving
tF, fall time of both SCL and SDA when transmitting
tF, fall time of both SCL and SDA when transmitting or receiving
Capacitive load for each bus line
1
Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.
All values referred to the VIH and the VIL levels given in Table 10.
3
t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.
4
A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH(min) of the SCL signal) to bridge the undefined region of
the falling edge of SCL.
5
The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal.
6
The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 − t10 − t5(min).
7
Cb is the total capacitance of one bus line in picofarads.
2
SDA
t3
t9
t10
t4
t11
SCL
t6
t2
t5
t7
REPEATED
START
CONDITION
Figure 34. I2C Timing Diagram
Rev. PrC | Page 15 of 32
t1
t8
STOP
CONDITION
08167-034
t4
START
CONDITION
ADXL346
Preliminary Technical Data
INTERRUPTS
The ADXL346 provides two output pins for driving interrupts:
INT1 and INT2. Each interrupt function is described in detail
in this section. All functions can be used simultaneously, with
the only limiting feature being that some functions may need
to share interrupt pins.
Interrupts are enabled by setting the appropriate bit in the
INT_ENABLE register (Address 0x2E) and are mapped to
either the INT1 or INT2 pin based on the contents of the
INT_MAP register (Address 0x2F). It is recommended that
interrupt bits be configured with the interrupts disabled,
preventing interrupts from being accidentally triggered during
configuration. This can be done by writing a value of 0x00 to the
INT_ENABLE register.
Clearing interrupts is performed either by reading the data
registers (Address 0x32 to Address 0x37) until the interrupt
condition is no longer valid for the data-related interrupts or by
reading the INT_SOURCE register (Address 0x30) for the
remaining interrupts. This section describes the interrupts that
can be set in the INT_ENABLE register and monitored in the
INT_SOURCE register.
DATA_READY
The DATA_READY bit is set when new data is available and is
cleared when no new data is available.
SINGLE_TAP
The SINGLE_TAP bit is set when a single acceleration event
that is greater than the value in the THRESH_TAP register
(Address 0x1D) occurs for less time than is specified in
the DUR register (Address 0x21).
DOUBLE_TAP
The DOUBLE_TAP bit is set when two acceleration events that
are greater than the value in the THRESH_TAP register
(Address 0x1D) occur for less time than is specified in the DUR
register (Address 0x21), with the second tap starting after the
time specified by the latent register (Address 0x22) but within
the time specified in the window register (Address 0x23). See the
Tap Detection section for more details.
Activity
The activity bit is set when acceleration greater than the value
stored in the THRESH_ACT register (Address 0x24) is
experienced.
Inactivity
The inactivity bit is set when acceleration of less than the value
stored in the THRESH_INACT register (Address 0x25) is experienced for more time than is specified in the TIME_INACT
register (Address 0x26). The maximum value for TIME_INACT
is 255 sec.
FREE_FALL
The FREE_FALL bit is set when acceleration of less than the
value stored in the THRESH_FF register (Address 0x28) is
experienced for more time than is specified in the TIME_FF
register (Address 0x29). The FREE_FALL interrupt differs from
the inactivity interrupt as follows: all axes always participate, the
timer period is much smaller (1.28 sec maximum), and the mode
of operation is always dc-coupled.
Watermark
The watermark bit is set when the number of samples in FIFO
equals the value stored in the samples bits (Register FIFO_CTL,
Address 0x38). The watermark bit is cleared automatically when
FIFO is read, and the content returns to a value below the value
stored in the samples bits.
Overrun
The overrun bit is set when new data replaces unread data. The
precise operation of the overrun function depends on the FIFO
mode. In bypass mode, the overrun bit is set when new data
replaces unread data in the DATAX, DATAY, and DATAZ registers
(Address 0x32 to Address 0x37). In all other modes, the overrun
bit is set when FIFO is filled. The overrun bit is automatically
cleared when the contents of FIFO are read.
Orientation
The orientation bit is set when the orientation of the accelerometer
changes from a valid orientation to different valid orientation.
An interrupt is not generated, however, if the orientation of the
accelerometer changes from a valid orientation to an invalid
orientation, or from a valid orientation to an invalid orientation
and then back to the same valid orientation. An invalid orientation
is defined as an orientation within the dead zone, or region of
hysteresis. This region helps to prevent rapid orientation change
due to noise when the accelerometer orientation is close to the
boundary between two valid orientations.
The orientations that are valid for the interrupt depends on which
mode, 2-D or 3-D, is linked to the orientation interrupt. The mode
is selected with the INT_3D bit in the ORIENT_CONF register
(Address 0x3B). Refer to the Register 0x3B—ORIENT_CONF
(Read/Write) section for more details on how to enable the
orientation interrupt.
FIFO
The ADXL346 contains patent pending technology for an
embedded memory management system with 32-level FIFO
that can be used to minimize host processor burden. This buffer
has four modes: bypass, FIFO, stream, and trigger (see Table
20). Each mode is selected by the settings of the FIFO_MODE
bits in the FIFO_CTL register (Address 0x38).
Bypass Mode
In bypass mode, FIFO is not operational and, therefore,
remains empty.
FIFO Mode
In FIFO mode, data from measurements of the x-, y-, and z-axes
are stored in FIFO. When the number of samples in FIFO
equals the level specified in the samples bits of the FIFO_CTL
register (Address 0x38), the watermark interrupt is set. FIFO
Rev. PrC | Page 16 of 32
Preliminary Technical Data
ADXL346
continues accumulating samples until it is full (32 samples from
measurements of the x-, y-, and z-axes) and then stops collecting
data. After FIFO stops collecting data, the device continues to
operate; therefore, features such as tap detection can be used
after FIFO is full. The watermark interrupt continues to occur
until the number of samples in FIFO is less than the value
stored in the samples bits of the FIFO_CTL register.
Stream Mode
In stream mode, data from measurements of the x-, y-, and zaxes are stored in FIFO. When the number of samples in FIFO
equals the level specified in the samples bits of the FIFO_CTL
register (Address 0x38), the watermark interrupt is set. FIFO
continues accumulating samples and holds the latest 32 samples
from measurements of the x-, y-, and z-axes, discarding older
data as new data arrives. The watermark interrupt continues
occurring until the number of samples in FIFO is less than the
value stored in the samples bits of the FIFO_CTL register.
Trigger Mode
In trigger mode, FIFO accumulates samples, holding the latest
32 samples from measurements of the x-, y-, and z-axes. After
a trigger event occurs and an interrupt is sent to the INT1 or
INT2 pin (determined by the trigger bit in the FIFO_CTL register),
FIFO keeps the last n samples (where n is the value specified by
the samples bits in the FIFO_CTL register) and then operates in
FIFO mode, collecting new samples only when FIFO is not full.
A delay of at least 5 μs should be present between the trigger event
occurring and the start of reading data from the FIFO to allow
the FIFO to discard and retain the necessary samples. Additional
trigger events cannot be recognized until the trigger mode is
reset. To reset the trigger mode, set the device to bypass mode
and then set the device back to trigger mode. Note that the FIFO
data should be read first because placing the device into bypass
mode clears FIFO.
the FIFO has completely popped. For SPI operation greater than
1.6 MHz, it is necessary to deassert the CS pin to ensure a total
delay of 5 μs; otherwise, the delay will not be sufficient. The total
delay necessary for 5 MHz operation is at most 3.4 μs. This is
not a concern when using I2C mode because the communication
rate is low enough to ensure a sufficient delay between FIFO reads.
SELF-TEST
The ADXL346 incorporates a self-test feature that effectively
tests its mechanical and electronic systems simultaneously.
When the self-test function is enabled (via the SELF_TEST bit
in the DATA_FORMAT register, Address 0x31), an electrostatic
force is exerted on the mechanical sensor. This electrostatic force
moves the mechanical sensing element in the same manner as
acceleration, and it is additive to the acceleration experienced
by the device. This added electrostatic force results in an output
change in the x-, y-, and z-axes. Because the electrostatic force
is proportional to VS2, the output change varies with VS. This
effect is shown in Figure 35. The scale factors shown in Table 12
can be used to adjust the expected self-test output limits for
different supply voltages, VS. The self-test feature of the ADXL346
also exhibits a bimodal behavior. However, the limits shown in
Table 1 and Table 13 to Table 16 are valid for both potential selftest values due to bimodality. Use of the self-test feature at data
rates less than 100 Hz may yield values outside these limits.
Therefore, the part should be placed into a data rate of 100 Hz
or greater when using self-test. The part also needs to be in
normal power operation (LOW_POWER bit = 0 in BW_RATE
register, Address 0x2C) for self-test to operate correctly.
Retrieving Data from FIFO
The FIFO data is read through the DATAX, DATAY, and DATAZ
registers (Address 0x32 to Address 0x37). When the FIFO is in
FIFO, stream, or trigger mode, reads to the DATAX, DATAY,
and DATAZ registers read data stored in the FIFO. Each time
data is read from the FIFO, the oldest x-, y-, and z-axes data are
placed into the DATAX, DATAY and DATAZ registers.
If a single-byte read operation is performed, the remaining
bytes of data for the current FIFO sample are lost. Therefore, all
axes of interest should be read in a burst (or multiple-byte) read
operation. To ensure that the FIFO has completely popped (that
is, that new data has completely moved into the DATAX, DATAY,
and DATAZ registers), there must be at least 5 μs between the
end of reading the data registers and the start of a new read of
the FIFO or a read of the FIFO_STATUS register (Address 0x39).
The end of reading a data register is signified by the transition
from Register 0x37 to Register 0x38 or by the CS pin going high.
For SPI operation at 1.6 MHz or less, the register addressing
portion of the transmission is a sufficient delay to ensure that
Figure 35. Self-Test Output Change Limits vs. Supply Voltage
Table 12. Self-Test Output Scale Factors for Different Supply
Voltages, VS
Supply Voltage, VS
1.70 V
1.80 V
2.00 V
2.50 V
2.75 V
Rev. PrC | Page 17 of 32
X-, y-Axes
TBD
TBD
TBD
1.00
TBD
Z-Axis
TBD
TBD
TBD
1.00
TBD
ADXL346
Preliminary Technical Data
Table 13. Self-Test Output in LSB for ±2 g, 10-Bit or Full
Resolution (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Axis
X
Y
Z
Min
62
−437
92
Max
437
−62
550
Unit
LSB
LSB
LSB
Table 14. Self-Test Output in LSB for ±4 g, 10-Bit Resolution
(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Axis
X
Y
Z
Min
31
−219
46
Max
219
−31
275
Unit
LSB
LSB
LSB
Table 15. Self-Test Output in LSB for ±8 g, 10-Bit Resolution
(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Axis
X
Y
Z
Min
15
−109
23
Max
109
−15
138
Unit
LSB
LSB
LSB
Table 16. Self-Test Output in LSB for ±16 g, 10-Bit Resolution
(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Axis
X
Y
Z
Min
8
−54
12
Max
54
−8
68
Unit
LSB
LSB
LSB
Rev. PrC | Page 18 of 32
Preliminary Technical Data
ADXL346
REGISTER MAP
Table 17. Register Map
Hex
0x00
0x01 to
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
Address
Dec
0
1 to
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
DEVID
Reserved
Type
R
Reset Value
11100101
Description
Device ID.
Reserved. Do not access.
THRESH_TAP
OFSX
OFSY
OFSZ
DUR
Latent
Window
THRESH_ACT
THRESH_INACT
TIME_INACT
ACT_INACT_CTL
THRESH_FF
TIME_FF
TAP_AXES
ACT_TAP_STATUS
BW_RATE
POWER_CTL
INT_ENABLE
INT_MAP
INT_SOURCE
DATA_FORMAT
DATAX0
DATAX1
DATAY0
DATAY1
DATAZ0
DATAZ1
FIFO_CTL
FIFO_STATUS
TAP_SIGN
ORIENT_CONF
Orient
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R
R
R
R
R
R
R/W
R
R
R/W
R
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00001010
00000000
00000000
00000000
00000010
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Tap threshold.
X-axis offset.
Y-axis offset.
Z-axis offset.
Tap duration.
Tap latency.
Tap window.
Activity threshold.
Inactivity threshold.
Inactivity time.
Axis enable control for activity and inactivity detection.
Free-fall threshold.
Free-fall time.
Axis control for single tap/double tap.
Source of single tap/double tap.
Data rate and power mode control.
Power-saving features control.
Interrupt enable control.
Interrupt mapping control.
Source of interrupts.
Data format control.
X-Axis Data 0.
X-Axis Data 1.
Y-Axis Data 0.
Y-Axis Data 1.
Z-Axis Data 0.
Z-Axis Data 1.
FIFO control.
FIFO status.
Sign and source for single tap/double tap
Orientation configuration
Orientation status
Rev. PrC | Page 19 of 32
ADXL346
Preliminary Technical Data
Register 0x25—THRESH_INACT (Read/Write)
REGISTER DEFINITIONS
Register 0x00—DEVID (Read Only)
The DEVID register holds a fixed device ID code of 0xE6
(346 octal).
The THRESH_INACT register is eight bits and holds the threshold
value for detecting inactivity. The data format is unsigned, so
the magnitude of the inactivity event is compared with the value
in the THRESH_INACT register. The scale factor is 62.5 mg/LSB.
A value of 0 may result in undesirable behavior if the inactivity
interrupt is enabled.
Register 0x1D—THRESH_TAP (Read/Write)
Register 0x26—TIME_INACT (Read/Write)
The THRESH_TAP register is eight bits and holds the threshold
value for tap interrupts. The data format is unsigned, so the
magnitude of the tap event is compared with the value in
THRESH_TAP for normal tap detection. For information on
improved tap detection, refer to the Improved Tap Detection
section. The scale factor is 62.5 mg/LSB (that is, 0xFF = +16 g).
A value of 0 may result in undesirable behavior if single tap/
double tap interrupts are enabled.
The TIME_INACT register is eight bits and contains an unsigned
time value representing the amount of time that acceleration
must be less than the value in the THRESH_INACT register for
inactivity to be declared. The scale factor is 1 sec/LSB. Unlike
the other interrupt functions, which use unfiltered data (see the
Threshold section), the inactivity function uses filtered output
data. At least one output sample must be generated for the
inactivity interrupt to be triggered. This results in the function
appearing unresponsive if the TIME_INACT register is set to a
value less than the time constant of the output data rate. A value
of 0 results in an interrupt when the output data is less than the
value in the THRESH_INACT register.
D7
1
D6
1
D5
1
D4
0
D3
0
D2
1
D1
1
D0
0
Register 0x1E, Register 0x1F, Register 0x20—OFSX,
OFSY, OFSZ (Read/Write)
The OFSX, OFSY, and OFSZ registers are each eight bits and
offer user-set offset adjustments in twos complement format
with a scale factor of 15.6 mg/LSB (that is, 0x7F = +2 g).
Register 0x21—DUR (Read/Write)
The DUR register is eight bits and contains an unsigned time
value representing the maximum time that an event must be
above the THRESH_TAP threshold to qualify as a tap event. For
information on improved tap detection, refer to the Improved Tap
Detection section. The scale factor is 625 µs/LSB. A value of 0
disables the single tap/double tap functions.
Register 0x22—Latent (Read/Write)
The latent register is eight bits and contains an unsigned time
value representing the wait time from the detection of a tap
event to the start of the time window (defined by the window
register) during which a possible second tap event can be detected.
For information on improved tap detection, refer to the Improved
Tap Detection section. The scale factor is 1.25 ms/LSB. A value of 0
disables the double tap function.
Register 0x23—Window (Read/Write)
Register 0x27—ACT_INACT_CTL (Read/Write)
D7
ACT ac/dc
D3
INACT ac/dc
D6
ACT_X enable
D2
INACT_X enable
D5
ACT_Y enable
D1
INACT_Y enable
D4
ACT_Z enable
D0
INACT_Z enable
ACT AC/DC and INACT AC/DC Bits
A setting of 0 selects dc-coupled operation, and a setting of 1
enables ac-coupled operation. In dc-coupled operation, the
current acceleration magnitude is compared directly with
THRESH_ACT and THRESH_INACT to determine whether
activity or inactivity is detected.
In ac-coupled operation for activity detection, the acceleration
value at the start of activity detection is taken as a reference
value. New samples of acceleration are then compared to this
reference value, and if the magnitude of the difference exceeds
the THRESH_ACT value, the device triggers an activity interrupt.
The window register is eight bits and contains an unsigned time
value representing the amount of time after the expiration of the
latency time (determined by the latent register) during which a
second valid tap can begin. For information on improved tap
detection, refer to the Improved Tap Detection section. The scale
factor is 1.25 ms/LSB. A value of 0 disables the double tap
function.
Similarly, in ac-coupled operation for inactivity detection, a
reference value is used for comparison and is updated whenever
the device exceeds the inactivity threshold. After the reference
value is selected, the device compares the magnitude of the
difference between the reference value and the current acceleration
with THRESH_INACT. If the difference is less than the value in
THRESH_INACT for the time in TIME_INACT, the device is
considered inactive and the inactivity interrupt is triggered.
Register 0x24—THRESH_ACT (Read/Write)
ACT_x Enable Bits and INACT_x Enable Bits
The THRESH_ACT register is eight bits and holds the threshold
value for detecting activity. The data format is unsigned, so the
magnitude of the activity event is compared with the value in
the THRESH_ACT register. The scale factor is 62.5 mg/LSB.
A value of 0 may result in undesirable behavior if the activity
interrupt is enabled.
A setting of 1 enables x-, y-, or z-axis participation in detecting
activity or inactivity. A setting of 0 excludes the selected axis
from participation. If all axes are excluded, the function is disabled.
Rev. PrC | Page 20 of 32
Preliminary Technical Data
ADXL346
Register 0x28—THRESH_FF (Read/Write)
The THRESH_FF register is eight bits and holds the threshold
value, in unsigned format, for free-fall detection. The root-sumsquare (RSS) value of all axes is calculated and compared with
the value in THRESH_FF to determine if a free-fall event occurred.
The scale factor is 62.5 mg/LSB. Note that a value of 0 mg may
result in undesirable behavior if the free-fall interrupt is enabled.
Values between 300 mg and 600 mg (0x05 to 0x09) are
recommended.
The TIME_FF register is eight bits and stores an unsigned time
value representing the minimum time that the RSS value of all axes
must be less than THRESH_FF to generate a free-fall interrupt.
The scale factor is 5 ms/LSB. A value of 0 may result in undesirable
behavior if the free-fall interrupt is enabled. Values between 100 ms
and 350 ms (0x14 to 0x46) are recommended.
Register 0x2A—TAP_AXES (Read/Write)
D6
0
D5
0
D4
Improved
tap
D3
Suppress
D2
TAP_X
enable
D1
TAP_Y
enable
D0
TAP_Z
enable
Improved Tap Bit
The improved tap bit is used to enable improved tap detection.
This mode of operation improves tap detection by performing
an ac-coupled differential comparison of the output acceleration
data. The improved tap detection is performed on the same output
data available in the DATAX, DATAY and DATAZ registers. Due
to the dependency on the output data rate and the ac-coupled
differential measurement, the threshold and timing values for
single taps and double taps need to be adjusted for improved tap
detection. For further explanation of improved tap detection, refer
to the Improved Tap Detection section.
Suppress Bit
Setting the suppress bit suppresses double tap detection if
acceleration greater than the value in THRESH_TAP is present
between taps. See the Tap Detection section for more details.
TAP_x Enable Bits
A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z
enable bit enables x-, y-, or z-axis participation in tap detection.
A setting of 0 excludes the selected axis from participation in
tap detection.
Register 0x2B—ACT_TAP_STATUS (Read Only)
D7
0
D6
ACT_X
source
D5
ACT_Y
source
D4
ACT_Z
source
D3
Asleep
D2
TAP_X
source
Asleep Bit
A setting of 1 in the asleep bit indicates that the part is asleep,
and a setting of 0 indicates that the part is not asleep. See the
Register 0x2D—POWER_CTL (Read/Write) section for more
information on autosleep mode.
Register 0x2C—BW_RATE (Read/Write)
D7
0
Register 0x29—TIME_FF (Read/Write)
D7
0
clears the corresponding source bit when the next activity or
single tap/double tap event occurs.
D1
TAP_Y
source
D0
TAP_Z
source
ACT_x Source and TAP_x Source Bits
These bits indicate the first axis involved in a tap or activity
event. A setting of 1 corresponds to involvement in the event,
and a setting of 0 corresponds to no involvement. When new
data is available, these bits are not cleared but are overwritten by
the new data. The ACT_TAP_STATUS register should be read
before clearing the interrupt. Disabling an axis from participation
D6
0
D5
0
D4
LOW_POWER
D3
D2
D1
Rate
D0
LOW_POWER Bit
A setting of 0 in the LOW_POWER bit selects normal operation,
and a setting of 1 selects reduced power operation, which has
somewhat higher noise (see the Power Modes section for details).
Rate Bits
These bits select the device bandwidth and output data rate (see
Table 6 and Table 7 for details). The default value is 0x0A, which
translates to a 100 Hz output data rate. An output data rate
should be selected that is appropriate for the communication
protocol and frequency selected. Selecting too high of an output
data rate with a low communication speed results in samples
being discarded.
Register 0x2D—POWER_CTL (Read/Write)
D7
0
D6
0
D5
Link
D4
AUTO_SLEEP
D3
Measure
D2
Sleep
D1 D0
Wakeup
Link Bit
A setting of 1 in the link bit with both the activity and inactivity
functions enabled delays the start of the activity function until
inactivity is detected. After activity is detected, inactivity detection
begins, preventing the detection of activity. This bit serially links
the activity and inactivity functions. When this bit is set to 0,
the inactivity and activity functions are concurrent. Additional
information can be found in the Link Mode section.
When clearing the link bit, it is recommended that the part be
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the link bit is cleared
may have additional noise, especially if the device was asleep
when the bit was cleared.
AUTO_SLEEP Bit
If the link bit is set, a setting of 1 in the AUTO_SLEEP bit sets
the ADXL346 to switch to sleep mode when inactivity is detected
(that is, when acceleration has been below the THRESH_INACT
value for at least the time indicated by TIME_INACT). A setting
of 0 disables automatic switching to sleep mode. See the description
of the sleep bit in this section for more information.
When clearing the AUTO_SLEEP bit, it is recommended that the
part be placed into standby mode and then set back to measure-
Rev. PrC | Page 21 of 32
ADXL346
Preliminary Technical Data
ment mode with a subsequent write. This is done to ensure that
the device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the AUTO_SLEEP
bit is cleared may have additional noise, especially if the device
was asleep when the bit was cleared.
Register 0x2F—INT_MAP (Read/Write)
D7
DATA_READY
D3
Inactivity
D6
SINGLE_TAP
D2
FREE_FALL
D5
DOUBLE_TAP
D1
Watermark
Measure Bit
D4
Activity
D0
Overrun/
orientation
A setting of 0 in the measure bit places the part into standby mode,
and a setting of 1 places the part into measurement mode. The
ADXL346 powers up in standby mode with minimum power
consumption.
Any bits set to 0 in this register send their respective interrupts to
the INT1 pin, whereas bits set to 1 send their respective interrupts
to the INT2 pin. All selected interrupts for a given pin are OR’ed.
Sleep Bit
D7
DATA_READY
D3
Inactivity
A setting of 0 in the sleep bit puts the part into the normal mode
of operation, and a setting of 1 places the part into sleep mode.
Sleep mode suppresses DATA_READY, stops transmission of data
to FIFO, and switches the sampling rate to one specified by the
wakeup bits. In sleep mode, only the activity function can be used.
When clearing the sleep bit, it is recommended that the part be
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the sleep bit is
cleared may have additional noise, especially if the device was
asleep when the bit was cleared.
Wakeup Bits
These bits control the frequency of readings in sleep mode as
described in Table 18.
Setting
D0
0
1
0
1
D6
SINGLE_TAP
D2
FREE_FALL
D5
DOUBLE_TAP
D1
Watermark
D5
DOUBLE_TAP
D1
Watermark
D4
Activity
D0
Overrun/
orientation
Register 0x31—DATA_FORMAT (Read/Write)
D6
SPI
D5
INT_INVERT
D4
0
D3
FULL_RES
D2
Justify
D1 D0
Range
The DATA_FORMAT register controls the presentation of data
to Register 0x32 through Register 0x37. All data, except that for
the ±16 g range, must be clipped to avoid rollover.
Frequency (Hz)
8
4
2
1
SELF_TEST Bit
Register 0x2E—INT_ENABLE (Read/Write)
D7
DATA_READY
D3
Inactivity
D6
SINGLE_TAP
D2
FREE_FALL
Bits set to 1 in this register indicate that their respective functions
have triggered an event, whereas a value of 0 indicates that the
corresponding event has not occurred. The DATA_READY,
watermark, and overrun bits are always set if the corresponding
events occur, regardless of the INT_ENABLE register settings,
and are cleared by reading data from the DATAX, DATAY, and
DATAZ registers. The DATA_READY and watermark bits may
require multiple reads, as indicated in the FIFO mode descriptions
in the FIFO section. Other bits, and the corresponding interrupts,
including orientation if enabled, are cleared by reading the
INT_SOURCE register.
D7
SELF_TEST
Table 18. Frequency of Readings in Sleep Mode
D1
0
0
1
1
Register 0x30—INT_SOURCE (Read Only)
D4
Activity
D0
Overrun/
orientation
Setting bits in this register to a value of 1 enables their respective
functions to generate interrupts, whereas a value of 0 prevents
the functions from generating interrupts. The DATA_READY,
watermark, and overrun bits enable only the interrupt output;
the functions are always enabled. It is recommended that interrupts
be configured before enabling their outputs.
A setting of 1 in the SELF_TEST bit applies a self-test force to
the sensor, causing a shift in the output data. A value of 0 disables
the self-test force.
SPI Bit
A value of 1 in the SPI bit sets the device to 3-wire SPI mode,
and a value of 0 sets the device to 4-wire SPI mode.
INT_INVERT Bit
A value of 0 in the INT_INVERT bit sets the interrupts to active
high, and a value of 1 sets the interrupts to active low.
FULL_RES Bit
When this bit is set to a value of 1, the device is in full resolution
mode, where the output resolution increases with the g range
set by the range bits to maintain a 4 mg/LSB scale factor. When
the FULL_RES bit is set to 0, the device is in 10-bit mode, and
the range bits determine the maximum g range and scale factor.
Rev. PrC | Page 22 of 32
Preliminary Technical Data
ADXL346
Justify Bit
Samples Bits
A setting of 1 in the justify bit selects left (MSB) justified mode,
and a setting of 0 selects right justified mode with sign extension.
The function of these bits depends on the FIFO mode selected
(see Table 21). Entering a value of 0 in the samples bits immediately
sets the watermark status bit in the INT_SOURCE register,
regardless of which FIFO mode is selected. Undesirable operation
may occur if a value of 0 is used for the samples bits when trigger
mode is used.
Range Bits
These bits set the g range as described in Table 19.
Table 19. g Range Setting
D1
0
0
1
1
Setting
D0
0
1
0
1
Table 21. Samples Bits Functions
g Range
±2 g
±4 g
±8 g
±16 g
FIFO Mode
Bypass
FIFO
Stream
Trigger
Register 0x32 to Register 0x37—DATAX0, DATAX1,
DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)
These six bytes (Register 0x32 to Register 0x37) are eight bits
each and hold the output data for each axis. Register 0x32 and
Register 0x33 hold the output data for the x-axis, Register 0x34 and
Register 0x35 hold the output data for the y-axis, and Register 0x36
and Register 0x37 hold the output data for the z-axis. The output
data is twos complement, with DATAx0 as the least significant
byte and DATAx1 as the most significant byte, where x represent X,
Y, or Z. The DATA_FORMAT register (Address 0x31) controls
the format of the data. It is recommended that a multiple-byte
read of all registers be performed to prevent a change in data
between reads of sequential registers.
Register 0x38—FIFO_CTL (Read/Write)
D7
D6
FIFO_MODE
D5
Trigger
D4
D3
D2
D1
Samples
D0
FIFO_MODE Bits
These bits set the FIFO mode, as described in Table 20.
Mode
Bypass
FIFO
1
0
Stream
1
1
Trigger
0x39—FIFO_STATUS (Read Only)
D7
FIFO_TRIG
D6
0
D5
D4
D3
D2
Entries
D1
D0
FIFO_TRIG Bit
A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,
and a 0 means that a FIFO trigger event has not occurred.
Entries Bits
These bits report how many data values are stored in FIFO.
Access to collect the data from FIFO is provided through the
DATAX, DATAY, and DATAZ registers. FIFO reads must be
done in burst or multiple-byte mode because each FIFO level is
cleared after any read (single- or multiple-byte) of FIFO. FIFO
stores a maximum of 32 entries, which equates to a maximum
of 33 entries available at any given time because an additional
entry is available at the output filter of the device.
Register 0x3A—TAP_SIGN (Read Only)
Table 20. FIFO Modes
Setting
D7 D6
0
0
0
1
Samples Bits Function
None.
Specifies how many FIFO entries are needed to
trigger a watermark interrupt.
Specifies how many FIFO entries are needed to
trigger a watermark interrupt.
Specifies how many FIFO samples are retained in
the FIFO buffer before a trigger event.
Function
FIFO is bypassed.
FIFO collects up to 32 values and then
stops collecting data, collecting new data
only when FIFO is not full.
FIFO holds the last 32 data values. When
FIFO is full, the oldest data is overwritten
with newer data.
When triggered by the trigger bit, FIFO
holds the last data samples before the
trigger event and then continues to collect
data until full. New data is collected only
when FIFO is not full.
Trigger Bit
A value of 0 in the trigger bit links the trigger event of trigger mode
INT1, and a value of 1 links the trigger event to INT2.
D7
0
D6
XSIGN
D5
YSIGN
D4
ZSIGN
D3
0
D2
XTAP
D1
YTAP
D0
ZTAP
xSIGN Bits
These bits indicate the sign of the first axis involved in a tap
event. A setting of 1 corresponds to acceleration in the negative
direction, and a setting of 0 corresponds to acceleration in the
positive direction. These bits update only when a new single
tap/double tap event is detected, and only the axes enabled in the
TAP_AXES register are updated. The TAP_SIGN register should
be read before clearing the interrupt. See the Tap Sign section for
more details.
xTAP Bits
These bits indicate the first axis involved in a tap event. A
setting of 1 corresponds to involvement in the event, and a
setting of 0 corresponds to no involvement. When new data is
available, these bits are not cleared but are overwritten by the
new data. The TAP_SIGN register should be read before clearing
Rev. PrC | Page 23 of 32
ADXL346
Preliminary Technical Data
the interrupt. Disabling an axis from participation clears the
corresponding source bit when the next single tap/double tap
event occurs.
orientation. A value of 1 generates an interrupt only if the 3-D
orientation changes from a valid 3-D orientation to a different
valid 3-D orientation.
Register 0x3B—ORIENT_CONF (Read/Write)
Divisor Bits
D7
INT_
ORIENT
D6
D5
D4
Dead zone
D3
D2
INT_
3D
D1
D0
Divisor
INT_ORIENT Bit
Setting the INT_ORIENT bit enables the orientation interrupt.
A value of 1 overrides the overrun function of the device and
replaces overrun in the INT_MAP, INT_ENABLE, and INT_
SOURCE registers with the orientation function. After setting
the INT_ORIENT bit, the orientation bit in the INT_MAP and
INT_ENABLE registers must be configured to map the orientation
interrupt to INT1 or INT2 and to enable generation of the interrupt
to the pin. The orientation interrupt is cleared by reading the
INT_SOURCE register. Additionally, writing to the BW_RATE
register, clearing the INT_ORIENT bit, or placing the part into
standby mode clears the orientation interrupt. A value of 0 for
the INT_ORIENT bit disables generation of the orientation
interrupt and permits the use of the overrun function.
Dead Zone Bits
These bits determine the region between two adjacent orientations,
where the orientation is considered invalid and is not updated. A
value of 0 may result in undesirable behavior when the orientation
is close to the bisector between two adjacent regions. The dead zone
angle is determined by these bits, as described in Table 22. See the
Orientation Sensing section for more details.
Table 22. Dead Zone and Divisor Codes
Decimal
0
1
2
3
4
5
6
7
Binary
000
001
010
011
100
101
110
111
Dead Zone Angle (Degrees)
3-D
2-D
3.3
5.8
8.2
10.3
12.3
14.1
15.6
17.0
2.5
6.3
9.8
13.0
16.0
18.6
20.9
23.0
These bits set the depth of the filter used to low-pass filter the
measured acceleration for stable orientation sensing. The divisor
length is determined by these bits, as detailed in Table 22. See the
Orientation Sensing section for more details.
Register 0x3C—Orient (Read Only)
D7
0
D6
V2
D5
D4
2D_ORIENT
D3
V3
D2
D1
D0
3D_ORIENT
Vx Bits
These bits show the validity of the 2-D (V2) and 3-D (V3) orientations. A value of 1 corresponds to the orientation being valid. A
value of 0 means that the orientation is invalid because the current
orientation is in the dead zone.
xD_ORIENT Bits
These bits represent the current 2-D (2D_ORIENT) and 3-D
(3D_ORIENT) orientations of the accelerometer. If the orientation interrupt is enabled, this register is read to determine the
orientation of the device when the interrupt occurs. Because this
register updates with each new samples of acceleration data, it
should be read at the time of the orientation interrupt to ensure
that the orientation change that caused the interrupt is obtained.
Orientation values are shown in Table 23 and Table 24. See the
Orientation Sensing section for more details
Changing the value in the BW_RATE register causes the orientation sensing filter to be cleared and the function to reset.
Table 23. 2-D Orientation Codes
Divisor
2
4
8
16
32
64
128
256
INT_3D
If the orientation interrupt is enabled, the INT_3D bit determines
whether 2-D or 3-D orientation detection generates an interrupt.
A value of 0 generates an interrupt only if the 2-D orientation
changes from a valid 2-D orientation to a different valid 2-D
Decimal
0
1
2
3
Binary
00
01
10
11
Orientation
Portrait positive
Portrait negative
Landscape positive
Landscape negative
Dominant Axis
+X
−X
+Y
−Y
Table 24. 3-D Orientation Codes
Decimal
3
4
2
5
1
6
Rev. PrC | Page 24 of 32
Binary
011
100
010
101
001
110
Orientation
Front
Back
Left
Right
Top
Bottom
Dominant Axis
+X
−X
+Y
−Y
+Z
−Z
Preliminary Technical Data
ADXL346
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
TAP DETECTION
A 1 μF tantalum capacitor (CS) at VS and a 0.1 μF ceramic capacitor
(CIO) at VDD I/O placed close to the ADXL346 supply pins is
recommended to adequately decouple the accelerometer from
noise on the power supply. If additional decoupling is necessary,
a resistor or ferrite bead, no larger than 100 Ω, in series with VS
may be helpful. Additionally, increasing the bypass capacitance
on VS to a 10 μF tantalum capacitor in parallel with a 0.1 μF
ceramic capacitor may also improve noise.
The tap interrupt function is capable of detecting either single
or double taps. The following parameters are shown in Figure 38
for a valid single and valid double tap event:
Care should be taken to ensure that the connection from the
ADXL346 ground to the power supply ground has low impedance
because noise transmitted through ground has an effect similar
to noise transmitted through VS. It is recommended that VS and
VDD I/O be separate supplies to minimize digital clocking noise
on the VS supply. If this is not possible, additional filtering of
the supplies as previously mentioned may be necessary.
VS
The tap detection threshold is defined by the THRESH_TAP
register (Address 0x1D).
The maximum tap duration time is defined by the DUR
register (Address 0x21).
The tap latency time is defined by the latent register
(Address 0x22) and is the waiting period from the end of
the first tap until the start of the time window, when a
second tap can be detected, which is determined by the
value in the window register (Address 0x23).
The interval after the latency time (set by the latent register) is
defined by the window register. Although a second tap must
begin after the latency time has expired, it need not finish
before the end of the time defined by the window register.
•
•
•
•
VDD I/O
CS
CIO
FIRST TAP
GND
CS
3-WIRE OR
4-WIRE SPI
OR I2C
INTERFACE
08167-035
SDA/SDI/SDIO
INT1 SDO/ALT ADDRESS
SCL/SCLK
INT2
XHI BW
ADXL346
INTERRUPT
CONTROL
SECOND TAP
VDD I/O
TIME LIMIT FOR
TAPS (DUR)
Figure 36. Application Diagram
The ADXL346 should be mounted on the PCB in a location
close to a hard mounting point of the PCB to the case. Mounting
the ADXL346 at an unsupported PCB location, as shown in
Figure 37, may result in large, apparent measurement errors due
to undampened PCB vibration. Locating the accelerometer near
a hard mounting point ensures that any PCB vibration at the
accelerometer is above the accelerometer’s mechanical sensor
resonant frequency and, therefore, effectively invisible to the
accelerometer. Multiple mounting points, close to the sensor,
and/or a thicker PCB also help to reduce the effect of system
resonance on the performance of the sensor.
ACCELEROMETERS
MOUNTING POINTS
08167-036
PCB
LATENCY
TIME
(LATENT)
INTERRUPTS
MECHANICAL CONSIDERATIONS FOR MOUNTING
THRESHOLD
(THRESH_TAP)
TIME WINDOW FOR
SECOND TAP (WINDOW)
SINGLE TAP
INTERRUPT
DOUBLE TAP
INTERRUPT
08167-037
VS
Figure 38. Tap Interrupt Function with Valid Single and Double Taps
If only the single tap function is in use, the single tap interrupt
is triggered when the acceleration goes below the threshold, as
long as DUR has not been exceeded. If both single and double
tap functions are in use, the single tap interrupt is triggered
when the double tap event has been either validated or
invalidated.
Several events can occur to invalidate the second tap of a double
tap event. First, if the suppress bit in the TAP_AXES register
(Address 0x2A) is set, any acceleration spike above the
threshold during the latency time (set by the latent register)
invalidates the double tap detection, as shown in Figure 39.
Figure 37. Incorrectly Placed Accelerometers
Rev. PrC | Page 25 of 32
ADXL346
Preliminary Technical Data
INVALIDATES DOUBLE TAP IF
SUPRESS BIT SET
LATENCY
TIME (LATENT)
TIME WINDOW FOR SECOND
TAP (WINDOW)
Figure 39. Double Tap Event Invalid Due to High g Event
When the Suppress Bit Is Set
A double tap event can also be invalidated if acceleration above
the threshold is detected at the start of the time window for the
second tap (set by the window register). This results in an invalid
double tap at the start of this window, as shown in Figure 40.
Additionally, a double tap event can be invalidated if an acceleration exceeds the time limit for taps (set by the DUR register),
resulting in an invalid double tap at the end of the DUR time
limit for the second tap event, also shown in Figure 40.
INVALIDATES DOUBLE TAP
AT START OF WINDOW
XHI BW
LATENCY
TIME
(LATENT)
TIME WINDOW FOR
SECOND TAP (WINDOW)
Improved tap detection is enabled by setting the improved tap
bit of the TAP_AXES register (Address 0x2A). When improved
tap detection is enabled, the filtered output data corresponding
to the output data rate set in the BW_RATE register is processed
to determine if a tap event occurred. In addition, an ac-coupled
differential measurement is used. This results in the timing values
and threshold values for improved tap detection being different
than those used for normal tap detection.
TAP SIGN
08167-039
XHI BW
TIME LIMIT
FOR TAPS
(DUR)
INVALIDATES
DOUBLE TAP AT
END OF DUR
IMPROVED TAP DETECTION
When improved tap detection is used, new values must be
determined based on test results. In general, no timing values
(in the DUR, latent, or window registers) should be set that are
less than the time step resolution set by the output data rate.
The threshold value for improved tap detection can typically be
set much lower than the threshold for normal tap detection.
The value used depends on the value in the BW_RATE register
and should be determined through system testing. Refer to the
Threshold section for more details.
TIME LIMIT
FOR TAPS
(DUR)
TIME LIMIT
FOR TAPS
(DUR)
After a tap interrupt has been received, the first axis to exceed
the THRESH_TAP level is reported in the ACT_TAP_STATUS
register (Address 0x2B). This register is never cleared, but is
overwritten with new data.
Figure 40. Tap Interrupt Function with Invalid Double Taps
Single taps, double taps, or both can be detected by setting the
respective bits in the INT_ENABLE register (Address 0x2E).
Control over participation of each of the three axes in single tap/
double tap detection is exerted by setting the appropriate bits in
the TAP_AXES register (Address 0x2A). For the double tap
function to operate, both the latent and window registers must
be set to a nonzero value.
A negative sign is produced by experiencing a negative
acceleration, which corresponds to tapping on the positive face
of the device for the desired axis. The positive face of the device
is the face such that movement in that direction would be positive
acceleration. For example, tapping on the face that corresponds
to the +X direction, labeled as front in Figure 41, would result
in a negative sign for the x-axis. Tapping on the face labeled as left
in Figure 41 would result in a negative sign for the y-axis, and
tapping on the face labeled top would result in a negative sign
for the z-axis. Conversely, tapping on the back, right, or bottom
sides would result in positive signs for the corresponding axes.
Every mechanical system has somewhat different single tap/
double tap responses based on the mechanical characteristics of
the system. Therefore, some experimentation with values for the
+z
TOP
(+Z)
+y
LEFT
(+Y)
+x
FRONT
(+X)
08167-046
TIME LIMIT
FOR TAPS
(DUR)
08167-038
XHI BW
latent, window, and THRESH_TAP registers is required. In
general, a good starting point is to set the latent register to a
value greater than 0x10, to set the window register to a value
greater than 0x10, and to set the THRESH_TAP register to be
greater than 3 g. Setting a very low value in the latent, window, or
THRESH_TAP register may result in an unpredictable response
due to the accelerometer picking up echoes of the tap inputs.
Figure 41. 3-D Orientation with Coordinate System
Rev. PrC | Page 26 of 32
Preliminary Technical Data
ADXL346
THRESHOLD
The lower output data rates are achieved by decimating a
common sampling frequency inside the device. The activity,
free-fall, and single tap/double tap detection functions without
improved tap enabled are performed using unfiltered data.
Since the output data is filtered, the high frequency and high g
data that is used to determine activity, free-fall, and single tap/
double tap events may not be present if the output of the
accelerometer is examined. This may result in trigger events being
detected when acceleration does not appear to trigger an event
because the unfiltered data may have exceeded a threshold or
remained below a threshold for a certain period of time while the
filtered output data has not exceeded such a threshold.
LINK MODE
The function of the link bit is to reduce the number of activity
interrupts that the processor must service by setting the device
to look for activity only after inactivity. For proper operation of
this feature, the processor must still respond to the activity and
inactivity interrupts by reading the INT_SOURCE register
(Address 0x30) and, therefore, clearing the interrupts. If an activity
interrupt is not cleared, the part cannot go into autosleep mode.
The asleep bit in the ACT_TAP_STATUS register (Address 0x2B)
indicates if the part is asleep.
SLEEP MODE VS. LOW POWER MODE
In applications where a low data rate is sufficient and low power
consumption is desired, it is recommended that the low power
mode be used in conjunction with the FIFO. The sleep mode, while
offering a low data rate and low average current consumption,
suppresses the DATA_READY interrupt, preventing the accelerometer from sending an interrupt signal to the host processor
when data is ready to be collected. In this application, setting the
part into low power mode (by setting the LOW_POWER bit in the
BW_RATE register) and enabling the FIFO in FIFO mode to
collect a large value of samples reduces the power consumption
of the ADXL346 and allows the host processor to go to sleep while
the FIFO is filling up.
USING SELF-TEST
The self-test change is defined as the difference between the
acceleration output of an axis with self-test enabled and the
acceleration output of the same axis with self-test disabled (see
Endnote 4 of Table 1). This definition assumes that the sensor
does not move between these two measurements, because if the
sensor moves, a non–self-test related shift corrupts the test.
Proper configuration of the ADXL346 is also necessary for an
accurate self-test measurement. The part should be set with a
data rate greater than or equal to 100 Hz. This is done by
ensuring that a value greater than or equal to 0x0A is written
into the rate bits (Bit D3 through Bit D0) in the BW_RATE
register (Address 0x2C). The part also needs to be placed into
normal power operation by ensuring the LOW_POWER bit in
the BW_RATE register is cleared (LOW_POWER bit = 0). It is
also recommended that the part be set to full-resolution, 16 g
mode to ensure that there is sufficient dynamic range for the
entire self-test shift. This is done by setting Bit D3 of the
DATA_FORMAT register (Address 0x31) and writing a value of
0x03 to the range bits (Bit D1 and Bit D0) of the DATA_FORMAT
register (Address 0x31). This results in a high dynamic range for
measurement and a 3.9 mg/LSB scale factor.
After the part is configured for accurate self-test measurement,
several samples of x-, y-, and z-axis acceleration data should be
retrieved from the sensor and averaged together. The number of
samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data, which corresponds
to 10 samples at 100 Hz data rate. The averaged values should
be stored and labeled appropriately as the self-test disabled data,
that is, XST_OFF, YST_OFF, and ZST_OFF.
Next, self-test should be enabled by setting Bit D7 of the
DATA_FORMAT register (Address 0x31). The output needs
some time (about four samples) to settle after enabling self-test.
After allowing the output to settle, several samples of the x-, y-,
and z-axis acceleration data should be taken again and averaged. It
is recommended that the same number of samples be taken for
this average as was previously taken. These averaged values should
again be stored and labeled appropriately as the value with selftest enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then
be disabled by clearing Bit D7 of the DATA_FORMAT register
(Address 0x31).
With the stored values for self-test enabled and disabled, the
self-test change is as follows:
XST = XST_ON − XST_OFF
YST = YST_ON − YST_OFF
ZST = ZST_ON − ZST_OFF
Because the measured output for each axis is expressed in LSBs,
XST, YST, and ZST are also expressed in LSBs. These values can be
converted to g’s of acceleration by multiplying each value by the
3.9 mg/LSB scale factor, if configured for full-resolution mode.
Additionally, Table 13 through Table 16 correspond to the selftest range converted to LSBs and can be compared with the
measured self-test change when operating at a VS of 2.5 V. For
other voltages, the minimum and maximum self-test output
values should be adjusted based on (multiplied by) the scale
factors shown in Table 12. If the part was placed into ±2 g, 10bit or full-resolution mode, the values listed in Table 13 should be
used. Although the fixed 10-bit mode or a range other than 16 g
can be used, a different set of values, as indicated in Table 14
through Table 16, would need to be used. Using a range below
8 g may result in insufficient dynamic range and should be
considered when selecting the range of operation for measuring
self-test.
If the self-test change is within the valid range, the test is considered
successful. Generally, a part is considered to pass if the minimum
magnitude of change is achieved. However, a part that changes
by more than the maximum magnitude is not necessarily a failure.
Rev. PrC | Page 27 of 32
ADXL346
Preliminary Technical Data
ORIENTATION SENSING
PORTRAIT
The orientation function of the ADXL346 reports both 2-D
and 3-D orientation concurrently through the orient register
(Address 0x3C). The V2 and V3 bits (Bit D6 and Bit D3 in the
orient register) report the validity of the 2-D and 3-D orientation
codes. If V2 or V3 are set, their respective code is a valid
orientation. If V2 or V3 are cleared, the orientation of the
accelerometer is unknown, such as when the orientation is
within the dead zone between valid regions.
In 3-D orientation, the z-axis is also included. If the accelerometer
is placed in a Cartesian coordinate system, as shown in Figure 41
of the Tap Sign section, the top of the device corresponds to the
positive z-axis direction, the front of the device corresponds to
the positive x-axis direction, and the right side of the device
corresponds to the positive y-axis direction.
+X
NEGATIVE (01)
DEADZONES
+Y
+Y
+g
+g
+X
LANDSCAPE
POSITIVE (10)
+Y
NEGATIVE (11)
+g
+X
+g
+X
08167-040
For 2-D orientation sensing, the relation of the x- and y-axes to
gravity is used to determine the accelerometer orientation (see
Figure 42 and Table 23). Portrait positive corresponds to the x-axis
being most closely aligned to the gravity vector and directed
upwards, opposite the gravity vector. Portrait negative is the
opposite of portrait positive with the x-axis pointing downwards
along the gravity vector. Landscape positive corresponds to the
y-axis being most closely aligned with the gravity vector and
directed upwards, away from the gravity vector. Landscape
negative is the orientation opposite landscape positive. The
dead zone regions are shown in the orientations for portrait
positive (+X) and portrait negative (−X) of Figure 42. These
regions also exist for landscape positive (+Y) and landscape
negative (−Y), as shown in Figure 42.
POSITIVE (00)
+Y
Figure 42. 2-D Orientation with Corresponding Codes
The width of the dead zone region between two or more
orientation positions is determined by setting the value of the
dead zone bits in the ORIENT_CONF register (Address 0x3B).
The dead zone region size can be specified with a resolution of
3.6°. The dead zone angle represents the total angle where the
orientation is considered invalid. Therefore, a dead zone of
10.8° corresponds to 5.4° in either direction away from the
bisector of two bordering regions. An example with a dead zone
region of 10.8° is shown in Figure 43.
PORTRAIT
POSITIVE
The algorithm to detect orientation change is performed after
filtering the output acceleration data to eliminate the effects of
high frequency motion. This is performed by using a moving
average filter of a depth set by the divisor bits (ORIENT_CONF
register, Address 0x3B). The orientation register is updated at
the same rate as the data rate set in the BW_RATE register, but
is effectively bandwidth limited to the accelerometer bandwidth
divided by the depth set by the divisor bits. To eliminate most
human motion, such as walking or shaking, the value in the
divisor bits should be selected to effectively limit the orientation
bandwidth to 1 Hz or 2 Hz.
50.4°
45°
39.6°
DEADZONE
+X
LANDSCAPE
POSITIVE
+Y
+g
08167-041
The states shown in Table 24 correspond to which side of the
accelerometer is directed upwards, opposite the gravity vector.
As shown in Figure 41, the accelerometer is oriented in the top
state. If the device is flipped over such that the top of the device
is facing down, towards gravity, the orientation is reported as
the bottom state. If the device is adjusted such that the positive
x-axis or positive y-axis direction is pointing upwards, away
from the gravity vector, the accelerometer reports the
orientation as front or left, respectively.
Figure 43. Orientation Showing a 10.8° Dead Zone Region
By setting the INT_ORIENT bit of the ORIENT_CONF register
(Address 0x3B), an interrupt can be generated when the device is
placed into a new valid orientation. Only one mode of orientation
detection, 2-D or 3-D, can generate an interrupt at a time. The
orientation detection mode is selected by setting or clearing the
INT_3D bit of the ORIENT_CONF register (Address 0x3B). For
more details, refer to the description of the ORIENT_CONF
register.
Rev. PrC | Page 28 of 32
Preliminary Technical Data
ADXL346
AXES OF ACCELERATION SENSITIVITY
AZ
AX
08167-042
AY
Figure 44. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis)
XOUT = 1g
YOUT = 0g
ZOUT = 0g
TOP
TOP
XOUT = 0g
YOUT = 1g
ZOUT = 0g
XOUT = –1g
YOUT = 0g
ZOUT = 0g
XOUT = 0g
YOUT = 0g
ZOUT = 1g
Figure 45. Output Response vs. Orientation to Gravity
Rev. PrC | Page 29 of 32
XOUT = 0g
YOUT = 0g
ZOUT = –1g
08167-043
TOP
XOUT = 0g
YOUT = –1g
ZOUT = 0g
TOP
GRAVITY
ADXL346
Preliminary Technical Data
LAYOUT AND DESIGN RECOMMENDATIONS
Figure 46 shows the recommended printed wiring board land pattern. Figure 47 and Table 25 provide details about the recommended
soldering profile.
0.8000
0.3000
3.3500
0.5000
08167-044
3.3500
Figure 46. Recommended Printed Wiring Board Land Pattern
(Dimensions shown in millimeters)
CRITICAL ZONE
TL TO TP
tP
TP
tL
TSMAX
TSMIN
tS
RAMP-DOWN
PREHEAT
08167-045
TEMPERATURE
RAMP-UP
TL
t25°C TO PEAK
TIME
Figure 47. Recommended Soldering Profile
Table 25. Recommended Soldering Profile1, 2
Profile Feature
Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP)
Preheat
Minimum Temperature (TSMIN)
Maximum Temperature (TSMAX)
Time from TSMIN to TSMAX (tS)
TSMAX to TL Ramp-Up Rate
Liquid Temperature (TL)
Time Maintained Above TL (tL)
Peak Temperature (TP)
Time of Actual TP − 5°C (tP)
Ramp-Down Rate
Time 25°C to Peak Temperature
1
2
Sn63/Pb37
3°C/sec max
Condition
Pb-Free
3°C/sec max
100°C
150°C
60 sec to 120 sec
3°C/sec max
183°C
60 sec to 150 sec
240 + 0/−5°C
10 sec to 30 sec
6°C/sec max
6 minutes max
Based on JEDEC Standard J-STD-020D.1.
For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used.
Rev. PrC | Page 30 of 32
150°C
200°C
60 sec to 180 sec
3°C/sec max
217°C
60 sec to 150 sec
260 + 0/−5°C
20 sec to 40 sec
6°C/sec max
8 minutes max
Preliminary Technical Data
ADXL346
OUTLINE DIMENSIONS
A1 PAD
CORNER
3.10
3.00 SQ
2.90
0.350
0.10
0.50
BSC
13 14
16
1
0.250
0.50
9
8
6
5
BOTTOM VIEW
TOP VIEW
0.275
END VIEW
0.79
0.74
0.69
SEATING
PLANE
061809-B
1.00
0.95
0.85
Figure 48. 16-Terminal Land Grid Array [LGA]
(CC-16-3)
Solder Terminations Finish Is Au over Ni
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADXL346BCCZ1
ADXL346BCCZ-RL1
ADXL346BCCZ-RL71
EVAL-ADXL346Z1
EVAL-ADXL346Z-M1
Measurement
Range (g)
±2, ±4, ±8, ±16
±2, ±4, ±8, ±16
±2, ±4, ±8, ±16
Specified
Voltage (V)
2.5
2.5
2.5
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
EVAL-ADXL346Z-S1
1
Z = RoHS Compliant Part.
Rev. PrC | Page 31 of 32
Package Description
16-Terminal Land Grid Array [LGA]
16-Terminal Land Grid Array [LGA]
16-Terminal Land Grid Array [LGA]
Evaluation Board
Analog Devices Inertial Sensor Evaluation
System, Includes ADXL346 Satellite
ADXL346 Satellite, Standalone
Package
Option
CC-16-3
CC-16-3
CC-16-3
ADXL346
Preliminary Technical Data
NOTES
Analog Devices offers specific products designated for automotive applications; please consult your local Analog Devices sales representative for details. Standard products sold by
Analog Devices are not designed, intended, or approved for use in life support, implantable medical devices, transportation, nuclear, safety, or other equipment where malfunction
of the product can reasonably be expected to result in personal injury, death, severe property damage, or severe environmental harm. Buyer uses or sells standard products for use
in the above critical applications at Buyer's own risk and Buyer agrees to defend, indemnify, and hold harmless Analog Devices from any and all damages, claims, suits, or expenses
resulting from such unintended use.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR08167-0-6/09(PrC)
Rev. PrC | Page 32 of 32