QUANTUM QN8006B

QN8006B/8006LB
High Performance Digital FM Transceiver for Portable Devices
81
9
__________________________ General Description __________________________
71
44
51
The QN8006 is a high performance, low power, fully integrated single-chip stereo FM transceiver designed for cell phones,
PMP/PNDs, and portable radios. It integrates both FM receiving and transmitting functions, auto-seek and clear channel
scan, and antenna tuning to ease matching in real applications. Advanced digital architecture enables superior receiver
sensitivity, crystal clear audio, unsurpassed spectral purity, ultra-low harmonic and spurious levels, and high immunity to
TDMA burst noise.
85
，
QQ
：
With its small footprint, minimal external component count and multiple clock frequency support, the QN8006 is easy to
integrate into a variety of small form-factor low power portable applications. An integrated voltage regulator enables direct
connection to a battery and provides high PSRR for superior noise suppression. A low-power Standby mode extends battery
life. ESD protection is on all pins. The QN8006 is fabricated in highly reliable CMOS technology.
43
41
5
_____________________________ Key Features _____________________________
技
有
限
公
司
，
• High Performance FM Receiver (FMR)
• Superior sensitivity: 1.2µVEMF
• High SNR: 66dB Stereo
• Ultra Low THD: 0.03%
• High interference rejection
• Integrated adaptive noise cancellation (SNC, HCC,
SM)
• Auto channel seek
讯
科
• High Performance FM Transmitter (FMT)
• 66dB Stereo SNR, 0.03% THD
• Maximum 121dBµVp RF output level with 42dB
adjustable range
• Integrated Clear Channel Scan
圳
市
金
合
• RDS/RBDS Transmit & Receive (QN8006B
Supported)
• Supports US and European data service,
including TMC (Traffic Messaging Channel) 深
_____________________________
Confidential A
• Flexible Audio Interfaces
• Digital audio interface supports I2S and a variety of
PCM data formats with 4 different data rates
• Programmable analog audio input/output
• Integrated audio AGC and soft clipping
• Ease of Integration
• Small footprint, 4 x 4 x 0.85 mm3 QFN24
• Adaptive antenna tuning
• Low cellular and GPS band spurs
• High Immunity to TDMA (GSM/GPRS) burst noise
• Multiple crystal frequencies supported
• 2-wire and 3-wire control interfaces
• Robust Operation
• -250C to +850C operation
• ESD protection on all input and output pads
Typical Applications __________________________ ƒ Cell Phones / PDAs / Smart Phones
ƒ Portable Audio & Media Players
Rev 2.08 (04/10)
• Very Low Power Consumption
• 9.2mA (Transmit Mode), 17mA (Receive Mode)
• Integrated voltage regulator, direct connect to battery
• Power saving IDLE and Standby modes
• Low shutdown leakage current
18
66
• Worldwide FM Band Receive and Transmit
• 76 MHz ~ 108 MHz full band tuning in
50/100/200 kHz step sizes
• 50/75μs pre-emphasis and de-emphasis
ƒ GPS Personal Navigation Devices
ƒ Automotive Accessories
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 1
QN8006B/8006LB
CONTENTS
1 Functional Block Diagram ..............................................................................................................................4 2 Pin Assignments ..............................................................................................................................................5 51
4 Functional Description ....................................................................................................................................9 81
3.1 I2S Interface Timing....................................................................................................................9 9
3 Electrical Specifications ..................................................................................................................................7 QQ
：
Audio Interface ...........................................................................................................................9 Audio Processing ........................................................................................................................9 Channel Setting...........................................................................................................................9 RDS/RBDS .................................................................................................................................9 85
，
4.4 4.5 4.6 4.7 71
44
4.1 Transmit Mode............................................................................................................................9 4.2 Receive Mode .............................................................................................................................9 4.3 Idle and Standby Mode ...............................................................................................................9 43
41
5
5 Control Interface Protocol ...............................................................................................................................9 5.1 2-Wire Serial Control Interface ..................................................................................................9 5.2 3-Wire Serial Control Interface ..................................................................................................9 18
66
6 Digital Audio Interface Protocol .....................................................................................................................9 司
，
6.1 Introduction.................................................................................................................................9 6.2 I2S BUS Signal Description ........................................................................................................9 6.3 I2S Interface Timing Description ................................................................................................9 公
6.3.1 MSB-Justified (Format 0) .............................................................................................................9 限
6.3.2 I2S (Format 1) ...............................................................................................................................9 技
有
6.3.3 DSP1 (Format 2)...........................................................................................................................9 讯
科
6.3.4 DSP2 (Format 3)...........................................................................................................................9 6.3.5 LSB-Justified (Format 4) ..............................................................................................................9 合
7 User Control Registers.....................................................................................................................................9 市
金
8 Package Description ........................................................................................................................................9 9 Solder Reflow Profile ......................................................................................................................................9 深
圳
9.1 Package Peak Reflow Temperature ............................................................................................9 9.2 Classification Reflow Profiles ....................................................................................................9 9.3 Maximum Reflow Times ............................................................................................................9 Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 2
QN8006B/8006LB
REVISION HISTORY
CHANGE DESCRIPTION
DATE
Initial from Qn8006/L datasheet v1.0
7/10/08
2.0
B1 register set incorporated.
7/25/08
2.01
Correct performance data in key feature section to accord with characteristics
table
2.01b
Further explain PWROUT_CAL[7:0] at 0Ch;
Modify the CIDR1 05h 0/1/2/3 minor version
Modify the CIDR2 06h A/B/C/D major version;
2.01c
Modify 2-wire to I2C, I2S to I2S, IDLE to IDLE, Table 1 and format
2.02
1. Table 3 Vcc range:2.7~5.0 v, TYP:3.3 v;
2. In Section 4.1: Modify 124 to 121dBµVp.
3. In Section 4.5: Delete” When there is no audio signal for a pre-determined
period, AGC will power down the transmitter. ”
03/17/09
2.03
Update the value in Section 2
06/15/09
2.04
Modify the register PWROUT_CALÆ PAC_TARGET and the description
07/30/09
2.05
Update the registers in Section 7.
08/05/09
2.06
Modify the description of register PAC_TARGET
81
18
66
43
41
5
85
，
QQ
：
71
44
8/25/08
02/04/09
10/12/09
2.07
1.
2.
3.
4.
5.
11/23/09
2.08
Minor changes in the “Key features”
04/20/10
讯
科
STATEMENT:
技
有
限
公
，
Modify I C to 2-wire;
Table 6: Rin 75 ΩÆ 5 kΩ;
Add Reg 21h , Reg 22h, Reg 59h, Reg 5Ah.
Update the grammar and syntax
Modify Vain Max value: 1400 mVÆ2000 mV
9/18/08
司
2
9
0.11
51
REVISION
深
圳
市
金
合
Users are responsible for compliance with local regulatory requirements for low power unlicensed FM
broadcast operation. Quintic is not responsible for any violations resulting from user’s intentional or
unintentional breach of regulatory requirements in personal or commercial use.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 3
QN8006B/8006LB
1 FUNCTIONAL BLOCK DIAGRAM
SCL
SDA
SEB
MCK
DIN
DOUT
WS
Digital Interface
Digital Audio
71
44
51
RX ANT
81
9
MOD
LDO
Voltage
Regulator
Vcc
DSP FSM
MPX
Pre
Emph
RDS
PHY
ARO
De
MPX
De
Emph
ALO
公
司
，
10µF
ARI
ALI
18
66
2.7 –5.0V
ΣΔ
ANT
Tuning
43
41
5
RFO
85
，
De
Mod
QQ
RFI
：
TX ANT
深
圳
市
金
合
讯
科
技
有
限
Figure 1: QN8006 Functional Blocks
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 4
QN8006B/8006LB
2 PIN ASSIGNMENTS
SEB
DIN/INT
AGND
21
20
19
9
SCL
22
81
SDA
23
51
VCC
44
71
：
XTAL 2
43
41
5
85
，
QQ
XTAL 1
11
12
CEN
MOD
16
XCLK
15
WS
14
DOUT /INT
13
MCK
限
10
6
VIO
AGND
9
5
18
66
ARI
(AGND )
- far side -
，
4
RFO
ALI
8
3
公
AUGND
17
Exposed Pad
Pin 25
司
2
RFGND
ARO
18
7
1
RFI
ALO
24
(Top View)
深
圳
市
金
合
讯
科
技
有
Figure 2: QN8006B Pin out
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 5
QN8006B/8006LB
Table 1: Pin Descriptions
PINS
NAME
1
ALO
Analog audio output – left channel (receiving mode only)
2
ARO
Analog audio output – right channel (receiving mode only)
3
AUGND
4
ALI
Analog audio input – left channel (transmitter mode only)
5
ARI
Analog audio input – right channel (transmitter mode only)
6
AGND
7
RFI
8
RFGND
9
RFO
Transmitter RF output – connect to matched antenna.
10
VIO
IO voltage – specifies voltage limit for all digital pins.
11
CEN
Chip enable: Chip power down if less than 0.6V, (see also MOD pin below)
power up if voltage applied >min (0.7*VIO, 1.8V).
12
MOD
13
MCK
14
DOUT/INT
15
WS
16
XCLK
External clock input (register 49h, bit 4 must be HIGH)
17
XTAL1
On-chip crystal driver port 1.
If using an external clock source, connect this pin to ground.
18
XTAL2
On-chip crystal driver port 2.
If using an external clock source, connect this pin to ground.
19
AGND
Analog ground
20
DIN/INT
21
SEB
22
SCL
23
SDA
24
VCC
Voltage supply
PAD
Exposed pad, must be soldered to the ground on the PCB.
9
81
51
44
Analog ground
71
Receiver RF input
85
，
QQ
：
RF ground
HIGH = 3-wire serial operation. LOW = 2-wire serial operation
Note: Both MOD=0 and CEN=0 to disable chip.
43
41
5
Bus mode:
Master clock – for digital audio interface.
技
有
限
公
司
，
18
66
Data out (receiving mode only), interrupt (transmitter mode only)
Word select (I2S mode only)
Data in (transmitter mode only), interrupt (receiving mode only)
Serves as the bus enable pin in 3-wire serial mode; serves as the address select pin in
2-wire serial mode, SEB = Low for default address, SEB = High for register controlled address.
讯
科
合
市
金
Audio ground
Clock for 2-wire or 3-wire serial bus.
Bi-directional data line for 2-wire or 3-wire serial bus.
深
圳
25
DESCRIPTION
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 6
QN8006B/8006LB
3 ELECTRICAL SPECIFICATIONS
Table 2: Absolute Maximum Ratings
CONDITIONS
MIN
MAX
UNIT
9
PARAMETER
81
SYMBOL
Supply voltage
VCC to GND
-0.3
5
V
VIO
Logic signals
CEN, SEB, SCL, SDA,
MOD, GSL to GND
-0.3
3.6
Ts
Storage temperature
-55
+150
V
o
C
Table 3: Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITIONS
Supply voltage
VCC to GND
TA
Operating temperature
Vain
L/R channel input
signal level
Single ended peak to
peak voltage
RFin
RF input level1
Peak input voltage
VIO
Digital I/O voltage
MIN
TYP
MAX
UNIT
2.7
3.3
5.0
V
+85
o
43
41
5
Vcc
85
，
QQ
：
71
44
51
Vbat
1.6
1000
C
2000
mV
0.3
V
3.6
V
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
-25
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 7
QN8006B/8006LB
Table 4: DC Characteristics
(Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V, f carrier=88 MHz and TA = 25oC).
Transmit mode supply current2
TYP
mA
analog audio interface
17
mA
digital audio interface
6.8
3.5
ISTBY
Standby mode supply current
Standby mode
350
IPDN
Power down leakage current
power down
Low level input voltage
85
，
QQ
μA
μA
15
0.9*VIO
18
66
VIL
mA
V
0.1*VIO
V
1.7 or
0.7*VIO
V
0.6
V
，
High level input voltage
mA
5
43
41
5
Interface
VIH
12.9
：
Idle mode
Low level output voltage
mA
9.2
Idle mode supply current
VOL
9
15.3
IIDLE
High level output voltage
UNIT
digital audio interface
analog audio interface
VOH
MAX
81
Receive mode supply current1
MIN
51
IRX
ITX
CONDITIONS
44
PARAMETER
71
SYMBOL
技
有
Table 5: AC Characteristics
限
公
司
Notes:
1. 76M, Type: RFI=10 dBμVp;
2. Max: RFO output level is 121dBuVp, Min: RFO=82 dBμVp.
讯
科
(Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.30V and TA = 25oC).
SYMBOL
PARAMETERS
Crystal or Clock
frequency
市
金
合
Fxtal
Fxtal_err
Crystal frequency
accuracy
CONDITIONS
MIN
MAX
7.6 - 38.41
Real-Time Clock
Over temperature, and aging
TYP
-20
UNIT
MHz
20
ppm
深
圳
Notes:
1. See also XSEL[3:0] (register 03h, bits 3:0).
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 8
QN8006B/8006LB
Table 6: Transmitter Characteristics
Audio input impedance
MIN
At pin ALI and ARI
1
TYP
10
Audio input capacitance
At pin ALI and ARI
Gaudio_In
Audio input gain
RIN[1:0] = 01
-1.5
ΔGaudio_In
Audio gain step
For any gain setting
0.5
1
Pre-emphasis time
constant1
PETC = 1
71.3
75
PETC = 0
47.5
50
MONO, Δf = 22.5 kHz
STEREO, Δf = 67.5 kHz,
Δfpilot = 6.75 kHz
αLR_tx
L/R separation 2, 3
BLR_tx
L/R channel imbalance 1, 2
Mpilot
2, 3, 6
，
38 kHz sub-carrier 2, 3
suppression
Ctune
Output capacitance tuning
range
Pout
RF output voltage swing4
40
7
μs
52.5
dB
66
0.03
0.1
%
45
dB
9.0
1
dB
15
%
dB
82
121
dBμVp
Power gain step
Over process, temperature
0.7
2.5
dB
Power gain flatness
Over 76 MHz ~ 108 MHz
-2
2
dB
技
有
限
RF Channel frequency =
88 MHz
RF output spectrum
mask5
-50
-45
240 kHz to 600 kHz offset
-55
-45
>600 kHz offset
dBc
-45
Fch
Channel frequency step
50
Ferr
Channel center frequency
accuracy
Fperr
Pilot Tone frequency
accuracy1
Fpk
Modulation peak
frequency deviation
Rev 2.08 (04/10)
1.5
120 kHz to 240 kHz offset
76
Confidential A
78.7
70
RF channel frequency
深
Frf
dB
pF
市
金
圳
Pmask
1.5
30
合
ΔPout
dB
5
讯
科
ΔGRF_Out
Relative to 75 kHz deviation
pF
15
L and R channel gain
imbalance at 1 kHz offset
from DC
司
SUPsub
19 kHz pilot modulation
5
QQ
Tx audio THD3
43
41
5
THDaudio_tx
STEREO, Δf = 67.5 kHz,
Δfpilot = 6.75 kHz
18
66
Tx audio SNR
公
SNRaudio_tx
kΩ
65
85
，
3
80
：
τemph
UNIT
2
71
Caudio_in
MAX
81
CONDITIONS
51
Raudio_in
PARAMETERS
44
SYMBOL
9
(Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V, f carrier=88 MHz and TA = 25oC).
108
MHz
200
kHz
-2
2
kHz
-2
2
Hz
100
75
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). kHz
Page 9
QN8006B/8006LB
SYMBOL
Notes:
1.
2.
3.
4.
5.
6.
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
44
51
81
9
Guaranteed by design.
Stereo (ST_MO_TX = 0).
1000mVp-p, 1 kHz tone at ALI pin, no input signal at ARI pin.
Into matched antenna (see application note for details).
Within operating band 76 MHz to 108 MHz.
Value set with GAIN_TXPLT [5:0] (reg. 0Fh, bits 5:0). The user must conform to local regulatory requirements
for low-power unlicensed FM broadcast operation when setting this value.
71
Table 7: Receiver Characteristics
PARAMETERS
CONDITIONS
FM sensitivity
(S+N)/N = 26dB
SRDS
RDS sensitivity
BER≤5%, average over 2000
blocks
IP3
Input referred IP3
At maximum gain
RejAM
AM suppression
TYP
8.9
μVEMF
105
dBμV
52
dB
5
kΩ
40
dB
dB
Adjacent channel
rejection
200 kHz offset
SRX_Alt
Alternate channel
rejection
400 kHz offset
40
MONO, Δf = 22.5 kHz1
65
STEREO, Δf = 67.5 kHz, Δfpilot =
6.75 kHz
66
L/R separation
AttPilot
Pilot rejection
Vaudio_out
，
司
公
市
金
圳
深
τemph
L/R channel imbalance
dB
MONO, Δf = 22.5 kHz
0.03
%
STEREO, Δf = 67.5 kHz, Δfpilot =
6.75 kHz
0.03
%
47
dB
65
dB
40
合
αLR_in
BLR
限
Audio THD
讯
科
THDaudio_in
18
66
SRX_Adj
Audio SNR
UNIT
μVEMF
At pin RFI
SNRaudio_in
MAX
1.2
RF input impedance
技
有
Rin
43
41
5
SRX
MIN
85
，
SYMBOL
QQ
：
(Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V, f carrier=88 MHz and TA = 25oC).
L and R channel gain imbalance
at 1 kHz offset from DC
1
dB
De-emphasis time
constant
PETC = 1
71.3
75
78.7
μs
PETC = 0
47.5
50
52.5
μs
Audio output voltage
Peak-Peak, single ended
0. 5
1
1.4
V
5
RLOAD
Audio output
impedance
0.6
Caudio_out
Audio output
capacitance
5
20
pF
RSSIerr
RSSI uncertainty
-3
3
dB
Rev 2.08 (04/10)
Confidential A
kΩ
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 10
QN8006B/8006LB
SYMBOL
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
Notes:
1. FORCE_MO=0;
CONDITIONS
Auto Standby time 2
TMOUT [1:0] = 00
1
TMOUT [1:0] = 01
3
TMOUT [1:0] = 10
Channel switching
time1
Clear channel scan time
Per channel.
Wake-up time from
standby to receive
τtune
讯
科
Tune time
公
技
有
Mode switch time from
receive to/from
transmit
τtrx
Standby to RX mode.
限
τwkup
25
司
Receiver Timing
81
Min
5
43
41
5
τCCS
18
66
Wake-up time from
standby to transmit
，
τwkup
Sec
Never
From any channel to any
channel.
Transmitter Timing
UNIT
：
71
0.6
TMOUT [1:0] = 11
τchsw
MAX
QQ
τastby
TYP
From rising edge of CEN to
PLL settled and transmitter
ready for transmission.
Chip power-up time 1
τpup
MIN
44
PARAMETER
85
，
SYMBOL
51
(Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and TA = 25oC).
9
Table 8: Timing Characteristics
RX mode to TX mode.
TX mode to RX mode.
Per channel, including Seek
1, 3
.
0.1
Sec
200
msec
5
msec
200
msec
500
µsec
100
msec
5
msec
深
圳
市
金
合
Notes:
1. Guaranteed by design.
2. Chip automatically goes from IDLE to standby mode; TMOUT = 11 equivalent to auto standby disabled.
3. More time is required until audio is output.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 11
QN8006B/8006LB
Table 9: 2-Wire Interface Timing Characteristics
PARAMETER
fSCL
2-wire clock frequency
tLOW
Clock Low time
0.5
μs
tHI
Clock High time
0.5
tST
SCL input to SDA
falling edge start 1,3
0.8
SDA falling edge to
SCL falling edge start3
0.6
SCL rising edge to
SDA rising edge 2,3
tw
Duration before restart3
Cb
SCL, SDA capacitive
loading3
51
44
：
85
，
tstp
20
ns
300
ns
ns
ns
0.6
μs
1.3
μs
10
pF
深
圳
市
金
合
讯
科
技
有
限
Notes:
1. Start signaling of 2-wire interface.
2. Stop signaling of 2-wire interface.
3. Guaranteed by design.
μs
300
900
43
41
5
SDA rising edge to
next SCL rising edge3
Level from 70% to 30%
18
66
tdtc
kHz
，
SCL falling edge to
next SDA rising edge3
400
司
tdtHD
UNIT
μs
QQ
SCL falling edge
MAX
μs
Level from 30% to 70%
3
tfc
TYP
71
SCL rising edge3
trc
MIN
公
tSTHD
CONDITIONS
9
SYMBOL
81
(Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and TA = 25oC).
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 12
43
41
5
85
，
QQ
：
71
44
51
81
9
QN8006B/8006LB
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
Figure 3: 2-Wire Serial Control Interface Timing Diagram
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 13
QN8006B/8006LB
Table 10: 3-Wire Interface Timing Characteristics
( Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and TA = 25oC).
CONDITIONS
MIN
TYP
MAX
UNIT
2.5
MHz
Bus clock frequency
25
ts
SEB and SDA falling
edge to clock rising
edge1
20
th
Data holding time1
10
ttr
SCL rising edge to
SDA output valid1
ted
SCL rising edge to
SDA output high Z1
2
ns
85
，
Only in read mode.
81
SCL low time
51
tLOW
ns
44
50
71
SCL high time
：
tHI
QQ
fCLK
PARAMETER
2
ns
ns
50
ns
25
ns
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
Notes:
1. Guaranteed by design.
9
SYMBOL
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 14
85
，
QQ
：
71
44
51
81
9
QN8006B/8006LB
Figure 5: 3-Wire Serial Control Interface Read Timing Diagram
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
Figure 4: 3-Wire Serial Control Interface Write Timing Diagram
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 15
QN8006B/8006LB
Table 11: Digital Audio Interface Timing Characteristics
Master Clock:
( Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and TA = 25oC).
MIN
TYP
MAX
UNIT
3.072
MHz
ns
Bus clock frequency
τrise_M
Rise-time
0.5
τfall_M
Fall-time
0.5
Ferr_M
Frequency accuracy
ns
44
fCLK_M
9
CONDITIONS
81
PARAMETER
51
SYMBOL
100
ppm
：
71
According to PLL.
QQ
Slave Clock:
Bus clock frequency
τrise_S
Rise-time
τfall_S
Fall-time
Ferr_S
Frequency accuracy
MIN
TYP
MAX
UNIT
10
MHz
1.5
ns
1.5
ns
100
ppm
深
圳
市
金
合
讯
科
技
有
限
公
司
，
fCLK_S
CONDITIONS
43
41
5
PARAMETER
18
66
SYMBOL
85
，
( Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and TA = 25oC).
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 16
QN8006B/8006LB
3.1 I2S Interface Timing
Note: The terms 'transmitter' and 'receiver' as described below are from the QN8006's point of view.
The delay between the external (master) clock and slave’s internal clock;
The delay between the internal clock and the data and/or word-select signals.
51
•
•
81
9
Either the QN8006 or the external device can act as the system master by providing the necessary clock signals. The slave
will usually derive its internal clock signal from an external clock input. This means, taking into account the propagation delay
between the master clock and the data and/or word-select signals, that the total delay is simply the sum of:
限
公
司
，
18
66
43
41
5
85
，
QQ
：
71
44
For data and word-select inputs, the external to internal clock delay is of no consequence because it only lengthens the
effective set-up time (see Figure 6). The major part of the time margin is to accommodate the difference between the
propagation delay of the transmitter, and the time required to set up the receiver. All timing requirements are specified
relative to the clock period or to the minimum allowed clock period of a device. This means that higher data rates can be
used in the future.
讯
科
技
有
Figure 6: Timing for QN8006 as I2S Slave and Transmitter
Table 12: Timing for QN8006 as I2S Slave and Transmitter
CONDITIONS
MIN
TYP
MAX
UNIT
市
金
2
I S clock period
100
ns
tLC
Clock low time
10
ns
tHC
Clock high time
10
ns
ts
WS setup time
10
ns
th
WS hold time
5
ns
tdtr
SD delay time
10
ns
tRC
Clock rise-time
5
ns
tFC
Clock fall-time
5
ns
深
圳
T
PARAMETER
合
SYMBOL
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 17
71
44
51
81
9
QN8006B/8006LB
QQ
：
Figure 7: Timing for QN8006 as I2S Master and Transmitter
CONDITIONS
MIN
TYP
MAX
43
41
5
PARAMETER
I2S clock period
tLC
Clock low time
tHC
Clock high time
tdtr
WS and SD delay time
tRC
Clock rise-time
tFC
Clock fall-time
UNIT
330
ns
120
ns
120
ns
10
ns
5
ns
5
ns
深
圳
市
金
合
讯
科
技
有
限
公
司
，
T
18
66
SYMBOL
85
，
Table 13: Timing for QN8006 as I2S Master and Transmitter
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 18
71
44
51
81
9
QN8006B/8006LB
QQ
：
Figure 8: Timing for QN8006 as I2S Slave and Receiver
T
I2S clock frequency
tLC
Clock low time
tHC
Clock high time
CONDITIONS
MIN
TYP
MAX
43
41
5
PARAMETER
WS and SD setup time
WS and SD hold time
tRC
Clock rise-time
tFC
Clock fall-time
UNIT
100
ns
10
ns
10
ns
10
ns
5
ns
5
ns
5
ns
深
圳
市
金
合
讯
科
技
有
限
公
司
，
ts
th
18
66
SYMBOL
85
，
Table 14: Timing for QN8006 as I2S Slave and Receiver
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 19
85
，
QQ
：
71
44
51
81
9
QN8006B/8006LB
43
41
5
Figure 9: Timing for QN8006 as I2S Master and Receiver
tLC
Clock low time
tHC
Clock high time
SD setup time
th
SD hold time
MIN
TYP
MAX
UNIT
330
ns
120
ns
120
ns
10
ns
5
ns
tdtr
WS delay time
10
ns
tRC
Clock rise-time
5
ns
tFC
讯
科
技
有
ts
司
I2S clock period
公
T
CONDITIONS
，
PARAMETER
限
SYMBOL
18
66
Table 15: Timing for QN8006 as I2S Master and Receiver
5
ns
深
圳
市
金
合
Clock fall-time
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 20
QN8006B/8006LB
4 FUNCTIONAL DESCRIPTION
9
The QN8006 is a high performance, low power, single chip FM transceiver IC that supports worldwide FM broadcast band
operation. It has transmit/receive modes for normal broadcasting/tuning as well as IDLE and standby modes for saving
power. RDS/RBDS data service is also supported in both transmit and receive modes.
51
81
4.1 Transmit Mode
QQ
：
71
44
The QN8006 transmitter uses a highly digitized architecture. The input left and right analog audio signals are first
adjusted by two automatic gain controlled (AGC) amplifiers, and then digitized by two high resolution ADCs into the
digital domain. If a digital audio interface is used, the analog input circuits and ADCs will be bypassed. Pre-emphasis,
soft clipping and MPX encoding are then performed. If RDS mode is enabled, the RDS signal will also be mixed with the
MPX signal and the combined output will be fed into a high performance digital FM modulator which generates FM
signal at RF carrier frequency. The FM signal is then filtered and amplified by the PA.
43
41
5
85
，
The QN8006 can deliver up to 121dBµVp output signal to an external antenna and/or matching network. An RF VGA
provides 42 dB of output power control range in 1.5dB steps and can be programmed through the serial control bus. Output
power control and in-band power flatness can be easily achieved by a calibration circuit. This wide range of control allows
for various antenna configurations such as loop, monopole, or meandering traces on PCB. An integrated RF bandpass filter
ensures optimal output spectal purity.
18
66
4.2 Receive Mode
The QN8006 receiver also uses a highly digitized low-IF architecture, allowing for the elimination of external components
and factory adjustments.
技
有
限
公
司
，
The received RF signal is first amplified by an integrated LNA and then quadrature down-converted to IF. An integrated IF
channel filter then rejects out-of-channel interference signals. AGC is also performed simultaneously to optimize the signal
to noise ratio as well as linearity and interference rejection. The filtered signal is digitized and further processed with a
digital FM demodulator and MPX decoder. Audio processing is then performed based on received signal quality and
channel condition. Two high-quality audio DACs are integrated on chip and will be used if an analog interface is used and
will be bypassed in case of a digital audio interface. The RDS signal will also be decoded if RDS reception is enabled.
讯
科
4.3 Idle and Standby Mode
圳
市
金
合
The QN8006 features low power IDLE and STANDBY modes for fast turn around and power saving. After power up,
the QN8006 will enter IDLE mode automatically. If there is no transmitting or receiving requirement in a pre-determined
time period, the QN8006 will enter STANDBY mode automatically. The auto-standby function can be enabled or
disabled through the serial control interface.
深
4.4 Audio Interface
The QN8006 supports both analog and digital audio interfaces in four different configurations, namely, analog
transmit/analog receive, analog transmit/digital receive, digital transmit/analog receive and digital transmit/digital receive,
thus, providing maximum flexibility in real applications.
Analog Audio Interface
The QN8006 has a highly flexible analog audio interface. In transmit mode, for audio input, the signal is AC coupled
with a 3dB corner frequency less than 50Hz. It has 4 different input impedances and 16.5 dB adjustable gain range (in
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 21
QN8006B/8006LB
1.5dB step) to optimize the SNR and linearity. The gain setting can be controlled automatically by integrated AGC or
manually set through serial interface.
In receive mode, the single ended audio output level is 1V peak to peak and will be AC coupled to external audio driver.
Digital Audio Interface
51
81
9
With digital audio, the interface operates in slave mode and supports MSB-Justified, LSB-Justified, I2S, DSP1, and DSP2.
The four interface lines are MCK, DIN, DOUT, and WS. MCK and WS can be tri-stated to allow for multiplexing.
71
44
4.5 Audio Processing
：
The QN8006 supports both transmit and receive mode audio processing.
85
，
QQ
In transmit mode, audio AGC, programmable pre-emphasis, and soft clipping are supported. The AGC state machine will
detect the signal level and control the VGA gain to optimize both SNR and THD. A saturation indicator is also integrated
which will be asserted when the input signal is out of the range of AGC. A soft clipping feature provides graceful
performance degradation when the signal level is higher than a pre-determined level.
43
41
5
Stereo signal is generated by the MPX circuit. It combines the left and right channel signals in the following way:
m(t ) = [ L (t ) + R (t ) ] + [ L(t ) − R (t ) ] sin(4π ft + 2θ 0 ) + α sin(2π ft + θ 0 ) + d (t ) sin(6π ft + 3θ 0 )
，
18
66
Here, L(t) and R(t) correspond to the audio signals on left and right channels respectively, f = 19 kHz, θ is the initial phase
of pilot tone and α is the magnitude of pilot tone, and d(t) is RDS signal. In mono mode, only the L+R portion of audio
signal is transmitted. The 19 kHz pilot tone is generated by the MPX circuit which contributes 9% of peak modulation,
and RDS signal will contribute 2.1% of peak modulation.
公
司
In receive mode, stereo noise cancellation (SNC), high cut control (HCC) and soft mute (SM) are supported. Stereo noise
suppression is achieved by gradually combining the left and right signals to be a mono signal as the received signal quality
degrades. SNC, HCC and SM are controlled by SNR and multipath channel estimation results.
深
圳
市
金
合
讯
科
技
有
限
Pre-emphasis and de-emphasis functions are also integrated with both 75μs and 50μs time constants. The time constant
can be programmed through the serial control interface.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 22
QN8006B/8006LB
4.6 Channel Setting
The QN8006 supports both auto tuning/scan and manual channel settings.
Manual Channel Setting
81
9
By programming channel index CH[9:0], the RF channel can be set to any frequency between 76 MHz ~ 108 MHz in 50
kHz steps. The channel index and RF frequency have the following relationship:
44
51
FRF = (76 + 0.05 x Channel Index), where FRF is the RF frequency in MHz.
：
71
The QN8006 has an integrated crystal oscillator and supports various crystal frequencies. Alternatively, the QN8006 can
be driven externally by various clock frequencies.
QQ
Clear Channel Scan
85
，
The QN8006 can automatically find the clearest channel and return the channel information for FM transmission. The
start, stop and frequency step of searching as well as upward or downward searching can be programmed through the
serial interface.
43
41
5
Auto Tuning
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
In receive mode, the QN8006 can automatically tune to stations having good signal quality. The start, stop and frequency
step of tuning as well as upward or downward tuning can be programmed through the serial interface.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 23
QN8006B/8006LB
4.7 RDS/RBDS
The QN8006 supports RDS/RBDS data transmitting and receiving, including station ID, Meta data, TMC information, etc.
The integrated RDS processor performs all symbol encoding/decoding, block synchronization, error detection and
correction functions. RDS/RBDS data communicates with an external MCU through the serial control interface.
51
81
9
When the chip is used as an FM receiver, the internal RDS buffer (the entire RDS Group (8 bytes) is full, an Interrupt signal
is generated. The signal waveform is shown in Figure 10. The user can also check the RDS buffer space by reading the
RDS_RXTXUPD bit in the STATUS2 register (reg. 1Bh [7]).
85
，
QQ
：
71
44
When the chip is used as an FM transmitter (RDS TX), ping-pong buffers are used so that the user can write into one buffer
while the RDS data in the other buffer is being transmitted. When the internal RDS buffer (8 bytes) is full, an Interrupt
signal is generated. The signal waveform is shown in Figure 10. The user should wait for the Interrupt signal (INT) before
toggling the RDSTXRDY bit in the SYSTEM2 register (reg. 01h [2]). Alternatively, the user can also check the RDS
buffer space by reading the RDS_RXTXUPD bit in the STATUS2 register (reg. 1Bh [7]).
4.55ms
18
66
43
41
5
INT
司
深
圳
市
金
合
讯
科
技
有
限
公
RDS/RSBS is not available in the QN8006LB.
，
Figure 10: Interrupt Output
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 24
QN8006B/8006LB
5 CONTROL INTERFACE PROTOCOL
The QN8006 supports 2-wire and 3-wire serial interfaces. The interface selection is controlled by the MOD pin which
determines whether a 2-wire or a 3-wire serial interface will be used. MOD = HIGH selects a 3-wire bus and LOW selects a
2-wire bus. At power-on, all register bits are set to default values.
81
9
5.1 2-Wire Serial Control Interface
QQ
：
71
44
51
The 2-wire bus is a simple bi-directional bus interface. The bus requires only serial data (SDA) and serial clock (SCL)
signals. The bus is 8-bit oriented. Each device is recognized with a unique address. Each register is also recognized with a
unique address. A third line (SEB) is used to choose the device address configuration. SEB = LOW selects the default
address (0101011), SEB = HIGH selects register defined addressing. The L2 bus operates with a maximum frequency of
400 kHz. Each data put on the SDA must be 8 bits long (Byte) from MSB to LSB and each byte sent should be
acknowledged by an “ACK” bit. In case a byte is not acknowledged, the transmitter should generate a stop condition or
restart the transmission. If a stop condition is created before the whole transmission is completed, the remaining bytes will
keep their old setting. In case a byte is not completely transferred, it will be discarded.
43
41
5
85
，
Data transfer to and from the QN8006 can begin when a start condition is created. This is the case if a transition from HIGH
to LOW on the SDA line occurs while the SCL is HIGH. The first byte transferred represents the address of the IC plus the
data direction. The default IC address is 0101011. A LOW LSB of this byte indicates data transmission (WRITE) while a
HIGH LSB indicates data request (READ). This means that the first byte to be transmitted to the QN8006 should be “56”
for a WRITE operation or “57” for a READ operation.
，
18
66
The second byte is the starting register address (N) for write/read operation. The following bytes are register data for
address N, N+1, N+2, etc. There is no limit on the number of bytes in each transmission. A transmission can be terminated
by generating a stop condition, which is SDA transition from LOW to HIGH while SCL is HIGH. For write operation,
master stops transmission after the last byte. For read operation, master doesn’t send ACK after receiving the last read back
byte; then stops the transmission.
DEVICE ADD
READ/WRITE
ACK
REG ADD
ACK
DATA
ACK
深
圳
市
金
合
讯
科
技
有
限
公
司
The following timing diagram is for both write and read.
Rev 2.08 (04/10)
Confidential A
Figure 11: 2-wire Serial Control Interface Protocol
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 25
QN8006B/8006LB
5.2 3-Wire Serial Control Interface
For 3-wire serial operation, a transfer begins when the SEB pin is set LOW on a rising SCL edge. The control word is
latched internally on rising SCL edges and is 8 bits in length, comprised of a 7-bit register address A6:A0, and a read/write
bit (read = 1, write = 0). The ordering of the control word is A6:A0, R/W as shown in Figure 11.
，
18
66
43
41
5
85
，
QQ
：
71
44
51
81
9
For write operations, the serial control word is followed by an 8-bit data word and is latched internally on rising SCL edges.
For read operations, a bus turn-around of half a cycle is followed by an 8-bit data word shifted out on rising SCL edges. The
transfer ends on the rising SCL edge after SEB is set HIGH. After the 16th data bit, a full clock with both rising and falling
edges is needed to shift in the control word.
深
圳
市
金
合
讯
科
技
有
限
公
司
Figure 12: 3-Wire Serial Control Interface Write Protocol
Figure 13: 3-Wire Serial Control Interface Read Protocol
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 26
QN8006B/8006LB
6 DIGITAL AUDIO INTERFACE PROTOCOL
6.1 Introduction
The QN8006 uses an I2S interface to transfer audio data to and from the external source.
Master or Slave modes are supported.
•
Multiple data widths are supported: 8, 16, 24, and 32 bits.
•
Multiple data alignments are supported: I2S, DSP1, DSP2, MSB-Justified, and LSB-Justified modes. All the above 5
modes are supported when the QN8006 works as a receiver, and only I2S normal and DSP2 mode is supported when
the QN8006 is a transmitter.
•
The terms 'transmitter' and 'receiver' as described below are from the QN8006's point of view.
：
71
44
51
81
9
•
QQ
6.2 I2S BUS Signal Description
Figure 14: Top Level Block Diagram of I2S
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
A 3-line serial bus is used consisting of a line for two time-multiplexed data channels, a word select line, and a clock line.
The following figure shows how to use these three signals in the QN8006.
In Master mode, the serial clock signal SCK and the word selection signal WS are generated by the QN8006 and are output
to the external device. In Slave mode, those two signals are input signals from the external device.
As transmitter, the QN8006 sends the serial data to the external device by the SD signal. As receiver, it receives the serial
data from the external device by the SD signal.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 27
QN8006B/8006LB
6.3 I2S Interface Timing Description
The word select line indicates the channel being transmitted:
•
•
WS = 0; channel 1(left);
WS = 1; channel 2(right).
81
9
WS sent by the transmitter is synchronized by the trailing (HIGH-to-LOW) edge of the serial clock signal and is latched
into the receiver on the leading (LOW-to-HIGH) edge of the serial clock signal.
71
44
51
The serial data signal SD has the same timing requirement as the WS signal. It is sent on the trailing edge of the clock signal
by the transmitter, and received on the leading edge of the clock signal by the receiver. The serial data is transmitted in
two’s complement with the MSB first. The MSB is transmitted first because the transmitter and the receiver may have
different word lengths. There are four data word lengths supported by the QN8006; 8, 16, 24 and 32.
QQ
：
There are five data alignment modes supported by QN8006. The detailed timing descriptions are shown as below.
85
，
6.3.1 MSB-Justified (Format 0)
WS
43
41
5
MCK
(Left)
DIN/DOUT
N-2
N-3
0
N-1
N-2
N-3
0
N-1
18
66
N-1
(Right)
司
，
The transmitter sends the MSB(N-1) bit of the next word when the WS changes and sends the second MSB bit in the next
clock period. Each bit is sent by the transmitter in one clock period until the LSB (0) bit is sent. The N indicates the word
length that can be 8, 16, 24, and 32.
公
This data alignment mode is supported by QN8006 as a receiver.
技
有
讯
科
MCK
WS
合
(Left)
N-1
N-2
(Right)
1
0
N-1
N-2
1
0
市
金
DIN/DOUT
限
6.3.2 I2S (Format 1)
深
圳
The transmitter sends the MSB (N-1) bit of the next word one clock period after the WS changes and sends the second MSB
bit in the next clock period. Each bit is sent by the transmitter in one clock period until the LSB (0) bit is sent. In the case
that the number of cycles equal the number of bits to be sent, the LSB (0) bit could be sent after the next WS change. The N
indicates the word length that can be 8, 16, 24, and 32.
This data alignment mode is supported by the QN8006 as either receiver or transmitter.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 28
QN8006B/8006LB
81
9
6.3.3 DSP1 (Format 2)
71
44
51
The transmitter sends the MSB(N-1) bit of the next word when the WS pulse occurs and sends the second MSB bit in the
next clock period. Each bit is sent by the transmitter in one clock period until the LSB (0) bit is sent. Following the first
LSB, transmitter sends the MSB(N-1) bit of a new word and then keeps sending data until the data transmission is finished.
The N indicates the word length that can be 8, 16, 24, and 32.
QQ
：
This data alignment mode is supported by the QN8006 as a receiver.
18
66
43
41
5
85
，
6.3.4 DSP2 (Format 3)
司
，
The transmitter sends the MSB(N-1) bit of the next word one clock period after the WS pulse occurs and sends the second
MSB bit in the next clock period. Each bit is sent by the transmitter in one clock period until the LSB (0) bit is sent.
Following the first LSB, transmitter sends the MSB (N-1) bit of a new word and then keeps sending data until the data
transmission is finished. The N indicates the word length that can be 8, 16, 24, and 32.
限
公
This data alignment mode is supported by the QN8006 as either receiver or transmitter.
市
金
合
讯
科
技
有
6.3.5 LSB-Justified (Format 4)
深
圳
The transmitter sends the MSB(N-1) bit of the next word in the (N-1)th clock period back-counting from the next WS
changes. The second MSB bit is sent in the next clock period. Finally, the LSB(0) bit is sent in the clock period that is just
before the next WS changes in one clock period. The N indicates the word length that can be 8, 16, 24, and 32.
This data alignment mode is supported by the QN8006 as either receiver or transmitter.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 29
QN8006B/8006LB
7 USER CONTROL REGISTERS
There are 35 user accessible control registers. All registers not listed below are for manufacturing use only.
Table 16: Summary of User Control Registers
USER CONTROL FUNCTIONS
SYSTEM1
Sets device modes.
01h
SYSTEM2
Sets device modes, resets.
02h
DEV_ADD
Sets device address.
03h
ANACTL1
Analog control functions.
04h
REG_VGA
TX mode input impedance, crystal cap load setting.
05h
CIDR1
Device ID numbers.
06h
CIDR2
Device ID numbers.
QQ
IS
Sets I2S parameters.
08h
CH
Lower 8 bits of 10-bit channel index.
09h
CH_START
Lower 8 bits of 10-bit channel scan start channel index.
0Ah
CH_STOP
Lower 8 bits of 10-bit channel scan stop channel index.
0Bh
CH_STEP
Channel scan frequency step. Highest 2 bits of channel indexes.
0Ch
PAC_TARGET
Output power calibration control.
0Dh
TXAGC GAIN
Sets TX parameters.
0Eh
TX_FDEV
Specify total TX frequency deviation.
0Fh
GAIN_TXPLT
Gain of TX pilot frequency deviation, I2S buffer clear.
10h
RDSD0
11h
RDSD1
12h
RDSD2
13h
RDSD3
RDS data byte 3.
14h
RDSD4
RDS data byte 4.
15h
RDSD5
RDS data byte 5.
RDSD6
RDS data byte 6.
RDSD7
RDS data byte 7.
RDSFDEV
Specify RDS frequency deviation, RDS mode selection.
19h
CCA
Sets CCA parameters.
1Ah
STATUS1
Device status indicators.
1Bh
STATUS3
RDS status indicators.
1Ch
RSSISIG
In-band signal RSSI dBµV value.
21h
RSSIMP
Multipath signal RSSI (Received signal strength indicator) DB value.
22h
SNR
Estimated RF input CNR value from noise floor around the pilot after
FM demodulation.
49h
REG_XLT3
XCLK pin control.
4Fh
REG_DAC
DAC output stage gain.
Rev 2.08 (04/10)
Confidential A
43
41
5
18
66
，
公
RDS data byte 0.
限
RDS data byte 1.
技
有
讯
科
圳
市
金
18h
合
17h
85
，
07h
司
2
：
71
44
51
81
00h
16h
深
NAME
9
REGISTER
RDS data byte 2.
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 30
QN8006B/8006LB
REGISTER
NAME
USER CONTROL FUNCTIONS
59h
PAC_CAL
PA tuning cap calibration.
5Ah
PAG_CAL
PA gain calibration.
9
Register Bit R/W Status:
71
Address: 00h
：
Word: SYSTEM1
44
51
81
RO - Read Only: You can not program these bits.
WO - Write Only: You can write and read these bits; the value you read back will be the same as written.
R/W - Read/Write: You can write and read these bits; the value you read back can be different from the value written.
Typically, the value is set by the chip itself. This could be a calibration result, AGC FSM result, etc.
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
rxreq
txreq
chsc
stnby
rxi2s
wo
wo
wo
wo
wo
RXREQ
0
6
TXREQ
0
wo
wo
wo
85
，
QQ
cca_ch_dis
43
41
5
7
rdsen
Description
Receiving request (overwrites TXREQ and STNBY):
18
66
Default
txi2s
0
Non RX mode. Either IDLE, standby or TX mode.
1
Enter Receiving mode.
，
Symbol
Bit 0
(LSB)
Transmission request:
Non TX mode. Either IDLE, standby or RX mode.
公
0
司
Bit
Bit 1
0
合
市
金
圳
3
STNBY
RXI2S
Rev 2.08 (04/10)
Confidential A
Channel Scan mode enable: Combined with TXREQ and RXREQ, chip
scans for occupied channel for receiving or empty channel for transmission.
After completing channel scanning, this bit will be cleared automatically.
For CCS (TX Scan), the clearest channel (channel with weakest RSSI) will
be selected (if TXCCAA is not equal to zero, another prior condition
should be met, see description of CCA register at 19h).
For RX Scan, the FIRST valid channel will be selected. To start CCA/CCS,
set CHSC (REG0 [5]) to 1. CHSH will be automatically cleared to 0 when
CCA/CCS is complete. To use the scanned channel, set CCA_CH_DIS to
0. (CCA_CH_DIS can be set to 0 at the same time CHSC=1).
深
4
Enter Transmit mode.
技
有
CHSC
讯
科
5
限
1
0
0
0
Normal operation.
1
Channel Scan mode operation.
Request immediately to enter Standby mode if the chip is in IDLE and no
TXREQ or RXREQ is received.
0
Non standby mode. Either IDLE, TX mode or RX mode.
1
Enter standby mode.
I2S enable in receiving mode:
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 31
QN8006B/8006LB
CCA_CH_DIS
1
Use analog input for TX audio.
1
Use I2S digital signal for TX audio.
9
0
RDS disable.
1
RDS enable.
51
0
81
RDS enable:
44
0
I2S enable in transmitting mode:
CH (channel index) selection method: See description for CH register at
08h and 0Bh for more information.
0
CH is determined by internal CCA (channel scan).
1
CH is determined by the content in CH[9:0].
85
，
0
RDSEN
Use I2S digital interface for RX audio.
71
1
0
1
：
TXI2S
Use analog output for RX audio.
QQ
2
0
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
Note: RXREQ has highest priority, TXREQ is the second, and STNBY has the lowest priority.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 32
QN8006B/8006LB
Word: SYSTEM2
Address: 01h
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
swrst
recal
force_mo
st_mo_tx
tc
rdstxrdy
tmout[1]
tmout[0]
wo
wo
wo
wo
wo
wo
wo
wo
5
4
RECAL
0
FORCE_MO
ST_MO_TX
TC
0
1
Reset to default values.
1:0
TMOUT[1:0]
0
0
No reset. FSM runs normally.
1
Reset the FSM. After this bit is de-asserted, FSM will go through
all the power up and calibration sequence.
Force receiver in MONO mode:
0
Not forced. ST/MONO auto selected.
1
Forced in MONO mode.
TX stereo and mono mode selection:
0
Stereo
1
Mono
Pre-emphasis and de-emphasis time constant: (µs)
0
50
1
75
合
市
金
圳
Toggle this bit to transmit all 8 bytes in RDS0~RDS7. The chip will
internally fetch these bytes after completing transmit of the current group.
Time out setting for IDLE to standby state transition: (min)
00
1
01
3
10
5
11
infinity (never)
深
01
44
Reset the state to initial states and recalibrate all blocks:
技
有
RDSTXRDY
讯
科
2
71
1
：
Keep the current value.
限
3
0
0
QQ
6
Reset all registers to default values:
85
，
0
43
41
5
SWRST
18
66
7
Description
，
Default
司
Symbol
公
Bit
51
81
9
Bit 7
(MSB)
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 33
QN8006B/8006LB
Address: 02h
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rxccad[5]
dadd[6]
dadd [5]
dadd [4]
dadd [3]
dadd [2]
dadd [1]
dadd [0]
wo
wo
wo
wo
wo
wo
wo
wo
Symbol
Default
7
RXCCAD[5]
0
6:0
DADD[6:0]
010 1010
Description
44
Bit
51
81
Bit 7
(MSB)
9
Word: DEV_ADD
71
RX CCA threshold MSB. See CCA register 19h [4:0].
0101011
1
DADD [6:0]
Address: 03h
85
，
0
18
66
Word: ANACTL1
Device address:
43
41
5
SEB
QQ
：
Programmed device address when SEB=1: If SEB=0, the default device
address (0101011) is used. After power up, if SEB=1, the device address is
decided by this register (default 010 1010).
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
ant_sel
xsel[3]
xsel[2]
xsel[1]
xsel[0]
wo
wo
wo
wo
wo
Bit 6
Bit 5
Bit 4
mute_en
i2s_sckinv
rstb_bb
wo
wo
wo
技
有
限
公
司
，
Bit 7
(MSB)
Symbol
Default
7
MUTE_EN
0
合
RSTB_BB
0
1
深
圳
5
I2S_SCKINV
市
金
6
讯
科
Bit
4
3:0
ANT_SEL
XSEL[3:0]
0
1011
Description
TX and RX audio mute enable:
0
Un-mute
1
Mute
2
I S MCK invert:
0
Non inverted
1
Inverted
Reset signal of baseband data-path: (Low active)
0
Reset
1
No action
Select the antenna for TX channel scan mode:
0
Use the receiver antenna from RFI.
1
Use the transmitter antenna on RFO.
Crystal Frequency Selection (MHz):
0000
Rev 2.08 (04/10)
Confidential A
11.2896
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 34
QN8006B/8006LB
12
0010
12.288
0011
13
0100
16.367
0101
18.414
0110
19.2
0111
Reserved
1000
22.5792
1001
24
1010
24.576
1011
26 (default)
1100
32.734
1101
36.828
1110
38.4
1111
7.6
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
QQ
：
71
44
51
81
9
0001
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 35
QN8006B/8006LB
Address: 04h
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rin[1]
rin[0]
xcsel[5]
xcsel[4]
xcsel[3]
xcsel[2]
xcsel[1]
xcsel[0]
wo
wo
wo
wo
wo
wo
wo
wo
7:6
RIN[1:0]
01
10
01
20
10
40
11
80
QQ
00
：
TX mode input impedance for both L/R channels: (kΩ)
85
，
XCSEL[5:0]
Description
Crystal cap load setting: The loading cap on each side is:
10 0000
43
41
5
5:0
51
Default
44
Symbol
71
Bit
81
Bit 7
(MSB)
9
Word: REG_VGA
Address: 05h (RO)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rsvd
rsvd
rsvd
cid1[2]
cid1[1]
cid1[0]
cid2[1]
cid2[0]
ro
ro
ro
ro
ro
ro
ro
ro
7:5
Rsvd
4:2
公
Description
CID1[2:0]
rrr
Chip ID for product family:
000
CID2[1:0]
rr
市
金
讯
科
reserved
深
Rev 2.08 (04/10)
Confidential A
限
value
rrr
圳
1:0
技
有
Symbol
合
Bit
，
Bit 7
(MSB)
司
Word: CIDR1
18
66
10+XCSEL*0.32 pF, i.e. it ranges from 10pF to 30pF. Default is 20 pF.
000
001-111
00
FM
Reserved
Chip ID for minor revision:
00
0
01
1
10
2
11
3
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 36
QN8006B/8006LB
Word: CIDR2
Address: 06h (RO)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
cid3[3]
cid3[2]
cid3[1]
cid3[0]
cid4[3]
cid4[2]
cid4[1]
cid4[0]
ro
ro
ro
ro
ro
ro
ro
ro
0011
0000
Reserved
0001
Reserved
0010
Reserved
0011
Transceiver – QN8006
0100
Reserved
0101
Reserved
0110
Reserved
0111
Transceiver – QN8006L
1000-1111
rrrr
0000
0001
0001
公
0010
0011
限
Reserved
A
，
CID4[3:0]
司
3:0
44
Chip ID for product ID:
71
rrrr
：
CID3[3:0]
QQ
7:4
Description
85
，
Devault
43
41
5
Symbol
18
66
Bit
51
81
9
Bit 7
(MSB)
C
D
Reserved
深
圳
市
金
合
讯
科
技
有
0100-1111
B
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 37
QN8006B/8006LB
Word: I2S
Bit 5
Bit 4
Bit 3
Bit 2
i2sbw[1]
i2sbw[0]
i2sdrate[1]
i2sdrate[0]
i2smode
i2sfmt[2]
wo
wo
wo
wo
wo
wo
5:4
I2SDRATE[1:0]
I2S bit width:
00
8-bit
01
16-bit
10
24-bit
11
32-bit
2
11
I S data rate:
00
32kbps
01
40kbps
10
44.1kbps
11
I2SMODE
48kbps
I2S mode:
0
司
0
，
3
001
I S format in TX mode:
技
有
讯
科
000
MSB justified mode
001
I S mode
010
DSP1 mode
011
DSP2 mode
100
LSB justified mode
101-111
(Not supported in RX mode.)
2
(Not supported in RX mode.)
(Not supported in RX mode.)
Reserved
深
圳
市
金
合
Master
2
限
I2SFMT[2:0]
Slave
公
1
2:0
44
Description
71
01
wo
：
I2SBW[1:0]
wo
QQ
7:6
i2sfmt[0]
85
，
Default
i2sfmt[1]
43
41
5
Symbol
Bit 0
(LSB)
18
66
Bit
Bit 1
81
Bit 6
51
Bit 7
(MSB)
9
Address: 07h
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 38
QN8006B/8006LB
Address: 08h (RW)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
ch[7]
ch[6]
ch[5]
ch[4]
ch[3]
ch[2]
ch[1]
ch[0]
rw
rw
rw
rw
rw
rw
rw
rw
51
81
Bit 7
(MSB)
9
Word: CH
Symbol
Default
Description
7:0
CH[7:0]
1010 0000
Lower 8 bits of 10-bit Channel Index: Channel used for TX/RX has two
origins, one is from this register and CH[9:8] at 0Bh which can be
written by the user, another is from CCA/CCS. CCA/CCS selected
channels are stored in an internal register, which is different from the CH
register, but it can be read out through register CH and be used for
TX/RX when CCA_CH_DIS (reg. 00h bit [0]) = 0.
Address: 09h
Bit 6
Bit 5
Bit 4
ch_sta[7]
ch_sta[6]
ch_sta[5]
ch_sta[4]
wo
wo
wo
wo
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
ch_sta[3]
ch_sta[2]
ch_sta[1]
ch_sta[0]
wo
wo
wo
wo
Default
7:0
CH_STA[7:0]
0000 0000
Lower 8 bits of 10-bit CCA (channel scan) start channel index.
Address: 0Ah
讯
科
Word: CH_STOP
Description
限
Symbol
技
有
Bit
公
司
，
Bit 7
(MSB)
18
66
Word: CH_START
43
41
5
85
，
QQ
：
71
44
Bit
合
Bit 7
(MSB)
市
金
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
ch_stp[6]
ch_stp[5]
ch_stp[4]
ch_stp[3]
ch_stp[2]
ch_stp[1]
ch_stp[0]
wo
wo
wo
wo
wo
wo
wo
wo
深
圳
ch_stp[7]
Bit
Symbol
Default
7:0
CH_STP[7:0]
1000 0000
Rev 2.08 (04/10)
Confidential A
Description
Lower 8 bits of 10-bit CCA (channel scan) stop channel index.
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 39
QN8006B/8006LB
Address: 0Bh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
fstep[1]
fstep[0]
ch_stp[9]
ch_stp[8]
ch_sta[9]
ch_sta[8]
ch[9]
ch[8]
wo
wo
wo
wo
wo
wo
rw
rw
Symbol
Default
7:6
FSTEP[1:0]
01
Description
44
Bit
51
81
Bit 7
(MSB)
9
Word: CH_STEP
01
100 kHz
10
200 kHz
11
Reserved
QQ
50 kHz
85
，
00
：
71
CCA (channel scan) frequency step:
CH_STP[9:8]
10
Highest 2 bits of 10-bit CCA (channel scan) stop channel index: Stop
freq is (76+CH_STP*0.05) MHz.
3:2
CH_STA[9:8]
00
Highest 2 bits of 10-bit CCA (channel scan) start channel index: Start
freq is (76+CH_STA*0.05) MHz.
1:0
CH[9:8]
00
Highest 2 bits of 10-bit channel index: Channel freq is (76+CH*0.05)
MHz.
pac_target
[7]
pac_target
[6]
wo
wo
合
wo
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
pac_target
[4]
pac_target
[3]
pac_target
[2]
pac_target
[1]
pac_target
[0]
wo
wo
wo
wo
wo
Default
Description
PAC_TARGET [7:0]
1111 1111
PA calibration target value. PA output target is
(0.37*PAC_TARGET+68) dBuV. Valid values are 31-131 dBuV.
深
圳
7:0
pac_target
[5]
Bit 4
Symbol
市
金
Bit
Bit 5
技
有
Bit 6
讯
科
Bit 7
(MSB)
限
公
司
Word: PAC_TARGET Address: 0Ch
，
18
66
43
41
5
5:4
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 40
QN8006B/8006LB
Word: TXAGC GAIN Address: 0Dh
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
tx_sftclpen
tagc_gain_
sel
imr
txagc
_gdb
txagc_gvga
[3]
txagc_gvga
[2]
txagc_gvga
[1]
txagc_gvga
[0]
wo
wo
rw
rw
rw
rw
rw
rw
Symbol
Default
7
TX_SFTCLPEN
0
5
IMR
Enabled
85
，
TX AGC Gain selection method:
0
Both the TX digital gain TXAGC_GDB and the TX input
buffer gain TXAGC_GVGA [3:0] are determined by TX
AGC FSM on chip.
1
Both the TX digital gain and the TX input buffer gain are
determined by the contents of TXAGC_GDB and
TXAGC_GVGA [3:0] respectively.
0
Image Rejection: In non-CCA mode (CCA_DIS=1), this is a user set
value. In CCA mode, this is CCA selection read out.
司
0
市
金
圳
深
Rev 2.08 (04/10)
Confidential A
0001
LO<RF, image is in lower side.
LO>RF, image is in upper side.
TX digital gain:
限
技
有
0
讯
科
TXAGC_GVGA
[3:0]
合
3:0
TXAGC_GDB
公
1
4
：
1
QQ
Disabled
43
41
5
0
0
18
66
TAGC_GAIN_
SEL
TX soft clipping enable:
，
6
Description
71
Bit
44
51
81
9
Bit 6
Bit 7
(MSB)
0
0 dB
1
1 dB
TX input buffer gain: (dB)
VGAG
[3:0]
RIN[1:0]
00
01
10
11
0000
4.5
-1.5
-7.5
-13.5
0001
6
0
-6
-12
0010
7.5
1.5
-4.5
-10.5
0011
9
3
-3
-9
0100
10.5
4.5
-1.5
-7.5
0101
12
6
0
-6
0110
13.5
7.5
1.5
-4.5
0111
15
9
3
-3
1000
16.5
10.5
4.5
-1.5
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 41
QN8006B/8006LB
1001
18
12
6
0
1010
19.5
13.5
7.5
1.5
1011
21
15
9
3
Reserved
Address: 0Eh
44
Word: TX_FDEV
51
81
9
11XX
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
tx_fdev[7]
tx_fdev[6]
tx_fdev[5]
tx_fdev[4]
tx_fdev[3]
tx_fdev[2]
tx_fdev[1]
tx_fdev[0]
wo
wo
wo
wo
wo
wo
wo
wo
Default
7:0
TX_FDEV[7:0]
0110 1100
QQ
85
，
Symbol
Description
43
41
5
Bit
71
Bit 6
：
Bit 0
(LSB)
Bit 7
(MSB)
Specify total TX frequency deviation:
TX frequency deviation = 0.69 kHz*TX_FEDV.
18
66
TX_FDEV[7:0]
0 ~ 255
深
圳
市
金
合
讯
科
技
有
限
公
司
，
0000 0000 - 1111 1111
Value
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 42
QN8006B/8006LB
Word: GAIN_TXPLT Address: 0Fh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
i2sundfl_
clr
i2sovfl_
clr
gain_txpl
[3]
gain_txplt
[2]
gain_txplt
[1]
gain_txplt
[0]
rds_int_en
cca_int_en
wo
wo
wo
wo
wo
wo
wo
wo
6
I2SOVFL_
CLR
5:2
No action
1
Clear
2
0
GAIN_TXPLT
[3:0]
0
10 01
0
No action
1
Clear
81
51
Gain of TX pilot to adjust pilot frequency deviation: Refer to peak frequency
deviation of MPX signal when audio input is full scale.
1000
，
1001
司
1010
8% * 75kHz
9% * 75kHz
10% * 75kHz
RDS RX/TX Interrupt Enable: When RDS_INT_EN=1, a 4.5ms low pulse
will be output from DIN/INT (RX mode) or DOUT/INT (TX mode) when a
new group of data in RDSD0~RDSD7 is loaded into the internal transmitting
buffer after user toggles RDSTXRDY (TX mode) or a new group of data is
received and stored into RDS0~RDS7 (RX mode).
公
0
7% * 75kHz
讯
科
技
有
限
RDS_INT_EN
44
I S buffer overflow clear: User has to de-assert this bit after clearing.
0111
1
71
I S buffer underflow clear: User has to de-assert this bit after clearing.
：
0
QQ
I2SUNDFL_
CLR
Description
2
85
，
7
Default
43
41
5
Symbol
18
66
Bit
9
Bit 7
(MSB)
CCA_INT_EN
0
Disable
1
Enable
TX CCA / RX CCA Interrupt Enable: When CCA_INT_EN=1, a 4.5ms low
pulse will be output from DIN/INT (RX mode) or DOUT/INT (TX mode)
when TXCCA (TX mode) or a RXCCA (RX mode) is finished.
0
Disable
1
Enable
深
圳
市
金
合
0
0
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 43
QN8006B/8006LB
Address: 10h (RW)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rdsd0[7]
rdsd0[6]
rdsd0[5]
rdsd0[4]
rdsd0[3]
rdsd0[2]
rdsd0[1]
rdsd0[0]
rw
rw
rw
rw
rw
rw
rw
rw
81
Bit 7
(MSB)
9
Word: RDSD0
Symbol
Default
Description
7:0
RDSD0[7:0]
0000 0000
RDS data byte 0: In TX mode, it is written by user. In RX mode, it is the
received data. In TX mode, data written into RDSD0~RDSD7 cannot be
read out unless RDSTXRDY is toggled to allow the data to be loaded
into the internal transmitting buffer.
Address: 11h (RW)
43
41
5
Word: RDSD1
85
，
QQ
：
71
44
51
Bit
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rdsd1[7]
rdsd1[6]
rdsd1[5]
rdsd1[4]
rdsd1[3]
rdsd1[2]
rdsd1[1]
rdsd1[0]
rw
rw
rw
rw
rw
rw
rw
7:0
RDSD1[7:0]
0000 0000
，
Default
Description
司
Symbol
rw
RDS data byte 1: In TX mode, it is written by user. In RX mode, it is the
received data.
Address: 12h (RW)
Bit 7
(MSB)
Bit 6
rdsd2[7]
合
讯
科
Word: RDSD2
技
有
限
公
Bit
18
66
Bit 7
(MSB)
市
金
rdsd2[6]
圳
rw
rw
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rdsd2[5]
rdsd2[4]
rdsd2[3]
rdsd2[2]
rdsd2[1]
rdsd2[0]
rw
rw
rw
rw
rw
rw
Symbol
Default
Description
7:0
RDSD2[7:0]
0000 0000
RDS data byte 2: In TX mode, it is written by user. In RX mode, it is the
received data.
深
Bit
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 44
QN8006B/8006LB
Address: 13h (RW)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rdsd3[7]
rdsd3[6]
rdsd3[5]
rdsd3[4]
rdsd3[3]
rdsd3[2]
rdsd3[1]
rdsd3[0]
rw
rw
rw
rw
rw
rw
rw
rw
51
81
Bit 7
(MSB)
9
Word: RDSD3
Symbol
Default
Description
7:0
RDSD3[7:0]
0000 0000
RDS data byte 3: In TX mode, it is written by user. In RX mode, it is the
received data.
Address: 14h (RW)
Bit 6
Bit 5
Bit 4
Bit 3
rdsd4[7]
rdsd4[6]
rdsd4[5]
rdsd4[4]
rdsd4[3]
rw
rw
rw
rw
rw
18
66
Default
7:0
RDSD4[7:0]
0000 0000
rdsd4[2]
rdsd4[1]
rdsd4[0]
rw
rw
rw
Description
，
Symbol
Bit 0
(LSB)
RDS data byte 4: In TX mode, it is written by user. In RX mode, it is the
received data.
限
公
司
Bit
Bit 1
Bit 2
43
41
5
Bit 7
(MSB)
85
，
Word: RDSD4
QQ
：
71
44
Bit
Address: 15h (RW)
技
有
Word: RDSD5
Bit 6
rdsd5[7]
rdsd5[6]
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rdsd5[5]
rdsd5[4]
rdsd5[3]
rdsd5[2]
rdsd5[1]
rdsd5[0]
rw
rw
rw
rw
rw
rw
合
讯
科
Bit 7
(MSB)
rw
Symbol
Default
7:0
RDSD5[7:0]
0000 0000
深
圳
Bit
市
金
rw
Rev 2.08 (04/10)
Confidential A
Description
RDS data byte 5: In TX mode, it is written by user. In RX mode, it is the
received data.
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 45
QN8006B/8006LB
Address: 16h (RW)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rdsd6[7]
rdsd6[6]
rdsd6[5]
rdsd6[4]
rdsd6[3]
rdsd6[2]
rdsd6[1]
rdsd6[0]
rw
rw
rw
rw
rw
rw
rw
rw
Default
Description
7:0
RDSD6[7:0]
0000 0000
44
Symbol
RDS data byte 6: In TX mode, it is written by user. In RX mode, it is the
received data.
Address: 17h (RW)
Bit 6
Bit 5
Bit 4
Bit 3
rdsd7[7]
rdsd7[6]
rdsd7[5]
rdsd7[4]
rdsd7[3]
rw
rw
rw
rw
rw
7:0
RDSD7[7:0]
0000 0000
18
66
Default
rdsd7[2]
rdsd7[1]
rdsd7[0]
rw
rw
rw
Description
，
Symbol
Bit 0
(LSB)
RDS data byte 7: In TX mode, it is written by user. Writing to this byte
will cause the entire group (8 bytes) to be updated into the internal
transmitting buffer. In RX mode, it is the received data.
深
圳
市
金
合
讯
科
技
有
限
公
司
Bit
Bit 1
Bit 2
43
41
5
Bit 7
(MSB)
85
，
Word: RDSD7
QQ
：
71
Bit
51
81
Bit 7
(MSB)
9
Word: RDSD6
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 46
QN8006B/8006LB
Word: RDSFDEV
Address: 18h
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rds_only
rdsfdev[6]
rdsfdev[5]
rdsfdev[4]
rdsfdev[3]
rdsfdev[2]
rdsfdev[1]
rdsfdev[0]
wo
wo
wo
wo
wo
wo
wo
wo
Default
7
RDS_ONLY
1
RDSFDEV[6:0]
81
Description
000 0110
71
RDS mode selection:
Received bit-stream has both RDS and MMBS blocks
('E' block).
1
Received bit-stream has RDS block only, no MMBS block
('E' block).
QQ
：
0
Specify RDS frequency deviation:
85
，
6:0
51
Symbol
44
Bit
9
Bit 7
(MSB)
RDSFDEV[6:0]
Value
0 ~ 127
18
66
000 0000 - 111 1111
Address: 19h
Bit 5
txccaa[2]
txccaa[1]
txccaa[0]
wo
wo
wo
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rxccad[4]
rxccad[3]
rxccad[2]
rxccad[1]
rxccad[0]
wo
wo
wo
wo
wo
Bit 4
公
Bit 6
Bit
Symbol
技
有
限
Bit 7
(MSB)
司
，
Word: CCA
43
41
5
RDS frequency deviation = 0.35 kHz*RDSFDEV.
7:5
TXCCAA[2:0]
010
Scaling factor to determine in-band noise power to out-of-band noise power
ratio. Value 0 ~ 7 directly written in, default is 2. When TXCCAA is not zero,
valid channels must satisfy the condition "in-ban power > TXCCAA * out-ofband power", which usually is set to select channels without adjacent channel
interference. When TXCCAA=0, this condition is omitted.
0 1001
Lower 5 bits of RXCCAD [5:0]. See reg. 02h [7] for RXCCAD [5]. RXCCAD
[5:0] is used to set the threshold for RX CCA. When RSSI is selected as
RXCCA criteria (default), channel with RSSI (dBuV) > (RXCCAD-10) dBuV
is selected as valid channel. When SNR is selected as criteria for CCA, channel
with CNR at RF input > RXCCAD will be selected as valid channel.
RXCCAD[4:0]
深
圳
4:0
市
金
合
讯
科
Default
Rev 2.08 (04/10)
Confidential A
Description
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 47
QN8006B/8006LB
Word: STATUS1 Address: 1Ah (RO)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rsvd
rxcca_fail
i2sovfl
i2sundfl
insat
rxagcset
rxagcerr
st_mo_rx
ro
ro
ro
ro
ro
ro
ro
ro
51
81
9
Bit 7
(MSB)
Symbol
Default
Description
7
rsvd
r
Reserved
6
RXCCA_FAIL
r
RXCCA Status Flag: Indicates whether a valid channel is found during RX
CCA. If a valid channel is found, channel index will stay there, and
RXCCA_FAIL=0; otherwise, it will stay at the end of scan range and
RXCCA_FAIL=1.
I2SUNDFL
INSAT
r
I S overflow indicator:
0
No overflow
1
Overflow
2
I S underflow indicator:
0
No underflow
1
Underflow
Input level saturation flag:
限
0
讯
科
r
RXAGCERR
r
ST_MO_RX
深
圳
0
市
金
合
1
RXAGCSET
技
有
1
2
Rev 2.08 (04/10)
Confidential A
r
43
41
5
RX CCA fails to find a valid channel.
公
3
r
1
2
18
66
r
RX CCA successful finds a valid channel.
，
4
I2SOVFL
0
司
5
85
，
QQ
：
71
44
Bit
No saturation
Input level too high, Channel saturates.
RX AGC settling status:
0
Not settled
1
Settled
RXAGC status:
0
No error
1
AGC error
Stereo receiving status:
1
Mono
0
Stereo
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 48
QN8006B/8006LB
Word: STATUS3 Address: 1Bh (RO)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rds_rxtxupd
e_det
rdsc0c1
rdssync
rdsd0err
rdsd1err
rdsd2err
rdsd3err
ro
ro
ro
ro
ro
ro
ro
ro
Default
7
RDS_RXTXUPD
r
Description
44
Symbol
RDS RX: RDS received group updated. Each time a new group is
received, this bit will be toggled.
：
71
Bit
51
81
9
Bit 7
(MSB)
85
，
QQ
RDS TX: If the user wants the chip to transmit all of the 8 bytes in
RDS0~RDS7, the user should toggle the register bit RDSTXRDY. Then
the chip internally will fetch these bytes after completing transmission of
the current group. Once the chip internally has fetched these bytes, it will
toggle this bit.
r
A new set (8 bytes) of data is received.
0->0 or 1->1
New data is in receiving.
‘E’ block (MMBS block) detected:
0
RDS0ERR
r
RDS1ERR
r
r
深
圳
市
金
合
3
2
技
有
RDSSYNC
讯
科
4
1
0
RDS2ERR
RDS3ERR
Rev 2.08 (04/10)
Confidential A
r
r
Not detected
Detected
Type indicator of the RDS third block in one group:
公
r
限
RDSC0C1
司
1
5
18
66
E_DET
0->1 or 1->0
，
6
43
41
5
If RDS_INT_EN=1, then at the same time this bit is toggled, the interrupt
output pin (INT) will output a 4.5 ms low pulse.
0
C0
1
C1
RDS block synchronous indicator:
0
Non-synchronous
1
Synchronous
Received RDS block 0 status indicator:
0
No error
1
Error
Received RDS block 1 status indicator:
0
No error
1
Error
Received RDS block 2 status indicator:
0
No error
1
Error
Received RDS block 3 status indicator:
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 49
QN8006B/8006LB
No error
1
Error
Address: 1Ch (RO)
81
9
Word: RSSISIG
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rssidb[7]
rssidb[6]
rssidb[5]
rssidb[4]
rssidb[3]
rssidb[2]
rssidb[1]
rssidb[0]
ro
ro
ro
ro
ro
ro
ro
7:0
RSSIDB[7:0]
rrrr rrrr
44
71
：
Default
Description
QQ
Symbol
ro
In-band signal RSSI (Received Signal Strength Indicator) dBµV value:
85
，
Bit
51
Bit 7
(MSB)
43
41
5
dBµV = RSSI (with AGC correction) - 40
18
66
Word: RSSIMP Address: 21h (RO)
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rssimpdb[4]
rssimpdb[3]
rssimpdb[2]
rssimpdb[1]
rssimpdb[0]
ro
ro
ro
ro
ro
Bit 6
Bit 5
Bit 4
rsvd
rssimpdb[6]
rssimpdb[5]
ro
ro
ro
Bit
Symbol
Default
Description
7
rsvd
reserved
6:00
RSSIMPDB
技
有
限
公
司
，
Bit 7
(MSB)
Multipath signal RSSI (Received signal strength indicator) dB value.
讯
科
rrrrrrr
合
Address: 22h (RO)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
snrdb[7]
snrdb[6]
snrdb[5]
snrdb[4]
snrdb[3]
snrdb[2]
snrdb[1]
snrdb[0]
ro
ro
ro
ro
ro
ro
ro
ro
Bit
Symbol
Default
7:00
SNRDB
rrrrrrrr
深
Bit 7
(MSB)
Bit 6
圳
市
金
Word: SNR
r
Rev 2.08 (04/10)
Confidential A
Description
Estimated RF input CNR (Carrier Noise Ratio) value from noise floor
around the pilot after FM demodulation.
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 50
QN8006B/8006LB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rsvd
rsvd
rsvd
xtlbyp
rsvd
rsvd
rsvd
rsvd
wo
wo
wo
wo
wo
wo
wo
wo
000
4
XTLBYP
0
rsvd
0100
Reserved
Direct inject crystal oscillation from external XCLK pin.
0
Use internal crystal oscillator.
1
Inject external clock from pin XCLK.
Reserved
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
3:0
44
rsvd
71
7:5
Description
：
Default
QQ
Symbol
85
，
Bit
51
81
Bit 7
(MSB)
9
Word: REG_XLT3 Address: 49h
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 51
QN8006B/8006LB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
dacg[1]
dacg[0]
ro
ro
ro
ro
ro
ro
rw
rw
7:2
rsvd
rrrr rr
1:0
DACG[1:0]
01
51
Default
Description
44
Symbol
Reserved
71
Bit
01
0dB
10
-3dB
11
-6dB
85
，
43
41
5
18
66
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
司
Word: PAC_CAL Address: 59h
QQ
3dB
：
DAC output stage gain:
00
81
Bit 7
(MSB)
pacap[3]
pacap[2]
pacap[1]
pacap[0]
rw
rw
rw
rw
rw
Bit 6
Bit 5
Bit 4
pac_req
pac_dis
pacap[5]
pacap[4]
wo
wo
rw
技
有
限
公
，
Bit 7
(MSB)
9
Word: REG_DAC Address: 4Fh
Symbol
Default
7
PAC_REQ
讯
科
Bit
PAC_DIS
0
深
圳
6
市
金
合
0
5:0
PACAP[5:0]
Rev 2.08 (04/10)
Confidential A
000000
Description
Manually request PA tuning cap and gain calibration
PAC_REQ
Calibration request
1
Reset the calibration
0
At the 1->0 transition, calibration starts
Disable PA tuning cap calibration and use PACAP as circuit setting
PAC_DIS
Status of calibration
0
Use calibrated value
1
No calibration and use user-set value
User-set PA Tuning cap. Each LSB is 0.3pF. The read back value is the
calibration result.
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 52
QN8006B/8006LB
Word: PAG_CAL Address: 5Ah
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
rsvd
pag_dis
paipow[ 1]
paipow[ 0]
pagain[3]
pagain[2]
pagain[1]
pagain[0]
wo
wo
rw
rw
rw
rw
rw
rw
44
51
81
9
Bit 7
(MSB)
Symbol
Default
7
rsvd
r
Reserved
6
PAG_DIS
0
Disable PA output power calibration and use IPOW, PAGAIN as circuit
setting
IPOW[1:0]
QQ
：
00
Status of calibration
0
Use calibrated value
1
No calibration and use user-set value
85
，
PAG_DIS
43
41
5
5:4
Description
71
Bit
Set PA current. The read back value is the calibration result.
IPOW[1:0]
Current consumption in PA
4mA
18
66
00
2mA
10
1mA
11
0.5mA
1111
Set PAGAIn setting. The read back value is the calibration result.
Transmitter output voltage on the RFO pin (dBuV) is
124dBuV-1.5dB*PAGAIN [3:0].
公
PAGAIN[3:0]
深
圳
市
金
合
讯
科
技
有
限
3:0
司
，
01
Rev 2.08 (04/10)
Confidential A
POUT[3:0]
Power w matching
0
124
1
122.5
10
121
11
119.5
100
118
101
116.5
110
115
111
113.5
1000
112
1001
110.5
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 53
107.5
1100
106
1101
104.5
1110
103
1111
101.5
81
1011
51
109
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
QQ
：
71
44
1010
9
QN8006B/8006LB
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 54
QN8006B/8006LB
8 PACKAGE DESCRIPTION
43
41
5
85
，
QQ
：
71
44
51
81
9
24-Lead plastic Quad Flat, No Lead Package (ML) – 4x4 mm2 Body [QFN]
18
66
Figure 15: QN8006B/8006L-B Device
Units
MIN
公
Pitch
Standoff
技
有
Contact Thickness
限
Overall Height （SLP）
讯
科
Exposed Pad Width
0.50 BSC
0.80
0.85
0.00
0.90
0.05
0.203 REF
4.00 BSC
2.65
Overall Length
2.70
2.75
4.00 BSC
2.65
2.70
2.75
Contact Width
0.20
0.25
0.30
Contact Length
0.35
0.40
0.45
-
0.25
-
合
Exposed Pad Length
市
金
圳
MAX
24
司
Number of pins
Overall Width
NOM
，
Dimension Limits
Millimeters
Contact-to-Exposed Pad
深
Notes:
1.
2.
3.
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated.
Dimensioning and tolerance per ASME Y 14.5M.
BSC: Basic Dimension. The theoretically exact value is shown without tolerance.
REF: Reference Dimension, usually without tolerance, for information purpose only.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 55
QN8006B/8006LB
43
41
5
85
，
QQ
：
71
44
51
81
9
Carrier Tape Dimensions
18
66
Figure 16: QN8006B/8006LB Carrier Tape Dimensions
NOTES:
1. 10 sprocket hole pitch cumulative tolerance +0.2.
，
U
2. Camber in compliance with EIA-481.
限
技
有
4. A0 = 4.35
B0 = 4.35
K0 = 1.10
公
司
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole.
深
圳
市
金
合
讯
科
5. Reels are shipped in one of two sizes: 2,500 or 5,000 pieces per reel.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 56
QN8006B/8006LB
9 SOLDER REFLOW PROFILE
9.1 Package Peak Reflow Temperature
81
9
QN8006 is assembled in a lead-free QFN24 package. Since the geometrical size of QN8006 is 4 × 4 × 0.85 mm3, the
volume and thickness is in the category of volume<350 mm3 and thickness<1.6 mm in Table 4-2 of IPC/JEDEC J-STD020C. The peak reflow temperature is:
：
71
The temperature tolerance is +0oC and -5oC. Temperature is measured at the top of the package.
44
51
Tp = 260 o C
85
，
QQ
9.2 Classification Reflow Profiles
Specification*
Average Ramp-Up Rate (tsmax to tP)
3°C/second max.
Temperature Min (Tsmin)
Temperature Max (Tsmax)
Time (ts)
，
Temperature (TL)
Time (tL)
司
Time
maintained
above:
18
66
Pre-heat:
公
Peak/Classification Temperature (Tp)
限
Time within 5°C of Actual Peak
Temperature (tp)
技
有
Ramp-Down Rate
150°C
200°C
60-180 seconds
217°C
60-150 seconds
260°C
20-40 seconds
6°C/second max.
8 minutes max.
*Note: All temperatures are measured at the top of the package.
深
圳
市
金
合
讯
科
Time 25°C to Peak Temperature
43
41
5
Profile Feature
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 57
QQ
：
71
44
51
81
9
QN8006B/8006LB
85
，
Figure 17: Reflow Temperature Profile
43
41
5
9.3 Maximum Reflow Times
合
讯
科
技
有
限
公
司
，
18
66
All package reliability tests were performed and passed with a pre-condition procedure that repeat a reflow profile, which
conforms to the requirements in Section 9.2, three (3) times.
市
金
CONTACT INFORMATION
Quintic Microelectronics (China)
3211 Scott Blvd., Suite 203
Santa Clara, CA 95054
Tel: +1.408.970.8808
Fax: +1.408.970.8829
Email: [email protected]
Web: www.quinticcorp.com
Building 8 B-301A Tsinghua Science Park
1st East Zhongguancun Rd, Haidian
Beijing, China 100084
Tel: +86 (10) 8215-1997
Fax: +86 (10) 8215-1570
Web: www.quinticcorp.com
深
圳
Quintic Corporation (USA)
HU
HU
U
U
H
Quintic Microelectronics and Quintic are trademarks of Quintic Corporation. All Rights Reserved.
Rev 2.08 (04/10)
Confidential A
Copyright ©2010 by Quintic Corporation
Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 58