QN8035 Single-Chip Low-Power FM Receiver for Portable Devices __________________________ General Description __________________________ 9 The QN8035 is a high performance, low power; full-featured single-chip stereo FM receiver designed for cell phones, MP3 players. It integrates FM receive functions, auto-seek and clear channel scan. Advanced digital architecture enables superior receiver sensitivity and crystal clear audio. With its small footprint, minimal external component count and multiple clock frequency support, the QN8035 is easy to integrate into a variety of small form-factor low power portable applications. 81 _______________________________ Key Features ___________________________ 51 • Worldwide FM Band Coverage • 60 MHz to 108 MHz full band tuning in 50/100/200 kHz step sizes • 50/75μs de-emphasis : 85 , QQ • High Performance • Superior sensitivity, 1.1 µVEMF • 65dB stereo SNR, 0.04% THD • Improved auto channel seek • L/R separation 44dB • Robust Operation • -250C to +850C operation • ESD protection on all input and output pads • 1 KHz Tone Generator Inside 18 66 • Very Low Power Consumption • 12.8 mA typical • VCC: 2.7~5.0V, integrated LDO, support battery direct connection • Power saving Standby mode • Low shutdown leakage current • Accommodate 1.6~3.6V digital interface • Volume Control 43 41 5 • Ease of Integration • Small footprint, available in MSOP10 packages • 32.768 kHz and Multiple MHz crystal and direct clock input supported • I2C control interface 71 44 • Adaptive Noise Cancellation • Integrated adaptive noise cancellation (SNC, HCC, SM) , • Direct Earphone Driving 深 圳 市 金 合 讯 科 技 有 QN8035 Functional Blocks: 限 公 司 ___________________________ Typical Applications ________________________ • Feature Phone / Smart Phones • Netbook • Portable Audio & Media Players Ordering Information appears at Section 6. Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 1 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 CONTENTS 1 Pin Assignment ................................................................................................................................................5 2 Electrical Specifications ..................................................................................................................................6 81 51 3.1 FM Receiver ............................................................................................................................. 11 9 3 Functional Description ..................................................................................................................................11 44 3.2 Audio Processing ...................................................................................................................... 12 71 3.3 RDS/RBDS ............................................................................................................................... 13 : 3.4 Auto Seek (CCA) ...................................................................................................................... 13 QQ 4 Control Interface Protocol .............................................................................................................................14 85 , 5 Typical Application Schematic .....................................................................................................................16 43 41 5 6 Ordering Information.....................................................................................................................................17 7 Package Description ......................................................................................................................................18 18 66 8 Solder Reflow Profile ....................................................................................................................................20 8.1 Package Peak Reflow Temperature .......................................................................................... 20 , 8.2 Classification Reflow Profiles .................................................................................................. 20 技 有 限 公 司 8.3 Maximum Reflow Times ..........................................................................................................21 讯 科 REVISION HISTORY REVISION 2011-08-08 合 Draft. DATE 深 圳 市 金 0.1 CHANGE DESCRIPTION Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 2 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 1 PIN ASSIGNMENT ALO 2 9 SCL ARO 3 8 GND AGND 4 7 XCLK RFI 5 6 INT 81 SDA 51 10 44 1 43 41 5 Pin Descriptions NAME 1 VCC Voltage supply 2 ALO Analog audio output – left channel 3 ARO Analog audio output – right channel 4 AGND 5 RFI 6 INT 7 XCLK 8 GND Ground 9 SCL Clock for I2C serial bus. SDA Bi-directional data line for I2C serial bus. , Ground 司 FM Receiver RF input 限 公 Interrupt output, active low, need pull-up externally Clock input 深 圳 市 金 合 讯 科 10 DESCRIPTION 18 66 MSOP10 技 有 Table 1: QN8035-SANE Pin Out MSOP10 85 , Figure 1 QQ : 71 VCC 9 (Top View) Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 5 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 2 ELECTRICAL SPECIFICATIONS Table 2: Absolute Maximum Ratings CONDITIONS MIN MAX UNIT V Supply voltage VCC to GND -0.3 5 VIO1 Logic signal level SCL, SDA, INT to GND -0.3 3.6 -55 +150 Storage temperature V 44 Ts 81 Vbat o C Table 3: Recommended Operating Conditions CONDITIONS Vcc Supply voltage VCC to GND TA Operating temperature RFin RF input level1 VIO2 Digital I/O voltage MIN TYP MAX UNIT 2.7 3.3 5.0 V +85 o 0.3 V 3.6 V 43 41 5 PARAMETER 18 66 SYMBOL 85 , QQ : 71 Notes: 1. VIO is pulled up externally via resisters. 9 PARAMETER 51 SYMBOL -25 1.6 司 , Peak input voltage C 深 圳 市 金 合 讯 科 技 有 限 公 Notes: 1. At RF input pin, RFI. 2. VIO is pulled up externally via resisters. Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 6 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 Table 4: DC Characteristics (Typical values are at Vcc = 3.3V and TA = 25oC). PARAMETER CONDITIONS IIDLE Idle mode supply current ISTBY Standby mode supply current MAX UNIT 13.1 mA Idle mode 650 μA Standby mode 50 9 Receive mode supply current TYP μA 51 IRX MIN 81 SYMBOL Low level output voltage VIH High level input voltage 1.1 VIL Low level input voltage , (Typical values are at Vcc = 3.3V and TA = 25oC). 司 公 Clock frequency accuracy CONDITIONS Over temperature, and aging 限 Fxtal_err QQ V 0.3 V MIN TYP MAX UNIT 1 0.032768 -40 -50 MHz 50 ppm 技 有 Clock frequency V 18 66 Table 5: AC Characteristics PARAMETERS 0.1*VIO1 V 43 41 5 Notes: 1. VIO is pulled up externally via resisters. Fxtal 71 VOL : High level output voltage 85 , 0.9*VIO1 VOH SYMBOL 44 Interface 深 圳 市 金 合 讯 科 Notes: 1. See also XTAL_DIV[10:0], PLL_DLT[12:0] Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 7 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 Table 6: Receiver Characteristics (Typical values are at Vcc = 3.3V, f carrier=88 MHz and TA = 25oC). SYMBOL PARAMETERS CONDITIONS MIN TYP MAX UNIT FM sensitivity (S+N)/N = 26dB 1.1 μVEMF IP3 Input referred IP3 At maximum gain 120 dBμV RejAM AM suppression 52 dB Adjacent channel rejection 200 kHz offset 49 SRX_Alt Alternate channel rejection 400 kHz offset 62 MONO, Δf = 22.5 kHz1 STEREO, Δf = 67.5 kHz, Δfpilot = 6.75 kHz MONO, Δf = 75 kHz AttPilot out 43 41 5 De-emphasis time constant Audio output voltage Audio output Loading Resistance CLOAD Audio output loading capacitance RSSIerr RSSI uncertainty 讯 科 合 Audio THD after earphone driver 市 金 THDdriver 0.04 % 0.03 % 47 dB 70 dB 1 dB PETC = 1 71.3 75 78.7 μs PETC = 0 47.5 50 52.5 μs 1 1 V Peak-Peak, single ended 技 有 RLOAD dB dB 67 L and R channel gain imbalance at 1 kHz offset from DC , L/R channel imbalance τemph1 Vaudio Pilot rejection 司 BLR L/R separation 18 66 in STEREO, Δf = 67.5 kHz, Δfpilot = 6.75 kHz 限 αLR Audio THD 公 THDaudio_in dB 58 QQ Audio SNR 85 , SNRaudio_in 81 SRX_Adj kΩ 51 5 44 At pin RFI 71 RF input impedance : Rin 9 SRX Ω 32 -3 RLOAD=32Ω, 1 Vpp output 0.05 RLOAD=1kΩ, 1 Vpp output 0.03 20 pF 3 dB % 深 圳 Notes: 1. Guaranteed by design. Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 8 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 Table 7: Timing Characteristics (Typical values are at Vcc = 3.3V and TA = 25oC). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Chip power-up time 1 From power up to register access. 20 ms τchsw Channel switching time1 From any channel to any channel. 200 ms 200 τtune Tune time Per channel during CCA. 50 (Typical values are at Vcc = 3.3V and TA = 25oC). I2C clock frequency tLOW Clock Low time tHI Clock High time tST SCL input to SDA falling edge start 1,3 85 , 司 公 限 技 有 SCL rising edge3 3 SCL falling edge SCL falling edge to next SDA rising edge3 MIN TYP MAX UNIT 400 kHz 1.3 μs 0.6 μs 0.8 μs 0.8 μs Level from 30% to 70% 300 ns Level from 70% to 30% 300 ns 20 ns tdtc tstp SCL rising edge to SDA rising edge 2,3 0.6 μs tw Duration before restart3 1.3 μs Cb SCL, SDA capacitive loading3 SDA rising edge to next SCL rising edge3 市 金 圳 深 ms 合 tdtHD SDA falling edge to SCL falling edge start3 讯 科 tfc , fSCL CONDITIONS 18 66 PARAMETER 43 41 5 Table 8: I2C Interface Timing Characteristics trc ms QQ Notes: 1. Guaranteed by design. tSTHD 81 51 Standby to RX mode. 71 Wake-up time from standby to receive : τwkup 44 Receiver Timing SYMBOL 9 τpup 900 10 ns pF Notes: 1. Start signaling of I2C interface. 2. Stop signaling of I2C interface. 3. Guaranteed by design. Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 9 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. 18 66 I2C Serial Control Interface Timing Diagram 深 圳 市 金 合 讯 科 技 有 限 公 司 , Figure 2 43 41 5 85 , QQ : 71 44 51 81 9 QN8035 Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 10 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 3 FUNCTIONAL DESCRIPTION 43 41 5 85 , QQ : 71 44 51 81 9 The QN8035 is a high performance, low power, single chip FM receiver IC that supports worldwide FM broadcast band (60 to 108MHz). RDS/RBDS data service is also supported. QN8035 Functional Blocks 18 66 Figure 3 技 有 限 公 司 , The QN8035 integrates FM receive functions, including RF front-end circuits (LNA, Mixer and channel selective filter etc), a fully digitized FM demodulator, MPX decoder, de-emphasis and audio processing (SM, HCC, and SNC). Advanced digital architecture enables superior receiver sensitivity and crystal clear audio. The QN8035's Auto Seek function enables automatically selecting the channel of better sound quality. 深 圳 市 金 合 讯 科 The QN8035 supports a small footprint, high level of integration and multiple clock frequencies. These features make it easy to be integrated into a variety of small form-factor, low-power portable applications. Low phase noise digital synthesizers and extensive on-chip auto calibration ensures robust and consistent performance over temperature and process variations. An integrated voltage regulator enables direct connection to a Li-ion battery and provides high PSRR for superior noise suppression. A low-power IDLE and Standby mode extends battery life. 3.1 FM Receiver The QN8035 receiver uses a highly digitized low-IF architecture, allowing for the elimination of external components and factory adjustments. The received RF signal is first amplified by an integrated LNA and then down converted to an intermediate frequency (IF) via a quadrature mixer. To improve image rejection (IMR), the quadrature mixer can be programmed to be at high-side or low-side injection. An integrated IF channel filter rejects out-of-channel interference signals. AGC is also performed simultaneously to optimize the signal to noise ratio as well as linearity and interference rejection. The filtered signal is digitized and further processed with a digital FM demodulator and MPX decoder. Audio processing is then performed based on received signal quality and channel condition. Two highquality audio DACs are integrated on chip to drive the audio output. The RDS signal will also be decoded if RDS reception is enabled. A receive signal strength indicator (RSSI) is provided and can be read from RSSIDB [7:0]. Figure 4 shows the curve of RSSI vs. different RF input levels. Auto seek utilizes RSSI to search for available channels. Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 11 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 Single-Chip Low-Power FM Receiver for Portable Devices , 18 66 43 41 5 85 , QQ : 71 44 51 81 9 The following figure is measured at FM=88MHz. The RSSI Curve is not varied by FM frequency. RSSI vs RF Input 技 有 3.2 Audio Processing 限 公 司 Figure 4 讯 科 The MPX signal after FM demodulation is comprised of left and right channel signal, pilot and RDS signal in the following way: 合 m (t ) = [ L (t ) + R (t ) ] + [ L (t ) − R (t ) ] sin(4π ft + 2θ 0 ) + α sin(2π ft + θ 0 ) + d (t ) sin(6π ft + 3θ 0 ) 深 圳 市 金 Here, L(t) and R(t) correspond to the audio signals on the left and right channels respectively, f = 19 kHz, θ is the initial phase of pilot tone and α is the magnitude of the pilot tone, and d(t) is the RDS signal. In stereo mode, both L and R are recovered by de-MPX. In mono mode, only the L+R portion of audio signal exists. L(t) and R(t) are recovered by de-MPX. Rev 0.23 (03/09) In receive mode, stereo noise cancellation (SNC) for FM only, high cut control (HCC) and soft mute (SM) are supported. Stereo noise suppression is achieved by gradually combining the left and right signals to be a mono signal as the received signal quality degrades. SNC, HCC and SM are controlled by SNR and multipath channel estimation results. The three functions will be archived automatically in the device. The QN8035 has an integrated mono or stereo audio status indicator. There is also a Read ST_MO_RX (Reg04h [0]) bit to get status. In addition, there also is a force mono function to constrain output mono in Reg00h[2]. Two selectable de-emphasis time constants (75us and 50us) supported. Copyright ©2009 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. Page 1 18 66 43 41 5 85 , QQ : 71 44 51 81 9 QN8035 , Figure 5 encoding/decoding, block synchronization, error detection and correction functions. RDS/RBDS data communicates with an external MCU through the serial control interface. 讯 科 3.3 RDS/RBDS 技 有 限 公 司 The audio output can be muted with the MUTE_EN (Reg14h[7]) bit and the output can also be replaced by an internally generated 1KHz tone whenever the RFI has a RF signal input. Audio Response 3.4 Auto Seek (CCA) In receive mode, the QN8035 can automatically tune to stations with good signal quality. The auto seek function is referred to CCA (Clear Channel Assessment). 深 圳 市 金 合 The QN8035 supports RDS/RBDS data reception in FM mode, including station ID, Meta data, TMC information, etc. The integrated RDS processor performs all symbol Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 13 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 4 CONTROL INTERFACE PROTOCOL The QN8035 supports the standard I2C serial interfaces. At power-on, all register bits are set to default values. I2C Serial Control Interface 51 81 9 QN8035 provides an I2C-compatible serial interface. It consists of two wires; serial bi-directional data line (SDA) and input clock line (SCL). It operates as a slave on the bus and the slave address is 0010000. The data transfer rate on the bus is up to 400 Kbit/s. : 71 44 SDA must be stable during the high period of SCL, except for start and stop conditions. SDA can only change with SCL being low. A high-to-low transition on SDA while SCL is high indicates a start condition. A low-to-high transition on SDA while SCL is high indicates a stop condition. 43 41 5 85 , QQ An I2C master initiates a data transfer by generating a start condition followed by the QN8035 slave address, MSB first, followed by a 0 to indicate a write cycle. After receiving an ACK from the QN8035 (by pulling SDA low), the master sends the sub-address of the register, or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The QN8035 acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by generating a stop condition (P). 18 66 The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the QN8035 by generating a start condition (S) followed by the QN8035 slave address, MSB first, followed by a 0 to indicate a write cycle. After receiving ACK from the QN8035, the master sends the sub-address of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P). 深 圳 市 金 合 讯 科 技 有 限 公 司 , The second phase is the data phase. In this phase, an I2C master initiates a read operation to the QN8035 by generating a start condition followed by the QN8035 slave address, MSB first, followed by a 1 to indicate a read cycle. After an acknowledge from the QN8035, the I2C master receives one or more bytes of data from the QN8035. The I2C master acknowledges the transfer at the end of each byte. After the last data byte to be sent has been transferred from the QN8035 to the master, the master generates a NACK followed by a stop. Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 14 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 Figure 6 The default IC address is 0010000. “20” for a WRITE operation, “21” for a READ operation. 深 圳 市 金 合 讯 科 技 有 限 公 司 , 1. 2. I2C Serial Control Interface Protocol 18 66 Notes: 43 41 5 85 , QQ : 71 44 51 81 9 The timing diagrams below illustrate both write and read operations. Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 15 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 5 TYPICAL APPLICATION SCHEMATIC VCC_3.3V U7 9 SDA 10 GND GND ARO SCL ALO SDA VCC 51 2 VCC_3.3V 4.7uF/16V 0603 1 ARO ALO 0.1uF/10V 0402 Typical Application Schematic 深 圳 市 金 合 讯 科 技 有 限 公 司 , 18 66 Figure 7 3 43 41 5 QN8035 MSOP10 4 Antenna 1000p 330nH 0402 0603 0603 4.7uF/16V 44 XCLK 5 71 8 56p/10V SCL RFI : 7 XCLK INT QQ 6 85 , INT 81 9 10K 10K 10K Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 16 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 6 ORDERING INFORMATION Package The QN8035-SANE is Single-Chip Low-Power FM receiver. Body [MSOP10] 深 圳 市 金 合 讯 科 技 有 限 公 司 , 18 66 43 41 5 85 , QQ : 71 44 51 81 QN8035-SANE Description 9 Part Number Rev 0.2 (11/10) Confidential A Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 17 QN8035 7 PACKAGE DESCRIPTION 43 41 5 85 , QQ : 71 44 51 81 9 10-Lead plastic Quad Flat, No Lead Package (ML) –Body [MSOP] A1 Board standoff A2 Package thickness b Lead width c Millimeters Minimum Nominal Maximum 0.820 0.95 1.100 0.020 - 0.150 0.750 0.85 0.950 0.180 0.23 0.280 Lead thickness 0.090 - 0.230 D Package’s outside, X-axis 2.900 3.00 3.100 e Lead pitch 0.50 (BSC) E Package’s outside, Y-axis 2.900 3.00 3.100 Lead to lead, Y-axis 4.750 4.90 5.050 L Foot length 0.400 0.60 0.800 θ Foot to board angle 0° - 6° 限 技 有 合 圳 市 金 E1 司 Overall package height 公 A 18 66 Description 讯 科 Symbol MSOP10 Package Outline Dimensions , Figure 8 深 Notes: 1. 2. Pin 1 visual index feature may vary, but must be located within the area indicated in the drawing. Dimensioning and tolerance per ASME Y 14.5M. BSC: Basic Dimension. The theoretically exact value is shown without tolerance. Carrier Tape Dimensions Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 18 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 MSOP10 Carrier Tape Drawing 18 66 Figure 9 43 41 5 85 , QQ : 71 44 51 81 9 MSOP10 Carrier Tape NOTES: 1. 10 sprocket hole pitch cumulative tolerance +0.2mm maximum. 2. Camber not to exceed 1mm in 100mm: <1mm/100mm. 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. 深 圳 市 金 合 讯 科 技 有 限 公 司 , U Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 19 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QN8035 8 SOLDER REFLOW PROFILE 8.1 Package Peak Reflow Temperature 9 QN8035 are assembled in a lead-free MSOP10 package. Since the geometrical size of QN8035 is 3 × 3 × 0.85 mm, the volume and thickness is in the category of volume<350 mm3 and thickness<1.6 mm in Table 4-2 of IPC/JEDEC J-STD020C. The peak reflow temperature is: 71 The temperature tolerance is +0oC and -5oC. Temperature is measured at the top of the package. 44 51 81 Tp = 260 o C 85 , QQ : 8.2 Classification Reflow Profiles Specification* Average Ramp-Up Rate (tsmax to tP) 3°C/second max. Temperature Min (Tsmin) Temperature Max (Tsmax) Time (ts) Temperature (TL) Time (tL) , Time maintained above: 18 66 Pre-heat: 司 Peak/Classification Temperature (Tp) 限 公 Time within 5°C of Actual Peak Temperature (tp) 技 有 Ramp-Down Rate Time 25°C to Peak Temperature 150°C 200°C 60-180 seconds 217°C 60-150 seconds 260°C 20-40 seconds 6°C/second max. 8 minutes max. *Note: All temperatures are measured at the top of the package. 深 圳 市 金 合 讯 科 43 41 5 Profile Feature Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 20 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice. QQ : 71 44 51 81 9 QN8035 85 , Figure 1: Reflow Temperature Profile 43 41 5 8.3 Maximum Reflow Times 讯 科 技 有 限 公 司 , 18 66 All package reliability tests were performed and passed with a pre-condition procedure that repeat a reflow profile, which conforms to the requirements in Section 8.2, three (3) times. 市 金 合 CONTACT INFORMATION Quintic Corporation (USA) Quintic Microelectronics (China) 深 圳 3211 Scott Blvd., Suite 203 Santa Clara, CA 95054 Tel: +1.408.970.8808 Fax: +1.408.970.8829 Email: [email protected] Web: www.quinticcorp.com HU HU U U Building 8 B-301A Tsinghua Science Park 1st East Zhongguancun Rd, Haidian Beijing, China 100084 Tel: +86 (10) 8215-1997 Fax: +86 (10) 8215-1570 Web: www.quinticcorp.com H Quintic Microelectronics and Quintic are trademarks of Quintic Corporation. All Rights Reserved. Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 21 Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice.