RICHTEK RT8065

RT8065
3A, 2MHz, Synchronous Step-Down Converter
General Description
Features
The RT8065 is a high efficiency synchronous, step-down
DC/DC converter. Its input voltage range is from 2.7V to
5.5V and provides an adjustable regulated output voltage
from 0.8V to 5V while delivering up to 3A of output current.
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The internal synchronous low on-resistance power
switches increase efficiency and eliminate the need for
an external Schottky diode. The default switching
frequency is set at 2MHz, if the RT pin is left open. It can
also be varied from 200kHz to 2MHz by adding an external
resistor. Current mode operation with external
compensation allows the transient response to be
optimized over a wide range of loads and output capacitors.
z
z
z
z
z
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3
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Note :
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Pin Configurations
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LCD TV and Monitor
Notebook Computers
Distributed Power Systems
IP Phones
Digital Cameras
5
2
5
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
(TOP VIEW)
8
COMP
SS
2
EN
3
VIN
4
GND
PGOOD
7
FB
6
RT
5
LX
9
SOP-8 (Exposed Pad)
RoHS compliant and compatible with the current require-
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Suitable for use in SnPb or Pb-free soldering processes.
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Marking Information
RT8065ZSP
市
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COMP
SS
EN
VIN
8
1
3
GND
ments of IPC/JEDEC J-STD-020.
`
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Package Type
SP : SOP-8 (Exposed Pad-Option 2)
QW : WDFN-8L 3x3 (W-Type)
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RT8065
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Ordering Information
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Applications
The RT8065 operates in forced continuous PWM Mode,
which minimizes ripple voltage and reduces the noise and
RF interference.
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High Efficiency : Up to 95%
Adjustable Frequency : 200kHz to 2MHz
No Schottky Diode Required
0.8V Reference Allows Low Output Voltage
Forced Continuous Mode Operation
Low Dropout Operation : 100% Duty Cycle
Enable Function
External Soft-Start
Power Good Function
RoHS Compliant and Halogen Free
6
4
9
5
2
7
PGOOD
FB
RT
LX
WDFN-8L 3x3
RT8065ZSP : Product Number
深
RT8065
ZSPYMDNN
YMDNN : Date Code
RT8065ZQW
29 : Product Code
29 YM
DNN
YMDNN : Date Code
DS8065-03 March 2011
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1
RT8065
Typical Application Circuit
VIN
2.7V to 5.5V
RT8065
5
LX
VIN
4
L
VOUT
CIN
10µF
R3
100k
R1
FB
8 PGOOD
PGOOD
ROSC
6 RT
COMP
7
COUT
RCOMP
1
R2
CCOMP
Chip Enable
3
GND 9 (Exposed Pad)
SS 2
CSS
0.1nF
EN
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Table 1. Recommended Components Selection for fSW = 1MHz
R1 (kΩ)
R2 (kΩ)
RCOMP (kΩ)
CCOMP (pF)
L (μH)
75
24
33
560
2
51
24
22
560
2
30
24
15
560
1.5
21
24
13
560
1.5
12
24
11
560
1.5
6
24
8.2
560
1.5
电
VOUT (V)
3.3
2.5
1.8
1.5
1.2
1
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5
1
Pin No.
SOP-8
(Exposed Pad)
2
5
1
1
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EN
VIN
5
LX
6
RT
7
7
FB
8
8
PGOOD
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深
6
9 (Exposed Pad) 9 (Exposed Pad) GND
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Pin Function
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Error Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. Connect
external compensation elements to this pin to stabilize the
control loop.
Soft-Start Control Input. Connect a capacitor from SS to GND
to set the soft-start period. A 10nF capacitor sets the
soft-start period to 800μs (typ.).
Enable Control Input. Float or connect this pin to logic high
for enable. Connect to GND for disable.
Power Input Supply. Decouple this pin to GND with a
capacitor.
Internal Power MOSFET Switches Output. Connect this pin
to the inductor.
Oscillator Resistor Input. Connect a resistor from this pin to
GND sets the switching frequency. If this pin is floating, the
frequency will be set at 2MHz internally.
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COUT (μF)
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Pin Name
38
WDFN-8L 3x3
4
4
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Functional Pin Description
50
Feedback Pin. Receives the feedback voltage from a
resistive divider connected across the output.
Power Good Indicator. This pin is an open drain logic output
that is pulled to ground when the output voltage is not within
±12.5% of regulation point.
Ground Pin. The exposed pad must be soldered to a large
PCB and connected to GND for maximum power dissipation.
DS8065-03 March 2011
RT8065
Function Block Diagram
RT
SD
VIN
ISEN
Slope
Com
OSC
COMP
0.8V
FB
OC
Limit
Output
Clamp
EA
10µA
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Driver
Hiccup
SS
Control
Logic
0.7V
EN
Enable
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P-G
0.4V
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2
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38
2
5
GND
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N-MOSFET ILIM
3
8
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PGOOD
0
5
4
4
1
2
NISEN
OTP
UV
LX
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RT8065
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, VIN ---------------------------------------------------------------------------------------- −0.3V to 6V
LX Pin Switch Voltage -------------------------------------------------------------------------------------------- −0.3V to (VIN + 0.3V)
z Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to (VIN + 0.3V)
z LX Pin Switch Current -------------------------------------------------------------------------------------------- 5A
z Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) ------------------------------------------------------------------------------------------ 1.333W
WDFN-8L 3x3 ------------------------------------------------------------------------------------------------------ 1.429W
z Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA -------------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC ------------------------------------------------------------------------------------- 15°C/W
WDFN-8L 3x3, θJA ------------------------------------------------------------------------------------------------- 70°C/W
WDFN-8L 3x3, θJC ------------------------------------------------------------------------------------------------- 8.2°C/W
z Junction Temperature --------------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C
z Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ---------------------------------------------------------------------------------------------- 200V
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Recommended Operating Conditions
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(Note 4)
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Supply Input Voltage, VIN ---------------------------------------------------------------------------------------- 2.7V to 5.5V
Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------ −40°C to 85°C
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Electrical Characteristics
(VIN = 3.3V, TA = 25°C, unless otherwise specified)
Parameter
-2
Symbol
55
Feedback Reference Voltage
Output Voltage Line Regulation
Output Voltage Load Regulation
Error Amplifier
gm
Trans-conductance
Current Sense Trans-resistance RT
Min
Typ
Max
Unit
0.784
0.8
0.816
V
Active , VFB = 0.78V, Not Switching
Shutdown
---
460
--
-10
μA
VIN = 2.7V to 5.5V
0A < ILOAD < 3A
---
0.1
0.25
---
%/V
%
--
400
--
μA/V
Ω
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Test Conditions
VREF
07
DC Bias Current
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5
1
--
0.3
--
ROSC = 330kΩ
0.8
1
1.2
Switching
0.2
--
2
VIH
EN Rising
1.6
--
--
VIL
EN Falling
--
--
0.4
Switch On-Resistance, High
RDS(ON)_P ILX = 0.5A
--
120
180
mΩ
Switch On-Resistance, Low
RDS(ON)_N ILX = 0.5A
--
80
120
mΩ
Peak Current Limit
ILIM
3.6
4.5
--
A
VIN Rising
--
2.4
--
VIN Falling
--
2.2
--
圳
Switching Frequency
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Enable Threshold Voltage
Under Voltage Lockout
Threshold
MHz
V
V
To be continued
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DS8065-03 March 2011
RT8065
Parameter
Symbol
RT Shutdown Threshold
Soft-Start Period
Test Conditions
VRT
VRT Rising
tSS
CSS = 10nF
Min
Typ
Unit
VIN − 0.7 VIN − 0.4
--
PGOOD Trip Threshold
Max
V
--
800
--
μs
--
87.5
--
%VOUT
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
packages.
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Note 3. Devices are ESD sensitive. Handling precaution is recommended.
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Note 4. The device is not guaranteed to function outside its operating conditions.
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RT8065
Typical Operating Characteristics
Efficiency vs. Output Current
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Efficiency vs. Output Current
60
50
40
30
60
50
40
30
20
20
10
0
0
0
0.5
1
1.5
2
2.5
电
3
0
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Output Current (A)
佳
Output Voltage vs. Output Current
圳
25
55
1.100
1
8
3
1.090
2
5
1.080
5
7
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0
0.5
1
1.5
2
3
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0.99
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0.98
0.97
0.96
VIN = 5V, VOUT = 1.1V, IOUT = 0.6A,
RRT = 330kΩ
0.95
1
1.5
2
2.5
3
Reference Voltage vs. Temperature
0.83
圳
1.00
0.5
Output Current (A)
Reference Voltage (V)
Switching Frequency (MHz)1
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VIN = 5V, VOUT = 3.3V, IOUT = 0A to 3A
0.84
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3.320
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1.02
3
3.300
北
1.03
2.5
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3.330
Switching Frequency vs. Temperature
1.04
2
4
4
3.340
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2.5
Output Current (A)
1.5
3.310
VIN = 5V, VOUT = 1.1V, IOUT = 0A to 3A
1.070
50
1
Output Current (A)
/8
3.350
深
1.110
0.5
1
2
3
3.360
Output Voltage (V)
1.120
VIN = 5V, VOUT = 3.3V, IOUT = 0A to 3A
Output Voltage vs. Output Current
富
1.130
Output Voltage (V)
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VIN = 5V, VOUT = 1.1V, IOUT = 0A to 3A
0.82
0.81
0.80
0.79
0.78
0.77
VIN = 5V, VOUT = 1.1V
0.76
0.94
-50
-25
0
25
50
Temperature (°C)
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100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
DS8065-03 March 2011
RT8065
Enable Voltage vs. Temperature
1.6
2.7
1.5
2.6
1.4
2.5
Enable Voltage (V)
VIN UVLO (V)
VIN UVLO vs. Temperature
2.8
Rising
2.4
2.3
2.2
Falling
2.1
1.3
Rising
1.2
1.1
1.0
Falling
0.9
2.0
0.8
1.9
0.7
1.8
0.6
-50
-25
0
25
50
75
100
-50
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Temperature (°C)
佳
Load Transient Response
圳
5
2
5
38
2
5
5
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0
Switching
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VOUT
(10mV/Div)
125
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VIN = 5V, VOUT = 3.3V, IOUT = 1A to 3A,
RCOMP = 33kΩ, CCOMP = 560pF
Time (100μs/Div)
VLX
(5V/Div)
VOUT
(10mV/Div)
VIN = 5V, VOUT = 1.1V, IOUT = 3A
Time (500ns/Div)
DS8065-03 March 2011
100
Switching
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VLX
(5V/Div)
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IOUT
(1A/Div)
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Time (100μs/Div)
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VIN = 5V, VOUT = 1.1V, IOUT = 1A to 3A,
RCOMP = 10kΩ, CCOMP = 560pF
50
25
Temperature (°C)
/8
5
1
IOUT
(1A/Div)
0
1
2
3
VOUT
(200mV/Div)
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-25
Load Transient Response
富
VOUT
(200mV/Div)
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VIN = 5V, VOUT = 3.3V, IOUT = 3A
Time (500ns/Div)
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RT8065
Power On from VIN
Power Off from VIN
VIN
(5V/Div)
VIN
(5V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
VPGOOD
(10V/Div)
VPGOOD
(10V/Div)
IOUT
(2A/Div)
IOUT
(2A/Div)
VIN = 5V, VOUT = 1.1V, IOUT = 3A, EN = High
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VIN = 5V, VOUT = 1.1V, IOUT = 3A, EN = High
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Time (2.5ms/Div)
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Power On from EN
5
2
5
VOUT
(2V/Div)
5
1
38
VPGOOD
(5V/Div)
IOUT
(5A/Div)
2
5
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Time (500μs/Div)
VPGOOD
(5V/Div)
IOUT
(5A/Div)
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VIN = 5V, VOUT = 1.1V, IOUT = 3A
5
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0
3
8
/
VEN
(5V/Div)
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VOUT
(2V/Div)
4
1
2
Power Off from EN
富
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VEN
(5V/Div)
0
5
4
Time (5ms/Div)
VIN = 5V, VOUT = 1.1V, IOUT = 3A
Time (250μs/Div)
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DS8065-03 March 2011
RT8065
Application Information
The basic IC application circuit is shown in Typical
Application Circuit. External component selection is
determined by the maximum load current and begins with
the selection of the inductor value and operating frequency
followed by CIN and COUT.
for the external capacitor. If 10nF capacitor is used to set
the soft-start, the period will be 800μs (typ.).
Power Good Output
Main Control Loop
The power good output is an open-drain output and requires
a pull up resistor. When the output voltage is 12.5% above
or 12.5% below its set voltage, PGOOD will be pulled
low. It is held low until the output voltage returns to within
the allowed tolerances once more. During soft-start,
PGOOD is actively held low and is only allowed to transition
high when soft-start is over and the output voltage reaches
87.5% of its set voltage.
During normal operation, the internal upper power switch
(P-MOSFET) is turned on at the beginning of each clock
cycle. Current in the inductor increases until the peak
inductor current reaches the value defined by the output
voltage (VCOMP) of the error amplifier. The error amplifier
adjusts its output voltage by comparing the feedback signal
from a resistive voltage-divider on the FB pin with an
internal 0.8V reference. When the load current increases,
it causes a reduction in the feedback voltage relative to
the reference. The error amplifier increases its output
voltage until the average inductor current matches the new
load current. When the upper power MOSFET shuts off,
the lower synchronous power switch (N-MOSFET) turns
on until the beginning of the next clock cycle.
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RT8065
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R1
R2
GND
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Figure 1. Setting the Output Voltage
Soft-Start
The IC contains an external soft-start clamp that gradually
raises the output voltage. The soft-start timing is
programmed by the external capacitor between SS pin
and GND. The chip provides an internal 10μA charge current
DS8065-03 March 2011
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RT pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing capacitor within the oscillator. The practical switching
frequency ranges from 200kHz to 2MHz. However, when
the RT pin is floating, the internal frequency is set at 2MHz.
Determine the RT resistor value by examining the curve
below.
际
2.4
Switching Frequency (MHz)1
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The resistive voltage divider allows the FB pin to sense a
fraction of the output voltage as shown in Figure 1
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The operating frequency of the IC is determined by an
external resistor, ROSC, that is connected between the
38
The output voltage is set by an external resistive voltage
divider according to the following equation :
R1 ⎞
⎛
VOUT = VREF × ⎜ 1 +
⎟
R2 ⎠
⎝
where VREF equals to 0.8V typical.
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3
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2
5
5
1
Output Voltage Setting
4
1
2
Selection of the operating frequency is a tradeoff between
efficiency and component size. Higher frequency operation
allows the use of smaller inductor and capacitor values.
Lower frequency operation improves efficiency by reducing
internal gate charge and switching losses but requires
larger inductance and/or capacitance to maintain low output
ripple voltage.
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0
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4
Operating Frequency
2.0
1.6
1.2
0.8
0.4
0.0
0
300
600
900
1200
1500
1800
2100
RRT (k Ω)
Figure 2. Switching Frequency vs. RT Resistor
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9
RT8065
used to monitor over current condition, so the maximum
output current stays relatively constant regardless of the
duty cycle.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current, ΔIL, increases with higher VIN and decreases
with higher inductance.
Hiccup Mode Under Voltage Protection
⎤
V
⎡V
⎤ ⎡
ΔIL = ⎢ OUT ⎥ × ⎢1 − OUT ⎥
VIN ⎦
⎣ f ×L ⎦ ⎣
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. Highest efficiency operation is achieved by reducing
ripple current at low frequency, but attaining this goal
requires a large inductor.
A Hiccup Mode Under Voltage Protection (UVP) function
is provided for the IC. When the FB voltage drops below
half of the feedback reference voltage, VFB, the UVP
function is triggered to auto soft-start the power stage
until this event is cleared. The Hiccup Mode UVP reduces
the input current in short circuit conditions, but will not be
triggered during soft-start process.
For the ripple current selection, the value of ΔIL = 0.4(IMAX)
is a reasonable starting point. The largest ripple current
occurs at the highest VIN. To guarantee that the ripple
current stays below a specified maximum value, the
inductor value needs to be chosen according to the following
equation :
Under Voltage Lockout Threshold
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⎡ VOUT ⎤ ⎡
⎤
V
L= ⎢
⎥ × ⎢1− OUT ⎥
⎣⎢ f × ΔIL(MAX) ⎦⎥ ⎣⎢ VIN(MAX) ⎦⎥
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1
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
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Slope Compensation and Peak Inductor Current
深
Slope compensation provides stability in constant
frequency architectures by preventing sub- harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by adding a compensating ramp
to the inductor current signal. Normally, the peak inductor
current is reduced when slope compensation is added.
For the IC, however, separated inductor current signal is
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For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
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Thermal Considerations
38
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Using Ceramic Input and Output Capacitors
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The RT8065 includes an input under voltage lockout
protection (UVLO) function. If the input voltage exceeds
the UVLO rising threshold voltage, the converter will reset
and prepare the PWM for operation. However, if the input
voltage falls below the UVLO falling threshold voltage during
normal operation, the device will stop switching. The UVLO
rising and falling threshold voltage has a hysteresis to
prevent noise-caused reset.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8065, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θ JA , is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θJA, is 75° C/W on a standard JEDEC 51-7 four-layer
thermal test board. For WDFN-8L 3x3 packages, the
thermal resistance, θJA, is 70°C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum power
DS8065-03 March 2011
RT8065
Layout Considerations
dissipation at TA =25°C can be calculated by the following
formulas :
Follow the PCB layout guidelines for optimal performance
of the IC.
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
`
Connect the terminal of the input capacitor(s), CIN, as
close to the VIN pin as possible. This capacitor provides
the AC current into the internal power MOSFETs.
`
LX node experiences high frequency voltage swings so
should be kept within a small area.
`
Keep all sensitive small signal nodes away from the LX
node to prevent stray capacitive noise pick up.
`
Connect the FB pin directly to the feedback resistors.
The resistive voltage-divider must be connected between
VOUT and GND.
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-8L 3x3 package
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
电
Four-Layer PCB
0
25
50
维
富
圳
深
CCOMP
5/
2
5
5
GND
VIN
华
市
圳
深
7
GND
3
6
9
4
5
厦
FB
RT
COUT
大
R1
ROSC
LX
L1
VOUT
国
诚
鼎
强
28
2
CIN
室
5
0
R2
PGOOD
际
23
北
8
VOUT
GND
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace
Place the input and output capacitors
as close to the IC as possible
Figure 3. Derating Curve for the RT8065 Package
0
VIN
125
Ambient Temperature (°C)
75
EN
CSS
100
5-
COMP
SS
Place the feedback
resistors as close to
the IC as possible
4
1
2
83
GND
RCOMP
81
75
0
5
4
Place the compensation
components as close to
the IC as possible
佳
WDFN-8L 3x3
SOP-8 (Exposed Pad)
子
Place the feedback
resistors as close to
the IC as possible
Place the compensation
components as close to
the IC as possible
GND
R2
CCOMP
RCOMP
CSS
GND
CIN
VIN
COMP
SS
EN
1
VIN
4
2
3
8
GND
Maximum Power Dissipation (W)1
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. For the RT8065 package, the derating
curves in Figure 3 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
9
7
6
5
PGOOD
FB
RT
LX
L1
COUT
VOUT
R1
VOUT
GND
ROSC
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace
Place the input and output capacitors
as close to the IC as possible
Figure 4. PCB Layout Guide
DS8065-03 March 2011
www.richtek.com
11
RT8065
Outline Dimension
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
B
X
F
子
电
0
5
4
C
I
维
佳
D
Dimensions In Millimeters
富
Symbol
Min
圳
A
深
B
C
4.000
Option 2
华
强
X
Y
0.157
28
1.346
0.047
0.170
0.254
0.007
0.010
0.000
0.152
0.000
0.006
5.791
6.200
0.228
0.244
1.270
0.016
0.050
0.069
2.300
0.079
0.091
2.000
2.300
0.079
0.091
2.100
2.500
0.083
0.098
3.000
3.500
0.118
0.138
厦
大
际
国
诚
鼎
2.000
北
Y
0.150
0.013
0.406
X
0.197
0.510
38
Option 1
0.189
0.053
5
1
M
5/
室
5
0
Max
1.753
1.194
2
5
Min
52
1.346
F
J
市
3.810
0.330
I
5
7
0
5.004
D
H
83
Max
4.801
4
1
2
Dimensions In Inches
0.020
0.053
8-Lead SOP (Exposed Pad) Plastic Package
圳
深
www.richtek.com
12
DS8065-03 March 2011
RT8065
D2
D
L
E
E2
SEE DETAIL A
1
e
b
2
1
2
1
A
A1
A3
子
电
DETAIL A
Pin #1 ID and Tie Bar Mark Options
0
5
4
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
维
佳
富
0.700
0.800
0.000
0.050
3
8
/
0.250
0.007
0.300
0.008
3.050
0.116
0.120
0.083
0.093
Dimensions In Millimeters
Symbol
圳
Min
深
A
A1
0.175
b
1
8
3
0.200
2.950
2
5
D2
E
5
7
0
E2
25
Min
28
0.028
0.031
0.000
0.002
厦
大
际
0.010
0.012
2.350
2.950
3.050
0.116
0.120
1.600
0.053
0.063
1.350
鼎
北
0.425
强
华
国
诚
室
5
0
Max
2.100
e
L
Max
Dimensions In Inches
55
A3
D
4
1
2
0.650
0.026
0.525
0.017
0.021
W-Type 8L DFN 3x3 Package
市
圳
深
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8065-03 March 2011
www.richtek.com
13