a
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus and Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator and Shifter
Single-Cycle Instruction Execution and Multifunction
Instructions
On-Chip Program Memory ROM and Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate (5 V)
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC and MQFP Packages
GENERAL DESCRIPTION
The ADSP-216x Family processors are single-chip microcomputers␣ optimized␣ for␣ digital␣ signal␣ processing␣ (DSP)
and other high speed numeric processing applications. The
ADSP-216x processors are all built upon a common core with
ADSP-2100. Each processor combines the core DSP architecture—computation units, data address generators and program
sequencer—with features such as␣ on-chip program ROM and
data memory RAM, a programmable timer and two serial ports.
The ADSP-2165/ADSP-2166 also adds program memory and
power-down mode.
This data sheet describes the following ADSP-216x Family
processors:
ADSP-2161/ADSP-2162/
ADSP-2163/ADSP-2164
ADSP-2165/ADSP-2166
Custom ROM-programmed DSPs:
ROM-programmed ADSP-216x
processors with power-down and
larger on-chip memories (12K Program Memory ROM, 1K Program
Memory RAM, 4K Data Memory
RAM)
DSP Microcomputers with ROM
ADSP-216x
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
MEMORY
PROGRAM
SEQUENCER
PROGRAM
MEMORY
DATA
MEMORY
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
EXTERNAL
DATA
BUS
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC
SHIFTER
SERIAL PORTS
EXTERNAL
ADDRESS
BUS
TIMER
SPORT 0 SPORT 1
ADSP-2100 CORE
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-216x processors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and comprehensive instruction set support a high degree of parallelism.
In one cycle the ADSP-216x can␣ perform␣ all of␣ the␣ following
operations:
•␣ Generate the next program address
•␣ Fetch the next instruction
•␣ Perform one or two data moves
•␣ Update one or two data address pointers
•␣ Perform a computation
•␣ Receive and transmit data via one or two serial ports
Table I shows the features of each ADSP-216x processor.
The ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. These devices offer different
amounts of on-chip memory for program and data storage.
Table I shows the features available in the ADSP-216x series of
custom ROM-coded processors.
The ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire application program in on-chip ROM. These devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADSP-216x
TABLE OF CONTENTS
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING PARAMETERS
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . .
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . .
CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . .
INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . .
BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . .
MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING PARAMETERS
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . .
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . .
CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . .
INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . . .
BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . .
MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONFIGURATIONS
68-Lead PLCC (ADSP-216x) . . . . . . . . . . . . . . . . . . . . .
80-Lead MQFP (ADSP-216x) . . . . . . . . . . . . . . . . . . . . .
PACKAGE OUTLINE DIMENSIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 3
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Entering Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Exiting Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 10
ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Procedure for ADSP-216x ROM Processors . . . . 10
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPECIFICATIONS–RECOMMENDED OPERATING
CONDITIONS
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 13
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 13
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 13
SPECIFICATIONS–SUPPLY CURRENT AND POWER
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 14
POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 15
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 15
CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 15
SPECIFICATIONS–
␣ ␣ (ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 16
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPECIFICATIONS–RECOMMENDED OPERATING
CONDITIONS
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 17
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 17
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17
SPECIFICATIONS–SUPPLY CURRENT AND POWER
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 18
POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 19
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 19
CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 19
–2–
20
20
20
21
21
21
21
22
23
24
25
26
27
28
28
28
28
29
30
31
32
33
34
35
36
37
38
39
REV. 0
ADSP-216x
Table I. ADSP-216x ROM-Programmed Processor Features
Feature
2161
2162
2163
2164
2165
2166
Data Memory (RAM)
Program Memory (ROM)
Program Memory (RAM)
Timer
Serial Port 0 (Multichannel)
Serial Port 1
Supply Voltage
Speed Grades (Instruction Cycle Time)
10.24 MHz (97.6 ns)
13.00 MHz (76.9 ns)
16.67 MHz (60 ns)
20.00 MHz (50 ns)
25 MHz (40 ns)
Packages
68-Lead PLCC
80-Lead MQFP
Temperature Grades
K Commercial, 0°C to +70°C
B Industrial, –40°C to +85°C
1/2K
8K
1/2K
8K
1/2K
4K
1/2K
4K
4K
12K
1K
4K
12K
1K
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5V
3.3 V
5V
3.3 V
5V
3.3 V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Development Tools
ARCHITECTURE OVERVIEW
The ADSP-216x processors are supported by a complete set of
tools for system development. The ADSP-2100 Family Development Software includes C and assembly language tools that
allow programmers to write code for any of the ADSP-216x
processors. The ANSI C compiler generates ADSP-216x assembly source code, while the runtime C library provides ANSIstandard and custom DSP library routines. The ADSP-216x
assembler produces object code modules that the linker combines into an executable file. The processor simulators provide
an interactive instruction-level simulation with a reconfigurable,
windowed user interface. A PROM splitter utility generates
PROM programmer compatible files.
Figure 1 shows a block diagram of the ADSP-216x architecture.
The processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract operations. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The
shifter can be used to efficiently implement numeric format control
including multiword floating-point representations.
EZ-ICE® in-circuit emulators allow debugging of ADSP-21xx
systems by providing a full range of emulation functions such
as modification of memory and register values and execution
breakpoints. EZ-LAB® demonstration boards are complete DSP
systems that execute EPROM-based programs.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-216x executes looped code with zero
overhead—no explicit jump instructions are required to maintain the loop.
The EZ-Kit Lite is a very low-cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Additional details and ordering information are available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) onchip memory.
Additional Information
This data sheet provides a general overview of ADSP-216x
processor functionality. For detailed design information on the
architecture and instruction set, refer to the ADSP-2100 Family
User’s Manual, Third Edition, available from Analog Devices.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
REV. 0
–3–
ADSP-216x
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
PROGRAM
MEMORY
DATA
MEMORY
SRAM
& ROM
SRAM
PROGRAM
SEQUENCER
16
24
14 PMA BUS
BOOT
ADDRESS
GENERATOR
PMA BUS
14
EXTERNAL
ADDRESS
BUS
MUX
DMA BUS
14 PMA BUS
TIMER
PMD BUS
24 PMA BUS
24
BUS
EXCHANGE
EXTERNAL
DATA
BUS
MUX
16 PMA BUS
DMD BUS
16
INPUT REGS
INPUT REGS
INPUT REGS
ALU
MAC
SHIFTER
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
SERIAL
PORT 1
16
R BUS
5
5
Figure 1. ADSP-216x Block Diagram
Efficient data transfer is achieved with the use of five internal
buses:
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
•
•
•
•
•
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS and PMS signals indicate which memory space
is using the external buses.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Program memory can store both instructions and data, permitting the ADSP-216x to fetch two operands in a single cycle,
one from program memory and one from data memory. The
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
Serial Ports
The memory interface supports slow memories and memorymapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of operation are available. Each SPORT can generate an internal programmable serial clock or accept an external serial clock.
One bus grant execution mode (GO Mode) allows the ADSP216x to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-216x processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. There is also a master
RESET signal.
The ADSP-216x processors include two synchronous serial
ports (SPORTs) for serial communications and multiprocessor
communication. All of the ADSP-216x processors have two
serial ports (SPORT0, SPORT1).
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
Function
SCLK
RFS
TFS
DR
DT
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
Transmit Frame Synchronization (I/O)
Serial Data Receive
Serial Data Transmit
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2161 to use a 200 ns EPROM as
–4–
REV. 0
ADSP-216x
The ADSP-216x uses a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
received. Interrupts can be optionally nested so that a higher
priority interrupt can preempt the currently executing interrupt
service routine. Each interrupt vector location is four instructions in length so that simple service routines can be coded
entirely in this space. Longer service routines require an additional JUMP or CALL instruction.
The ADSP-216x serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
Flexible Framing—The SPORTs have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals internally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulsewidths and
timings.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on Bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
Different Word Lengths—Each SPORT supports serial data
word lengths from 3 to 16 bits.
Companding in Hardware—Each SPORT provides optional
A-law and µ-law companding according to CCITT recommendation G.711.
Flexible Interrupt Scheme—Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
The interrupt force and clear register, IFC, is a write-only register that contains a force bit and a clear bit for each interrupt.
When responding to an interrupt, the ASTAT, MSTAT and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep to allow interrupt nesting.
The stack is automatically popped when a return from the interrupt instruction is executed.
Autobuffering with Single-Cycle Overhead—Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Multichannel Capability (SPORT0 Only)—SPORT0 provides a multichannel interface to selectively receive or transmit a
24-word or 32-word, time-division multiplexed serial bit stream;
this feature is especially useful for T1 or CEPT interfaces, or as
a network communication scheme for multiple processors.
Pin Definitions
Pin Function Descriptions show pin definitions for the ADSP216x processors. Any inputs not used must be tied to VDD.
SYSTEM INTERFACE
Alternate Configuration—SPORT1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
Figure 3 shows a typical system for the ADSP-216x with two
serial I/O devices, an optional external program and data
memory. A total of 12K words of data memory and 15K words
of program memory is addressable.
Interrupts
The ADSP-216x’s interrupt controller lets the processor respond to interrupts with a minimum of overhead. Up to three
external interrupt input pins, IRQ0, IRQ1 and IRQ2, are provided. IRQ2 is always available as a dedicated pin; IRQ1 and
IRQ0 may be alternately configured as part of Serial Port 1. The
ADSP-216x also supports internal interrupts from the timer and
the serial ports. The interrupts are internally prioritized and
individually maskable (except for RESET which is nonmaskable).
The IRQx input pins can be programmed for either level- or
edge-sensitivity. The interrupt priorities for each ADSP-216x
processor are shown in Table II.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
The ADSP-216x processors also provide either: one external
interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT0).
Clock Signals
The ADSP-216x processors’ CLKIN input may be driven by a
crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
Table II.␣ Interrupt Vector Addresses and Priority
ADSP-216x Interrupt Source
Interrupt
Vector Address
RESET Startup
IRQ2 or Power-Down
SPORT0 Transmit
SPORT0 Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
0x0014
0x0018 (Low Priority)
REV. 0
If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
Because the ADSP-216x processors include an on-chip oscillator circuit, an external crystal may also be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in Figure 2. A parallelresonant, fundamental frequency, microprocessor-grade crystal
should be used.
–5–
ADSP-216x
CLKIN
XTAL
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 tCK cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulsewidth specification, tRSP.
CLKOUT
ADSP-216x
Figure 2. External Crystal Connections
A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor’s internal cycles.
To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
Reset
The RESET signal initiates a complete reset of the ADSP-216x.
The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the chip
is configured for booting, with MMAP = 0). The first instruction is
then fetched from internal program memory location 0x0000.
PIN FUNCTION DESCRIPTIONS
Pin
Name(s)
# of
Pins
Input/
Output
Address
Data1
14
24
O
I/O
RESET
IRQ2
BR2
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN, XTAL
CLKOUT
VDD
GND
SPORT0
SPORT1
or Interrupts and Flags:
IRQ0 (RFS1)
IRQ1 (TFS1)
FI (DR1)
FO (DT1)
PWDACK3
PWDFLAG3
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
I
O
5
5
I/O
I/O
1
1
1
1
1
1
I
I
I
O
O
I
Function
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request #2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
Ground Pins
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
External Interrupt Request #0
External Interrupt Request #1
Flag Input Pin
Flag Output Pin
Indicates when the processor has entered power-down.
Low-to-High Transition of the Power-Down Flag. Input pin can
be used to terminate power-down.
NOTES
1
Unused data bus lines may be left floating.
2
BR must be tied high (to V DD) if not used.
3
Only on ADSP-2165/ADSP-2166.
–6–
REV. 0
ADSP-216x
ADSP-2165/ADSP-2166
CLOCK OR
CRYSTAL
CLKIN
XTAL
CLKOUT
3
4
VDD
GND
SERIAL
PORT 0
RESET
IRQ2
ADSP-216x
BR
SCLK
RFS
TFS
DT
DR
When MMAP = 0, on-chip program memory ROM occupies
12K words beginning at address 0x0000. Internal program
memory RAM occupies 1K words beginning at address 0x3000.
Off-chip program memory uses the 2K words beginning at
address 0x3800. The ADSP-2165/ADSP-2166 does not support
boot memory.
SERIAL
DEVICE
(OPTIONAL)
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 10K words of on-chip program memory
ROM at 0x800 to 0x2FFF, and the remainder 2K words of
program memory ROM is at 0x3800 to 0x3FFF. Internal program memory RAM occupies 1K words at address 0x300 to
0x33FF.
SCLK
RFS OR IRQ0
BG
SERIAL
PORT 1
MMAP
PMS
RD RW ADDRESS DATA DMS BMS
14
TFS OR IRQ1
DT OR FO
SERIAL
DEVICE
(OPTIONAL)
DR OR FI
2K
EXTERNAL
D23-8
16
A D CS
OE
WE
PROGRAM
MEMORY
(OPTIONAL)
A
OE
D
0x0000
0x0000
24
0x07FF
0x0800
12K 3 24
INTERNAL
ROM
CS
10K 3 24
INTERNAL
ROM
WE
DATA
MEMORY
&
PERIPHERALS
0x2FFF
0x3000
0x2FFF
0x3000
1K 3 24 RAM
1K 3 24 RAM
0x33FF
0x3400
0x33FF
0x3400
Figure 3. Basic System Configuration
RESERVED
RESERVED
Program Memory Interface
2K 3 24
EXTERNAL
The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the onchip data memory buses (DMA, DMD), creating a single external data bus and a single external address bus. The external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
0x37FF
0x3800
0x3FFF
MMAP = 0
2K 3 24
INTERNAL
ROM
0x37FF
0x3800
0x3FFF
MMAP = 1
Figure 4. ADSP-2165/ADSP-2166 Program Memory Maps
ADSP-2161/ADSP-2162
When MMAP = 0, on-chip program memory ROM occupies
8K words beginning at address 0x0000. Off-chip program
memory uses the remaining 8K words beginning at address
0x2000.
The external address bus is 14 bits wide. For the ADSP-216x,
these lines can directly address up to 16K words, of which 2K
are on-chip.
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 6K words of on-chip program memory ROM
are at 0x0800 to 0x1FF0, and the remainder 2K words of program memory ROM is at 0x3800 to 0x3FFF. An additional 6K
of off-chip program memory is at 0x2000 to 0x37FF.
The data lines are bidirectional. The program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. The write (WR) signal indicates a
write operation and is used as a write strobe. The read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
0x0000
0x0000
2K
EXTERNAL
The ADSP-216x processors write data from their 16-bit registers to 24-bit program memory using the PX register to provide
the lower eight bits. When the processor reads 16-bit data from
24-bit program memory to a 16-bit data register, the lower eight
bits are placed in the PX register.
0x7FFF
0x0800
8K
INTERNAL
ROM
6K
INTERNAL
ROM
0x1FF0
0x1FF0
RESERVED
The program memory interface can generate 0 to 7 wait states for
external memory devices; default is to 7 wait states after RESET.
RESERVED
0x1FFF
0x2000
0x1FFF
0x2000
Program Memory Maps
6K
EXTERNAL
8K
EXTERNAL
Program memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 4 shows the program memory
map for the ADSP-2165/ADSP-2166. Figures 5 and 6 show the
program memory maps for the ADSP-2161/ADSP-2162 and
ADSP-2163/ADSP-2164, respectively.
0x3FFF
MMAP = 0
2K
INTERNAL
ROM
0x37FF
0x3800
0x3FFF
MMAP = 1
Figure 5. ADSP-2161/ADSP-2162 Program Memory Maps
REV. 0
–7–
ADSP-216x
ADDRESS (HEX)
ADSP-2163/ADSP-2164
0x0000
When MMAP = 0, on-chip program memory ROM occupies
4K words beginning at address 0x0000. Off-chip program
memory uses the remaining 12K words beginning at address
0x1000.
1K EXTERNAL
DWAIT0
0x0400
EXTERNAL
RAM
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 2K words of on-chip program memory ROM
is at 0x0800 to 0x0FF0, and the remainder 2K words of program memory ROM is at 0x3800 to 0x3FFF. An additional
10K of off-chip program memory is at 0x1000 to 0x37FF.
0x0000
0x2000
4K 3 16 INTERNAL
0x0000
0x0FF0
RESERVED
2K
INTERNAL
ROM
INTERNAL
RAM
0x07FF
0x0800
0x0FF0
0x0FFF
0x1000
0x3FFF
Figure 7. ADSP-2165/ADSP-2166 Data Memory Map
10K
EXTERNAL
12K
EXTERNAL
0x3FFF
MMAP = 0
0x3000
4K 3 16
MEMORY-MAPPED
REGISTERS
& RESERVED
RESERVED
0x0FFF
0x1000
0x0800
6K EXTERNAL
DWAIT2
2K
EXTERNAL
4K
INTERNAL
ROM
1K EXTERNAL
DWAIT1
2K
INTERNAL
ROM
ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164
For the ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164, onchip data memory RAM resides in the 512 words beginning at
address 0x3800, also shown in Figure 8. Data memory locations
from 0x3A00 to the end of data memory at 0x3FFF are reserved.
Control and status registers for the system, timer, wait-state
configuration, and serial port operations are located in this
region of memory.
0x37FF
0x3800
0x3FFF
MMAP = 1
Figure 6. ADSP-2163/ADSP-2164 Program Memory Maps
Data Memory Interface
The data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
ADDRESS (HEX)
0x0000
1K EXTERNAL
DWAIT0
0x0400
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
1K EXTERNAL
DWAIT1
0x0800
EXTERNAL
RAM
10K EXTERNAL
DWAIT2
The ADSP-216x processors support memory-mapped I/O, with
the peripherals memory-mapped into the data memory address
space and accessed by the processor in the same manner as data
memory.
0x3000
1K EXTERNAL
DWAIT3
0x3400
1K EXTERNAL
DWAIT4
Data Memory Map
0x3800
512
ADSP-2161/62/63/64
For the ADSP-2165/ADSP-2166, on-chip data memory RAM
resides in the 4K words beginning at address 0x2000, as shown
in Figure 7. Data memory locations from 0x3000 to the end of
data memory at 0x3FFF are reserved. Control and status registers for the system, timer, wait-state configuration, and serial port
operations are located in this region of memory.
0x3A00
0x3C00
INTERNAL
RAM
MEMORY-MAPPED
CONTROL REGISTERS
& RESERVED
0x3FFF
The remaining 8K of data memory is located off-chip. This
external data memory is divided into three zones, each associated with its own wait-state generator. This allows slower peripherals to be memory-mapped into data memory for which
wait states are specified. By mapping peripherals into different
zones, you can accommodate peripherals with different waitstate requirements. All zones default to 7 wait states after
RESET.
Figure 8. ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164
Data Memory Map
The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state requirements. All zones default to seven wait states after RESET.
–8–
REV. 0
ADSP-216x
• Low-to-high transition of the power-down flag input pin
(PWDFLAG) can be used to terminate power-down.
Bus Interface
The ADSP-216x processors can relinquish control of their data
and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the ADSP-216x is not performing an external
memory access, it responds to the active BR input in the next
cycle by:
• The RESET pin also can also be used to terminate
power-down.
Power-Down Control
• Three-stating the data and address buses and the PMS,
DMS, BMS, RD, WR output drivers,
Several parameters of power-down operation can be controlled
through control bits of the “power-down/sportl autobuffer control register.” This control register is memory-mapped at location 0x3FEF and the power-down control bits are as follows:
• Asserting the bus grant (BG) signal, and halting program
execution.
bit[15] xtal: xtal pin disable during power-down
1 = disabled, 0 = enable (default)
If the Go mode is set, however, the ADSP-216x will not halt
program execution until it encounters an instruction that
requires an external memory access.
bit[14] pwdflag: (read only )
when pwdena = 1, the value of bit [14] pwdflag is equal to the
status of the pwdflag input pin.
If the ADSP-216x is performing an external memory access
when the external device asserts the BR signal, it will not threestate the memory interfaces or assert the BG signal until the
cycle after the access completes (up to eight cycles later depending on the number of wait states). The instruction does not need
to be completed when the bus is granted; the ADSP-21xx will
grant the bus between two memory accesses if an instruction
requires more than one external memory access.
bit[13] pwdena: power-down enable
1 = enable, 0 = disable (default)
if pwdena is set to 0, then the output pin PWDACK is driven
low and the input pin PWDFLAG is disabled
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point at which it stopped.
bit[12] pucr: power-up context reset
1 = soft reset, 0 = resume execution (default)
The bus request feature operates at all times, including when the
processor is booting and when RESET is active. If this feature is
not used, the BR input should be tied high (to VDD).
The power-down sequence is defined as follows:
POWER-DOWN
Note: In order to power-down, the PWDENA bit must be set
before the IRQ2 interrupt is initiated.
when pwdena = 0, the value of bit [14] pwdflag is equal to 0.
Note: It is not recommended that power-down enable be set or
cleared during an IRQ2 interrupt.
Entering Power-Down
• Enable power-down logic by setting the pwdena bit in the
power-down/sportl autobuffer control register.
The ADSP-2165/ADSP-2166 processors have a low power
feature that lets the processor enter a very low power dormant
state through hardware or software control. A list of powerdown features follows:
• Initiate the power-down sequence by generating an IRQ2
interrupt either externally or by software use of the IFC
register.
• Processor registers and on-chip memory contents are maintained during power-down.
• The processor vectors to the IRQ2 interrupt vector located at
0x0004.
• Power-down mode holds the processor in CMOS standby
with a maximum current of less than 100 µA in some modes.
• Any number of housekeeping instructions, starting at location 0x0004 can be executed prior to the processor entering
the power-down mode.
• Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during
power-down without affecting the lowest power rating.
• The processor enters the power-down mode when the processor executes an IDLE instruction while executing the
IRQ2 interrupt routine.
• Support for crystal operation includes disabling the oscillator
to save power. (The processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabilize).
Notes:
• If an RTI instruction is executed before the processor encounter an IDLE instruction, then the processor returns
from the IRQ2 interrupt and the power-down sequence is
aborted.
• When power-down mode is enabled, powering down of the
processor can be initiated either by externally generated
IRQ2 interrupt or by using the IRQ2 force bit in the IFC
register.
• The user can differentiate between a “normal” IRQ2 interrupt and a “power-down” IRQ2 interrupt by resetting the
PWDFLAG pin and checking the status of this pin by testing
the PWDFLAG bit in the power-down/SPORT1 autobuffer
control register located at DM[0x3FEF].
• Power-Down Acknowledge Pin (PWDACK) indicates when
the processor has entered power-down.
• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
REV. 0
–9–
ADSP-216x
Exiting Power-Down
ADSP-216x Prototyping
The power-down mode can be exited with the use of the
PWDFLAG or RESET pin. Applying a low-to-high transition to
the PWDFLAG pin takes the processor out of power-down
mode. In this case, a delay of 4096 cycles is automatically induced by the processor. Also, depending on the status of the
power-up context reset bit (pucr), the processor either
You can prototype your ADSP-216x system with either ADSP2101 or ADSP-2103 RAM-based processors. When code is fully
developed and debugged, it can be submitted to Analog Devices
for conversion into an ADSP-216x ROM product.
1) continues to execute instructions following the IDLE instruction that caused the power-down. A RTI instruction is required to pass control back to the main routine (pucr = 0)
or
2) resumes operation from power-down by clearing the PC,
STATUS, LOOP and CNTR stack. The IMASK and
ASTAT registers are set to 0 and the SSTAT goes to 0x55.
The processor then starts executing instructions from the
address zero (pucr = 1).
Additional overlay memory is used for emulation of ADSP2161/ADSP-2162 systems. It should be noted that due to the
use of off-chip overlay memory to emulate the ADSP-2161/
ADSP-2162, a performance loss may be experienced when both
executing instructions and fetching program memory data from
the off-chip overlay memory in the same cycle. This can be
overcome by locating program memory data in on-chip memory.
Ordering Procedure for ADSP-216x ROM Processors
In the case where the power-down mode is exited by asserting
the RESET pin, the processor state is reset and instruction are
executed from address 0x0000. The RESET pin in this case
must be held low long enough for the external crystal (if any)
and the on-chip PLL to stabilize and lock.
To place an order for a custom ROM-coded ADSP-2161,
ADSP-2162, ADSP-2163, ADSP-2164 , ADSP-2165 or ADSP2166 processor, you must:
Low Power IDLE Instruction
The IDLE instruction places the ADSP-216x processor in low
power state in which it waits for an interrupt. When an interrupt
occurs, it is serviced and execution continues with instruction
following IDLE. Typically this next instruction will be a JUMP
back to the IDLE instruction. This implements a low power
standby loop.
The IDLE n instruction is a special version of IDLE that slows
the processor’s internal clock signal to further reduce power
consumption. The reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. The syntax of the
instruction is:
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-216x ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Preproduction ROM Products
2. Return the forms to Analog Devices along with two copies of the
Memory Image File (.EXE file) of your ROM code. The files must
be supplied on two 3.5" or 5.25" floppy disks for the IBM PC
(DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for nonrecurring
engineering changes (NRE) associated with ROM product
development.
IDLE n;
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
where n = 16, 32, 64 or 128.
The instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT, and the timer
clock, are reduced by the same ratio. Upon receipt of an enabled interrupt, the processor will stay in the IDLE state for up
to a maximum of n CLKIN cycles, where n is the divisor specified in the instruction, before resuming normal operation.
When the IDLE n instruction is used, it slows the processor’s
internal clock and thus its response time to incoming interrupts–
the 1-cycle response time of the standard IDLE state is increased
by n, the clock divisor. When an enabled interrupt is received,
the ADSP-216x will remain in the IDLE state for up to a maximum of n CLKIN cycles (where n = 16, 32, 64 or 128) before
resuming normal operation.
When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of n
CLKIN cycles).
The ADSP-2101 EZ-ICE emulator can be used for development
of ADSP-216x systems. For the 3.3 V ADSP-2162/ADSP-2164
and ADSP-2166, a voltage converter interface board provides
3.3 V emulation.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
A signed ROM Verification Form and a purchase order for
production units are required prior to any product being manufactured. Prototype units may be applied toward the minimum
order quantity.
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.
There is a charge for each ROM mask generated and a minimum order quantity. Consult your sales representative for details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
–10–
REV. 0
ADSP-216x
Instruction Set
The ADSP-216x assembly language uses an algebraic syntax for
ease of coding and readability. The sources and destinations of
computations and data movements are written explicitly in each
assembly statement, eliminating cryptic assembler mnemonics.
parallelism. There are five basic categories of instructions: data
move instructions, computational instructions, multifunction
instructions, program flow control instructions and miscellaneous instructions. Multifunction instructions perform one or
two data moves and a computation.
Every instruction assembles into a single 24-bit word and executes
in a single cycle. The instructions encompass a wide variety of
instruction types along with a high degree of operational
The instruction set is summarized below. The ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.
ALU Instructions
[IF cond]
AR|AF =
=
=
=
=
=
=
=
=
=
=
=
=
=
xop + yop [+ C] ;
xop – yop [+ C– 1] ;
yop – xop [+ C– 1] ;
xop AND yop ;
xop OR yop ;
xop XOR yop ;
PASS xop ;
– xop ;
NOT xop ;
ABS xop ;
yop + 1 ;
yop – 1 ;
DIVS yop, xop ;
DIVQ xop ;
Add/Add with Carry
Subtract X – Y/Subtract X – Y with Borrow
Subtract Y – X/Subtract Y – X with Borrow
AND
OR
XOR
Pass, Clear
Negate
NOT
Absolute Value
Increment
Decrement
Divide
xop * yop ;
MR + xop * yop ;
MR – xop * yop ;
MR ;
0;
Multiply
Multiply/Accumulate
Multiply/Subtract
Transfer MR
Clear
Conditional MR Saturation
MAC Instructions
[IF cond]
IF MV
MR|MF =
=
=
=
=
SAT MR ;
Shifter Instructions
[IF cond]
[IF cond]
[IF cond]
[IF cond]
[IF cond]
SR = [SR OR] ASHIFT xop ;
SR = [SR OR] LSHIFT xop ;
SR = [SR OR] ASHIFT xop BY <exp>;
SR = [SR OR] LSHIFT xop BY <exp>;
SE = EXP xop ;
SB = EXPADJ xop ;
SR = [SR OR] NORM xop ;
Arithmetic Shift
Logical Shift
Arithmetic Shift Immediate
Logical Shift Immediate
Derive Exponent
Block Exponent Adjust
Normalize
Data Move Instructions
reg = reg ;
reg = <data> ;
reg = DM (<addr>) ;
dreg = DM (Ix , My) ;
dreg = PM (Ix , My) ;
DM (<addr>) = reg ;
DM (Ix , My) = dreg ;
PM (Ix , My) = dreg ;
Register-to-Register Move
Load Register Immediate
Data Memory Read (Direct Address)
Data Memory Read (Indirect Address)
Program Memory Read (Indirect Address)
Data Memory Write (Direct Address)
Data Memory Write (Indirect Address)
Program Memory Write (Indirect Address)
Multifunction Instructions
<ALU>|<MAC>|<SHIFT> , dreg = dreg ;
<ALU>|<MAC>|<SHIFT> , dreg = DM (Ix , My) ;
<ALU>|<MAC>|<SHIFT> , dreg = PM (Ix , My) ;
DM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;
PM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;
dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
<ALU>|<MAC> , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
REV. 0
–11–
Computation with Register-to-Register Move
Computation with Memory Read
Computation with Memory Read
Computation with Memory Write
Computation with Memory Write
Data & Program Memory Read
ALU/MAC with Data & Program Memory Read
ADSP-216x
Program Flow Instructions
DO <addr> [UNTIL term] ;
[IF cond] JUMP (Ix) ;
[IF cond] JUMP <addr>;
[IF cond] CALL (Ix) ;
[IF cond] CALL <addr>;
IF [NOT ] FLAG_IN
JUMP <addr>;
IF [NOT ] FLAG_IN
CALL <addr>;
[IF cond] SET|RESET|TOGGLE
FLAG_OUT [, ...] ;
[IF cond] RTS ;
[IF cond] RTI ;
IDLE [(n)] ;
Do Until Loop
Jump
Call Subroutine
Jump/Call on Flag In Pin
Modify Flag Out Pin
Return from Subroutine
Return from Interrupt Service Routine
Idle
Miscellaneous Instructions
NOP ;
MODIFY (Ix , My);
[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;
ENA|DIS
SEC_REG [, ...] ;
BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE
No Operation
Modify Address Register
Stack Control
Mode Control
Notation Conventions
Ix
My
<data>
<addr>
<exp>
<ALU>
<MAC>
<SHIFT>
cond
term
dreg
reg
;
,
[
]
[, ...]
option1 | option2
Index registers for indirect addressing
Modify registers for indirect addressing
Immediate data value
Immediate address value
Exponent (shift value) in shift immediate instructions (8-bit signed number)
Any ALU instruction (except divide)
Any multiply-accumulate instruction
Any shift instruction (except shift immediate)
Condition code for conditional instruction
Termination code for DO UNTIL loop
Data register (of ALU, MAC, or Shifter)
Any register (including dregs)
A semicolon terminates the instruction
Commas separate multiple operations of a single instruction
Optional part of instruction
Optional, multiple operations of an instruction
List of options; choose one.
Assembly Code Example
The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
MF=MX0*MY1(RND), MX0=DM(I2,M1);
{MF=error*beta}
MR=MX0*MF(RND), AY0=PM(I6,M5);
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt:
PM(I6,M6)=AR, MR=MX0*MF(RND);
MODIFY(I2,M3);
MODIFY(I6,M7);
{Point to oldest data}
{Point to start of data}
–12–
REV. 0
ADSP-216x
SPECIFICATIONS
ADSP-2161/ADSP-2163/ADSP-2165–RECOMMENDED OPERATING CONDITIONS
Parameter
Min
K Grade
Max
Min
B Grade
Max
VDD
TAMB
4.50
0
5.50
+70
4.50
–40
5.50
+85
Supply Voltage
Ambient Operating Temperature
Unit
V
°C
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter
1, 2
VIH
VIH
VIL
VOH
Hi-Level Input Voltage
Hi-Level CLKIN and Reset Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
IIH
IIL
IOZH
IOZL
CI
CO
Lo-Level Output Voltage1, 4, 5
Hi-Level Input Current3
Lo-Level Input Current3
Three-State Leakage Current7
Three-State Leakage Current7
Input Pin Capacitance3, 6, 9
Output Pin Capacitance6, 7, 9, 10
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOH = –100 µA6
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max8
@ VDD = max, VIN = 0 V8
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
2.0
2.2
Max
Unit
V
V
V
V
V
V
µA
µA
µA
µA
pF
pF
0.8
2.4
VDD – 0.3
0.4
10
10
10
10
8
8
NOTES
1
Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.
2
Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0.
3
Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.
4
Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.
5
Although specified for TTL outputs, all ADSP-21xx outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6
Guaranteed but not tested.
␣7
Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RFS1, TFS1, DT0, SCLK0, RFS0, TFS0.
8
0 V on BR, CLKIN Active (to force three-state condition).
9
Applies to PLCC, MQFP package types.
10
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . –40°C to +85°C
(No Extended Temperature Range)
Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300ºC
Lead Temperature (5 sec) PLCC, MQFP, TQFP . . . . +280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-216x features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–13–
WARNING!
ESD SENSITIVE DEVICE
ADSP-216x
SPECIFICATIONS
ADSP-2161/ADSP-2163/ADSP-2165–SUPPLY CURRENT AND POWER
Parameter
Test Conditions
1
IDD
Supply Current (Dynamic)
IDD
Supply Current (Idle)1, 3
Min
2
@ VDD = max, tCK = 40 ns
@ VDD = max, tCK = 50 ns2
@ VDD = max, tCK = 60 ns2
@ VDD = max, tCK = 40 ns
@ VDD = max, tCK = 50 ns
@ VDD = max, tCK = 60 ns
Max
Unit
38
31
27
12
11
10
mA
mA
mA
mA
mA
mA
NOTES
1
Current reflects device operating with no output loads.
2
VIN = 0.4 V and 2.4 V.
3
Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
For typical supply current (internal power dissipation) figures, see Figure 9.
Specifications subject to change without notice.
IDD DYNAMIC1
220
205mW
200
POWER – mW
180
VDD = 5.5V
160
157mW
140
120
100
129mW
VDD = 5.0V
118mW
100mW
VDD = 4.5V
80
74mW
60
10.00
13.83
20.00
25.00
FREQUENCY – MHz
30.00
IDD IDLE1,2
70
IDD IDLE n MODES3
65
64mW
64mW
60
60
VDD = 5.5V
POWER – mW
40
38mW
30
28mW
IDD IDLE
49mW
VDD = 5.0
35mW
VDD = 4.5V
55
POWER – mW
51mW
50
50
45
IDLE 16
20
40
10
35
0
10.00
13.83
20.00
25.00
FREQUENCY – MHz
30
10.00
30.00
51mW
41mW
40mW
43mW
42mW
IDLE 128
13.83
20.00
25.00
FREQUENCY – MHz
30.00
VALID FOR ALL TEMPERATURE GRADES.
REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2IDLE REFERS TO ADSP-216x OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3MAXIMUM POWER DISSIPATION AT V
DD = 5.5V DURING EXECUTION OF IDLE n INSTRUCTION.
1POWER
Figure 9. ADSP-2161/ADSP-2163/ADSP-2165 (Typical) vs. Frequency
–14–
REV. 0
ADSP-216x
ADSP-2161/ADSP-2163/ADSP-2165
POWER DISSIPATION EXAMPLE
CAPACITIVE LOADING
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
Figures 10 and 11 show capacitive loading characteristics for the
ADSP-2161/ADSP-2163/ADSP-2165.
C × VDD2 ×␣ f
8
C = load capacitance,␣ f␣ = output switching frequency.
7
RISE TIME (0.4V – 2.0V) – ns
Example:
In an ADSP-2161 application where external data memory is
used and no other outputs are active, power dissipation is calculated as follows:
Assumptions:
• External data memory is accessed every cycle with 50% of
the address pins switching.
• External data memory writes occur every other cycle with
50% of the data pins switching.
6
VDD = 4.5V
5
4
3
2
1
• Each address and data pin has a 10 pF total load at the pin.
0
• The application operates at VDD = 5.0 V and tCK = 50 ns.
0
25
50
75
100
CL – pF
125
150
175
Figure 10. Typical Output Rise Time vs. Load Capacitance, CL
(at Maximum Ambient Operating Temperature)
Total Power Dissipation = PINT + (C × VDD2 ×␣ f )
PINT = internal power dissipation (from Figure 9).
(C × VDD2 × f ) is calculated for each output:
Address, DMS
Data, WR
RD
CLKOUT
8
9
1
1
× 10 pF
× 10 pF
× 10 pF
× 10 pF
ⴛ VDD2 ⴛ f
× 52 V
× 52 V
× 52 V
× 52 V
× 20 MHz
× 10 MHz
× 10 MHz
× 20 MHz
Total power dissipation for this example = PINT
= 40.0
= 22.5
= 2.5
= 5.0
mW
mW
mW
mW
70.0 mW
+ 70.0 mW.
ENVIRONMENTAL CONDITIONS
4
3
VDD = 4.5V
2
1
0
–1
–2
–3
Ambient Temperature Rating:
␣ ␣ TAMB = TCASE – (PD × θCA)
␣ ␣ TCASE = Case Temperature in °C
␣ ␣ PD = Power Dissipation in W
␣ ␣ θCA = Thermal Resistance (Case-to-Ambient)
␣ ␣ θJA = Thermal Resistance (Junction-to-Ambient)
␣ ␣ θJC = Thermal Resistance (Junction-to-Case)
0
25
50
75
100
CL – pF
125
150
175
Figure 11. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
Package
JA
JC
CA
PLCC
MQFP
27°C/W
60°C/W
16°C/W
18°C/W
11°C/W
42°C/W
REV. 0
VALID OUTPUT DELAY OR HOLD – ns
Output
# of
Pins ⴛ C
5
–15–
ADSP-216x
SPECIFICATIONS
ADSP-2161/ADSP-2163/ADSP-2165
TEST CONDITIONS
Output Enable Time
Figure 12 shows voltage reference levels for ac measurements.
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 13. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
INPUT
3.0V
1.5V
0.0V
OUTPUT
2.0V
1.5V
0.8V
Figure 12.␣ Voltage␣ Reference␣ Levels for AC Measurements
(Except Output Enable/Disable)
REFERENCE
SIGNAL
tMEASURED
tENA
VOH
(MEASURED)
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in Figure 13. The time tMEASURED is the interval from
when a reference signal reaches a high or low voltage level to
when the output voltages have changed by 0.5 V from the measured output high or low voltage.
OUTPUT
VOH
(MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
VOL
(MEASURED)
VOL
(MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 13. Output Enable/Disable
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be approximated by the following equation:
t DECAY =
tDIS
IOL
CL × 0.5V
iL
from which
TO
OUTPUT
PIN
tDIS = t MEASURED – t DECAY
+1.5V
50pF
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
IOH
Figure 14. Equivalent Device Loading for AC
Measurements (Except Output Enable/Disable)
–16–
REV. 0
ADSP-216x
ADSP-2162/ADSP-2164/ADSP-2166–RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Ambient Operating Temperature
VDD
TAMB
K Grade
Min
Max
B Grade
Min
Max
Unit
3.00
0
3.00
–40
V
°C
3.60
+70
3.60
+85
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIL
VOH
VOL
IIH
IIL
IOZH
IOZL
CI
CO
1, 2
Hi-Level Input Voltage
Hi-Level CLKIN and Reset Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 4
Lo-Level Output Voltage2, 3, 4
Hi-Level Input Current3
Lo-Level Input Current3
Three-State Leakage Current5
Three-State Leakage Current5
Input Pin Capacitance1, 7, 8
Output Pin Capacitance2, 7, 8, 9
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min, IOH = –0.5 mA4
@ VDD = min, IOL = 2 mA4
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max6
@ VDD = max, VIN = 0 V6
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
2.0
2.2
0.4
2.4
NOTES
1
Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.
2
Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.
3
Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.
4
All ADSP-2162, ADSP-2164 and ADSP-2166 outputs are CMOS and will drive to V DD and GND with no dc loads.
5
Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RFS1, TFS1, DT0, SCLK0, RFS0, TFS0.
6
0 V on BR, CLKIN Active (to force three-state condition).
7
Guaranteed but not tested.
8
Applies to PLCC and MQFP package types.
9
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.5 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . –40ºC to +85ºC
Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (5 sec) PLCC, MQFP . . . . . . . . . . +280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at
these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
REV. 0
–17–
Max
0.4
10
10
10
10
8
8
Unit
V
V
V
V
V
µA
µA
µA
µA
pF
pF
ADSP-216x
SPECIFICATIONS
ADSP-2162/ADSP-2164/ADSP-2166–SUPPLY CURRENT AND POWER
Parameter
Test Conditions
1
IDD
Supply Current (Dynamic)
IDD
Supply Current (Idle)1, 3
Min
2
@ VDD = max, tCK = 60 ns
@ VDD = max, tCK = 76.9 ns
@ VDD = max, tCK = 97.6 ns
@ VDD = max, tCK = 60 ns
@ VDD = max, tCK = 76.9 ns
@ VDD = max, tCK = 97.6 ns
Max
Unit
16
15
14
5
4
4
mA
mA
mA
mA
mA
mA
NOTES
1
Current reflects device operating with no output loads.
2
VIN = 0.4 V and 2.4 V.
3
Idle refers to ADSP-216x state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
For typical supply current (internal power dissipation) figures, see Figure 15.
Specifications subject to change without notice.
IDD DYNAMIC1,2
50
48mW
45
VDD = 3.6V
VDD = 3.30V
37mW
40
POWER – mW
35
30
29mW
25
24mW
20
19mW
15
15mW
VDD = 3.0V
10
5
0
5.00
7.00
10.00
13.83
FREQUENCY – MHz
IDD IDLE1
14
15.00
IDD IDLE n MODES3
14
13mW
12
9mW
IDD IDLE
10mW
VDD = 3.30V
8
8mW
6mW
5mW
6
VDD = 3.0V
10
POWER – mW
10
POWER – mW
13mW
12
VDD = 3.6V
9mW
8
IDLE 16
4
2
2
7.00
10.00
13.83
FREQUENCY – MHz
0
5.00
15.00
6mW
5mW
4
0
5.00
7mW
6
4mW
IDLE 128
7.00
10.00
13.83
FREQUENCY – MHz
15.00
VALID FOR ALL TEMPERATURE GRADES.
REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
REFERS TO ADSP-216x OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3MAXIMUM POWER DISSIPATION AT V
DD = 3.6V DURING EXECUTION OF IDLE n INSTRUCTION.
1POWER
2IDLE
Figure 15. ADSP-2162 Power (Typical) vs. Frequency)
–18–
REV. 0
ADSP-216x
ADSP-2162/ADSP-2164/ADSP-2166
POWER DISSIPATION EXAMPLE
CAPACITIVE LOADING
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
Figures 16 and 17 show capacitive loading characteristics for
the ADSP-2162 and ADSP-2164.
C × VDD2 ×␣ f
35
C = load capacitance,␣ f␣ = output switching frequency.
30
RISE TIME (0.4V – 2.0V) – ns
Example:
In an ADSP-2162 application where external data memory is
used and no other outputs are active, power dissipation is calculated as follows:
Assumptions:
•␣ External data memory is accessed every cycle with 50% of the
␣ ␣ address pins switching.
•␣ External data memory writes occur every other cycle with
␣ ␣ 50% of the data pins switching.
25
20
VDD = 3.0V
15
10
5
•␣ Each address and data pin has a 10 pF total load at the pin.
0
0
25
75
50
•␣ The application operates at VDD = 3.3 V and tCK = 100 ns.
100
CL – pF
125
150
175
Figure 16. Typical Output Rise Time vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature)
Total Power Dissipation = PINT + (C × VDD2 ×␣ f)
PINT = internal power dissipation (from Figure 15).
10
(C × VDD2 × f) is calculated for each output:
Output
# of
Pins ⴛ C
Address, DMS
Data, WR
RD
CLKOUT
8
9
1
1
× 10 pF
× 10 pF
× 10 pF
× 10 pF
RISE TIME (0.4V – 2.0V) – ns
8
ⴛ VDD2 ⴛ f
× 3.32 V
× 3.32 V
× 3.32 V
× 3.32 V
× 10 MHz
× 5 MHz
× 5 MHz
× 10 MHz
Total power dissipation for this example = PINT
=
=
=
=
8.71 mW
4.90 mW
0.55 mW
1.09 mW
15.25 mW
+ 15.25 mW.
6
4
VDD = 3.0V
2
NOMINAL
–2
–4
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
25
50
75
100
CL – pF
125
150
175
Figure 17. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
␣ ␣ TAMB = TCASE – (PD × θCA)
␣ ␣ TCASE = Case Temperature in °C
␣ ␣ PD = Power Dissipation in W
␣ ␣ θCA = Thermal Resistance (Case-to-Ambient)
␣ ␣ θJA = Thermal Resistance (Junction-to-Ambient)
␣ ␣ θJC = Thermal Resistance (Junction-to-Case)
Package
JA
JC
CA
MQFP
60°C/W
18°C/W
42°C/W
REV. 0
0
–19–
ADSP-216x
SPECIFICATIONS
ADSP-2162/ADSP-2164/ADSP-2166
TEST CONDITIONS
Output Enable Time
Figure 18 shows voltage reference levels for ac measurements.
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 19. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
VDD
INPUT
2
VDD
OUTPUT
2
REFERENCE
SIGNAL
Figure 18.␣ Voltage Reference Levels␣ for␣ AC Measurements
(Except Output Enable/Disable)
tMEASURED
tENA
Output Disable Time
VOH
(MEASURED)
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in Figure 19. The time tMEASURED is the interval from
when a reference signal reaches a high or low voltage level to
when the output voltages have changed by 0.5 V from the measured output high or low voltage.
OUTPUT
VOL
(MEASURED)
VOH
(MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
VOL
(MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be approximated by the following equation:
t DECAY =
tDIS
Figure 19. Output Enable/Disable
IOL
CL × 0.5V
iL
from which
TO
OUTPUT
PIN
t DIS = tMEASURED – tDECAY
VDD
2
50pF
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
IOH
Figure 20. Equivalent Device Loading for AC
Measurements (Except Output Enable/Disable)
–20–
REV. 0
ADSP-216x
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
GENERAL NOTES
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While
addition or subtraction would yield meaningful results for an
individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
TIMING NOTES
MEMORY REQUIREMENTS
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
The table below shows common memory device specifications
and the corresponding ADSP-216x timing parameters, for your
convenience.
Memory Device Specification
ADSP-216x
Timing Parameter
Timing Parameter Definition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
tASW
tAW
tWRA
tDW
tDH
tRDD
tAA
A0–A13, DMS, PMS Setup Before WR Low
A0–A13, DMS, PMS Setup Before WR Deasserted
A0–A13, DMS, PMS Hold After WR Deasserted
Data Setup Before WR High
Data Hold After WR High
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
REV. 0
–21–
ADSP-216x
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
CLOCK SIGNALS AND RESET
Parameter
Timing Requirements:
tCK
CLKIN Period
tCKL CLKIN Width Low
tCKH CLKIN Width High
RESET Width Low
tRSP
Switching Characteristics:
CLKOUT Width Low
tCPL
tCPH CLKOUT Width High
tCKOH CLKIN High to CLKOUT High
16.67 MHz
Min Max
20 MHz
Min Max
25 MHz
Min Max
Frequency Dependency
Min
Max
Unit
60
20
20
300
50
20
20
250
40
15
15
200
tCK
20
20
5tCK1
150
ns
ns
ns
ns
0.5tCK – 10
0.5tCK – 10
0
202
ns
ns
ns
20
20
0
150
150
15
15
0
20
20
10
10
0
150
152
NOTES
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal
oscillator startup time).
2
For 25 MHz only, the maximum frequency dependency for t CKOH = 15 ns.
t CK
t CKH
CLKIN
t CKL
t CHOK
t CPH
CLKOUT
t CPL
Figure 21. Clock Signals
–22–
REV. 0
ADSP-216x
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
INTERRUPTS AND FLAGS
Parameter
Timing Requirements:
tIFS
IRQx1 or FI Setup Before
CLKOUT Low2, 3
tIFS
IRQx1 or FI Setup Before
CLKOUT Low2, 3
tIFH
IRQx1 or FI Hold After CLKOUT
High2, 3
Switching Characteristics:
tFOH FO Hold After CLKOUT High
tFOD FO Delay from CLKOUT High
16.67 MHz
Min Max
20 MHz
Min Max
25 MHz
Min Max
Frequency Dependency
Min
Max
Unit
30
27.5
25
0.25tCK + 15
ns
33
30.5
28
0.25tCK + 18
ns
15
12.5
10
0.25tCK
ns
0
0
0
15
15
0
124
154
ns
ns
NOTES
1
IRQx = IRQ0, IRQ1, and IRQ2.
2
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual, Third Edition for further
information on interrupt servicing.)
3
Edge-sensitive interrupts require pulsewidths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
4
For 25 MHz only, the maximum frequency dependency for t FOD = 12 ns.
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
tIFH
IRQx
FI
tIFS
Figure 22. Interrupts and Flags
REV. 0
–23–
ADSP-216x
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
BUS REQUEST/BUS GRANT
Parameter
Timing Requirements:
tBH
BR Hold After CLKOUT High1
BR Setup Before CLKOUT Low1
tBS
Switching Characteristics:
CLKOUT High to DMS,
tSD
PMS, BMS, RD, WR Disable
DMS, PMS, BMS, RD, WR
tSDB
Disable to BG Low
BG High to DMS, PMS,
tSE
BMS, RD, WR Enable
DMS, PMS, BMS, RD, WR
tSEC
Enable to CLKOUT High
16.67 MHz
Min Max
20 MHz
Min Max
25 MHz
Min Max
Frequency Dependency
Min
Max
Unit
20
35
17.5
32.5
15
30
0.25tCK + 5
0.25tCK + 20
ns
ns
35
32.5
30
0.25tCK + 20
ns
0
0
0
0
ns
0
0
0
0
ns
5
2.5
1.52
0.25tCK – 102
ns
NOTES
1
If BR meets the tBS and t BH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
a pulsewidth greater than 10 ns.
2
For 25 MHz only, the minimum frequency dependency formula for t SEC = (0.25tCK – 8.5).
Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual, Third Edition, states that “When BR is recognized, the processor responds
immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after BR is
recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
tSD
tSEC
tSDB
tSE
Figure 23. Bus Request/Bus Grant
–24–
REV. 0
ADSP-216x
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
MEMORY READ
16.67 MHz
Min
Max
Parameter
Timing Requirements:
tRDD
RD Low to Data Valid
A0–A13, PMS, DMS, BMS to Data Valid
tAA
Data Hold from RD High
tRDH
Switching Characteristics:
RD Pulsewidth
tRP
CLKOUT High to RD Low
tCRD
A0–A13, PMS, DMS, BMS Setup Before RD Low
tASR
A0–A13, PMS, DMS, BMS Hold After RD Deasserted
tRDA
tRWR
RD High to RD or WR Low
20 MHz
Min
Max
17
27
12
19.5
0
0
22
10
5
6
25
Parameter
Timing Requirements:
tRDD
RD Low to Data Valid
A0–A13, PMS, DMS, BMS to Data Valid
tAA
Data Hold from RD High
tRDH
Switching Characteristics:
RD Pulsewidth
tRP
CLKOUT High to RD Low
tCRD
A0–A13, PMS, DMS, BMS Setup Before RD Low
tASR
A0–A13, PMS, DMS, BMS Hold After RD Deasserted
tRDA
tRWR
RD High to RD or WR Low
17
7.5
2.5
3.5
20
25
Min
0
22.5
12
5
1.51
1
15
20
0.5tCK – 13 + w
0.75tCK – 18 + w
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
0
0.5tCK – 8 + w
0.25tCK – 5
0.25tCK – 101
0.25tCK – 9
0.5tCK – 5
0.25tCK + 10
CLKOUT
A0–A13
DMS, PMS,
BMS
tRDA
RD
tASR
tRP
tCRD
tRWR
D
tRDD
WR
Figure 24. Memory Read
REV. 0
7
12
Frequency Dependency
(CLKIN ≤ 25 MHz)
Max
NOTES
1For 25 MHz only, minimum frequency dependency formula for t
ASR = (0.25t CK – 8.5).
w = wait states × tCK.
tAA
25 MHz
Min
Max
–25–
tRDH
ns
ns
ns
ns
ns
ADSP-216x
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
MEMORY WRITE
Parameter
16.67 MHz
Min
Max
20 MHz
Min
Max
25 MHz
Min
Max
Unit
Switching Characteristics:
tDW
Data Setup Before WR High
Data Hold After WR High
tDH
WR Pulsewidth
tWP
WR Low to Data Enabled
tWDE
A0–A13, DMS, PMS Setup Before WR Low
tASW
Data Disable Before WR or RD Low
tDDR
CLKOUT High to WR Low
tCWR
A0–A13, DMS, PMS, Setup Before WR Deasserted
tAW
A0–A13, DMS, PMS Hold After WR Deasserted
tWRA
tWWR
WR High to RD or WR Low
17
5
22
0
5
5
10
23
6
25
12
2.5
17
0
2.5
2.5
7.5
15.5
3.5
20
7
0
12
0
1.51
1.51
5
8
1
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
22.5
Parameter
Frequency Dependency
(CLKIN ≤ 25 MHz)
Min
Max
Switching Characteristics:
tDW
Data Setup Before WR High
Data Hold After WR High
tDH
WR Pulsewidth
tWP
WR Low to Data Enabled
tWDE
A0–A13, DMS, PMS Setup Before WR Low
tASW
Data Disable Before WR or RD Low
tDDR
CLKOUT High to WR Low
tCWR
A0–A13, DMS, PMS, Setup Before WR Deasserted
tAW
A0–A13, DMS, PMS Hold After WR Deasserted
tWRA
tWWR
WR High to RD or WR Low
0.5tCK – 13 + w
0.25tCK – 10
0.5tCK – 8 + w
0
0.25tCK – 101
0.25tCK – 101
0.25tCK – 5
0.75tCK – 22 + w
0.25tCK – 9
0.5tCK – 5
20
Unit
ns
ns
ns
0.25tCK + 10
ns
ns
ns
ns
ns
ns
NOTES
1
For 25 MHz only, the minimum frequency dependency formula for t ASW and tDDR = (0.25tCK – 8.5).
w = wait states × tCK.
CLKOUT
A0–A13
DMS, PMS,
BMS
tWRA
WR
tASW
tWWR
tWP
tAW
tDH
tCWR
tDDR
D
tDW
tWDE
RD
Figure 25. Memory Write
–26–
REV. 0
ADSP-216x
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
SERIAL PORTS
Parameter
Timing Requirements:
tSCK
SCLK Period
DR/TFS/RFS Setup Before SCLK Low
tSCS
DR/TFS/RFS Hold After SCLK Low
tSCH
SCLKIN Width
tSCP
Switching Characteristics:
CLKOUT High to SCLKOUT
tCC
SCLK High to DT Enable
tSCDE
SCLK High to DT Valid
tSCDV
TFS/RFSOUT Hold After SCLK High
tRH
TFS/RFSOUT Delay from SCLK High
tRD
DT Hold After SCLK High
tSCDH
TFS (Alt) to DT Enable
tTDE
TFS (Alt) to DT Valid
tTDV
SCLK High to DT Disable
tSCDD
RFS (Multichannel, Frame Delay Zero)
tRDV
to DT Valid
13.824 MHz*
Min
Max
Frequency Dependency
Min
Max
Unit
72.3
8
10
28
72.3
8
10
28
ns
ns
ns
ns
18.1
0
33.1
0.25tCK
0
20
20
0
0
20
20
0
0
0
0
18
25
20
18
25
20
*Maximum serial port operating frequency is 13.824 MHz for all processor speed grades.
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCS
tSCP
tSCH
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
(ALTERNATE
FRAME MODE)
tRDV
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0})
Figure 26. Serial Ports
REV. 0
0.25tCK + 15
–27–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-216x
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
GENERAL NOTES
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While
addition or subtraction would yield meaningful results for an
individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
TIMING NOTES
MEMORY REQUIREMENTS
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
The table below shows common memory device specifications
and the corresponding ADSP-216x timing parameters, for your
convenience.
Memory Device Specification
ADSP-216x
Timing Parameter
Timing Parameter Definition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
tASW
tAW
tWRA
tDW
tDH
tRDD
tAA
A0–A13, DMS, PMS Setup Before WR Low
A0–A13, DMS, PMS Setup Before WR Deasserted
A0–A13, DMS, PMS Hold After WR Deasserted
Data Setup Before WR High
Data Hold After WR High
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
–28–
REV. 0
ADSP-216x
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
CLOCK SIGNALS AND RESET
Parameter
Timing Requirements:
tCK
CLKIN Period
tCKL CLKIN Width Low
tCKH CLKIN Width High
RESET Width Low
tRSP
Switching Characteristics:
CLKOUT Width Low
tCPL
tCPH CLKOUT Width High
tCKOH CLKIN High to CLKOUT High
10.24 MHz
Min
Max
13.0 MHz
Min
Max
16.67 MHz
Min
Max
Frequency
Dependency
Min
Max
Unit
97.6
20
20
488
76.9
20
20
384.5
60.0
20
20
300
tCK
20
20
5tCK1
ns
ns
ns
ns
38.8
38.8
0
150
28.5
28.5
0
20
150
20
20
20
0
150
20
0.5tCK – 10
0.5tCK – 10
0
150
20
ns
ns
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator startup time).
t CK
t CKH
CLKIN
t CKL
t CHOK
t CPH
CLKOUT
t CPL
Figure 27. Clock Signals
REV. 0
–29–
ADSP-216x
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
INTERRUPTS AND FLAGS
Parameter
Timing Requirements:
tIFS
IRQx1 or FI Setup Before
CLKOUT Low2, 3
IRQx1 or FI Hold After
tIFH
CLKOUT High2, 3
Switching Characteristics:
tFOH FO Hold After CLKOUT High
tFOD FO Delay from CLKOUT High
10.24 MHz
Min
Max
13.0 MHz
Min
Max
16.67 MHz
Min
Max
Frequency
Dependency
Min
Max
Unit
44.4
39.2
35.0
0.25tCK + 20
ns
24.4
19.2
15.0
0.25tCK
ns
0
0
15
0
15
0
15
15
ns
ns
NOTES
1
IRQx = IRQ0, IRQ1, and IRQ2.
2
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual, Third Edition, for further
information on interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
tIFH
IRQx
FI
tIFS
Figure 28. Interrupts and Flags
–30–
REV. 0
ADSP-216x
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
BUS REQUEST/BUS GRANT
Parameter
Timing Requirements:
tBH
BR Hold After CLKOUT High1
BR Setup Before CLKOUT Low1
tBS
Switching Characteristics:
CLKOUT High to DMS, PMS,
tSD
BMS, RD, WR Disable
DMS, PMS, BMS, RD, WR
tSDB
Disable to BG Low
BG High to DMS, PMS, BMS,
tSE
RD, WR Enable
DMS, PMS, BMS, RD, WR
tSEC
Enable to CLKOUT High
10.24 MHz
Min
Max
13.0 MHz
Min Max
16.67 MHz
Min
Max
Frequency Dependency
Min
Max
Unit
29.4
44.4
24.2
39.2
20.0
35.0
0.25tCK + 5
0.25tCK + 20
ns
ns
44.4
39.2
0.25tCK + 20
35.0
ns
0
0
0
0
ns
0
0
0
0
ns
14.4
9.2
5.0
0.25tCK – 10
ns
NOTES
1
If BR meets the t BS and t BH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulsewidth greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual, Third Edition, states that, “When BR is recognized, the processor responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after BR is recognized.
No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
tSD
tSEC
tSDB
tSE
Figure 29. Bus Request/Grant
REV. 0
–31–
ADSP-216x
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
MEMORY READ
Parameter
Timing Requirements:
tRDD RD Low to Data Valid
A0–A13, PMS, DMS, BMS to
tAA
Data Valid
tRDH Data Hold from RD High
Switching Characteristics:
RD Pulsewidth
tRP
tCRD CLKOUT High to RD Low
A0–A13, PMS, DMS, BMS
tASR
Setup Before RD Low
tRDA A0–A13, PMS, DMS, BMS
Hold After RD Deasserted
tRWR RD High to RD or WR Low
10.24 MHz
Min
Max
13.0 MHz
Min
Max
33.8
23.5
49.2
0
43.8
19.4
16.67 MHz
Min
Max
15
33.7
0.5tCK – 15 + w
21
0
34.4
Frequency Dependency
Min
Max
0
33.25
14.2
25
10.0
29.2
0
25.0
Unit
ns
0.75tCK – 24 + w ns
ns
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK + 10
ns
ns
12.4
7.2
3.0
0.25tCK – 12
ns
14.4
38.8
9.2
28.5
5.0
20.0
0.25tCK – 10
0.5tCK – 10
ns
ns
w = wait states × tCK.
CLKOUT
A0–A13
DMS, PMS,
BMS
tRDA
RD
tASR
tRP
tCRD
tRWR
D
tRDD
tAA
tRDH
WR
Figure 30. Memory Read
–32–
REV. 0
ADSP-216x
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
MEMORY WRITE
Parameter
Switching Characteristics:
tDW
Data Setup Before WR High
Data Hold After WR High
tDH
WR Pulsewidth
tWP
tWDE WR Low to Data Enabled
tASW A0–A13, DMS, DMS Setup
Before WR Low
tDDR Data Disable Before WR
or RD Low
tCWR CLKOUT High to WR Low
A0–A13, DMS, PMS, Setup
tAW
Before WR Deasserted
tWRA A0–A13, DMS, PMS Hold
After WR Deasserted
tWWR WR High to RD or WR Low
10.24 MHz
Min
Max
13.0 MHz
Min
Max
16.67 MHz
Min
Max
Frequency
Dependency
Min
Max
38.8
14.4
43.8
0
28.25
9.2
33.25
0
20
5.0
25
0
0.5tCK – 10 + w
0.25tCK – 10
0.5tCK – 5 + w
0
ns
ns
ns
12.4
7.2
3.0
0.25tCK – 12
ns
14.4
19.4
34.4
9.2
14.2
5.0
10.0
29.2
25.0
0.25tCK – 10
0.25tCK – 5
ns
ns
58.2
42.7
30
0.75tCK – 15 + w
ns
14.4
38.8
9.2
28.25
5.0
20
0.25tCK – 10
0.5tCK – 10
ns
ns
w = wait states × tCK.
CLKOUT
A0–A13
DMS, PMS,
BMS
tWRA
WR
tASW
tWWR
tWP
tAW
tDH
tCWR
D
tDW
tWDE
RD
Figure 31. Memory Write
REV. 0
0.25tCK + 10
Unit
–33–
tDDR
ADSP-216x
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
SERIAL PORTS
Parameter
Timing Requirements:
tSCK SCLK Period
DR/TFS/RFS Setup
tSCS
Before SCLK Low
tSCH DR/TFS/RFS Hold After
SCLK Low
SCLKIN Width
tSCP
Switching Characteristics:
CLKOUT High to SCLKOUT
tCC
tSCDE SCLK High to DT Enable
tSCDV SCLK High to DT Valid
TFS/RFSOUT Hold After
tRH
SCLK High
TFS/RFSOUT Delay from
tRD
SCLK High
tSCDH DT Hold After SCLK High
tTDE TFS (Alt) to DT Enable
tTDV TFS (Alt) to DT Valid
tSCDD SCLK High to DT Disable
tRDV RFS (Multichannel, Frame 20
Delay Zero) to DT Valid
10.24 MHz
Min Max
13.0 MHz
Min Max
13.824 MHz1
Min Max
Frequency Dependency
Min
Max
Unit
97.6
76.9
72.31
tCK1
ns
8
8
8
8
ns
10
28
10
28
10
28
10
28
ns
ns
24.4
0
39.4
19.2
0
282
0
34.2
18.1
0
20
0.25tCK
0
0
0
ns
ns
ns
ns
202
18
302
18
25
18
25
18
252
ns
ns
ns
ns
ns
20
20
20
20
ns
0
0
20
0.25tCK + 15
202
20
0
282
33.1
20
0
0
0
0
0
0
NOTES
1
Maximum serial port operating frequency is 13.824 MHz for all processor speed grades faster then 13.824 MHz.
2
For 10.24 MHz only, the maximum frequency dependency for t SCDV = 28 ns, t RD = 28 ns, t SCDD = 30 ns.
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCS
tSCP
tSCH
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
(ALTERNATE
FRAME MODE)
tRDV
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0})
Figure 32. Serial Ports
–34–
REV. 0
ADSP-216x
PIN CONFIGURATIONS
GND
2
4
D4
D3
3
6
D5
GND
D11
5
7
D7
D6
D12
8
D9
D8
D14
D13
9
D10
D18
D17
D16
D15
68-Lead PLCC
1 68 67 66 65 64 63 62 61
10
PIN 1
IDENTIFIER
D19 11
D20 12
60
D2
59
D1
D0
58
D21 13
57
D22 14
D23 15
56
VDD
SCLK1
55
FI
VDD 16
MMAP 17
54
53
TOP VIEW
(Not to Scale)
BR 18
IRQ2
RESET
A0
A1
IRQ0
IRQ1
52 FO
ADSP-216x
19
51
SCLK0
DR0
20
50
21
49
22
48
GND
RFS0
A2 23
47
TFS0
A3 24
A4 25
46
DT0
45
RD
VDD 26
44
WR
CLKIN
CLKOUT
BG
XTAL
DMS
BMS
A13
PMS
A11
A12
A8
A9
A10
A5
A6
GND
A7
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PLCC
Number
Pin
Name
PLCC
Number
Pin
Name
PLCC
Number
Pin
Name
PLCC
Number
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
D11
GND
D12
D13
D14
D15
D16
D17
D18
GND
D19
D20
D21
D22
D23
VDD
MMAP
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
BR
IRQ2
RESET
A0
A1
A2
A3
A4
VDD
A5
A6
GND
A7
A8
A9
A10
A11
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
A12
A13
PMS
DMS
BMS
BG
XTAL
CLKIN
CLKOUT
WR
RD
DT0
TFS0
RFS0
GND
DR0
SCLK0
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
FO
IRQ1
IRQ0
FI
SCLK1
VDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
REV. 0
–35–
(DT1)
(TFS1)
(RFS1)
(DR1)
ADSP-216x
PIN CONFIGURATIONS
62 GND
61 GND
64 D20
63 D19
66 D22
65 D21
68 V
DD
67 D23
69 VDD
70 MMAP
72 IRQ2
71 BR
74 A0
73 RESET
76 A2
75 A1
80 VDD
79 VDD
78 A4
77 A3
80-Lead MQFP
60 D18
A5
A6
1
GND
3
GND
4
58 D16
57 D15
A7
5
56 D14
A8
A9
6
55 D13
54 D12
A10
A11
8
2
PIN 1
IDENTIFIER
59 D17
7
9
53 GND
52 GND
ADSP-216x
A12 10
51 D11
TOP VIEW
(Not to Scale)
A13 11
PMS 12
50 D10
49 D9
DMS 13
BMS 14
48 D8
BG 15
XTAL 16
46 D6
47 D7
45 D5
44 D4
CLKIN 17
*PWDACK 18
43 NC
42 NC
*PWDFLAG 19
NC 20
D2 39
D3 40
D1 38
D0 37
FI 34
SCLK1 35
VDD 36
FO 31
IRQ1 32
IRQ0 33
DR0 29
SCLK0 30
GND 27
GND 28
RFS0 26
RD 23
DT0 24
TFS0 25
CLKOUT 21
WR 22
41 NC
NC = NO CONNECT
MQFP
Number
Pin
Name
MQFP
Number
Pin
Name
MQFP
Number
Pin
Name
MQFP
Number
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A5
A6
GND
GND
A7
A8
A9
A10
A11
A12
A13
PMS
DMS
BMS
BG
XTAL
CLKIN
PWDACK*
PWDFLAG*
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CLKOUT
WR
RD
DT0
TFS0
RFS0
GND
GND
DR0
SCLK0
FO
(DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
(DR1)
SCLK1
VDD
D0
D1
D2
D3
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
NC
NC
NC
D4
D5
D6
D7
D8
D9
D10
D11
GND
GND
D12
D13
D14
D15
D16
D17
D18
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND
GND
D19
D20
D21
D22
D23
VDD
VDD
MMAP
BR
IRQ2
RESET
A0
A1
A2
A3
A4
VDD
VDD
*ADSP-2165/ADSP-2166 only.
Others “NC”.
–36–
REV. 0
ADSP-216x
OUTLINE DIMENSIONS
ADSP-216x
68-Lead Plastic Leaded Chip Carrier (PLCC)
0.175 (4.45)
0.169 (4.29)
0.995 (25.27)
SQ
0.985 (25.02)
9
10
PIN 1
IDENTIFIER
61
60
0.050
(1.27)
TYP
PIN 1
IDENTIFIER
0.925 (23.50)
0.895 (22.73)
TOP VIEW
BOTTOM VIEW
(PINS DOWN)
(PINS UP)
0.019 (0.48)
0.017 (0.43)
0.029 (0.74)
0.027 (0.69)
26
44
43
27
0.954 (24.23)
SQ
0.950 (24.13)
REV. 0
0.104 (2.64) TYP
–37–
ADSP-216x
OUTLINE DIMENSIONS
ADSP-216x
80-Lead Plastic Quad Flatpack (MQFP)
0.690 (17.45)
0.667 (16.95)
0.555 (14.10)
0.547 (13.90)
0.486 (12.35) BSC
0.134 (3.40)
MAX
0.041 (1.03)
0.031 (0.78)
80
1
61
60
0.486 (12.35) BSC
0.555 (14.10)
0.547 (13.90)
0.690 (17.45
0.667 (16.95)
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.004 (0.10)
MAX
20
21
0.010 (0.25)
MIN
0.120 (3.05)
0.100 (2.55)
41
40
0.026 (0.65)
BSC
0.014 (0.35)
0.010 (0.25)
THE ACTUAL POSITION OF EACH LEAD
IS WITHIN 0.0047 (0.12) FROM ITS IDEAL
POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
–38–
REV. 0
ADSP-216x
ORDERING GUIDE
Instruction
Rate (MHz)
Package
Description
Package
Option
ADSP-2161KP-662
ADSP-2161BP-662
ADSP-2161KS-662
ADSP-2161BS-662
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67
16.67
16.67
16.67
68-Lead PLCC
68-Lead PLCC
80-Lead MQFP
80-Lead MQFP
P-68A
P-68A
S-80
S-80
ADSP-2162KP-40 (3.3 V)2
ADSP-2162BP-40 (3.3 V)2
ADSP-2162KS-40 (3.3 V)2
0°C to +70°C
–40°C to +85°C
0°C to +70°C
10.24
10.24
10.24
68-Lead PLCC
68-Lead PLCC
80-Lead MQFP
P-68A
P-68A
S-80
ADSP-2163KP-662
ADSP-2163BP-662
ADSP-2163KS-662
ADSP-2163BS-662
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67
16.67
16.67
16.67
68-Lead PLCC
68-Lead PLCC
80-Lead MQFP
80-Lead MQFP
P-68A
P-68A
S-80
S-80
ADSP-2163KP-1002
ADSP-2163BP-1002
ADSP-2163KS-1002
ADSP-2163BS-1002
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
25
25
25
25
68-Lead PLCC
68-Lead PLCC
80-Lead MQFP
80-Lead MQFP
P-68A
P-68A
S-80
S-80
ADSP-2164KP-40 (3.3 V)2
ADSP-2164BP-40 (3.3 V)2
ADSP-2164KS-40 (3.3 V)2
ADSP-2164BS-40 (3.3 V)2
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
10.24
10.24
10.24
10.24
68-Lead PLCC
68-Lead PLCC
80-Lead MQFP
80-Lead MQFP
P-68A
P-68A
S-80
S-80
ADSP-2165KS-80
ADSP-2165KS-100
ADSP-2165BS-80
ADSP-2165BS-100
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
20.00
25.00
20.00
25.00
80-Lead MQFP
80-Lead MQFP
80-Lead MQFP
80-Lead MQFP
S-80
S-80
S-80
S-80
ADSP-2166KS-52 (3.3 V)
ADSP-2166KS-66 (3.3 V)
ADSP-2166BS-52 (3.3 V)
ADSP-2166BS-66 (3.3 V)
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
13.00
16.67
13.00
16.67
80-Lead MQFP
80-Lead MQFP
80-Lead MQFP
80-Lead MQFP
S-80
S-80
S-80
S-80
C3511–3–10/99
Part Number1
Ambient
Temperature
Range
PRINTED IN U.S.A.
NOTES
1K = Commercial Temperature Range (0°C to +70°C).
B = Industrial Temperature Range (–40°C to +85°C).
P = PLCC (Plastic Leaded Chip Carrier).
S = MQFP (Plastic Quad Flatpack).
2Minimum order quantities required. Contact factory for further information.
3Refer to the section titled “Ordering Procedure for ROM-Coded ADSP-216x Processors” for information about ROM coded parts.
REV. 0
–39–