OB39R08A3
SM39R08A3
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Product List ................................................................................................................................................................. 3
Description .................................................................................................................................................................. 3
Ordering Information .................................................................................................................................................... 3
Features ...................................................................................................................................................................... 3
Pin Configuration ......................................................................................................................................................... 4
Block Diagram ............................................................................................................................................................. 6
Pin Description ............................................................................................................................................................ 7
Special Function Register (SFR) .................................................................................................................................. 8
Function Description .................................................................................................................................................. 12
1.
General Features .............................................................................................................................................. 12
1.1
Embedded Flash ....................................................................................................................................... 12
1.2
IO Pads..................................................................................................................................................... 12
1.3
Instruction timing Selection........................................................................................................................ 12
1.4
The Clock Out Selection............................................................................................................................ 13
1.5
RESET...................................................................................................................................................... 13
1.5.1 Hardware RESET function .................................................................................................................... 13
1.5.2 Software RESET function...................................................................................................................... 13
1.5.3 Reset status .......................................................................................................................................... 14
1.5.4 Time Access Key register (TAKEY)........................................................................................................ 14
1.5.5 Software Reset register (SWRES) ......................................................................................................... 14
1.5.6 Example of software reset ..................................................................................................................... 15
1.6
Clocks....................................................................................................................................................... 15
2.
Instruction Set ................................................................................................................................................... 16
3.
Memory Structure .............................................................................................................................................. 20
3.1
Program Memory ...................................................................................................................................... 20
3.2
Data Memory ............................................................................................................................................ 21
3.3
Data memory - lower 128 byte (00h to 7Fh) ............................................................................................... 21
3.4
Data memory - higher 128 byte (80h to FFh) ............................................................................................. 21
3.5
Data memory - Expanded 256 bytes ($00 到 $FF) ..................................................................................... 21
4.
CPU Engine ...................................................................................................................................................... 22
4.1
Accumulator .............................................................................................................................................. 22
4.2
B Register ................................................................................................................................................. 22
4.3
Program Status Word ................................................................................................................................ 23
4.4
Stack Pointer............................................................................................................................................. 23
4.5
Data Pointer .............................................................................................................................................. 23
4.6
Data Pointer 1 ........................................................................................................................................... 24
4.7
Clock control register................................................................................................................................. 24
4.8
Interface control register............................................................................................................................ 25
5.
GPIO ................................................................................................................................................................. 26
6.
Timer 0 and Timer 1........................................................................................................................................... 28
6.1
Timer/counter mode control register (TMOD) ............................................................................................. 28
6.2
Timer/counter control register (TCON) ....................................................................................................... 29
6.3
Peripheral Frequency control register ........................................................................................................ 30
6.4
Mode 0 (13-bit Counter/Timer)................................................................................................................... 30
6.5
Mode 1 (16-bit Counter/Timer)................................................................................................................... 31
6.6
Mode 2 (8-bit auto-reload Counter/Timer) .................................................................................................. 32
6.7
Mode 3 (Timer 0 acts as two independent 8 bit Timers / Counters) ............................................................ 32
7.
Timer 2 and Capture Compare Unit ................................................................................................................... 33
7.1
Timer 2 function ........................................................................................................................................ 36
7.1.1 Timer mode........................................................................................................................................... 36
7.1.2 Event counter mode .............................................................................................................................. 36
7.1.3 Gated timer mode ................................................................................................................................. 37
7.1.4 Reload of Timer 2.................................................................................................................................. 37
7.2
Compare function ...................................................................................................................................... 37
7.2.1 Compare Mode 0 .................................................................................................................................. 38
7.2.2 Compare Mode 1 .................................................................................................................................. 38
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
-1-
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
7.3
Capture function........................................................................................................................................ 39
7.3.1 Capture Mode 0 (by Hardware) ............................................................................................................. 39
7.3.2 Capture Mode 1(by Software) ............................................................................................................... 39
8.
Serial interface .................................................................................................................................................. 40
8.1
Serial interface .......................................................................................................................................... 41
8.1.1 Mode 0 ................................................................................................................................................. 41
8.1.2 Mode 1 ................................................................................................................................................. 42
8.1.3 Mode 2 ................................................................................................................................................. 42
8.1.4 Mode 3 ................................................................................................................................................. 42
8.2
Multiprocessor Communication of Serial Interface ..................................................................................... 43
8.3
Peripheral Frequency control register ........................................................................................................ 43
8.4
Baud rate generator .................................................................................................................................. 43
8.4.1 Serial interface modes 1 and 3 .............................................................................................................. 43
9.
Watchdog timer ................................................................................................................................................. 45
10.
Interrupt ........................................................................................................................................................ 49
10.1
Priority level structure ................................................................................................................................ 52
11.
Power Management Unit ............................................................................................................................... 54
11.1
Idle mode .................................................................................................................................................. 54
11.2
Stop mode................................................................................................................................................. 54
12.
Pulse Width Modulation (PWM) ..................................................................................................................... 55
13.
IIC function .................................................................................................................................................... 59
14.
SPI Function - Serial Peripheral Interface ...................................................................................................... 64
15.
KBI – Keyboard Interface............................................................................................................................... 69
16.
LVI & LVR – Low Voltage Interrupt and Low Voltage Reset ............................................................................ 72
17.
10-bit Analog-to-Digital Converter (ADC) ....................................................................................................... 73
18.
In-System Programming (Internal ISP) .......................................................................................................... 77
18.1
ISP service program .................................................................................................................................. 77
18.2
Lock Bit (N) ............................................................................................................................................... 77
18.3
Program the ISP Service Program ............................................................................................................. 78
18.4
Initiate ISP Service Program ...................................................................................................................... 78
18.5
ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC .......................................................... 79
19.
Comparator ................................................................................................................................................... 82
Operating Conditions ................................................................................................................................................. 85
DC Characteristics ..................................................................................................................................................... 85
ADC Characteristics................................................................................................................................................... 87
Comparator Characteristics........................................................................................................................................ 87
LVI& LVR Characteristics ........................................................................................................................................... 88
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
-2-
39 R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Product List
SM39R08A3U20,
SM39R08A3U16,
SM39R08A3U14,
Features
OB39R08A3U20,
OB39R08A3U16,
OB39R08A3U14,
Description
The SM39R08A3 is a 1T (one machine cycle per clock)
single-chip 8-bit microcontroller. It has 8KB+1KB
embedded Flash for program, and executes all ASM51
instructions fully compatible with MCS-51.
SM39R08A3 contains 512B on-chip RAM, up to 18
GPIOs (20L package), various serial interfaces and
many peripheral functions as described below. It can be
programmed via writers. Its on-chip ICE is convenient for
users in verification during development stage.
The high performance of SM39R08A3 can achieve
complicated manipulation within short time. About one
third of the instructions are pure 1T, and the average
speed is 8 times of traditional 8051, the fastest one
among all the 1T 51-series.Its excellent EMI and ESD
characteristics are advantageous for many different
applications.
Ordering Information
SM39R08A3 ihhkL yymmv 39R08A3U20GP
i: process identifier { U = 1.8V ~ 5.5V}
hh: pin count
k: package type postfix {as table below }
L:PB Free identifier
{No text is Non-PB free，”P” is PB free}
yy: year
mm: month
v: version identifier{ A, B,…}
Tel:021-58998693
www.fosvos.com
Postfix
N
S
O
G
Operating Voltage:1.8V ~ 5.5V
High speed architecture of 1 clock/machine cycle
runs up to 25MHz.
1~8T can be switched on the fly.
Instruction-set compatible with MCS-51.
22.1184MHz Internal RC oscillator, with
programmable clock divider
8KB+1KB on-chip program memory.
512B RAM as standard 8052,
Dual 16-bit Data Pointers (DPTR0 & DPTR1).
One serial peripheral interfaces in full duplex mode.
Additional Baud Rate Generator
Three 16-bit Timer/Counters. (Timer 0,1,2）
12 ~18 GPIOs(14L ~ 20L package)
External interrupt 0,1 with four priority levels
Programmable watchdog timer.
One IIC interface. (Master/Slave mode)
One SPI interface (Master/Slave mode)
4-channel PWM
4-channel 16-bit PCA for compare(PWM) / capture
/ reload functions
7-channel 10-bit analog-to-digital converter (ADC)
and 1-channel ADC0 connect to internal reference
voltage
CMP x1 Set (2 devices)
ISP/IAP/ICP functions.
ISP service program space configurable in N*128
byte (N=0 to 8) size.
EEPROM function.
On-Chip in-circuit emulator (ICE) functions with OnChip Debugger (OCD).
Keyboard interface (KBI) for four more interrupts.
LVI/LVR (LVR deglitch 500ns)
IO PAD ESD over 4KV
Enhance user code protection.
Power management unit for IDLE and power down
modes.
Package
PDIP (300 mil)
SOP (300 mil)
SOP (150 mil)
SSOP (150 mil)
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
-3-
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Pin Configuration
20 Pin PDIP/SOP/SSOP
1
20
P0.1/KBI1/ADC1/Cmp1NIn
PWM1/MOSI/CC2/P1.7
2
19
P0.2/KBI2/ADC2/Cmp1PIn
PWM0/MISO/CC1/P1.6
3
18
P0.3/KBI3/T2/ADC3/Cmp0NIn
RST/P1.5
4
17
P0.4/ADC4/Cmp0PIn
VSS
5
16
P0.5/ADC5/CC0/PWM2
OSC_IN/XTAL1/P3.1
6
15
VDD
CLKOUT/XTAL2/P3.0
7
14
P0.6/ADC6/Cmp0Out
SS/INT1/P1.4
8
13
P0.7/T1/ADC7/CC3/PWM3
OCISDA/IICSDA/INT0/P1.3
9
12
P1.0/TXD
OCISCL/IICSCL/T0/P1.2 10
11
P1.1/RXD/T2EX
16
P0.3/KBI3/T2/ADC3/Cmp0NIn
15
P0.4/ADC4/Cmp0PIn
14
P0.5/ADC5/CC0/PWM2
13
VDD
12
P0.6/ADC6/Cmp0Out
11
P0.7/T1/ADC7/CC3/PWM3
10
P1.0/TXD
9
P1.1/RXD/T2EX
SM39R08A3
yymmv
(20 Pin Top View)
Cmp1Out/SPICLK/KBI0/P0.0
16 Pin PDIP/SOP
1
RST/P1.5
2
VSS
3
OSC_IN/XTAL1/P3.1
4
CLKOUT/XTAL2/P3.0
5
SS/INT1/P1.4
6
OCISDA/IICSDA/INT0/P1.3
7
OCISCL/IICSCL/T0/P1.2
8
SM39R08A3
yymmv
(16 Pin Top View)
PWM0/MISO/CC1/P1.6
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
-4-
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
14 Pin PDIP/SOP
1
PWM0/MISO/CC1/P1.6
2
RST/P1.5
3
VSS
4
OSC_IN/XTAL1/P3.1
5
CLKOUT/XTAL2/P3.0
6
OCISDA/IICSDA/INT0/P1.3
7
SM39R08A3
yymmv
(14 Pin Top View)
PWM1/MOSI/CC2/P1.7
14
P0.0/KBI0/SPICLK/Cmp1Out
13
P0.1/KBI1/ADC1/Cmp1NIn
12
P0.2/KBI2/ADC2/Cmp1PIn
11
VDD
10
P1.0/TXD
9
P1.1/RXD/T2EX
8
P1.2/IICSCL/T0/OCISCL
Notes：
(1) The pin Reset/P1.5 factory default is GPIO (P1.5), user must keep this pin at low during power-up. User
can configure it to Reset by a flash programmer.
(2) To avoid accidentally entering ISP-Mode(refer to section 18.4), care must be taken not asserting pulse
signal at RXD P1.1 during power-up while P1.6 are set to high.
(3) To apply ICP function, OSI_SDA/P1.3 and OCI_SCL/P1.2 must be set to Bi-direction mode if they are
configured as GPIO in system..
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
-5-
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
UART
ADC
IIC
SRAM
512Bytes
XTAL2
XTAL1
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_SS
PWM
IIC_SCL
IIC_SDA
Cmp0
Cmp1
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
PWM0
PWM1
PWM2
PWM3
MAX810
Cmp0PIn/Cmp1PIn
Cmp0NIn/Cm1NIn
Cmp0Out/Cmp1Out
RESET
TXD
RXD
Block Diagram
SPI
Port 0
Port 0
Port 1
Port 1
Port 3
Port 3
Timer 0/1
T0
T1
Flash 8K+1K
Bytes
CPU
Watchdog
Interrupt
ICE
ICP
CC0~CC3
T2
T2EX
OCI_SCL
(share with IIC)
OCI_SDA
(share with IIC)
Interface control
Timer2
& CCU
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
-6-
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Pin Description
20L
16L
14L
Symbol
P0.0/KBI0/
SPICLK/ADC0/
CMP1Out
I/O
1
-
14
2
-
1
P1.7/CC2/MOSI/PWM1
I/O
3
1
2
P1.6/CC1/MISO/PWM0
I/O
4
5
6
7
2
3
4
5
3
4
5
6
P1.5/RST
VSS
P3.1/XTAL1/OSC_IN
P3.0/XTAL2/CLKOUT
I/O
I
I/O
I/O
8
6
-
P1.4/INT1/SS
I/O
9
7
7
P1.3/INT0/
IICSDA/OCISDA
I/O
10
8
8
P1.2/T0/IICSCL/
OCISCL
I/O
11
9
9
P1.1/RXD/T2EX
I/O
12
10
10
P1.0/TXD
I/O
13
11
-
P0.7/T1/ADC7/
CC3/PWM3
I/O
14
15
12
13
11
P0.6/ADC6/CMP0Out
VDD
I/O
I
16
14
-
P0.5/ADC5/CC0/PWM2
I/O
17
15
-
P0.4/ADC4/ CMP0PIn
I/O
18
16
-
19
-
12
20
-
13
P0.3/KBI3/T2/
ADC3/CMP0NIn
P0.2/KBI2/ADC2/
CMP1PIn
P0.1/KBI1/ADC1/
CMP1NIn
I/O
I/O
I/O
I/O
Description
Bit 0 of port 0 & KBI interrupt 0 & SPI interface Clock pin
& Cmp1 output
Bit 7 of port 1 & Timer 2 compare/capture Channel 2 &
SPI interface Serial Data Master Output or Slave Input
pin & PWM Channel 1
Bit 6 of port 1 & Timer 2 compare/capture Channel 1 &
SPI interface Serial Data Master Input or Slave Output
pin & PWM Channel 0
Bit 5 of port 1 & Reset pin(default)
Power supply
Bit 1 of port 3 & Crystal input(default) & Oscillator input
Bit 0 of port 3 & Crystal output(default) & Clock Output
Bit 4 of port 1 & External interrupt 1 & SPI interface Slave
Select pin
Bit 3 of port 1 & External interrupt 0 & IIC SDA pin & OnChip Instrumentation Command and data I/O pin
synchronous to OCI_SCL in ICE and ICP functions
Bit 2 of port 1 & Timer 0 external input & IIC SCL pin &
On-Chip Instrumentation Clock I/O pin of ICE and ICP
functions
Bit 1 of port 1 & Serial interface channel 0
receive/transmit data & Timer 2 capture trigger
Bit 0 of port 1 & Serial interface channel 0 transmit data
or receive clock in mode 0
Bit 7 of port 0 & Timer 1 external input & ADC input
channel 7& Timer 2 compare/capture Channel 3& PWM
Channel 3
Bit 6 of port 0 & ADC input channel 6 & Cmp0 Output
Power supply
Bit 5 of port 0 & ADC input channel 5 & Timer 2
compare/capture Channel 0& PWM Channel 2
Bit 4 of port 0 & ADC input channel 4 & Cmp0 Positive
Input
Bit 3 of port 0 & KBI interrupt 3 & Timer 2 external input
clock & ADC input channel 3 & Cmp0 Negative Input
Bit 2 of port 0 & KBI interrupt 2 & ADC input channel 2 &
Cmp1 Positive Input
Bit 1 of port 0 & KBI interrupt 1 & ADC input channel 1 &
Cmp1 Negative Input
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
-7-
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Special Function Register (SFR)
A map of the Special Function Registers is shown as below：
Hex\Bin
F8
X000
X001
X010
X011
X100
X101
X110
X111
IICS
IICCTL
IICA1
IICA2
IICRWD
IICEBT
CMP0CON
CMP1CON
F0
E8
E0
B
SPIC1
SPIC2
SPITXD
SPIRXD
SPIS
OPPIN
TAKEY
ACC
ISPFAH
PFCON
ISPFAL
P3M0
ISPFD
P3M1
ISPFC
LVC
SWRES
P0M1
CRCH
CCH1
P1M0
TL2
CCL2
PWMD0
H
D8
D0
C8
C0
PSW
T2CON
IRCON
CCEN2
CCCON
CCEN
P0M0
CRCL
CCL1
B8
IEN1
IP1
SRELH
B0
P3
A8
A0
98
IEN0
SCON
PWMD2
H
IP0
RSTS
SBUF
90
88
80
Hex\Bin
P1
TCON
P0
X000
AUX
TMOD
SP
X001
PWMD2L
SRELL
PWMD3
H
ADCC1
TL0
DPL
X010
F7
EF
E7
DF
P1M1
TH2
CCH2
PWMMDH
CCL3
PWMMDL
CCH3
D7
CF
C7
PWMD0L
PWMD1H
PWMD1L
BF
PWMD3L
PWMC
WDTC
WDTK
B7
ADCC2
ADCDH
ADCDL
ADCCS
AF
A7
9F
KBE
TH0
DPL1
X100
KBF
TH1
DPH1
X101
KBD
CKCON
IRCON2
IFCON
PCON
X111
97
8F
87
Bin/Hex
IEN2
KBLS
TL1
DPH
X011
Bin/Hex
FF
X110
Note: Special Function Registers reset values and description for SM39R08A3
Register
Location
Reset value
Description
SP
ACC
PSW
B
DPL
DPH
DPL1
DPH1
81h
E0h
D0h
F0h
82h
83h
84h
85h
07h
00h
00h
00h
00h
00h
00h
00h
Stack Pointer
Accumulator
Program Status Word
B Register
Data Pointer 0 low byte
Data Pointer 0 high byte
Data Pointer 1 low byte
Data Pointer 1 high byte
AUX
PCON
CKCON
91h
87h
8Eh
00h
00h
10h
Auxiliary register
Power Control
Clock control register
SYSTEM
INTERRUPT & PRIORITY
IRCON
C0h
00h
Interrupt Request Control Register
IRCON2
97h
00h
Interrupt Request Control Register 2
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
-8-
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Register
Location
Reset value
Description
IEN0
IEN1
IEN2
A8h
B8h
9Ah
00h
00h
00h
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
IP0
A9h
00h
Interrupt Priority Register 0
IP1
B9h
00h
Interrupt Priority Register 1
KBLS
93h
00h
Keyboard level selector Register
KBE
KBF
KBD
94h
95h
96h
00h
00h
00h
Keyboard input enable Register
Keyboard interrupt flag Register
Keyboard interface De-bounce control register
PCON
87h
00h
Power Control
AUX
SCON
SBUF
SRELL
SRELH
PFCON
91h
98h
99h
AAh
BAh
D9h
00h
00h
00h
00h
00h
00h
Auxiliary register
Serial Port, Control Register
Serial Port, Data Buffer
Serial Port, Reload Register, low byte
Serial Port, Reload Register, high byte
Peripheral Frequency control register
ABh
ACh
ADh
AEh
AFh
00h
00h
00h
00h
00h
ADC Control 1 Register
ADC Control 2 Register
ADC data high byte
ADC data low byte
ADC clock select
A1h
B6h
B7h
F7h
00h
04h
00h
00h
Reset status register
Watchdog timer control register
Watchdog timer refresh key.
Time Access Key register
PWMC
PWMD0H
PWMD0L
PWMD1H
B5h
BCh
BDh
BEh
00h
00h
00h
00h
PWM control register
PWM channel 0 data high byte
PWM channel 0 data low byte
PWM channel 1 data high byte
PWMD1L
PWMD2H
PWMD2L
PWMD3H
PWMD3L
PWMMDH
BFh
B1h
B2h
B3h
B4h
CEh
00h
00h
00h
00h
00h
00h
PWM channel 1 data low byte
PWM channel 2 data high byte
PWM channel 2 data low byte
PWM channel 3 data high byte
PWM channel 3 data low byte
PWM Max Data Register, high byte.
PWMMDL
CFh
FFh
PWM Max Data Register, low byte.
KBI
UART
ADC
ADCC1
ADCC2
ADCDH
ADCDL
ADCCS
WDT
RSTS
WDTC
WDTK
TAKEY
PWM
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
-9-
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Register
Location
Reset value
Description
TCON
TMOD
TL0
TL1
TH0
TH1
88h
89h
8Ah
8Bh
8Ch
8Dh
00h
00h
00h
00h
00h
00h
Timer/Counter Control
Timer Mode Control
Timer 0, low byte
Timer 1, low byte
Timer 0, high byte
Timer 1, high byte
PFCON
D9h
00h
Peripheral Frequency control register
CCEN
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
T2CON
CCCON
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Compare/Capture Enable Register
Compare/Capture Register 1, low byte
Compare/Capture Register 1, high byte
Compare/Capture Register 2, low byte
Compare/Capture Register 2, high byte
Compare/Capture Register 3, low byte
Compare/Capture Register 3, high byte
Timer 2 Control
Compare/Capture Control
CRCL
CRCH
TL2
TH2
CCEN2
CAh
CBh
CCh
CDh
D1h
00h
00h
00h
00h
00h
Compare/Reload/Capture Register, low byte
Compare/Reload/Capture Register, high byte
Timer 2, low byte
Timer 2, high byte
Compare/Capture Enable 2 register
80h
90h
B0h
D2h
D3h
D4h
D5h
DAh
DBh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
Port 0
Port 1
Port 3
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 3 output mode 0
Port 3 output mode 1
IFCON
8Fh
00h
Interface control register
ISPFAH
ISPFAL
ISPFD
ISPFC
E1h
E2h
E3h
E4h
FFh
FFh
FFh
00h
ISP Flash Address-High register
ISP Flash Address-Low register
ISP Flash Data register
ISP Flash control register
TAKEY
F7h
00h
Time Access Key register
TIMER0/TIMER1
PCA(TIMER2)
GPIO
P0
P1
P3
P0M0
P0M1
P1M0
P1M1
P3M0
P3M1
ISP/IAP/EEPROM
LVI/LVR/SOFTRESET
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 10 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Register
Location
Reset value
Description
RSTS
LVC
SWRES
A1h
E6h
E7h
00h
20h
00h
Reset status register
Low voltage control register
Software Reset register
TAKEY
F7h
00h
Time Access Key register
AUX
SPIC1
91h
F1h
00h
08h
Auxiliary register
SPI control register 1
SPIC2
SPITXD
SPIRXD
SPIS
F2h
F3h
F4h
F5h
00h
00h
00h
40h
SPI control register 2
SPI transmit data buffer
SPI receive data buffer
SPI status register
AUX
IICS
IICCTL
IICA1
IICA2
IICRWD
91h
F8h
F9h
FAh
FBh
FCh
00h
00h
04h
A0h
60h
00h
Auxiliary register
IIC status register
IIC control register
IIC channel 1 Address 1 register
IIC channel 1 Address 2 register
IIC channel 1 Read / Write Data buffer
IICEBT
FDh
00h
IIC Enable Bus Transaction register
F6h
FEh
FFh
00H
00h
00h
Comparator Pin Select register
Comparator 0 Control register
Comparator 1 Control register
SPI
IIC
OPA
OPPIN
CMP0CON
CMP1CON
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ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 11 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Function Description
1. General Features
SM39R08A3 is an 8-bit micro-controller. All of its functions and the detailed meanings of SFR will be given in the
following sections.
1.1
Embedded Flash
The program can be loaded into the embedded 8KB+1KB Flash memory via its writer or In-System Programming (ISP).
The high-quality Flash has a 100K-write cycle life，suitable for re-programming and data recording as EEPROM.
1.2
IO Pads
The SM39R08A3 has Three I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0, 1, 2 are 8-bit ports and Port 3 is a 2-bit
port. These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. As description
in section 5.
All the pads for P0、P1、P2 and P3 are with slew rate to reduce EMI. The IO pads can withstand 4KV ESD in human
body mode guaranteeing the SM39R08A3 is quality in high electro-static environments.
The RESET Pin can define as General I/O P1.5 when user use Internal RESET.
The XTAL2 and XTAL1 can define as P3.0 and P3.1 by writer or ISP，when user use internal OSC as system clock；
when user use external OSC as system clock and input into XTAL1，Only XTAL2 can be defined as P3.0.
1.3
Instruction timing Selection
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM39R08A3 is a 1T to 8T
MCU, i.e., its machine cycle is one-clock to eight-clock. In the other words, it can execute one instruction within one
clock to only eight clocks.
Mnemonic: CKCON
7
6
5
ITS[2:0]
4
3
-
2
-
Address: 8Eh
1
0
Reset
CLKOUT[1:0]
10H
ITS: Instruction timing select.
ITS [2:0]
Instruction timing
000
1T mode
001
2T mode (default)
010
3T mode
011
4T mode
100
5T mode
101
6T mode
110
7T mode
111
8T mode
The default is in 2T mode, and it can be changed to another Instruction timing mode if CKCON [6:4] (at
address 8Eh) is change any time. Not every instruction can be executed with one machine cycle. The exact
machine cycle number for all the instructions are given in the next section.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 12 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
1.4
The Clock Out Selection
The SM39R08A3 can Generator a clock out signal at P3.0， when user use Oscillator (XTAL1 as clock input) or
internal OSC as system clock. The CKCON [1:0] (at address 8Eh) can change any time.
CLKOUT: Clock output select.
CKCON [1:0]
00
01
10
11
1.5
Mode.
GPIO(default)
Fosc
Fosc/2
Fosc/4
RESET
1.5.1
Hardware RESET function
SM39R08A3 provides Internal reset circuit inside，the Internal reset time can set by writer or ISP.。
Internal Reset time
25ms (default)
200ms
100ms
50ms
16ms
8ms
4ms
1.5.2
Software RESET function
SM39R08A3 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware
must write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset
register (SWRES) write attribute. After SWRES register obtain the write authority, the firmware can write FFh to the
SWRES register. The hardware will decode a reset signal that “OR” with the other hardware reset. The SWRES
register is self-reset at the end of the software reset procedure.
Mnemonic
Description
Addr
ess
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
WDTF
SWRF
LVRF
PORF
00H
Software Reset function
RSTS
TAKEY
SWRES
Reset
status
register
Time Access Key
register
Software
Reset
register
A1h
-
-
-
PDRF
F7h
TAKEY [7:0]
00H
E7h
SWRES [7:0]
00H
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ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 13 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
1.5.3
Reset status
Mnemonic: RSTS
7
6
-
5
-
4
PDRF
3
WDTF
2
SWRF
1
LVRF
Address: A1h
0
Reset
PORF
00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag
clear by software.
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software.
SWRF: Software reset flag.
When MCU is reset by software, SWRF flag will be set to one by hardware. This flag
clear by software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear
by software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear
by software.
1.5.4
Time Access Key register (TAKEY)
Mnemonic: TAKEY
7
6
5
4
3
TAKEY [7:0]
2
1
Address: F7H
0
Reset
00H
Software reset register (SWRES) is read-only by default; software must write three specific values 55h, AAh
and 5Ah sequentially to the TAKEY register to enable the SWRES register write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
1.5.5
Software Reset register (SWRES)
Mnemonic: SWRES
7
6
5
4
3
SWRES [7:0]
2
1
Address: E7H
0
Reset
00H
SWRES[7:0]: Software reset register bit. These 8-bit is self-reset at the end of the reset procedure.
SWRES [7:0] = FFh, software reset.
SWRES [7:0] = 00h ~ FEh, MCU no action.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 14 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
1.5.6
Example of software reset
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah; enable SWRES write attribute
MOV SWRES, #0FFh ; software reset MCU
1.6
Clocks
The default clock is the 22.1184MHz Internal OSC. This clock is used during the initialization stage. The major work of
the initialization stage is to determine the clock source used in normal operation.
The internal clock sources are from the internal OSC with difference frequency division as given in Table 1-1，the
clock source can set by writer or ICP..
Table 1-1: Selection of clock source
Clock source
external crystal (use XTAL1 and XTAL2 pins )
external crystal (only use XTAL1, the XTAL2 define as I/O)
22.1184MHz from internal OSC
22.1184MHz/2 from internal OSC
22.1184MHz/4 from internal OSC
22.1184MHz/8 from internal OSC
22.1184MHz/16 from internal OSC
There may be having a little variance in the frequency from the internal OSC. The max variance as giving in Table 1-2
Table 1-2: Temperature with variance
Temperature Max Variance
25℃
±2%
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Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 15 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
2. Instruction Set
All SM39R08A3 instructions are binary code compatible and perform the same functions as they do with the industry
standard 8051. The following tables give a summary of the instruction set cycles of the SM39R08A3 Microcontroller
core.
Mnemonic
ADD A,Rn
ADD A,direct
Table 2-1: Arithmetic operations
Description
Add register to accumulator
Add direct byte to accumulator
Code
28-2F
25
Bytes
1
2
Cycles
1
2
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
26-27
24
38-3F
35
1
2
1
2
2
2
1
2
ADDC A,@Ri
Add indirect RAM to A with carry flag
36-37
1
2
ADDC A,#data
SUBB A,Rn
SUBB A,direct
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
34
98-9F
95
2
1
2
2
1
2
SUBB A,@Ri
SUBB A,#data
INC A
INC Rn
INC direct
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
Increment register
Increment direct byte
96-97
94
04
08-0F
05
1
2
1
1
2
2
2
1
2
3
INC @Ri
INC DPTR
DEC A
Increment indirect RAM
Increment data pointer
Decrement accumulator
06-07
A3
14
1
1
1
3
1
1
DEC Rn
Decrement register
18-1F
1
2
DEC direct
DEC @Ri
MUL AB
DIV
DA A
Decrement direct byte
Decrement indirect RAM
Multiply A and B
Divide A by B
Decimal adjust accumulator
15
16-17
A4
84
D4
2
1
1
1
1
3
3
5
5
1
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ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 16 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic
ANL A,Rn
ANL A,direct
Table 2-2: Logic operations
Description
AND register to accumulator
AND direct byte to accumulator
Code
58-5F
55
Bytes
1
2
Cycles
1
2
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
56-57
54
52
53
1
2
2
3
2
2
3
4
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,#data
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
48-4F
45
46-47
44
1
2
1
2
1
2
2
2
ORL direct,A
ORL direct,#data
XRL A,Rn
XRL A,direct
OR accumulator to direct byte
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
42
43
68-6F
65
2
3
1
2
3
4
1
2
XRL A,@Ri
Exclusive OR indirect RAM to accumulator
66-67
1
2
XRL A,#data
XRL direct,A
XRL direct,#data
Exclusive OR immediate data to accumulator
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
64
62
63
2
2
3
2
3
4
CLR A
Clear accumulator
E4
1
1
CPL A
RL A
RLC A
RR A
Complement accumulator
Rotate accumulator left
Rotate accumulator left through carry
Rotate accumulator right
F4
23
33
03
1
1
1
1
1
1
1
1
RRC A
SWAP A
Rotate accumulator right through carry
Swap nibbles within the accumulator
13
C4
1
1
1
1
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ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 17 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic
MOV A,Rn
MOV A,direct
Table 2-3: Data transfer
Description
Move register to accumulator
Move direct byte to accumulator
Code
E8-EF
E5
Bytes
1
2
Cycles
1
2
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV Rn,direct
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
E6-E7
74
F8-FF
A8-AF
1
2
1
2
2
2
2
4
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct1,direct2
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
78-7F
F5
88-8F
85
2
2
2
3
2
3
3
4
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
86-87
75
F6-F7
A6-A7
2
3
1
2
4
3
3
5
MOV @Ri,#data
Move immediate data to indirect RAM
76-77
2
3
MOV DPTR,#data16
Load data pointer with a 16-bit constant
90
3
3
MOVC A,@A+DPTR
MOVC A,@A+PC
PUSH direct
Move code byte relative to DPTR to accumulator
Move code byte relative to PC to accumulator
Push direct byte onto stack
93
83
C0
1
1
2
3
3
4
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low-order nibble indir. RAM with A
D0
C8-CF
C5
C6-C7
D6-D7
2
1
2
1
1
3
2
3
3
3
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 18 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic
ACALL addr11
LCALL addr16
Table 2-4: Program branches
Description
Absolute subroutine call
Long subroutine call
Code
xxx11
12
Bytes
2
3
Cycles
6
6
RET
RETI
AJMP addr11
LJMP addr16
from subroutine
from interrupt
Absolute jump
Long iump
22
32
xxx01
02
1
1
2
3
4
4
3
4
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
Short jump (relative addr.)
Jump indirect relative to the DPTR
Jump if accumulator is zero
Jump if accumulator is not zero
80
73
60
70
2
1
2
2
3
2
3
3
JC rel
JNC
JB bit,rel
JNB bit,rel
Jump if carry flag is set
Jump if carry flag is not set
Jump if direct bit is set
Jump if direct bit is not set
40
50
20
30
2
2
3
3
3
3
4
4
JBC bit,direct rel
Jump if direct bit is set and clear bit
10
3
4
CJNE A,direct rel
CJNE A,#data rel
CJNE Rn,#data rel
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immed. to reg. and jump if not equal
B5
B4
B8-BF
3
3
3
4
4
4
CJNE @Ri,#data rel
Compare immed. to ind. and jump if not equal
B6-B7
3
4
DJNZ Rn,rel
DJNZ direct,rel
NOP
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
D8-DF
D5
00
2
3
1
3
4
1
CLR C
CLR bit
Table 2-5: Boolean manipulation
Description
Clear carry flag
Clear direct bit
Code
C3
C2
Bytes
1
2
Cycles
1
3
SETB C
SETB bit
CPL C
CPL bit
Set carry flag
Set direct bit
Complement carry flag
Complement direct bit
D3
D2
B3
B2
1
2
1
2
1
3
1
3
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
AND direct bit to carry flag
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
82
B0
72
A0
2
2
2
2
2
2
2
2
MOV C,bit
MOV bit,C
Move direct bit to carry flag
Move carry flag to direct bit
A2
92
2
2
2
3
Mnemonic
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ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 19 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
3. Memory Structure
The SM39R08A3 memory structure follows general 8052 structure. It is 8KB+1KB program memory.
3.1
Program Memory
The SM39R08A3 has 8KB+1KB on-chip flash memory which can be used as general program memory or EEPROM,
on which include up to 1K byte specific ISP service program memory space. The address range for the 16K byte is
$0000 to $3FFF. The address range for the ISP service program is $3C00 to $3FFF. The ISP service program size can
be partitioned as N blocks of 128 byte (N=0 to 8). When N=0 means no ISP service program space available, total
8KB+1KB memory used as program memory. When N=1 means address $3F80 to $3FFF reserved for ISP service
program. When N=2 means memory address $3F00 to $3FFF reserved for ISP service program…etc. Value N can be
set and programmed into SM39R08A3 by the writer or ICP. It can be used to record any data as EEPROM(If you need
modify the data on program memory, please page erase first ). The procedure of this EEPROM application function is
described in the section 18 on internal ISP。
ISP service
Program space,
Up to 1K
3FFF
3F80
3F00
3E80
3E00
3D80
3D00
3C80
3C00
N=0
N=1
N=2
N=3
N=4
N=5
N=6
N=7
N=8
1FFF
8K Program
Memory space
0000
Fig. 3-1: SM39R08A3 programmable Flash
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ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 20 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
3.2
Data Memory
The SM39R08A3 has 512B on-chip SRAM; as below Fig. 3-2; 256 Bytes of it are the same as general 8052 internal
memory structure.
FF
FF
80
7F
00
Higher 128 Bytes (Accessed by
indirect addressing mode only)
SFR (Accessed by direct
addressing mode only)
FF
Expanded 256 Bytes
(Accessed by direct
external addressing
mode by instruction
MOVX)
80
Lower 128 Bytes (Accessed by
direct & indirect addressing
mode )
00
Fig. 3-2: RAM architecture
3.3
Data memory - lower 128 byte (00h to 7Fh)
Data memory 00h to FFh is the same as 8052.
The address 00h to 7Fh can be accessed by direct and indirect addressing modes.
Address 00h to 1Fh is register area.
Address 20h to 2Fh is memory bit area.
Address 30h to 7Fh is for general memory area.
3.4
Data memory - higher 128 byte (80h to FFh)
The address 80h to FFh can be accessed by indirect addressing mode.
Address 80h to FFh is data area.
3.5
Data memory - Expanded 256 bytes ($00 到 $FF)
From external address 00h to FFh is the on-chip expanded SRAM area, total 256 Bytes. This area can be accessed by
external direct addressing mode (by instruction MOVX).
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ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 21 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
4. CPU Engine
The SM39R08A3 engine is composed of four components:
(1) Control unit
(2) Arithmetic – logic unit
(3) Memory control unit
(4) RAM and SFR control unit
The SM39R08A3 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The
following chapter describes the main engine register.
Mnemonic
Description
Dir.
Bit 7
ACC
B
Accumulator
B register
Program status
word
Stack Pointer
Data pointer low 0
Data pointer high
0
Data pointer low 0
Data pointer high
0
Auxiliary register
Clock control
register
Interface control
register
E0h
F0h
ACC.7
B.7
D0h
CY
PSW
SP
DPL
DPH
DPL1
DPH1
AUX
CKCON
IFCON
4.1
Bit 6
Bit 5
8051 Core
ACC.6 ACC.5
B.6
B.5
AC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
ACC.4
B.4
ACC.3
B.3
ACC.2
B.2
ACC.1
B.1
ACC.0
B.0
00H
00H
OV
PSW.1
P
00H
F0
RS[1:0]
81h
82h
SP[7:0]
DPL[7:0]
07H
00H
83h
DPH[7:0]
00H
84h
DPL1[7:0]
00H
85h
DPH1[7:0]
00H
91h
BRGS
8Eh
-
8Fh
-
-
-
-
-
-
ITS[2:0]
CDPR
-
-
-
-
-
DPS
00H
CLKOUT[1:0]
10H
-
ISPE
00H
Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC
7
6
5
ACC.7 ACC.6 ACC05
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
Address: E0h
0
Reset
ACC.0
00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator。
4.2
B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store
temporary data.
Mnemonic: B
7
6
B.7
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
Address: F0h
0
Reset
B.0
00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 22 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
4.3
Program Status Word
Mnemonic: PSW
7
6
CY
AC
5
F0
4
3
RS [1:0]
2
OV
1
F1
Address: D0h
0
Reset
P
00h
CY: Carry flag.
AC: Auxiliary Carry flag for BCD operations.
F0: General purpose Flag 0 available for user.
RS[1:0]
00
01
10
11
Bank Selected
Bank 0
Bank 1
Bank 2
Bank 3
Location
00h – 07h
08h – 0Fh
10h – 17h
18h – 1Fh
OV: Overflow flag.
F1: General purpose Flag 1 available for user.
P: Parity flag, affected by hardware to indicate odd/even number of “one” bits in the
Accumulator, i.e. even parity
4.4
Stack Pointer
The stack pointer is a 1-byte register initialized to 07h after reset. This register is incremented before PUSH and CALL
instructions, causing the stack to start from location 08h.
Mnemonic: SP
7
6
5
4
3
2
1
SP [7:0]
Address: 81h
0
Reset
07h
SP[7:0]: The Stack Pointer stores the scratchpad RAM address where the stack begins. In other
words, it always points to the top of the stack.
4.5
Data Pointer
The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte
register (e.g. MOV DPTR, #data16) or as two separate registers (e.g. MOV DPL,#data8). It is generally used to access
the external code or data space (e.g. MOVC A, @A+DPTR, @DPTR respectively).
Mnemonic: DPL
7
6
5
3
DPL [7:0]
2
1
Address: 82h
0
Reset
00h
4
3
DPH [7:0]
2
1
Address: 83h
0
Reset
00h
4
DPL[7:0]: Data pointer Low 0
Mnemonic: DPH
7
6
5
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 23 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
DPH [7:0]: Data pointer High 0
4.6
Data Pointer 1
The Dual Data Pointer accelerates the moves of data block. The standard DPTR is a 16-bit register that is used to
address external memory or peripherals. In the SM39R08A3 core the standard data pointer is called DPTR, the second
data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is
located in LSB of AUX register (DPS).
The user switches between pointers by toggling the LSB of AUX register. All DPTR-related instructions use the
currently selected DPTR for any activity.
Mnemonic: DPL1
7
6
5
4
3
DPL1 [7:0]
2
1
Address: 84h
0
Reset
00h
4
3
DPH1 [7:0]
2
1
Address: 85h
0
Reset
00h
4
-
3
-
2
-
1
-
3
-
2
-
DPL1[7:0]: Data pointer Low 1
Mnemonic: DPH1
7
6
5
DPH1[7:0]: Data pointer High 1
Mnemonic: AUX
7
6
BRGS
-
5
-
Address: 91h
0
Reset
DPS
00H
DPS: Data Pointer select register.
DPS = 1 is selected DPTR1.
4.7
Clock control register
Mnemonic: CKCON
7
6
5
ITS[2:0]
4
Address: 8Eh
1
0
Reset
CLKOUT[1:0]
10H
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 24 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
ITS[2:0]: Instruction timing select.
ITS [2:0]
Mode
000
1T mode
001
2T mode (default)
010
3T mode
011
4T mode
100
5T mode
101
6T mode
110
7T mode
111
8T mode
CLKOUT: Clock output select.
CKCON [1:0]
Mode.
00
GPIO(default)
01
Fosc
10
Fosc/2
11
Fosc/4
It can be used when the system clock is the internal RC oscillator.
4.8
Interface control register
Mnemonic: IFCON
7
6
5
CDPR
-
4
-
3
-
2
-
1
-
Address: 8Fh
0
Reset
ISPE
00H
CDPR: Code protect (Read Only)
ISPE: ISP function enable bit
ISPE = 1, enable ISP function
ISPE = 0, disable ISP function
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 25 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
5. GPIO
The SM39R08A3 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1, 2 are 8-bit ports and Port 3 is a 2-bit
port. These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. Two
configuration registers for each port select the output type for each port pin. All I/O port pins on the SM39R08A3 may
be configured by software to one of four types on a pin-by-pin basis, shown as below:
Mnemonic
Description
Dir.
P0M0
P0M1
P1M0
P1M1
P3M0
P3M1
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 3 output mode 0
Port 3 output mode 1
D2h
D3h
D4h
D5h
DAh
DBh
PxM1.y
0
0
1
1
PxM0.y
0
1
0
1
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
I/O port function register
P0M0 [7:0]
P0M1[7:0]
P1M0[7:0]
P1M1[7:0]
Bit 2
Bit 1
Bit 0
P3M0[1:0]
P3M1[1:0]
RST
00H
00H
00H
00H
00H
00H
Port output mode
Quasi-bidirectional (standard 8051 port outputs) (pull-up)
Push-pull
Input only (high-impedance)
Open drain
The RESET Pin can define as General I/O P1.5 when user use Internal RESET.
The XTAL2 and XTAL1 can define as P3.0 and P3.1 by writer or ISP，when user use internal OSC as system clock；
when user use external OSC as system clock and input into XTAL1，Only XTAL2 can be defined as P3.0.
For general-purpose applications, every pin can be assigned to either high or low independently as given below:
Mnemonic
Description
Dir.
Bit 7
Port 3
Port 1
Port 0
Port 3
Port 1
Port 0
B0h
90h
80h
P1.7
P0.7
Mnemonic: P0
7
6
P0.7
P0.6
5
P0.5
Bit 6
Bit 5
Ports
P1.6
P1.5
P0.6
P0.5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
P1.4
P0.4
P1.3
P0.3
P1.2
P0.2
P3.1
P1.1
P0.1
P3.0
P1.0
P0.0
FFh
FFh
FFh
4
P0.4
3
P0.3
2
P0.2
1
P0.1
Address: 80h
0
Reset
P0.0
FFh
4
P1.4
3
P1.3
2
P1.2
1
P1.1
Address: 90h
0
Reset
P1.0
FFh
P0.7~ 0: Port0 [7] ~ Port0[0]
Mnemonic: P1
7
6
P1.7
P1.6
P1.7~ 0:
5
P1.5
Port1 [7] ~ Port1 [0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 26 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: P3
7
6
-
5
-
4
-
3
-
2
-
1
P3.1
Address: B0h
0
Reset
P3.0
FFh
P3.1~ 0: Por3 [1] ~ Port3 [0]
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 27 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
6. Timer 0 and Timer 1
The SM39R08A3 has three 16-bit timer/counter registers: Timer 0, Timer 1 and Timer 2. All can be configured for
counter or timer operations.
In timer mode, the Timer 0 register or Timer 1 register is incremented every 1/12/96 machine cycles, which means that
it counts up after every 1/12/96 periods of the clk signal. It‟s dependent on SFR(PFCON).
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0or T1.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator
frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input
should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function registers (TMOD and TCON) are
used to select the appropriate mode.
Mnemonic
Description
Dir.
TL0
TH0
TL1
TH1
Timer 0, low byte
Timer 0, high byte
Timer 1, lowbyte
Timer 1, high byte
8Ah
8Ch
8Bh
8Dh
TMOD
Timer Mode
Control
89h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
TCON
Timer/Counter
Control
Peripheral
Frequency control
register
88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
D9h
-
-
PFCON
6.1
Bit 7
Bit 6
Bit 5
Timer 0 and 1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TL0[7:0]
TH0[7:0]
TL1[7:0]
TH1[7:0]
SRELPS[1:0]
RST
00H
00H
00H
00H
T1PS[1:0]
T0PS[1:0]
00H
Timer/counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE
C/T
M1
Timer 1
4
M0
3
GATE
2
1
C/T
M1
Timer 0
Address: 89h
0
Reset
M0
00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON
register), a counter is incremented every falling edge on T0 or T1 input pin.
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is
performed, when cleared to 0, the corresponding register will function as a
timer.
M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 28 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
6.2
M1
0
M0
0
Mode
Mode0
0
1
1
0
Mode1
Mode2
1
1
Mode3
Function
13-bit counter/timer, with 5 lower bits in TL0 or TL1
register and 8 bits in TH0 or TH1 register (for Timer 0
and Timer 1, respectively). The 3 high order bits of TL0
and TL1 are hold at zero.
16-bit counter/timer.
8 -bit auto-reload counter/timer. The reload value is kept
in TH0 or TH1, while TL0 or TL1 is incremented every
machine cycle. When TLx overflows, a value from THx
is copied to TLx.
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. If
Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as
two independent 8 bit timers / counters.
Timer/counter control register (TCON)
Mnemonic: TCON
7
6
5
TF1
TR1
TF0
4
TR0
3
IE1
2
IT1
1
IE0
Address: 88h
0
Reset
IT0
00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin
INT1 is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt. IT1=1, interrupt 1 select falling edge trigger. IT1=0, interrupt1
select low level trigger.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin
INT0 is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt. IT0=1, interrupt 0 select falling edge trigger. IT0=0, interrupt
0 select low level trigger.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 29 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
6.3
Peripheral Frequency control register
Mnemonic: PFCON
7
6
5
4
SRELPS[1:0]
6.4
Address: D9h
1
0
Reset
T0PS[1:0]
00H
3
2
T1PS[1:0]
T1PS[1:0]: Timer1 Prescaler select
T1PS[1:0]
00
01
10
11
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
T0PS[1:0]: Timer0 Prescaler select
T0PS[1:0]
00
01
10
11
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
Mode 0 (13-bit Counter/Timer)
÷12
OSC
00
01
÷96
10
C/T = 1
T1PS[1:0]
T1 pin
TR1
GATE1
ET1
C/T = 0
TL1
TH1
(5 Bits) (8 Bits)
0
0
1
1
Control
If not higher priority
Interrupt Processing
AND
NOT
TF1
EA
Jump
001BH
OR
INT1 pin
D0D1D2D3D4
D5D6D7
TL1
D0D1D2D3D4D5D6D7
TF1
TH1
Fig. 6-1: Mode 0 -13 bit Timer / counter operation
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 30 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
6.5
Mode 1 (16-bit Counter/Timer)
Fig. 6-2: Mode 1 -16 bit Timer / counter operation
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 31 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
6.6
Mode 2 (8-bit auto-reload Counter/Timer)
÷12
00
OSC
01
÷96
ET1
C/T = 0
10
TL1
(8 Bits)
C/T = 1
TR1
Auto
Reload
AND
GATE1
NOT
0
1
1
Control
T1PS[1:0]
T1 pin
0
TF1
EA
OR
If not higher priority
Interrupt Processing
TH1
(8 Bits)
INT1 pin
Jump
001BH
Fig. 6-3: Mode 2 8 bit Auto-reload Counter/Timer
6.7
Mode 3 (Timer 0 acts as two independent 8 bit Timers / Counters)
÷12
00
TH0
(8 Bits)
TF1
Interrupt
Request
(001BH)
TL0
(8 Bits)
TF0
Interrupt
Request
(000BH)
TR1
OSC
01
÷96
C/T = 0
10
C/T = 1
T0PS[1:0]
T0 pin
TR0
GATE0
Control
AND
NOT
OR
/INT0 pin
Fig. 6-4: Mode 3 - two independent 8 bit Timers / Counters (Only Timer 0)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 32 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
7. Timer 2 and Capture Compare Unit
Timer 2 is not only a 16-bit timer, also a 4-channel unit with compare, capture and reload functions. It is very similar to
the programmable counter array (PCA) in some other MCUs except pulse width modulation (PWM).
Mnemoni
c
T2CON
CCCON
CCEN
CCEN2
TL2
TH2
CRCL
CRCH
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
Description
Dir.
Timer 2 control
Compare/Capture
Control
Compare/Capture
Enable register
Compare/Capture
Enable 2 register
Timer 2, low byte
Timer 2, high byte
Compare/Reload/
Capture register,
low byte
Compare/Reload/
Capture register,
high byte
Compare/Capture
register 1, low
byte
Compare/Capture
register 1, high
byte
Compare/Capture
register 2, low
byte
Compare/Capture
register 2, high
byte
Compare/Capture
register 3, low
byte
Compare/Capture
register 3, high
byte
C8h
C9h
Bit 7
Bit 5
Bit 4
Bit 3
Timer 2 and Capture Compare Unit
T2PS[2:0]
T2R[1:0]
CCI3
C1h
D1h
Bit 6
-
CCI2
CCI1
CCI0
Bit 2
-
CCF3
CCF2
Bit 1
Bit 0
RST
T2I[1:0]
CCF
CCF1
0
00H
00H
COCAM1[2:0]
-
COCAM0[2:0]
00H
COCAM3[2:0]
-
COCAM2[2:0]
00H
CCh
CDh
TL2[7:0]
TH2[7:0]
CAh
CRCL[7:0]
CBh
CRCH[7:0]
C2h
CCL1[7:0]
C3h
CCH1[7:0]
C4h
CCL2[7:0]
C5h
CCH2[7:0]
C6h
CCL3[7:0]
C7h
CCH3[7:0]
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 33 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: T2CON
7
6
5
T2PS[2:0]
T2PS[2:0]:
4
3
T2R[1:0]
2
-
1
Address: C8h
0
Reset
T2I[1:0]
00H
Prescaler select bit:
T2PS = 000 – timer 2 is clocked with the oscillator frequency.
T2PS = 001 – timer 2 is clocked with 1/2 of the oscillator frequency.
T2PS = 010 – timer 2 is clocked with 1/4 of the oscillator frequency.
T2PS = 011 – timer 2 is clocked with 1/6 of the oscillator frequency.
T2PS = 100 – timer 2 is clocked with 1/8 of the oscillator frequency.
T2PS = 101 – timer 2 is clocked with 1/12 of the oscillator frequency.
T2PS = 110 – timer 2 is clocked with 1/24 of the oscillator frequency.
T2R[1:0]:
Timer 2 reload mode selection
T2R[1:0] = 0X – Reload disabled
T2R[1:0] = 10 – Mode 0: Auto Reload
T2R[1:0] = 11 – Mode 1: T2EX Falling Edge Reload
T2I[1:0]:
Timer 2 input selection
T2I[1:0] = 00 – Timer 2 stop
T2I[1:0] = 01 – Input frequency from prescaler (T2PS[2:0])
T2I[1:0] = 10 – Timer 2 is incremented by external signal at pin T2
T2I[1:0] = 11 – internal clock input is gated to the Timer 2
Mnemonic: CCCON
7
6
5
CCI3
CCI2
CCI1
4
CCI0
3
CCF3
2
CCF2
1
CCF1
Address: C9h
0
Reset
CCF0
00H
CCI3: Compare/Capture 3 interrupt control bit.
“1” is enable.
CCI2: Compare/Capture 2 interrupt control bit.
“1” is enable.
CCI1: Compare/Capture 1 interrupt control bit.
“1” is enable.
CCI0: Compare/Capture 0 interrupt control bit.
“1” is enable.
CCF3: Compare/Capture 3 flag set by hardware. This flag can be cleared by software.
CCF2: Compare/Capture 2 flag set by hardware. This flag can be cleared by software.
CCF1: Compare/Capture 1 flag set by hardware. This flag can be cleared by software.
CCF0: Compare/Capture 0 flag set by hardware. This flag can be cleared by software.
Compare/Capture interrupt share T2 interrupt vector.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 34 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: CCEN
7
6
5
4
COCAM1[2:0]
3
-
2
Address: C1h
1
0
Reset
COCAM0[2:0]
00H
COCAM1[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC1
101: Capture on falling edge at pin CC1
110: Capture on both rising and falling edge at pin CC1
111: Capture on write operation into register CC1
COCAM0[2:0] 000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC0
101: Capture on falling edge at pin CC0
110: Capture on both rising and falling edge at pin CC0
111: Capture on write operation into register CC0
Mnemonic: CCEN2
7
6
5
4
COCAM3[2:0]
COCAM3[2:0]
3
-
2
Address: D1h
1
0
Reset
COCAM2[2:0]
00H
000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC3
101: Capture on falling edge at pin CC3
110: Capture on both rising and falling edge at pin CC3
111: Capture on write operation into register CC3
COCAM2[2:0]
000: Compare/Capture disable
001: Compare enable but no output on Pin
010: Compare mode 0
011: Compare mode 1
100: Capture on rising edge at pin CC2
101: Capture on falling edge at pin CC2
110: Capture on both rising and falling edge at pin CC2
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 35 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
111: Capture on write operation into register CC2
7.1
Timer 2 function
Timer 2 can operate as timer, event counter, or gated timer as explained later.
7.1.1
Timer mode
As below Fig. 7-1; In this mode Timer 2 can by incremented in various frequency that depending on the prescaler. The
prescaler is selected by bit T2PS[2:0] in register T2CON.
Fig. 7-1: Timer mode and Reload mode function
7.1.2
Event counter mode
As below Fig. 7-2; In this mode, the timer is incremented when external signal T2 change value from 1 to 0. The T2
input is sampled in every cycle. Timer 2 is incremented in the cycle following the one in which the transition was
detected.
Fig. 7-2: Event counter mode function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 36 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
7.1.3
Gated timer mode
As below Fig. 7-3; In this mode, the internal clock which incremented timer 2 is gated by external signal T2.
Fig. 7-3: Gated timer mode function
7.1.4
Reload of Timer 2
Reload (16-bit reload from the crc register) can be executed in the following two modes:
Mode 0: Reload signal is generate by a Timer 2 overflows - auto reload
Mode 1: Reload signal is generate by a negative transition at the corresponding input pin T2EX.
7.2
Compare function
In the four independent comparators, the value stored in any compare/capture register is compared with the contents
of the timer register. The compare modes 0 and 1 are selected by bits C0CAMx . In both compare modes, the results
of comparison arrives at Port 1 within the same machine cycle in which the internal compare signal is activated.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 37 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
7.2.1
Compare Mode 0
As below Fig. 7-4; In mode 0, when the value in Timer 2 equals the value of the compare register, the output signal
changes from low to high. It goes back to a low level on timer overflow. In this mode, writing to the port will have no
effect, because the input line from the internal bus and the write-to-latch line are disconnected. The following figure
illustrates the function of compare mode 0.
Contents of
Timer 2
CRC or CCx
Reload value
CCx Output
Timer 2 = CCx value
Timer 2 overflow
Fig. 7-4: Compare mode 0 function
7.2.2
Compare Mode 1
In compare mode 1, the transition of the output signal can be determined by software. A timer 2 overflow causes no
output change. In this mode, both transitions of a signal can be controlled. Fig. 7-5 shows a functional diagram of a
register/port configuration in compare Mode 1. In compare Mode 1, the value is written first to the “Shadow Register”,
when compare signal is active, this value is transferred to the output register.
Contents of
Timer 2
CRC or CCx
Reload value
CCx Output
Output register
Shadow register
CCx Output
Timer 2 = CCx value
Fig. 7-5: Comparison mode 1 function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 38 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
7.3
Capture function
Actual timer/counter contents can be saved into registers CCx or CRC upon an external event (mode 0) or a software
write operation (mode 1).
7.3.1
Capture Mode 0 (by Hardware)
As below Fig. 7-6; In mode 0, value capture of Timer 2 is executed when:
(1) Rising edge on input CC0-CC3
(2) Falling edge on input CC0-CC3
(3) Both rising and falling edge on input CC0-CC3
The contents of Timer 2 will be latched into the appropriate capture register.
Fig. 7-6: Capture mode 0
7.3.2
Capture Mode 1(by Software)
As below Fig. 7-7; In mode 1, value capture of timer 2 is caused by writing any value into the low-order byte of the
dedicated capture register. The value written to the capture register is irrelevant to this function. The contents of Timer
2 will be latched into the appropriate capture register.
Fig. 7-7: Capture mode 1 function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 39 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
8. Serial interface
The serial buffer consists of two separate registers, a transmit buffer and a receive buffer.
Writing data to the Special Function Register SBUF sets this data in serial output buffer and starts the transmission.
Reading from the SBUF reads data from the serial receive buffer. The serial port can simultaneously transmit and
receive data. It can also buffer 1 byte at receive, which prevents the receive data from being lost if the CPU reads the
first byte before transmission of the second byte is completed.
Mnemonic
Description
Address
Bit 7
PCON
AUX
Power control
Auxiliary register
Serial Port control
register
Serial Port reload
register low byte
Serial Port reload
register high byte
Serial Port data
buffer
Peripheral
Frequency control
register
87H
91h
SMOD
BRGS
98H
SM0
SM1
SM2
AAH
SREL.7
SREL.6
BAH
-
-
SCON
SRELL
SRELH
SBUF
PFCON
Bit 6
Bit 5
Bit 4
Serial interface 0 and 1
-
Bit 3
Bit 2
Bit 1
Bit 0
RST
-
-
STOP
-
IDLE
DPS
00H
00H
REN
TB8
RB8
TI
RI
00H
SREL.5
SREL.4
SREL.3
SREL.2
SREL.1
SREL.0
00H
-
-
-
-
SREL.9
SREL.8
00H
99H
SBUF[7:0]
D9h
Mnemonic: AUX
7
6
BRGS
-
-
5
-
-
4
-
SRELPS[1:0]
00H
T1PS[1:0]
T0PS[1:0]
2
-
1
-
Address: 91h
0
Reset
DPS
00H
2
RB8
1
TI
Address: 98h
0
Reset
RI
00h
3
-
00H
BRGS: BRGS = 0 – baud rate generator from Timer 1.
BRGS = 1 – baud rate generator by SREL.
Mnemonic: SCON
7
6
5
SM0
SM1
SM2
4
REN
3
TB8
SM0,SM1: Serial Port 0 mode selection.
SM0 SM1
Mode
0
0
0
0
1
1
1
0
2
1
1
3
The 4 modes in UART, Mode 0 ~ 3, are explained later.
SM2: Enables multiprocessor communication feature
REN: If set, enables serial reception. Cleared by software to disable reception.
th
The 9 transmitted data bit in modes 2 and 3. Set or cleared by the CPU
TB8:
depending on the function it performs such as parity check, multiprocessor
communication etc.
In modes 2 and 3, it is the 9th data bit received. In mode 1, if SM2 is 0, RB8 is
RB8:
the stop bit. In mode 0, this bit is not used. Must be cleared by software.
TI: Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 40 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
RI: Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
8.1
Serial interface
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Board Rate
Fosc/12
Variable
Fosc/32 or Fosc/64
Variable
Here Fosc is the crystal or oscillator frequency.
8.1.1
Mode 0
As below Figure. Pin RXD serves as input and output. TXD outputs the shift clock. 8 bits are transmitted with LSB first.
The baud rate is fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting the flags in SCON
as follows: RI = 0 and REN = 1. In other modes, a start bit when REN = 1 starts receiving serial data.
Fig. 8-1: Transmit mode 0
Fig. 8-2: Receive mode 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 41 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
8.1.2
Mode 1
As below Figure.Pin RXD serves as input, and TXD serves as serial output. No external shift clock is used, 10 bits are
transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes
the transmission, 8 data bits are available by reading SBUF, and stop bit sets the flag RB8 in the Special Function
Register SCON. In mode 1 either internal baud rate generator or timer 1 can be use to specify baud rate.
Fig. 8-3: Transmit mode 1
Fig. 8-4: Receive mode 0
8.1.3
Mode 2
This mode is similar to Mode 1, with two differences. The baud rate is fixed at 1/32 (SMOD=1) or 1/64(SMOD=0) of
oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9 th bit,
and a stop bit (1). The 9th bit can be used to control the parity of the serial interface: at transmission, bit TB8 in SCON
is output as the 9th bit, and at receive, the 9th bit affects RB8 in Special Function Register SCON.
8.1.4
Mode 3
As below Figure. The only difference between Mode 2 and Mode 3 is that in Mode 3 either internal baud rate generator
or timer 1 can be use to specify baud rate.
Fig. 8-5: Transfer Mode 2 and Mode 3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 42 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Fig. 8-6: The receiving modes 2 and 3
8.2
Multiprocessor Communication of Serial Interface
The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface can be used for multiprocessor communication. In
this case, the slave processors have bit SM2 in SCON set to 1. When the master processor outputs slave‟s address, it
th
sets the 9 bit to 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received
byte with their network address. If there is a match, the addressed slave will clear SM2 and receive the rest of the
message, while other slaves will leave SM2 bit unaffected and ignore this message. After addressing the slave, the
th
host will output the rest of the message with the 9 bit set to 0, so no serial port receive interrupt will be generated in
unselected slaves.
8.3
Peripheral Frequency control register
Mnemonic: PFCON
7
6
5
4
SRELPS[1:0]
SRELPS[1:0]: SREL Prescaler select
SRELPS[1:0]
00
01
10
11
T1PS[1:0]: Timer1 Prescaler select
T1PS[1:0]
00
01
10
11
8.4
3
2
T1PS[1:0]
Address: D9h
1
0
Reset
T0PS[1:0]
00H
Prescaler
Fosc/64
Fosc /32
Fosc /16
Fosc /8
Prescaler
Fosc/12
Fosc
Fosc/96
reserved
Baud rate generator
8.4.1
Serial interface modes 1 and 3
8.4.1.1
When BRGS = 0 (in Special Function Register AUX).
(1) T1PS[1:0] is 00
Baud Rate
2SMOD Fosc
32 12 256 TH1
(2) T1PS[1:0] is 01
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 43 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Baud Rate
2SMOD Fosc
32 256 TH1
(3) T1PS[1:0] is 10
2SMOD Fosc
Baud Rate
32 96 256 TH1
8.4.1.2
When BRGS = 1 (in Special Function Register AUX).
(1) SRELPS[1:0] is 00
2 SMOD Fosc
Baud Rate
64 210 SREL
2SMOD Fosc
Baud Rate
32 210 SREL
2 SMOD Fosc
16 210 SREL
(2) SRELPS[1:0] is 01
(3) SRELPS[1:0] is 10
Baud Rate
(4) SRELPS[1:0] is 11
2 SMOD Fosc
Baud Rate
8 210 SREL
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 44 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
9. Watchdog timer
The Watch Dog Timer (WDT) is an 8-bit free-running counter that generate reset signal if the counter overflows. The
WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing
software dead loop or runaway. The WDT function can help user software recover from abnormal software condition.
The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by
software periodically clearing the WDT counter. User should check WDTF bit of WDTC register whenever un-predicted
reset happened. After an external reset the watchdog timer is disabled and all registers are set to zeros.
The watchdog timer has a free running on-chip RC oscillator (23 KHz). The WDT will keep on running even after the
system clock has been turned off (for example, in sleep mode). During normal operation or sleep mode, a WDT timeout (if enabled) will cause the MCU to reset. The WDT can be enabled or disabled any time during the normal mode.
Please refer the WDTE bit of WDTC register. The default WDT time-out period is approximately 178.0ms (WDTM [3:0]
= 0100b).
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit3 ~
bit0 (WDTM [3:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
23KHz
2 WDTM
256
Watchdog reset time =
WDTCLK
WDTCLK
Table 9-1: WDT time-out period
Divider
WDTM [3:0]
Time period @ 23KHz
(23 KHz RC oscillator in)
0000
1
11.1ms
0001
2
22.2ms
0010
4
44.5ms
0011
8
89.0ms
0100
16
178.0ms (default)
0101
32
356.1ms
0110
64
712.3ms
0111
128
1.4246s
1000
256
2.8493s
1001
512
5.6987s
1010
1024
11.397s
1011
2048
22.795s
1100
4096
45.590s
1101
8192
91.180s
1110
16384
182.36s
1111
32768
364.72s
Note: RC oscillator (23 KHz), about ± 20% of variation
When MCU is reset, the MCU will be read WDTEN control bit status. When WDTEN bit is set to 1, the watchdog
function will be disabled no matter what the WDTE bit status is. When WDTEN bit is clear to 0, the watchdog function
will be enabled if WDTE bit is set to 1 by program. User can to set WDTEN on the writer or ISP.
The program can enable the WDT function by programming 1 to the WDTE bit premise that WDTEN control bit is clear
to 0. After WDTE set to 1, the 8 bit-counter starts to count with the selected time base source clock which set by
WDTM [3:0]. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when MCU
been reset, either hardware reset or WDT reset.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 45 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter restart to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF
flag can be clear by software or external reset or power on reset.
Clear
WDTF = 0
1. Power on reset
2. External reset
3. Software write “0”
23KHz RC
oscillator
WDTF
Set WDTF = 1
CWDTR = 0
WDTCLK
1
TAKEY
(55, AA, 5A)
2WDTM
WDTM[3:0]
Enable/Disable
WDT
WDT time-out
reset
WDT
time-out
select
WDT
Counter
CWDTR = 1
Refresh
WDT Counter
WDT time-out
Interrupt
WDTC
Enable WDTC
write attribute
WDTK
(0x55)
WDTEN
Fig. 9-1: Watchdog timer block diagram
Mnemon
ic
Description
Addre
ss
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
Watchdog Timer
TAKEY
WDTC
WDTK
RSTS
Time Access
Key register
Watchdog timer
control register
Watchdog timer
refresh key
Reset status
register
F7h
B6h
TAKEY [7:0]
-
CWDTR
WDTE
B7h
A1h
-
00H
WDTM [3:0]
04H
WDTK[7:0]
-
Mnemonic: TAKEY
7
6
5
-
-
4
3
TAKEY [7:0]
PDRF
2
WDTF
1
00H
SWRF
LVRF
PORF
00H
Address: F7h
0
Reset
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific values 55h,
AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 46 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: WDTC
7
6
CWDTR
5
WDTE
4
-
3
2
1
WDTM [3:0]
Address: B6h
0
Reset
04H
CWDTR: Watch dog states select bit(Support stop mode wakeup)
0: Enable watch dog reset.
1: Enable watch dog interrupt.
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
can be disabled / enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read
and written.
WDTM [3:0]: WDT clock source divider bit. Please see Table 9-1 to reference the WDT time-out
period.
Mnemonic: RSTS
7
6
-
5
-
4
PDRF
3
WDTF
2
SWRF
1
LVRF
Address: A1h
0
Reset
PORF
00h
WDTF: Watchdog timer reset flag. When MCU is reset by watchdog, WDTF flag will be set to
one by hardware. This flag clear by software
Mnemonic: WDTK
7
6
5
4
3
WDTK[7:0]
2
1
Address: B7h
0
Reset
00h
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example 1, if enable WDT and select time-out reset period is 2.8493s.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 47 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
.
MOV WDTK, #55h
; Clear WDT timer to 0.
.
.
For example 2, if enable WDT and select time-out Interrupt period is 178.0ms.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
MOV WDTC, #64h
; enable WDTC write attribute.
; Set WDTM [3:0] = 0100b. Set WDTE =1 to enable WDT function
; and Set CWDTR =1 to enable period interrupt function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 48 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
10. Interrupt
The SM39R08A3 provides 14 interrupt sources with four priority levels. Each source has its own request flag(s) located
in a special function register. Each interrupt requested by the corresponding flag could individually be enabled or
disabled by the enable bits in SFR‟s IEN0, IEN1, and IEN2.
When the interrupt occurs, the engine will vector to the predetermined address as shown in Table 10-1. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a
return from instruction RETI. When an RETI is performed, the processor will return to the instruction that would have
been next when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless
of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, and then
samples are polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then
interrupt request flag is set. On the next instruction cycle the interrupt will be acknowledged by hardware forcing an
LCALL to appropriate vector address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt
occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be
invoked. In other cases, the response time depends on current instruction. The fastest possible response to an
interrupt is 7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles for perform the
LCALL.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Table 10-1: Interrupt vectors
Interrupt Vector
Interrupt Request Flags
Address
0003h
IE0 – External interrupt 0
000Bh
TF0 – Timer 0 interrupt
0013h
IE1 – External interrupt 1
001Bh
TF1 – Timer 1 interrupt
RI/TI – Serial channel interrupt
TF2/EXF2 – Timer 2 interrupt
PWMIF – PWM interrupt
SPIIF – SPI interrupt
ADCIF – A/D converter interrupt
KBIIF – keyboard Interface
interrupt
LVIIF – Low Voltage Interrupt
IICIF – IIC interrupt
WDTIF – Watchdog interrupt
Comparator interrupt
Interrupt Number
*(use Keil C Tool)
0
1
2
3
0023h
002Bh
0043h
004Bh
0053h
4
5
8
9
10
005Bh
11
0063h
006Bh
008Bh
0093h
12
13
17
18
* See Keil C about C51 User‟s Guide about Interrupt Function description
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 49 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic
IEN0
IEN1
IEN2
IRCON
IRCON2
IP0
IP1
Description
Interrupt Enable
0 register
Interrupt Enable
1 register
Interrupt Enable
2 register
Interrupt request
register
Interrupt request
register 2
Interrupt priority
level 0
Interrupt priority
level 1
Dir.
Bit 7
Bit 6
A8H
EA
-
B8H
EXEN
2
9AH
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
ET2
ES
ET1
EX1
ET0
EX0
00H
-
IEIIC
IELVI
IEKBI
IEADC
IESPI
IEPW
M
00H
-
-
-
-
-
ECmpI
EWDT
-
00H
C0H
EXF2
TF2
IICIF
LVIIF
KBIIF
ADCIF
SPIIF
PWMI
F
00H
97H
-
-
-
-
-
CmpIF
WDTI
F
-
00H
A9H
-
-
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
00H
B9H
-
-
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
00H
Mnemonic: IEN0
7
6
EA
-
5
ET2
Bit 5
Interrupt
4
ES0
3
ET1
2
EX1
1
ET0
Address: A8h
0
Reset
EX0
00h
EA: EA=0 – Disable all interrupt.
EA=1 – Enable all interrupt.
ET2: ET2=0 – Disable Timer 2 overflow or external reload interrupt.
ET2=1 – Enable Timer 2 overflow or external reload interrupt.
ES: ES=0 – Disable Serial channel interrupt.
ES=1 – Enable Serial channel interrupt.
ET1: ET1=0 – Disable Timer 1 overflow interrupt.
ET1=1 – Enable Timer 1 overflow interrupt.
EX1: EX1=0 – Disable external interrupt 1.
EX1=1 – Enable external interrupt 1.
ET0: ET0=0 – Disable Timer 0 overflow interrupt.
ET0=1 – Enable Timer 0 overflow interrupt.
EX0: EX0=0 – Disable external interrupt 0.
EX0=1 – Enable external interrupt 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 50 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: IEN1
7
6
EXEN2
-
5
IEIIC
4
IELVI
3
IEKBI
2
IEADC
1
IESPI
Address: B8h
0
Reset
IEPWM
00H
1
EWDT
Address: 9Ah
0
Reset
00H
EXEN2: Timer 2 reload interrupt enable.
EXEN2 = 0 – Disable Timer 2 external reload interrupt.
EXEN2 = 1 – Enable Timer 2 external reload interrupt.
IEIIC: IIC interrupt enable.
IEIIC = 0 – Disable IIC interrupt.
IEIIC = 1 – Enable IIC interrupt.
IELVI: LVI interrupt enable.
IELVI = 0 – Disable LVI interrupt.
IELVI = 1 – Enable LVI interrupt.
IEKBI: KBI interrupt enable.
IEKBI = 0 – Disable KBI interrupt.
IEKBI = 1 – Enable KBI interrupt.
IEADC: A/D converter interrupt enable
IEADC = 0 – Disable ADC interrupt.
IEADC = 1 – Enable ADC interrupt.
IESPI: SPI interrupt enable.
IESPI = 0 – Disable SPI interrupt.
IESPI = 1 – Enable SPI interrupt.
IEPWM: PWM interrupt enable.
IEPWM = 0 – Disable PWM interrupt.
IEPWM = 1 – Enable PWM interrupt.
Mnemonic: IEN2
7
6
-
5
-
4
-
3
-
2
ECmpI
ECmpI Enable Comparator interrupt(include comparator_0 and comparator_1).
ECmpI = 0 – Disable Comparator interrupt.
ECmpI = 1 – Enable Comparator interrupt.
EWDT: Enable Watch dog interrupt.
EWDT = 0 – Disable Watch dog interrupt.
EWDT = 1 – Enable Watch dog interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 51 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: IRCON
7
6
5
EXF2
TF2
IICIF
4
LVIIF
3
KBIIF
2
ADCIF
1
SPIIF
Address: C0h
0
Reset
PWMIF
00H
EXF2: Timer 2 external reload flag. Must be cleared by software.
TF2: Timer 2 overflow flag. Must be cleared by software.
IICIF: IIC interrupt flag.
LVIIF: LVI interrupt flag.
KBIIF: KBI interrupt flag.
ADCIF: A/D converter end interrupt flag.
SPIIF: SPI interrupt flag.
PWMIF: PWM interrupt flag. Must be cleared by software.
Mnemonic: IRCON2
7
6
5
-
4
-
3
-
2
CmpIF
1
WDTIF
Address: 97h
0
Reset
00H
CmpIF Comparator interrupt flag
HW will clear this flag automatically when enter interrupt vector.
SW can clear this flag also.(in case analog comparator INT disable)
WDTIF: Watch dog interrupt flag
10.1 Priority level structure
All interrupt sources are combined in groups:
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel interrupt
Timer 2 interrupt
Table 10-2: Priority level groups
Groups
Watchdog interrupt
Comparator interrupt
-
PWM interrupt
SPI interrupt
ADC interrupt
KBI interrupt
LVI interrupt
IIC interrupt
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one
bit in the special function register ip0 and one in ip1. If requests of the same priority level will be received
simultaneously, an internal polling sequence determines which request is serviced first
Mnemonic: IP0
7
6
-
5
IP0.5
4
IP0.4
3
IP0.3
2
IP0.2
1
IP0.1
Address: A9h
0
Reset
IP0.0
00h
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 52 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: IP1
7
6
-
5
IP1.5
4
IP1.4
IP1.x
0
0
1
1
3
IP1.3
2
IP1.2
1
IP1.1
Address: B9h
0
Reset
IP1.0
00h
Table 10-3: Priority levels
IP0.x
Priority Level
0
1
0
1
Level0 (lowest)
Level1
Level2
Level3 (highest)
Table 10-4: Groups of priority
Group
Bit
IP1.0, IP0.0
IP1.1, IP0.1
IP1.2, IP0.2
IP1.3, IP0.3
IP1.4, IP0.4
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
IP1.5, IP0.5
Timer 2 interrupt
-
PWM interrupt
SPI interrupt
ADC interrupt
KBI interrupt
LVI interrupt
Watchdog interrupt
Comparator interrupt
-
IIC interrupt
Table 10-5: Polling sequence
Interrupt source
SPI interrupt
External interrupt 1
Comparator interrupt
ADC interrupt
Timer 1 interrupt
KBI interrupt
Sequence
Polling sequence
External interrupt 0
PWM interrupt
Timer 0 interrupt
Watchdog interrupt
Serial channel 0 interrupt
LVI interrupt
Timer 2 interrupt
IIC interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 53 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
11. Power Management Unit
Power management unit serves two power management modes, IDLE and STOP, for the users to do power saving
function.
Mnemonic: PCON
7
6
SMOD
-
5
-
4
-
3
-
2
-
1
STOP
Address: 87h
0
Reset
IDLE
00h
STOP: Stop mode control bit. Setting this bit turning on the Stop Mode.
Stop bit is always read as 0
IDLE: Idle mode control bit. Setting this bit turning on the Idle Mode.
Idle bit is always read as 0
11.1 Idle mode
Setting the IDLE bit of PCON register invokes the IDLE mode. The IDLE mode leaves internal clocks and peripherals
running. Power consumption drops because the CPU is not active. The CPU can exit the IDLE state with any interrupts
or a reset.
11.2 Stop mode
Setting the STOP bit of PCON register invokes the STOP mode. All internal clocking in this mode is turn off. The CPU
will exit this state from a no-clocked interrupt (external INT0/1 and LVI、Watchdog interrupt) or a reset (WDT and LVR)
condition. Internally generated interrupts (timer, serial port ...) have no effect on stop mode since they require clocking
activity.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 54 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
12. Pulse Width Modulation (PWM)
SM39R08A3 provides two-channel PWM outputs.
The interrupt vector is 43h.
Mnemonic
PWMC
PWMD0H
PWMD0L
PWMD1H
PWMD1L
PWMD2H
PWMD2L
PWMD3H
PWMD3L
PWMMDH
PWMMDL
Description
PWM Control
register
PWM 0 Data
register high byte
PWM 0 Data
register low byte
PWM 1 Data
register high byte
PWM 1 Data
register low byte
PWM 2 Data
register high byte
PWM 2 Data
register low byte
PWM 3 Data
register high byte
PWM 3 Data
register low byte
PWM Max Data
register high byte
PWM Max Data
register low byte
Dir.
Bit 7
B5h
Bit 6
Bit 5
PWM
PWMCS[2:0]
PWMP
0
BCh
-
-
BDh
Bit 3
Bit 2
Bit 1
Bit 0
RST
-
PWM3
EN
PWM2
EN
PWM1
EN
PWM0
EN
00H
-
-
-
PWMD0[9:8]
PWMD0[7:0]
PWMP
1
BEh
-
-
-
BFh
-
PWMP
2
-
-
-
B2h
-
-
PWMD1[9:8]
PWMP
3
-
-
-
B4h
-
-
PWMD2[9:8]
-
-
-
-
CFh
-
-
PWMD3[9:8]
PWMCS[2:0]
PWMCS[2:0]: PWM clock select.
PWMCS [2:0]
000
001
010
011
100
101
110
111
4
-
3
2
1
PWM3EN PWM2EN PWM1EN
00H
00H
-
PWMMD[9:8]
PWMMD[7:0]
5
00H
00H
PWMD3[7:0]
CEh
00H
00H
PWMD2[7:0]
B3h
00H
00H
PWMD1[7:0]
B1h
Mnemonic: PWMC
7
6
Bit 4
00H
FFH
Address: B5h
0
Reset
PWM0EN
00H
Mode
Fosc
Fosc/2
Fosc/4
Fosc/6
Fosc/8
Fosc/12
Timer 0 overflow
Timer 0 external input (P3.4/T0)
PWM3EN PWM channel 3 enable control bit.
PWM3EN = 1 – PWM channel 1 enable.
PWM3EN = 0 – PWM channel 1 disable.
PWM2EN PWM channel 2 enable control bit.
PWM2EN = 1 – PWM channel 1 enable.
PWM2EN = 0 – PWM channel 1 disable.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 55 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
PWM1EN: PWM channel 1 enable control bit.
PWM1EN = 1 – PWM channel 1 enable.
PWM1EN = 0 – PWM channel 1 disable.
PWM0EN: PWM 0 enable control bit.
PWM0EN = 1 – PWM channel 0 enable.
PWM0EN = 0 – PWM channel 0 disable.
Mnemonic: PWMD0H
7
6
5
PWMP0
Mnemonic: PWMD0L
7
6
5
4
-
3
-
4
3
PWMD0[7:0]
2
-
2
Address: BCh
1
0
Reset
PWMD0[9:8]
00H
1
Address: BDh
0
Reset
00h
PWMP0: PWM channel 0 idle polarity select.
“0” – PWM channel 0 will idle low.
“1” – PWM channel 0 will idle high.
PWMD0[9:0]: PWM channel 0 data register.
Mnemonic: PWMD1H
7
6
5
PWMP1
Mnemonic: PWMD1L
7
6
5
4
-
3
-
4
3
PWMD1[7:0]
2
-
2
Address: BEh
1
0
Reset
PWMD1[9:8]
00H
1
Address: BFh
0
Reset
00H
PWMP1: PWM channel 1 idle polarity select.
“0” – PWM channel 1 will idle low.
“1” – PWM channel 1 will idle high.
PWMD1[9:0]: PWM channel 1 data register.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 56 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: PWMD2H
7
6
5
PWMP1
Mnemonic: PWMD2L
7
6
5
4
-
3
-
4
3
PWMD2[7:0]
2
-
2
Address: B1h
1
0
Reset
PWMD1[9:8]
00H
1
Address: B2h
0
Reset
00H
PWMP2: PWM channel 2 idle polarity select.
“0” – PWM channel 2 will idle low.
“1” – PWM channel 2 will idle high.
PWMD2[9:0]: PWM channel 2 data register.
Mnemonic: PWMD3H
7
6
5
PWMP3
Mnemonic: PWMD3L
7
6
5
4
-
3
-
4
3
PWMD3[7:0]
2
-
2
Address: B3h
1
0
Reset
PWMD1[9:8]
00H
1
Address: B4h
0
Reset
00H
PWMP3: PWM channel 3 idle polarity select.
“0” – PWM channel 3 will idle low.
“1” – PWM channel 3 will idle high.
PWMD3[9:0]: PWM channel 3 data register.
Mnemonic: PWMMDH
7
6
5
Mnemonic: PWMMDL
7
6
5
4
-
3
-
4
3
PWMMD[7:0]
2
-
2
Address: CEh
1
0
Reset
PWMMD[9:8]
00H
1
Address: CFh
0
Reset
FFH
PWMMD[9:0]: PWM Max Data register.
PWM count from 0000h to PWMMD[9:0]. When PWM count data equal PWMMD[9:0]
is overflow.
PWMPx = 0 & PWMDx = 00h
PWMx
Low
PWMPx = 0 & PWMDx ≠ 00h
PWMx
PWMPx = 1 & PWMDx = 00h
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 57 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
PWMx
High
PWMPx = 1 & PWMDx ≠ 00h
PWMx
PWMMD 1
PWM clock
PWMDx
Leader pulse
PWM clock
PWM period
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 58 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
13. IIC function
The IIC module uses the SCL (clock) and the SDA (data) line to communicate with external IIC interface. Its
speed can be selected to 400Kbps (maximum) by software setting the IICBR [2:0] control bit. The IIC
module provided 2 interrupts (RXIF, TXIF). It will generate START, repeated START and STOP signals
automatically in master mode and can detects START, repeated START and STOP signals in slave mode. The
maximum communication length and the number of devices that can be connected are limited by a maximum
bus capacitance of 400pF.
The interrupt vector is 6Bh.
Mnemonic
AUX
IICCTL
Description
Auxiliary register
IIC control
register
Dir.
Bit 7
91h
BRGS
Bit 6
Bit 5
IIC function
-
Bit 4
F9h
IICEN
MSS
MAS
AB_E
N
-
MPIF
LAIF
RXIF
Bit 3
IICS
IIC status register
F8h
IICA1
IIC Address 1
register
FAh
IICA1[7:1]
IICA2
IIC Address 2
register
FBh
IICA2[7:1]
IICRWD
IICEBT
IIC Read/Write
register
IIC Enaable Bus
Transaction
FCh
FDh
BF_EN
TXIF
Bit 2
Bit 1
Bit 0
RST
-
-
DPS
00H
IICBR[2:0]
RXAK
TXAK
04H
RW or
BB
MATC
H1or
RW1
MATC
H2 or
RW2
IICRWD[7:0]
FU_EN
Mnemonic: IICCTL
7
6
5
IICEN
MSS
MAS
4
AB_EN
-
3
BF_EN
-
2
-
1
IICBR[2:0]
00H
A0H
60H
00H
-
-
-
00H
Address: F9h
0
Reset
04h
IICEN: Enable IIC module
IICEN = 1 is Enable
IICEN = 0 is Disable.
MSS: Master or slave mode select.
MSS = 1 is master mode.
MSS = 0 is slave mode.
*The software must set this bit before setting others register.
MAS: Master address select (master mode only)
MAS = 0 is to use IICA1.
MAS = 1 is to use IICA2.
AB_EN: Arbitration lost enable bit. (Master mode only)
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred,
hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration lost
condition. Set this bit when multi-master and slave connection. Clear this bit when single
master to single slave.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 59 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
BF_EN: Bus busy enable bit. (Master mode only)
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear this bit
will always generate a start condition to bus when MStart is set. Set this bit when multi-master
and slave connection. Clear this bit when single master to single slave.
IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator
frequency. The default is Fosc/512 for users‟ convenience.
IICBR[2:0]
Baud rate
000
Fosc/32
001
Fosc/64
010
Fosc/128
011
Fosc/256
100
Fosc/512
101
Fosc/1024
110
Fosc/2048
111
Fosc/4096
Mnemonic: IICS
7
6
MPIF
5
LAIF
4
RXIF
3
TXIF
2
RXAK
1
TxAK
Address: F8H
0
Reset
RW or BB
00H
MPIF: The Stop condition Interrupt Flag
The stop condition occurred and this bit will be set. Software need to clear this bit
LAIF: Arbitration lost bit. (Master mode only)
The Arbitration Interrupt Flag, the bus arbitration lost occurred and this bit will be set.
Software need to clear this bit
RxIF: The data Receive Interrupt Flag (RXIF) is set after the IICRWD (IIC Read Write Data
Buffer) is loaded with a newly receive data.
TxIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the IICRWD (IIC Read
Write Data Buffer) is downloaded to the shift register.
RxAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has
been received after the complete 8 bits data transmit on the bus.
TxAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will
set (NoAck) or clear (Ack) and transmit to master to indicate the receive status.
RW or BB: Master Mode:
BB : Bus busy bit
If detect scl=0 or sda=0 or bus start, this bit will be set. If detect stop,this bit will be
cleared. This bit can be cleared by software to return ready state.
Slave Mode:
RW:The slave mode read (received) or wrote (transmit) on the IIC bus. When this bit is
clear, the slave module received data on the IIC bus (SDA).(Slave mode only)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 60 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
th
Fig. 13-1: Acknowledgement bit in the 9 bit of a byte transmission
Mnemonic: IICA1
7
6
5
4
IICA1[7:1]
R/W
3
2
1
Address: FAH
0
Reset
Match1 or RW1
A0H
R or R/W
Slave mode:
IICA1[7:1]: IIC Address registers
This is the first 7-bit address for this slave module. It will be checked when an address (from
master) is received
Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets first data, this bit will clear.
Master mode:
IICA1[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It
appears at the 8th bit after the IIC address as shown in Fig. 13-2. It is used to tell the salve the
direction of the following communication. If it is 1, the module is in master receive mode. If 0, the
module is in master transmit mode.
RW1=1, master receive mode
RW1=0, master transmit mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 61 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Fig. 13-2: RW bit in the 8th bit after IIC address
Mnemonic: IICA2
7
6
5
Address: FBh
4
IICA2[7:1]
R/W
3
2
1
0
Match2 or RW2
R or R/W
Reset
60h
Slave mode:
IICA2[7:1]: IIC Address registers
This is the second 7-bit address for this slave module.
It will be checked when an address (from master) is received
Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets first data, this bit will clear.
Master mode:
IICA2[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is
used to tell the salve the direction of the following communication. If it is 1, the module is in
master receive mode. If 0, the module is in master transmit mode.
RW2=1, master receive mode
RW2=0, master transmit mode
Mnemonic: IICRWD
7
6
5
4
3
IICRWD[7:0]
2
Address: FCh
0
Reset
00h
1
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
In transmitting mode, the byte to be shifted out through SDA stays here.
Mnemonic: IICEBT
7
6
FU_EN
5
-
4
-
3
-
2
-
1
-
Address: FDH
Res
0
et
00H
Master Mode:
00: reserved
01: IIC bus module will enable read/write data transfer on SDA and SCL.
10: IIC bus module generate a start condition on the SDA/SCL, then send out
address which is stored in the IICA1/IICA2(selected by MAS control bit)
11: IIC bus module generates a stop condition on the SDA/SCL.
FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6] repeatedly
is necessary.
Slave mode:
01: FU_EN[7:6] should be set as 01 only. The other value is inhibited.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 62 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Notice:
1. FU_EN[7:6] should be set as 01 before read/write data transfer for bus
release; otherwise, SCL will be locked(pull low).
2. FU_EN[7:6] should be set as 01 after read/write data transfer for receiving a
stop condition from bus master.
3. In transmit data mode(slave mode), the output data should be filled into
IICRWD before setting FU_EN[7:6] as 01.
4. FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6]
repeatedly is necessary.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 63 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
14. SPI Function - Serial Peripheral Interface
Serial Peripheral Interface (SPI) is a synchronous protocol that allows a master device to initiate communication with
slave devices.
The interrupt vector is 4Bh.
There are 4 signals used in SPI, they are
SPI_MOSI: data output in the master mode, data input in the slave mode,
SPI_MISO: data input in the master mode, data output in the master mode,
SPI_SCK: clock output from the master, the above data are synchronous to this signal
SPI_SS: input in the slave mode.
This slave device detects this signal to judge if it is selected by the master.
In the master mode, it can select the desired slave device by any IO with value = 0. Fig. 14-1 is an example showing
the relation of the 4 signals between master and slaves.
Master
Slave 2
Slave 1
MOSI
MISO
CLK
IO
IO
MOSI
MISO
CLK
MOSI
MISO
CLK
SS
SS
Fig. 14-1: SPI signals between master and slave devices
There is only one channel SPI interface. The SPI SFRs are shown as below:
SPI
SPIC1
SPIC2
SPIS
SPITXD
SPIRXD
Description
SPI control register
1
SPI control register
2
SPI status register
SPI transmit data
buffer
SPI receive data
buffer
Addr
ess
F1h
F2h
F5h
Bit 7
SPIE
N
SPIF
D
SPIR
F
Bit 6
Bit 5
SPI function
SPIMS SPISS
S
P
Bit 4
Bit 3
SPICK
P
SPICK
E
SPIRS
T
SPITD
R
TBC[2:0]
SPIML
S
SPIOV
SPITX
IF
Bit 2
SPIRX
IF
Bit 1
Bit 0
RST
SPIBR[2:0]
08H
RBC[2:0]
00H
SPIRD
R
SPIRS
40H
F3h
SPITXD[7:0]
00H
F4h
SPIRXD[7:0]
00H
Mnemonic: SPIC1
7
6
SPIEN SPIMSS
5
SPISSP
4
SPICKP
3
SPICKE
Address: F1h
2
1
0
Reset
SPIBR[2:0]
08h
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 64 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
SPIEN: Enable SPI module.
“1” is Enable.
“0” is Disable.
SPIMSS: Master or Slave mode Select
“1” is Master mode.
“0” is Slave mode.
SPISSP: SS or CS active polarity.(Slave mode used only)
“1” - high active.
“0” - low active.
SPICKP: Clock idle polarity select. (Master mode used only)
“1” - SCK will idle high. Ex :
“0” - SCK will idle low. Ex :
SPICKE: Clock sample edge select.
“1” – rising edge latch data.
“0” – falling edge latch data.
* To ensure the data latch stability, SM39R08A3 generate the output data as given in
the following example, the other side can latch the stable data no matter in rising or
falling edge.
sufficient set-up time
sufficient hold time
SPIBR[2:0]: SPI baud rate select. (Master mode used only)
SPIBR[2:0]
Baud rate
0:0:0
Fosc/4
0:0:1
Fosc /8
0:1:0
Fosc /16
0:1:1
Fosc /32
1:0:0
Fosc /64
1:0:1
Fosc /128
1:1:0
Fosc /256
1:1:1
Fosc /512
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 65 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: SPIC2
7
6
5
SPIFD
TBC[2:0]
4
3
SPIRST
2
1
RBC[2:0]
Address: F2h
0
Reset
00h
SPIFD: Full-duplex mode enable.
“1” is enable full-duplex mode.
“0” is disable full-duplex mode.
When it is set, the TBC[2:0] and RBC[2:0] will be reset and keep to zero. When the Master
device transmits data to the Slave device via the MOSI line, the Slave device responds by
sending data to the Master device via the MISO line. This implies full-duplex transmission with
both data out and data in synchronized with the same clock.
Input Shift register
SPIRXD
Output Shift register
SPITXD
Clock Generator
MISO
MISO
MOSI
MOSI
SCK
SCK
On-Bright Master
Output Shift
register
SPITXD
Input Shift register
SPIRXD
On-Bright Slave
Fig. 14-2: SPI master and slave transmission method
TBC[2:0]: SPI transmitter bit counter.
TBC[2:0]
Bit counter
0:0:0
8 bits output
0:0:1
1 bit output
0:1:0
2 bits output
0:1:1
3 bits output
1:0:0
4 bits output
1:0:1
5 bits output
1:1:0
6 bits output
1:1:1
7 bits output
SPIRST: SPI Re-start (Slave mode used only)
SPIRST=0:Re-start function disable.SPI transmit/receive data when SS active.
In SPITXD/SPIRXD buffer, data got from previous SS active period will not be removed (i.e. it's
valid).
SPIRST=1:Re-start function enable.SPI transmit/receive new data when SS re-active;
In SPITXD/SPIRXD buffer, data got from previous SS active period will be removed (i.e. It's
invalid).
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 66 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
RBC[2:0]: SPI receiver bit counter.
RBC[2:0]
Bit counter
0:0:0
8 bits input
0:0:1
1 bit input
0:1:0
2 bits input
0:1:1
3 bits input
1:0:0
4 bits input
1:0:1
5 bits input
1:1:0
6 bits input
1:1:1
7 bits input
Mnemonic: SPIS
7
6
SPIRF
SPIMLS
5
4
3
2
1
SPIOV
SPITXIF
SPITDR
SPIRXIF
SPIRDR
Address:F5H
0
Reset
SPIRS
40H
SPIRF: SPI SS pin Release Flag.
This bit is set when SS pin release & SPIRST as „1‟.
SPIMLS: MSB or LSB first output /input Select.
“1” is MSB first output/input.
“0” is LSB first output/input.
SPIOV: Overflow flag.
When SPIRDR is set and next data already into shift register, this flag will be set.
It is clear by hardware, when SPIRDR is cleared.
SPITXIF: Transmit Interrupt Flag.
This bit is set when the data of the SPITXD register is downloaded to the shift register.
SPITDR: Transmit Data Ready.
When MCU finish writing data to SPITXD register, the MCU needs to set this bit to „1‟ to
inform the SPI module to send the data. After SPI module finishes sending the data
from SPITXD, this bit will be cleared automatically.
SPIRXIF: Receive Interrupt Flag.
This bit is set after the SPIRXD is loaded with a newly receive data.
SPIRDR: Receive Data Ready.
The MCU must clear this bit after it gets the data from SPIRXD register. The SPI
module is able to write new data into SPIRXD only when this bit is cleared.
SPIRS: Receive Start.
This bit set to “1” to inform the SPI module to receive the data into SPIRXD register.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 67 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: SPITXD
7
6
5
4
3
SPITXD[7:0]
2
1
0
Address: F3h
Reset
00h
SPITXD[7:0]: Transmit data buffer.
Mnemonic: SPIRXD
7
6
5
4
3
SPIRXD[7:0]
2
1
Address: F4h
0
Reset
00h
SPIRXD[7:0]: Receive data buffer.
P.S. MISO pin must be float when SS or CS no-active in slave mode.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 68 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
15. KBI – Keyboard Interface
Keyboard interface (KBI) can be connected to a 4 x n matrix keyboard or any similar devices. It has 4 inputs with
programmable interrupt capability on either high or low level. These 4 inputs can be the external interrupts to leave
from the idle and stop modes.
KBI0
Input
circuitry
KBI1
Input
circuitry
KBI2
Input
circuitry
KBI3
Input
circuitry
OR
KBIIF: KBI interrupt flag
IEKBI: KBI interrupt enable
Fig. 15-1: keyboard interface block diagram
250KHz
0
KBIx
De-bounce
KBF.x
1
KBD[1:0]
KBLS.x
KBE.x
Fig. 15-2: keyboard input circuitry
Mnemonic
KBLS
KBE
KBF
KBD
Description
KBI level
selection
KBI input enable
KBI flag
KBI De-bounce
control register
Dir.
Bit 7
93h
-
-
94h
95h
KBDE
N
96h
Bit 6
Bit 5
KBI function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
-
-
KBLS3
KBLS2
KBLS1
KBLS0
00H
-
-
-
KBE3
KBF3
KBE2
KBF2
KBE1
KBF1
KBE0
KBF0
00H
00H
-
-
-
-
-
KBD1
KBD0
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 69 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: KBLS
7
6
-
5
-
4
-
3
KBLS.3
2
KBLS.2
1
KBLS.1
Address: 93h
0
Reset
KBLS.0
00h
2
KBE.2
1
KBE.1
Address: 94h
0
Reset
KBE.0
00h
KBLS.3: Keyboard Line 3 level selection bit
0 : enable a low level detection on KBI3.
1 : enable a high level detection on KBI3.
KBLS.2: Keyboard Line 2 level selection bit
0 : enable a low level detection on KBI2.
1 : enable a high level detection on KBI2.
KBLS.1: Keyboard Line 1 level selection bit
0 : enable a low level detection on KBI1.
1 : enable a high level detection on KBI1.
KBLS.0: Keyboard Line 0 level selection bit
0 : enable a low level detection on KBI0.
1 : enable a high level detection on KBI0.
Mnemonic: KBE
6
7
-
5
-
4
-
3
KBE.3
KBE.3: Keyboard Line 3 enable bit
0 : enable standard I/O pin.
1 : enable KBF.3 bit in KBF register to generate an interrupt request.
KBE.2: Keyboard Line 2 enable bit
0 : enable standard I/O pin.
1 : enable KBF.2 bit in KBF register to generate an interrupt request.
KBE.1: Keyboard Line 1 enable bit
0 : enable standard I/O pin.
1 : enable KBF.1 bit in KBF register to generate an interrupt request.
KBE.0: Keyboard Line 0 enable bit
0 : enable standard I/O pin.
1 : enable KBF.0 bit in KBF register to generate an interrupt request.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 70 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Mnemonic: KBF
6
7
-
5
-
4
-
3
KBF.3
2
KBF.2
1
KBF.1
Address: 95h
0
Reset
KBF.0
00h
KBF.3: Keyboard Line 3 flag
This is set by hardware when KBI3 detects a programmed level.
It generates a Keyboard interrupt request if KBE.3 is also set. It must be cleared by
software.
KBF.2: Keyboard Line 2 flag
This is set by hardware when KBI2 detects a programmed level.
It generates a Keyboard interrupt request if KBE.2 is also set. It must be cleared by
software.
KBF.1: Keyboard Line 1 flag
This is set by hardware when KBI1 detects a programmed level.
It generates a Keyboard interrupt request if KBE.1 is also set. It must be cleared by
software.
KBF.0: Keyboard Line 0 flag
This is set by hardware when KBI0 detects a programmed level.
It generates a Keyboard interrupt request if KBE.0 is also set. It must be cleared by
software.
Mnemonic: KBD
7
6
KBDEN
-
5
-
4
-
3
-
2
-
1
KBD.1
Address: 96H
0
Reset
KBD.0
00H
KBDEN: Enable KBI de-bounce function. The default KBI function is enabled.
KBDEN = 0, enable KBI de-bounce function. The de-bounce time is selected by KBD
[1:0].
KBDEN = 1, disable KBI de-bounce function. The KBI input pin without de-bounce
mechanism.
KBD[1:0]: Select KBI de-bounce time. If KBDEN = “0”, the default de-bounce time is 320 ms.
KBD[1:0] = 00, the de-bounce time is 320 ms.
KBD[1:0] = 01, the de-bounce time is 160 ms.
KBD[1:0] = 10, the de-bounce time is 80 ms.
KBD[1:0] = 11, the de-bounce time is 40 ms.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 71 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
16. LVI & LVR – Low Voltage Interrupt and Low Voltage Reset
The interrupt vector 63h.
Mnemoni
c
Description
Addre
ss
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
LVRF
PORF
00H
LVI function
RSTS
LVC
Reset status
register
Low voltage
control
A1h
-
-
-
PDR
F
WDTF
SWRF
E6h
LVI_
EN
-
LVRE
LVIF
-
-
Mnemonic: RSTS
7
6
-
5
-
4
PDRF
3
WDTF
2
SWRF
1
LVRF
LVIS[1:0]
20H
Address: A1h
0
Reset
PORF
00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag
clear by software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear
by software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear
by software.
Mnemonic: LVC
7
6
5
LVI_EN
LVRE
4
LVIF
3
-
2
-
1
Address: E6h
0
Reset
LVIS[1:0]
20H
LVI_EN: Low voltage interrupt function enable bit.
LVI_EN = 0 - disable low voltage detect function.
LVI_EN = 1 - enable low voltage detect function.
LVRE: External low voltage reset function enable bit.
LVRE = 0 - disable external low voltage reset function.
LVRE = 1 - enable external low voltage reset function.
LVIF: Low Voltage interrupt Flag
LVIS LVI level select:
00: 1.7V
01: 2.6V
10: 3.2V
11: 4.0V
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 72 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
17. 10-bit Analog-to-Digital Converter (ADC)
The SM39R08A3 provides seven channels 10-bit ADC and one channel ADC0 connect to internal Vref of 1.2V±10%).).
The Digital output DATA [9:0] were put into ADCD [9:0].
The ADC interrupt vector is 53H.
Vref
1.2V±10%
ADCC1[7:0]
VDD
ADCCH[2:0]
Start
ADC0
AVDD
…
…
…
…
ADCD[9:0]
MUX
ADC6
High Speed
10 Bits
ADC Module
ADC7
ADC
Clock
Divider
Fosc
ADC_ISR
AVSS
ADCCS[4:0]
VSS
Fig. 17-1: ADC Operation setting of the analog-to-digital converter
The ADC SFR show as below:
Mnemoni
c
ADCC1
ADCC2
ADCDH
ADCDL
ADCCS
Description
ADC Control
register 1
ADC Control
register 2
ADC data high
byte
ADC data low
byte
ADC clock select
Addr
ess
Bit 7
Bit 6
ABh
ADC7E
N
ACh
Start
ADC6
EN
ADJU
ST
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
ADC
ADC5
EN
ADC4
EN
ADC3
EN
ADC2
EN
ADC1
EN
ADC0E
N
00H
-
-
ADCCH[2:0]
00H
ADh
ADCDH [7:0]
00H
AEh
ADCDL [7:0]
00H
AFh
Mnemonic: ADCC1
7
6
ADC7EN
Bit 5
ADC6EN
-
-
-
ADCCS[4:0]
5
4
3
2
1
ADC5EN
ADC4EN
ADC3EN
ADC2EN
ADC1EN
00H
Address: ABh
0
Reset
ADC0EN
00H
ADC7EN: ADC channels 7 enable.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 73 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
ADC7EN = 1 – Enable ADC channel 7
ADC6EN: ADC channels 6 enable.
ADC6EN = 1 – Enable ADC channel 6
ADC5EN: ADC channels 5 enable.
ADC5EN = 1 – Enable ADC channel 5
ADC4EN: ADC channels 4 enable.
ADC4EN = 1 – Enable ADC channel 4
ADC3EN: ADC channels 3 enable.
ADC3EN = 1 – Enable ADC channel 3
ADC2EN: ADC channels 2 enable.
ADC2EN = 1 – Enable ADC channel 2
ADC1EN: ADC channels 1 enable.
ADC1EN = 1 – Enable ADC channel 1
ADC0EN: ADC channels 0 enable.
ADC0EN = 1 – Enable ADC channel 0 (connect to internal Verf of 1.2V±10%)
Mnemonic: ADCC2
7
6
Start
ADJUST
5
4
-
3
-
2
1
ADCCH[2:0]
Address: ACh
0
Reset
00H
Start: When this bit is set, the ADC will be start conversion continuous.
ADJUST: Adjust the format of ADC conversion DATA.
ADJUST = 0: (default value)
ADC data high byte ADCD [9:2] = ADCDH [7:0].
ADC data low byte ADCD [1:0] = ADCDL [1:0].
ADJUST = 1: ADC data high byte ADCD [9:8] = ADCDH [1:0].
ADC data low byte ADCD [7:0] = ADCDL [7:0].
ADCCH[2:0]: ADC channel select.
ADCCH [2:0]
Channel
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 74 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
ADJUST = 0:
Mnemonic: ADCDH
7
6
ADCD[9]
ADCD[8]
5
4
3
2
1
ADCD[7]
ADCD[6]
ADCD[5]
ADCD[4]
ADCD[3]
Mnemonic: ADCDL
7
6
-
1
ADCD[1]
Address: ADh
0
Reset
ADCD[2]
00H
Address: AEh
0
Reset
ADCD[0]
00H
5
-
4
-
3
-
2
-
Mnemonic: ADCDH
7
6
-
5
-
4
-
3
-
2
-
1
ADCD[9]
Mnemonic: ADCDL
7
6
5
4
3
2
1
0
ADCD[5]
ADCD[4]
ADCD[3]
ADCD[2]
ADCD[1]
ADCD[0]
ADJUST = 1:
ADCD[7]
ADCD[6]
Address: ADh
0
Reset
ADCD[8]
00H
Address: AEh
Reset
00H
ADCD[9:0]: ADC data register.
Mnemonic: ADCCS
7
6
ADCCS[4:0]:
5
-
Address: AFh
Reset
4
3
2
1
0
ADCCS[4]
ADCCS[3]
ADCCS[2]
ADCCS[1]
ADCCS[0]
00H
ADC clock select.
*The ADC clock maximum 12.5MHz.
*The ADC Conversion rate maximum 961 KHz.
ADCCS[4:0]
ADC Clock(Hz)
Clocks for ADC Conversion
00000
Fosc /2
46
00001
Fosc/4
92
00010
Fosc /6
138
00011
Fosc /8
184
00100
Fosc /10
230
00101
Fosc /12
276
00110
Fosc /14
322
00111
Fosc /16
368
01000
Fosc /18
414
01001
Fosc /20
460
01010
Fosc /22
506
01011
Fosc /24
552
01100
Fosc /26
598
01101
Fosc /28
644
01110
Fosc /30
690
01111
Fosc /32
736
10000
Fosc /34
782
10001
Fosc /36
828
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 75 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Fosc /38
Fosc /40
Fosc /42
Fosc /44
Fosc /46
Fosc /48
Fosc /50
Fosc /52
Fosc /54
Fosc /56
Fosc /58
Fosc /60
Fosc /62
Fosc /64
874
920
966
1012
1058
1104
1150
1196
1242
1288
1334
1380
1426
1472
Fosc
2 ( ADCCS 1)
ADC_Clock
ADC _ Conversion _ Rate
13
ADC _ Clock
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 76 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
18. In-System Programming (Internal ISP)
The SM39R08A3 can generate flash control signal by internal hardware circuit. Users utilize flash control register, flash
address register and flash data register to perform the ISP function without removing the SM39R08A3 from the system.
The SM39R08A3 provides internal flash control signals which can do flash program/chip erase/page erase/protect
functions. User need to design and use any kind of interface which SM39R08A3 can input data. User then utilize ISP
service program to perform the flash program/chip erase/page erase/protect functions.
18.1 ISP service program
The ISP service program is a user developed firmware program which resides in the ISP service program space. After
user developed the ISP service program, user then determine the size of the ISP service program. User need to
program the ISP service program in the SM39R08A3 for the ISP purpose.
The ISP service programs were developed by user so that it should includes any features which relates to the flash
memory programming function as well as communication protocol between SM39R08A3 and host device which output
data to the SM39R08A3. For example, if user utilize UART interface to receive/transmit data between SM39R08A3 and
host device, the ISP service program should include baud rate, checksum or parity check or any error-checking
mechanism to avoid data transmission error.
The ISP service program can be initiated under SM39R08A3 active or idle mode. It can not be initiated under power
down mode.
18.2 Lock Bit (N)
The Lock Bit N has two functions: one is for service program size configuration and the other is to lock the ISP service
program space from flash erase function.
The ISP service program space address range $3C00 to $3FFF. It can be divided as blocks of N*128 byte. (N=0 to 8).
When N=0 means no ISP function, all of 8KB+1KB flash memory can be used as program memory. When N=1 means
ISP service program occupies 128 byte while the rest of 15.875K byte flash memory can be used as program memory.
The maximum ISP service program allowed is 1K byte when N=16. Under such configuration, the usable program
memory space is 15K byte.
After N determined, SM39R08A3 will reserve the ISP service program space downward from the top of the program
address $3FFF. The start address of the ISP service program located at $3x00 while x is depending on the lock bit N.
Please see Table 18-1. program memory diagram for this ISP service program space structure.
The lock bit N function is different from the flash protect function. The flash erase function can erase all of the flash
memory except for the locked ISP service program space. If the flash not has been protected, the content of ISP
service program still can be read. If the flash has been protected, the overall content of flash program memory space
including ISP service program space can not be read.
N
0
1
2
3
4
5
6
7
8
Table 18-1: ISP code area.
ISP service program address
No ISP service program
128 bytes ($3F80h ~ $3FFFh)
256 bytes ($3F00h ~ $3FFFh)
384 bytes ($3E80h ~ $3FFFh)
512 bytes ($3E00h ~ $3FFFh)
640 K bytes ($3D80h ~ $3FFFh)
768 K bytes ($3D00h ~ $3FFFh)
896 K bytes ($3C80h ~ $3FFFh)
1.0 K bytes ($3C00h ~ $3FFFh)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 77 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
ISP service program configurable in N*256 byte (N= 0 ~ 8)
18.3 Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be protected
(locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash memory
program/erase timing so the locked ISP service program can not be erased by flash erase function. If user needs to
erase the locked ISP service program, he can do it by writer only. User can not change ISP service program when
SM39R08A3 was in system.
18.4 Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and
execute it. There are four ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start address
of ISP service program. The hardware reset includes MAX810 (power on reset) and external pad reset. The
hardware will issue a strobe window about 256us after hardware reset.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
(3) Enter‟s ISP service program by hardware setting. User can force SM39R08A3 enter ISP service program
by setting P1.6 “ active low” during hardware reset period. The hardware reset includes MAX810 (power on
reset) and external pad reset. The hardware will issue after hardware reset. In application system design,
user should take care of the setting of P1.6 at reset period to prevent SM39R08A3 from entering ISP
service program.
(4) Enter‟s ISP service program by hardware setting, the P1.1(RXD) will be detected the two clock signals
during hardware reset period. The hardware reset includes MAX810 (power on reset) and external pad
reset. The hardware will issue to detect 2 clock signals after hardware reset.
During the strobe window, the hardware will detect the status of P1.6/P1.1. If they meet one of above conditions, chip
will switch to ISP mode automatically. After ISP service program executed, user need to reset the SM39R08A3, either
by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
There are 8 kinds of entry mechanisms for user different applications. This entry method will select on the writer or ISP.
(1)
(2)
(3)
(4)
(5)
(6)
First Address Blank. i.e. $0000 = 0xFF. And triggered by Internal reset signal.
First Address Blank. i.e. $0000 = 0xFF. And triggered by PAD reset signal.
P1.6 = 0. And triggered by Internal reset signal.
P1.6 = 0. And triggered by PAD reset signal.
P1.1 input 2 clocks. And triggered by Internal reset signal.
P1.1 input 2 clocks. And triggered by PAD reset signal.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 78 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
18.5 ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC
Mnemonic
TAKEY
IFCON
ISPFAH
ISPFAL
ISPFD
ISPFC
Description
Time Access
Key register
Interface Control
register
ISP Flash
Address – High
register
ISP Flash
Address – Low
register
ISP Flash Data
register
ISP Flash
Control register
Dir.
Bit 7
Bit 6
Bit 5
ISP function
F7h
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TAKEY [7:0]
8Fh
-
CDPR
E1h
-
-
-
-
RST
00H
-
-
-
ISPE
ISPFAH [5:0]
00H
FFH
E2h
ISPFAL [7:0]
FFH
E3h
ISPFD [7:0]
FFH
E4h
EMF1
-
EMF3
EMF4
-
ISPF.2
ISPF.1
ISPF.0
00H
Address: F7H
Mnemonic: TAKEY
7
6
5
4
3
TAKEY [7:0]
2
1
0
Reset
00H
ISP enable bit (ISPE) is read-only by default, software must write three specific values 55h, AAh and 5Ah sequentially
to the TAKEY register to enable the ISPE bit write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
Mnemonic: IFCON
7
6
CDPR
5
-
4
-
3
-
2
-
1
-
Address: 8FH
0
Reset
ISPE
00H
The bit 0 (ISPE) of IFCON is ISP enable bit. User can enable overall SM39R08A3 ISP function by setting ISPE
bit to 1, to disable overall ISP function by set ISPE to 0. The function of ISPE behaves like a security key. User
can disable overall ISP function to prevent software program be erased accidentally. ISP registers ISPFAH,
ISPFAL, ISPFD and ISPFC are read-only by default. Software must be set ISPE bit to 1 to enable these 4
registers write attribute.
Mnemonic: ISPFAH
7
6
-
-
5
4
3
2
1
ISPFAH5
ISPFAH4
ISPFAH3
ISPFAH2
ISPFAH1
Address: E1H
0
Reset
ISPFAH0
FFH
ISPFAH [5:0]: Flash address-high for ISP function
Mnemonic: ISPFAL
7
6
ISPFAL7 ISPFAL6
5
ISPFAL5
4
ISPFAL4
3
ISPFAL3
2
ISPFAL2
1
ISPFAL1
Address: E2H
0
Reset
ISPFAL0
FFH
ISPFAL [7:0]: Flash address-Low for ISP function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 79 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
The ISPFAH & ISPFAL provide the 14-bit flash memory address for ISP function. The flash memory address
should not include the ISP service program space address. If the flash memory address indicated by ISPFAH
& ISPFAL registers overlay with the ISP service program space address, the flash program/page erase of ISP
function executed thereafter will have no effect.
Mnemonic: ISPFD
7
6
ISPFD7
ISPFD6
5
ISPFD5
4
ISPFD4
3
ISPFD3
2
ISPFD2
1
ISPFD1
Address: E3H
0
Reset
ISPFD0
FFH
ISPFD [7:0]: Flash data for ISP function.
The ISPFD provide the 8-bit data register for ISP function.
Mnemonic: ISPFC
7
6
5
EMF1
EMF3
4
EMF4
3
-
2
ISPF[2]
1
ISPF[1]
Address: E4H
0
Reset
ISPF[0]
00H
EMF1: Entry mechanism (1) flag, clear by reset. (Read only)
EMF3: Entry mechanism (3) flag, clear by reset. (Read only)
EMF4: Entry mechanism (4) flag, clear by reset. (Read only)
ISPF [2:0]: ISP function select bit.
ISPF[2:0]
ISP function
000
Byte program
001
Chip protect
010
Page erase
011
Chip erase
100
Write option
101
Read option
110
Erase option
111
reserved
One page of flash memory is 128byte
The Option function can access the XTAL1 and XTAL2 swap to I/O pins
select(description in section 1.2)、Internal reset time select(description in section
1.4.1)、clock source select(description in section 1.5)、Reset swap to I/O pins
function select(description in section 5)、WDTEN control bit(description in section 9)、
or ISP entry mechanisms select(description in section 18).
When chip protected or no ISP service, option can only read.
The choice ISP function will start to execute once the software write data to ISPFC register.
To perform byte program/page erases ISP function, user need to specify flash address at first. When
performing page erase function, SM39R08A3 will erase entire page which flash address indicated by ISPFAH
& ISPFAL registers located within the page.
e.g. flash address: $ XYMN
page erase function will erase from $XY00 to $XYFF
To perform the chip erase ISP function, SM39R08A3 will erase all the flash program memory except the ISP
service program space. To perform chip protect ISP function, the SM39R08A3 flash memory content will be
read #00H.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 80 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable ISPE write attribute
ORL IFCON, #01H
; enable SM39R08A3 ISP function
MOV ISPFAH, #10H ; set flash address-high, 10H
MOV ISPFAL, #05H
; set flash address-low, 05H
MOV ISPFD, #22H
; set flash data to be programmed, data = 22H
MOV ISPFC, #00H
; start to program #22H to the flash address $1005H
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable ISPE write attribute
ANL IFCON, #0FEH
; disable SM39R08A3 ISP function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 81 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
19. Comparator
SM39R08A3 had integrated two Comparator module on chip. This module supports Comparator modes individually
according to user‟s configuration. When Comparator Mode enabled, an internal reference voltage is available to be
configured on comparator terminals.
Comparator SFRs as follows:
Mnemoni
c
OpPin
Cmp0CO
N
Cmp1CO
N
Description
OpCmp Pin
Select
Comparator_
0 control
Comparator_
1 control
Addr
F6h
FEh
FFh
Bit 7
Hys0E
n
Hys1E
n
Mnemonic: OpPin
7
6
5
Cmp0_E C0PosVB
n
G
Bit 6
Cmp0
_En
Cmp0
o
Cmp1
o
Bit 5
Bit 4
Comparator
C0PosVB C0PosP
G
ad
4
C0PosP
ad
Bit 3
-
CMF0MS[1:0]
CMF0
CMF1MS[1:0]
CMF1
3
-
2
Cmp1_
En
Bit 2
Bit 1
Bit 0
RST
Cmp1_
En
Cmp0
OutEN
Cmp1
OutEN
C1PosV
BG
C1PosP
ad
00h
-
-
00h
-
-
00h
1
C1PosVB
G
Address: F6h
0
Reset
C1PosP
00h
ad
Cmp0_En : Cmp0 enable.
1: Comparator_0 circuit enables and switch to corresponding signal in multifunction pin P0.3/P0.4/P0.6 by HW automatically.
C0PosVBG : Select Comparator_0 positive input source
1: set positive input source as internal reference voltage (1.2V±10%)
C0PosPad: Select Comparator_0 positive input source
1: set positive input source as external pin
Cmp1_En : Cmp1 enable.
1: Comparator_1 circuit enables and switch to corresponding signal in multifunction pin P0.0/P0.1/P0.2 by HW automatically.
C1PosVBG: Select Comparator_1 positive input source
1: set positive input source as internal reference voltage (1.2V±10%)
C1PosPad: Select Comparator_1 positive input source
1: set positive input source as external pin
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 82 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
CmpxOut、Cmpx_En、CxPosVBG及CxPosPad setting table：
Cmpx_En
0
1
1
1
1
CxPosVBG
CxPosPad
CmpxOut_En
X
X
0
1
0
1
1
0
1
0
Mnemonic: Cmp0CON
7
6
5
Hys0En
Cmp0o
CmpxPIn
IO
IO
IO
CMP
CMP
X
0
1
0
1
4
CMF0MS[1:0]
3
CMF0
2
Cmp0
OutEN
Comparator
CmpxNIn CmpxOUT
IO
IO
CMP
IO
IO
CMP
CMP
IO
CMP
CMP
Address:FEh
1
0
Reset
-
-
00h
Hys0En: Hysteresis function enable
0: disable Hysteresis at comparator_0 input
1: enable
Cmp0o: Comparator_0 output (read only)
0: The positive input source was lower than negative input source
1: The positive input source was higher than negative input source
CMF0MS[1:0] : CMF0(Comparator_0 Flag) setting mode select
00: CMF0 will be set when comprator_0 output toggle
01: CMF0 will be set when comprator_0 output rising
10: CMF0 will be set when comprator_0 output falling
11: reserved
CMF0: Comparator_0 Flag
This bit is setting by hardware according to meet CMF0MS [1:0] select condition.
This bit must clear by software.
Cmp0OutEN: Comparator0 Output Enable
0: Comparator0 will not output to external Pin
1: Comparator0 will output to external Pin
Mnemonic: Cmp1CON
7
6
5
Hys1En
Cmp1o
4
CMF1MS[1:0]
3
2
1
0
CMF1
Cmp1
OutEN
-
-
Address:FFh
Reset
00h
Hys1En: Hysteresis function enable
0: disable Hysteresis at comparator_1 input
1: enable
Cmp1o: Comparator_1 output (read only)
0: The positive input source was lower than negative input source
1: The positive input source was higher than negative input source
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 83 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
CMF1MS[1:0] : CMF1(Comparator_1 Flag) setting mode select
00: CMF1 will be set when comprator_1 output toggle
01: CMF1 will be set when comprator_1 output rising
10: CMF1 will be set when comprator_1 output falling
11: reserved
CMF1: Comparator_1 Flag
This bit is setting by hardware according to meet CMF1MS [1:0] select condition.
This bit must clear by software.
Cmp1OutEN: Comparator1 Output Enable
0: Comparator0 will not output to external Pin
1: Comparator0 will output to external Pin
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 84 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit.
Remarks
TA
Operating temperature
-40
25
85
℃
Ambient temperature under bias
VDD
Supply voltage
1.8
5.5
V
1.3
V
Vref
Internal reference voltage
1.1
1.2
DC Characteristics
TA = -40℃ to 85℃, Vcc = 5.0V
Symbol
Parameter
Valid
VIL1
Input Low-voltage
Port 0,1,3
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 0,1,3
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Port 0,1,3
P0.5/P0.7/P1.2/P1.5/
P1.6/P1.7/P3.0/P3.1
VOH1
VOH2
IIL
ITL
ILI
RRST
Min
TPY
Max
Units
-0.5
0.8
V
0
0.8
VCC +
0.5
VCC +
0.5
0.45
V
V
IOL=16mA Vcc=5V
0.45
V
IOL=39mA Vcc=5V
V
IOH= -8mA
V
IOH= -16mA
V
IOH= -250uA
-75
uA
Vin= 0.45V
-650
uA
Vin= 2.0V
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
3.3
5
mA
5
7
mA
4
6
mA
2
7
uA
2.0
70%Vcc
90% VCC
Port 0,1,3
Output High-voltage
(1)
using Strong Pull-up P0.5/P0.7/P1.2/P1.5/ 90% VCC
P1.6/P1.7/P3.0/P3.1
Output High-voltage
Port 0,1,3
2.4
using Weak Pull-up(2)
Logic 0 Input Current Port 0,1,3
Logical Transition
Port 0,1,3
Current
Input Leakage Current Port 0,1,3
Reset Pull-down
RES
50
Conditions
Vcc=5V
V
V
Resistor
CIO
ICC
Pin Capacitance
Power Supply Current VDD
Freq= 1MHz, Ta=
25℃
Active
mode ,IRC=22.1184MHz
Active mode, 12MHz
VCC =5V 25 ℃
Idle mode, 12MHz
VCC =5V 25 ℃
Power down mode
VCC =5V 25 ℃
Notes: 1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 85 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
TA = -40℃ to 85℃, VCC = 3.0V
Symbol
Parameter
Valid
VIL1
Input Low-voltage
Port 0,1,3
VIL2
Input Low-voltage
RES, XTAL1
VIH1
Input High-voltage
Port 0,1,3
VIH2
Input High-voltage
RES, XTAL1
VOL
Output Low-voltage
Port 0,1,3
P0.5/P0.7/P1.2/P1.5/
P1.6/P1.7/P3.0/P3.1
Output High-voltage
Port 0,1,3
VOH1
VOH2
IIL
ITL
ILI
RRST
CIO
ICC
Min
TPY
Max
Units
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc
VCC + 0.5
V
0.45
V
IOL=15mA
Vcc=3.0V
0.45
V
IOL=25mA
Vcc=3.0V
V
IOH= -5.5mA
90% VCC
using Strong Pull-up(1) P1.6/P1.7/P3.0/P3.1 90% VCC
Output High-voltage
(2)
using Weak Pull-up
Logic 0 Input Current
Port 0,1,3
Conditions
Vcc=3.0V
IOH= -11mA
2.4
V
IOH= -77uA
Port 0,1,3
-75
uA
Vin= 0.45V
Port 0,1,3
Current
Input Leakage Current Port 0,1,3
-650
uA
Vin=1.5V
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
3.2
5
mA
2.5
4
mA
2
3.5
mA
1
5
uA
Logical Transition
Reset Pull-down
RES
50
Resistor
Pin Capacitance
Power Supply Current VDD
Freq= 1MHz, Ta= 25℃
Active
mode ,IRC=22.1184MHz
Active mode ,12MHz
VCC = 3.0 V 25 ℃
Idle mode, 12MHz VCC
=3.0V 25 ℃
Power down mode VCC
=3.0V 25 ℃
Notes： 1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Absolute Maximum Ratings
SYMBOL
Maximum sourced current
PARAMETER
Total I/O pins
MAX
100
UNIT
mA
Total I/O pins
100
mA
Max. Junction Temperature
150
℃
(Push-pull)
Maximum sunk current
Tj
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 86 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
ADC Characteristics
Operation
Symbol
Test Condition
MIN
VDD
VDD
2.7
TYP
Resolution
MAX
Unit
5.5
V
10
bit
Conversion time
13tADC
us
Sample rate
870k
Hz
Integral Non-Linearity Error
INL
-1
1
LSB
Differential Non-Linearity
DNL
-1
1
LSB
-5.25
MHz
Clock frequency
ADCCLK
11.36
Comparator Characteristics
Ta=25℃
Symbol
IOP
Description
Test Condition
VDD
Condition
MIN
TPY
MAX
Unit
Operating current
5
-
-
10
10
uA
-
Power Down Current
5
-
-
-
0.1
uA
-
Offset voltage
5
-
-10
-
+10
mV
Input voltage commom mode
range
-
-
Vss
-
Vdd-1.5
V
Propagation delay
5
△
Vin=10mV
-
3
6
us
VCM
Tp
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 87 -
SM39R08A3
8-Bit Micro-controller
with 8KB+1KB ISP Flash
& 512B RAM embedded
LVI& LVR Characteristics
1.8V ~ 5.5V
Min
VIL=1.4V
LVR
Typical
VIL=1.5V
LVI
Min
Typical
LVIS[1:0] = 00
VIL=1.6V
VIL=1.7V
LVIS[1:0] = 01
VIL=2.5V
VIL=2.6V
LVIS[1:0] = 10
VIL=3.1V
VIL=3.2V
LVIS[1:0] = 11
VIL=3.9V
VIL=4.0V
Notes : The VLVI always above VLVR about 0.2V
Max
VIL=1.6V
Max
VIL=1.8V
VIL=2.7V
VIL=3.3V
VIL=4.1V
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M063
Ver C SM39R08A3 04/20/2013
- 88 -