Isolated, Single-Channel RS-232 Line Driver/Receiver ADM3251E FEATURES FUNCTIONAL BLOCK DIAGRAM C3 0.1µF 10V C1 0.1µF 16V C1+ C1– V+ ADM3251E VCC OSC VISO 0.1µF C2+ C2– VOLTAGE DOUBLER RECT C2 0.1µF 16V C4 0.1µF 16V V– VOLTAGE INVERTER REG 0.1µF ROUT TIN DECODE ENCODE ENCODE DECODE GND R T RIN* TOUT GNDISO *INTERNAL 5kΩ PULL-DOWN RESISTOR ON THE RS-232 INPUT. 07388-001 2.5 kV fully isolated (power and data) RS-232 transceiver isoPower integrated, isolated dc-to-dc converter 460 kbps data rate 1 Tx and 1 Rx Meets EIA/TIA-232E specifications ESD protection on RIN and TOUT pins ±8 kV: contact discharge ±15 kV: air gap discharge 0.1 μF charge pump capacitors High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals UL recognition 2500 V rms for 1 minute per UL 1577 VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01 CSA Component Acceptance Notice #5A Operating temperature range: −40°C to +85°C Wide body, 20-lead SOIC package Figure 1. APPLICATIONS High noise data communications Industrial communications General-purpose RS-232 data links Industrial/telecommunications diagnostic ports Medical equipment GENERAL DESCRIPTION The ADM3251E is a high speed, 2.5 kV fully isolated, singlechannel RS-232/V.28 transceiver device that operates from a single 5 V power supply. Due to the high ESD protection on the RIN and TOUT pins, the device is ideally suited for operation in electrically harsh environments or where RS-232 cables are frequently being plugged and unplugged. transformer. Special care must be taken during printed circuit board (PCB) layout to meet emissions standards. Refer to Application Note AN-0971, Control of Radiated Emissions with isoPower Devices, for details on board layout considerations. The ADM3251E incorporates dual-channel digital isolators with isoPower™ integrated, isolated power. There is no requirement to use a separate isolated dc-to-dc converter. Chip-scale transformer iCoupler® technology from Analog Devices, Inc., is used both for the isolation of the logic signals as well as for the integrated dc-to-dc converter. The result is a total isolation solution. Four external 0.1 μF charge pump capacitors are used for the voltage doubler/inverter, permitting operation from a single 5 V supply. The ADM3251E conforms to the EIA/TIA-232E and ITU-T V. 28 specifications and operates at data rates up to 460 kbps. The ADM3251E is available in a 20-lead, wide body SOIC package and is specified over the −40°C to +85°C temperature range. The ADM3251E contains isoPower technology that uses high frequency switching elements to transfer power through the Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. ADM3251E TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 11 Applications ....................................................................................... 1 Isolation of Power and Data ...................................................... 11 Functional Block Diagram .............................................................. 1 Charge Pump Voltage Converter ............................................. 12 General Description ......................................................................... 1 5.0 V Logic to EIA/TIA-232E Transmitter.............................. 12 Revision History ............................................................................... 2 EIA/TIA-232E to 5 V Logic Receiver ...................................... 12 Specifications..................................................................................... 3 High Baud Rate ........................................................................... 12 Package Characteristics ............................................................... 5 Thermal Analysis ....................................................................... 12 Regulatory Information ............................................................... 5 Insulation Lifetime ..................................................................... 12 Insulation and Safety-Related Specifications ............................ 5 Applications Information .............................................................. 13 DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01 Insulation Characteristics .............................................................................. 6 PCB Layout ................................................................................. 13 Absolute Maximum Ratings............................................................ 7 Isolated Power Supply Circuit .................................................. 14 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 15 Pin Configuration and Function Descriptions ............................. 8 Ordering Guide .......................................................................... 15 Example PCB for Reduced EMI ............................................... 13 Typical Performance Characteristics ............................................. 9 REVISION HISTORY 5/10—Rev. D to Rev. E Changes to Features Section............................................................ 1 Changes to Table 4 ............................................................................ 5 3/10—Rev. C to Rev. D Changes to Features and General Description Sections.............. 1 Changes to Table 4 and Table 5 ....................................................... 5 Changed DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics (Pending) Heading to DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01 Insulation Characteristics ................................................................................... 6 Changes to Pollution Degree and Input–to-Output Test Voltage Parameters, Table 6............................................................. 6 Added Applications Information Section and Example PCB for Reduced EMI Section .............................................................. 13 Added Table 9 and Table 10; Renumbered Sequentially ........... 13 Changes to PCB Layout Section ................................................... 13 Added Isolated Power Supply Circuit Section ............................ 14 Added Figure 22; Renumbered Sequentially .............................. 14 11/09—Rev. A to Rev. B Changes to Figure 1 ...........................................................................1 Changed to Primary Side Supply Input Current, ICC(DISABLE) Maximum Limit to 2.5 mA ..............................................................4 Changes to Table 4.............................................................................5 Changes to Figure 13...................................................................... 11 9/08—Rev. 0 to Rev. A Changes to Timing Parameters in Table 1 .....................................3 Changes to Timing Parameters in Table 2 .....................................4 Changes to Ordering Guide .......................................................... 14 7/08—Revision 0: Initial Version 1/10—Rev. B to Rev. C Changes to Table 4 ............................................................................ 5 Rev. E | Page 2 of 16 ADM3251E SPECIFICATIONS All voltages are relative to their respective ground; all minimum/maximum specifications apply over the entire recommended operating range; TA = 25°C and VCC = 5.0 V (dc-to-dc converter enabled), unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS VCC Operating Voltage Range DC-to-DC Converter Enable Threshold, VCC(ENABLE) 1 DC-to-DC Converter Disable Threshold, VCC(DISABLE)1 DC-to-DC Converter Enabled Input Supply Current, ICC(ENABLE) VISO Output 2 LOGIC Transmitter Input, TIN Logic Input Current, ITIN Logic Low Input Threshold, VTINL Logic High Input Threshold, VTINH Receiver Output, ROUT Logic High Output, VROUTH Min 4.5 4.5 AC SPECIFICATIONS Output Rise/Fall Time, tR/tF (10% to 90%) Common-Mode Transient Immunity at Logic High Output 4 Common-Mode Transient Immunity at Logic Low Output4 ESD PROTECTION (RIN And TOUT PINS) Max Unit 5.5 V V V 3.7 110 145 mA mA V +10 0.3 VCC μA V V 5.0 −10 +0.01 0.7 VCC VCC − 0.1 VCC − 0.5 Logic Low Output, VROUTL RS-232 Receiver, RIN EIA-232 Input Voltage Range 3 EIA-232 Input Threshold Low EIA-232 Input Threshold High EIA-232 Input Hysteresis EIA-232 Input Resistance Transmitter, TOUT Output Voltage Swing (RS-232) Transmitter Output Resistance Output Short-Circuit Current (RS-232) TIMING CHARACTERISTICS Maximum Data Rate Receiver Propagation Delay tPHL tPLH Transmitter Propagation Delay Transmitter Skew Receiver Skew Transition Region Slew Rate3 Typ −30 0.6 3 ±5 300 VCC VCC − 0.3 0.0 0.3 0.1 0.4 +30 2.0 2.1 0.1 5 2.4 7 ±5.7 ±12 460 5.5 190 135 650 80 70 10 30 V V V V Test Conditions/Comments VCC = 5.5 V, no load VCC = 5.5 V, RL = 3 kΩ IISO = 0 μA IROUTH = −20 μA IROUTH = −4 mA IROUTH = 20 μA IROUTH = 4 mA V V V V kΩ V Ω mA RL = 3 kΩ to GND VISO = 0 V kbps RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF ns ns ns ns ns V/μs RL = 3 kΩ, CL = 1000 pF +3 V to −3 V or −3 V to +3 V, VCC = +3.3 V, RL = 3 kΩ, CL = 1000 pF, TA = 25°C 2.3 ns kV/μs kV/μs CL = 15 pF, CMOS signal levels VCM = 1 kV, transient magnitude = 800 V VCM = 1 kV, transient magnitude = 800 V ±15 ±8 kV kV Human body model air discharge Human body model contact discharge 25 25 1 Enable/disable threshold is the VCC voltage at which the internal dc-to-dc converter is enabled/disabled. To maintain data sheet specifications, do not draw current from VISO. 3 Guaranteed by design. 4 VCM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 2 Rev. E | Page 3 of 16 ADM3251E All voltages are relative to their respective ground; all minimum/maximum specifications apply over the entire recommended operating range; TA = 25°C, VCC = 3.3 V (dc-to-dc converter disabled), and the secondary side is powered externally by VISO = 3.3 V, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS VCC Operating Voltage Range DC-to-DC Converter Disable Threshold, VCC(DISABLE) 1 DC-to-DC Converter Disabled VISO 2 Primary Side Supply Input Current, ICC(DISABLE) Secondary Side Supply Input Current, IISO(DISABLE) Secondary Side Supply Input Current, IISO(DISABLE) LOGIC Transmitter Input, TIN Logic Input Current, ITIN Logic Low Input Threshold, VTINL Logic High Input Threshold, VTINH Receiver Output, ROUT Logic High Output, VROUTH Min Max Unit 3.0 3.7 3.7 V V 3.0 5.5 2.5 12 V mA mA mA +10 0.3 VCC μA V V 6.2 −10 AC SPECIFICATIONS Output Rise/Fall Time, tR/tF (10% to 90%) Common-Mode Transient Immunity at Logic High Output 4 Common-Mode Transient Immunity at Logic Low Output4 ESD PROTECTION (RIN AND TOUT PINS) +0.01 0.7 VCC VCC − 0.1 VCC − 0.5 Logic Low Output, VROUTL RS-232 Receiver, RIN EIA-232 Input Voltage Range 3 EIA-232 Input Threshold Low EIA-232 Input Threshold High EIA-232 Input Hysteresis EIA-232 Input Resistance Transmitter, TOUT Output Voltage Swing (RS-232) Transmitter Output Resistance Output Short-Circuit Current (RS-232) TIMING CHARACTERISTICS Maximum Data Rate Receiver Propagation Delay tPHL tPLH Transmitter Propagation Delay Transmitter Skew Receiver Skew Transition Region Slew Rate3 Typ −30 0.6 3 ±5 300 VCC VCC − 0.3 0.0 0.3 0.1 0.4 +30 1.3 1.6 0.3 5 2.4 7 ±5.7 ±11 460 5.5 190 135 650 80 55 10 2.3 25 25 ±15 ±8 1 30 V V V V Test Conditions/Comments No load VISO = 5.5 V, RL = 3 kΩ RL = 3 kΩ IROUTH = −20 μA IROUTH = −4 mA IROUTH = 20 μA IROUTH = 4 mA V V V V kΩ V Ω mA RL = 3 kΩ to GND VISO = 0 V kbps RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF ns ns ns ns ns V/μs ns kV/μs kV/μs kV kV RL = 3 kΩ, CL = 1000 pF +3 V to −3 V or −3 V to +3 V, VCC = 3.3 V, RL = 3 kΩ, CL = 1000 pF, TA = 25°C CL = 15 pF, CMOS signal levels VCM = 1 kV, transient magnitude = 800 V VCM = 1 kV, transient magnitude = 800 V Human body model air discharge Human body model contact discharge Enable/disable threshold is the VCC voltage at which the internal dc-to-dc converter is enabled/disabled. To maintain data sheet specifications, do not draw current from VISO. Guaranteed by design. 4 VCM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 2 3 Rev. E | Page 4 of 16 ADM3251E PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input-to-Output) Capacitance (Input-to-Output) Input Capacitance IC Junction-to-Air Thermal Resistance Symbol RI-O CI-O CI θJA Min Typ 1012 2.2 4.0 47.05 Max Unit Ω pF pF °C/W Test Conditions f = 1 MHz REGULATORY INFORMATION Table 4. UL 1 Recognized under 1577 Component Recognition Program File E214100 1 2 VDE 2 Certified according to DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01 File 2471900-4880-0001/123328 CSA Approved under CSA Component Acceptance Notice #5A Basic Insulation per CSA 60950-1-07 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage File 2268268 In accordance with UL 1577, each ADM3251E is proof-tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA). Each ADM3251E is proof tested by applying an insulation test voltage ≥4000 V peak for 1 sec (partial discharge detection limit = 5 pC). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Maximum Working Voltage Compatible with 50-Year Service Life L(I01) Value 2500 7.7 Unit V rms mm L(I02) 4.16 mm 0.017 >175 IIIa 425 mm V Conditions 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 V peak Continuous peak voltage across the isolation barrier CTI VIORM Rev. E | Page 5 of 16 ADM3251E DIN EN 60747-5-2 (VDE 0884 TEIL 2): 2003-01 INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. Table 6. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms Climatic Classification Pollution Degree Maximum Working Insulation Voltage Input-to-Output Test Voltage Method b1 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Supply Current Insulation Resistance at TS Conditions VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure VIO = 500 V Rev. E | Page 6 of 16 Symbol Characteristic Unit VIORM I to IV I to III 40/105/21 2 424 V peak VPR 795 V peak VTR 4000 V peak TS IS1 RS 150 531 >109 °C mA Ω ADM3251E ABSOLUTE MAXIMUM RATINGS Table 7. Parameter VCC, VISO V+ V− Input Voltages TIN RIN Output Voltages TOUT ROUT Short-Circuit Duration TOUT Power Dissipation θJA, Thermal Impedance Operating Temperature Range Industrial Storage Temperature Range Pb-Free Temperature (Soldering, 30 sec) Rating −0.3 V to +6 V (VCC − 0.3 V) to +13 V –13 V to +0.3 V −0.3 V to (VCC + 0.3 V) ±30 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ±15 V −0.3 V to (VCC + 0.3 V) Continuous 47.05°C/W −40°C to +85°C −65°C to +150°C 260°C Rev. E | Page 7 of 16 ADM3251E NC 1 20 VISO VCC 2 19 V+ VCC 3 18 C1+ GND 4 ADM3251E 17 C1– GND 5 TOP VIEW (Not to Scale) 16 TOUT 15 RIN GND 7 14 C2+ ROUT 8 13 C2– TIN 9 12 V– GND 10 11 GNDISO GND 6 NC = NO CONNECT 07388-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2, 3 Mnemonic NC VCC 4, 5, 6, 7, 10 8 9 11 12 13, 14 GND ROUT TIN GNDISO V− C2−, C2+ 15 16 17, 18 RIN TOUT C1−, C1+ 19 20 V+ VISO Description No Connect. This pin should always remain unconnected. Power Supply Input. A 0.1 μF decoupling capacitor is required between VCC and ground. When a voltage between 4.5 V and 5.5 V is applied to the VCC pin, the integrated dc-to-dc converter is enabled. If this voltage is lowered to between 3.0 V and 3.7 V, the integrated dc-to-dc converter is disabled. Ground. Receiver Output. This pin outputs CMOS logic levels. Transmitter (Driver) Input. This pin accepts TTL/CMOS levels. Ground Reference for Isolator Primary Side. Internally Generated Negative Supply. Positive and Negative Connections for Charge Pump Capacitors. External Capacitor C2 is connected between these pins; a 0.1 μF capacitor is recommended, but larger capacitors up to 10 μF can be used. Receiver Input. This input accepts RS-232 signal levels. Transmitter (Driver) Output. This outputs RS-232 signal levels. Positive and Negative Connections for Charge Pump Capacitors. External Capacitor C1 is connected between these pins; a 0.1 μF capacitor is recommended, but larger capacitors up to 10 μF can be used. Internally Generated Positive Supply. Isolated Supply Voltage for Isolator Secondary Side. A 0.1 μF decoupling capacitor is required between VISO and ground. When the integrated dc-to-dc converter is enabled, the VISO pin should not be used to power external circuitry. If the integrated dc-to-dc converter is disabled, power the secondary side by applying a voltage in the range of 3.0 V to 5.5 V to this pin. Rev. E | Page 8 of 16 ADM3251E TYPICAL PERFORMANCE CHARACTERISTICS 12 12 Tx HIGH (VCC = 5V) Tx OUTPUT HIGH (VCC = 5V) 10 8 8 Tx HIGH (VISO = 3.3V) 4 6 Tx OUTPUT HIGH (VISO = 3.3V) Tx OUTPUT (V) Tx OUTPUT (V) 4 0 –4 Tx LOW (VISO = 3.3V) 2 0 –2 –4 Tx OUTPUT LOW (VISO = 3.3V) –6 –8 –8 –10 0 200 400 600 LOAD CAPACITANCE (pF) 800 07388-004 –12 1000 Tx OUTPUT LOW (VCC = 5V) –12 0 1 2 LOAD CURRENT (mA) 3 4 07388-006 Tx LOW (VCC = 5V) Figure 6. Transmitter Output Voltage High/Low vs. Load Current Figure 3. Transmitter Output Voltage High/Low vs. Load Capacitance at 460 kbps 12 15 Tx OUTPUT HIGH 10 V+ (VCC = 5V) 10 8 6 5 V+, V– (V) Tx OUTPUT (V) 4 2 0 –2 V+ (VISO = 3.3V) 0 V– (VISO = 3.3V) –5 –4 –6 –10 4.9 5.1 5.3 5.5 –15 VCC (V) 0 2 LOAD CURRENT (mA) 3 4 Figure 7. Charge Pump V+, V− vs. Load Current Figure 4. Transmitter Output Voltage High/Low vs. VCC, RL = 3 kΩ 400 12 V– 10 Tx OUTPUT HIGH 350 CHARGE PUMP IMPEDANCE (Ω) 8 6 Tx OUTPUT (V) 1 07388-007 4.7 07388-005 –10 4.5 V– (VCC = 5V) Tx OUTPUT LOW –8 4 2 0 –2 –4 Tx OUTPUT LOW –6 –8 300 250 V+ 200 150 100 50 3.5 4.0 4.5 VISO (V) 5.0 5.5 0 4.50 07388-009 –12 3.0 4.75 5.00 VCC (V) 5.25 Figure 8. Charge Pump Impedance vs. VCC Figure 5. Transmitter Output Voltage High/Low vs. VISO, RL = 3 kΩ Rev. E | Page 9 of 16 5.50 07388-008 –10 ADM3251E 400 250 200 5V/DIV V– 300 1 5V/DIV CHARGE PUMP IMPEDANCE (Ω) 350 2 V+ 150 100 50 3.75 4.00 4.25 4.50 VISO (V) 4.75 5.00 5.25 5.50 TIME (500ns/DIV) Figure 9. Charge Pump Impedance vs. VISO Figure 11. 460 kbps Data Transmission 5.0 200 4.5 180 VCC = 5.5V TIN VOLTAGE THRESHOLD (V) 160 140 120 VCC = 5V 100 VCC = 4.5V 80 60 40 4.0 3.5 HIGH THRESHOLD 3.0 2.5 2.0 LOW THRESHOLD 1.5 1.0 0 0 46 92 138 184 230 276 322 DATA RATE (kbps) 368 414 460 Figure 10. Primary Supply Current vs. Data Rate 0 4.50 4.75 5.00 VCC (V) 5.25 Figure 12. TIN Voltage Threshold vs. VCC Rev. E | Page 10 of 16 5.50 07388-011 0.5 20 07388-003 SUPPLY CURRENT (mA) 07388-012 3.25 3.50 VCC = 5V LOAD = 3kΩ AND 1nF 07388-010 0 3.00 ADM3251E THEORY OF OPERATION The TIN pin accepts TTL/CMOS input levels. The driver input signal that is applied to the TIN pin is referenced to logic ground (GND). It is coupled across the isolation barrier, inverted, and then appears at the transceiver section, referenced to isolated ground (GNDISO). Similarly, the receiver input (RIN) accepts RS-232 signal levels that are referenced to isolated ground. The RIN input is inverted and coupled across the isolation barrier to appear at the ROUT pin, referenced to logic ground. The ADM3251E is a high speed, 2.5 kV fully isolated, singlechannel RS-232 transceiver device that operates from a single power supply. The internal circuitry consists of the following main sections: Isolation of power and data A charge pump voltage converter A 5.0 V logic to EIA/TIA-232E transmitter A EIA/TIA-232E to 5.0 V logic receiver C1+ C1– V+ ADM3251E VCC OSC 0.1µF VISO C2+ C2– VOLTAGE DOUBLER RECT C2 0.1µF 16V The digital signals are transmitted across the isolation barrier using iCoupler technology. Chip-scale transformer windings couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer of the winding. At the secondary winding, the induced waveforms are decoded into the binary value that was originally transmitted. C4 0.1µF 16V V– VOLTAGE INVERTER REG 0.1µF TIN DECODE ENCODE ENCODE DECODE GND R T RIN* TOUT GNDISO VISO 07388-013 ROUT There is hysteresis in the VCC input voltage detect circuit. Once the dc-to-dc converter is active, the input voltage must be decreased below the turn-on threshold to disable the converter. This feature ensures that the converter does not go into oscillation due to noisy input power. *INTERNAL 5kΩ PULL-DOWN RESISTOR ON THE RS-232 INPUT. 4.5V TO 5.5V VCC 0.1µF Figure 13. Functional Block Diagram V+ ADM3251E C1+ C1– ISOLATION OF POWER AND DATA The ADM3251E incorporates a dc-to-dc converter section, which works on principles that are common to most modern power supply designs. VCC power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. Power is transferred to the secondary side, where it is rectified to a high dc voltage. The power is then linearly regulated to about 5.0 V and supplied to the secondary side data section and to the VISO pin. The VISO pin should not be used to power external circuitry. CMOS OUTPUT RIN CMOS INPUT TIN C2+ C2– V– ISOLATION BARRIER GND + 0.1µF + C1 0.1µF 16V EIA/TIA-232E OUTPUT EIA/TIA-232E INPUT + C2 0.1µF 16V C4 + 0.1µF 16V GNDISO Figure 14. Typical Operating Circuit with the DC-to-DC Converter Enabled (VCC = 4.5 V to 5.5 V) Because the oscillator runs at a constant high frequency independent of the load, excess power is internally dissipated in the output voltage regulation process. Limited space for transformer coils and components also adds to internal power dissipation. This results in low power conversion efficiency. 3.0V TO 5.5V ISOLATED SUPPLY VISO 3.0V TO 3.7V VCC 0.1µF The ADM3251E can be operated with the dc-to-dc converter enabled or disabled. The internal dc-to-dc converter state of the ADM3251E is controlled by the input VCC voltage. In normal operating mode, VCC is set between 4.5 V and 5.5 V and the internal dc-to-dc converter is enabled. To disable the dc-to-dc converter, lower VCC to a value between 3.0 V and 3.7 V. In this mode, the user must externally supply isolated power to the VISO pin. An isolated secondary side voltage of between 3.0 V and 5.5 V and a secondary side input current, IISO, of 12 mA (maximum) is required on the VISO pin. The signal channels of the ADM3251E then continue to operate normally. TOUT ROUT C3 + 0.1µF 10V 07388-014 C3 0.1µF 10V C1 0.1µF 16V V+ ADM3251E C1+ C1– CMOS OUTPUT TOUT ROUT RIN CMOS INPUT TIN C2+ C2– V– ISOLATION BARRIER GND GNDISO C3 + 0.1µF 10V + 0.1µF + C1 0.1µF 16V EIA/TIA-232E OUTPUT EIA/TIA-232E INPUT + C2 0.1µF 16V C4 + 0.1µF 16V 07388-015 • • • • Figure 15. Typical Operating Circuit with the DC-to-DC Converter Disabled (VCC = 3.0 V to 3.7 V) Rev. E | Page 11 of 16 ADM3251E CHARGE PUMP VOLTAGE CONVERTER THERMAL ANALYSIS The charge pump voltage converter consists of a 200 kHz oscillator and a switching matrix. The converter generates a ±10.0 V supply from the input 5.0 V level. This is done in two stages by using a switched capacitor technique as illustrated in Figure 16 and Figure 17. First, the 5.0 V input supply is doubled to 10.0 V by using C1 as the charge storage element. The +10.0 V level is then inverted to generate −10.0 V using C2 as the storage element. C3 is shown connected between V+ and VISO, but is equally effective if connected between V+ and GNDISO. Each ADM3251E device consists of three internal die, attached to a split-paddle lead frame. For the purposes of thermal analysis, it is treated as a thermal unit with the highest junction temperature reflected in the θJA value from Table 7. The value of θJA is based on measurements taken with the part mounted on a JEDEC standard 4-layer PCB with fine-width traces in still air. Following the recommendations in the PCB Layout section decreases the thermal resistance to the PCB, allowing increased thermal margin at high ambient temperatures. Capacitor C3 and Capacitor C4 are used to reduce the output ripple. Their values are not critical and can be increased, if desired. Larger capacitors (up to 10 μF) can be used in place of C1, C2, C3, and C4. INSULATION LIFETIME 5.0 V LOGIC TO EIA/TIA-232E TRANSMITTER The transmitter driver converts the 5.0 V logic input levels into RS-232 output levels. When driving an RS-232 load with VCC = 5.0 V, the output voltage swing is typically ±10 V. The insulation lifetime of the ADM3251E depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 18, Figure 19, and Figure 20 illustrate these different isolation voltage waveforms. S3 + S2 + C1 S4 V+ = 2VISO C3 VISO 07388-016 GND INTERNAL OSCILLATOR Bipolar ac voltage is the most stringent environment. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. Figure 16. Charge Pump Voltage Doubler S1 V+ FROM VOLTAGE DOUBLER GNDISO + S2 RATED PEAK VOLTAGE S3 C2 + S4 GNDISO 07388-019 S1 VISO All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADM3251E. 0V C4 V– = –(V+) 07388-017 Figure 18. Bipolar AC Waveform EIA/TIA-232E TO 5 V LOGIC RECEIVER The receiver is an inverting level-shifter that accepts the RS-232 input level and translates it into a 5.0 V logic output level. The input has an internal 5 kΩ pull-down resistor to ground and is also protected against overvoltages of up to ±30 V. An unconnected input is pulled to 0 V by the internal 5 kΩ pull-down resistor. This, therefore, results in a Logic 1 output level for an unconnected input or for an input connected to GND. The receiver has a Schmitt-trigger input with a hysteresis level of 0.1 V. This ensures error-free reception for both a noisy input and for an input with slow transition times. HIGH BAUD RATE The ADM3251E offers high slew rates, permitting data transmission at rates well in excess of the EIA/TIA-232E specifications. The RS-232 voltage levels are maintained at data rates up to 460 kbps. Rev. E | Page 12 of 16 0V 07388-020 RATED PEAK VOLTAGE Figure 17. Charge Pump Voltage Inverter Figure 19. Unipolar AC Waveform RATED PEAK VOLTAGE 0V 07388-021 INTERNAL OSCILLATOR Figure 20. DC Waveform Outline Dimensions ADM3251E APPLICATIONS INFORMATION PCB LAYOUT EXAMPLE PCB FOR REDUCED EMI The ADM3251E requires no external circuitry for its logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 21). Bypass capacitors are conveniently connected between Pin 3 and Pin 4 for VCC and between Pin 19 and Pin 20 for VISO. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. The choice of how aggressively EMI must be addressed for a design to pass emissions levels depends on the requirements of the design as well as cost and performance trade-offs. Because it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipating into the PCB through the ground pins. If the device is used at high ambient temperatures, care should be taken to provide a thermal path from the ground pins to the PCB ground plane. The board layout in Figure 21 shows enlarged pads for Pin 4, Pin 5, Pin 6, Pin 7, Pin 10, and Pin 11. Multiple vias should be implemented from each of the pads to the ground plane, which significantly reduce the temperatures inside the chip. The dimensions of the expanded pads are left to the discretion of the designer and the available board space. VIA TO GNDISO 0.1µF VISO C3 V+ NC VCC ADM3251E VCC C1+ 0.1µF C1 GND GND TOUT RIN C2+ GND C2– TIN 07388-018 GNDISO NC = NO CONNECT Layer Top Inner Layer 1 Inner Layer 2 Inner Layer 3 Inner Layer 4 Bottom Description Components and ground planes VCC planes All tracks Blank Buried capacitive plane Ground planes EMI Test Results 2-Layer PCB Emissions 6-Layer PCB Emissions Achieved EMI Reduction V– C4 GND Table 9. PCB Layers Table 10. EMI Test Results C2 ROUT A 6-layer PCB that employs edge guarding and buried capacitive bypassing, which are EMI mitigation techniques described in detail in Application Note AN-0971, was manufactured. The stackup of the 6-layer test PCB is shown in Table 9. PCB layout Gerber files are available upon request. EMI testing was repeated on the optimized board. The resulting reduction in radiated emissions is shown in Table 10. This board meets FCC Class B standards with no external shielding by utilizing buried stitching capacitors and edge fencing. C1– GND The starting point for this example is a 2-layer PCB. EMI reductions are relative to the emissions and noise from this board. To conform to FCC Class B levels, the emissions at these two frequencies must be less than 46 dBμV/m, normalized to 3 m antenna distance. As expected, EMI testing confirmed that the largest emissions peaks occur at the tank frequency and rectifier frequency. Figure 21. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. The power supply section of the ADM3251E uses a 300 MHz oscillator frequency to pass power through its chip-scale transformers. Operation at these high frequencies may raise concerns about radiated emissions and conducted noise. PCB layout and construction is a very important tool for controlling radiated emissions. Refer to Application Note AN-0971, Control of Radiated Emissions with isoPower Devices, for extensive guidance on radiation mechanisms and board layout considerations. Rev. E | Page 13 of 16 300 MHz 48 dB 36 dB 12 dB 600 MHz 53 dB 32 dB 21 dB ADM3251E ISOLATION BARRIER VCC To operate the ADM3251E with its internal dc-to-dc converter disabled, connect a voltage of between 3.0 V and 3.7 V to the VCC pin and apply an isolated power of between 3.0 V and 5.5 V to the VISO pin, referenced to GNDISO. SD103C 5V IN + TRANSFORMER DRIVER A transformer driver circuit with a center-tapped transformer and LDO can be used to generate the isolated supply, as shown in Figure 22. The center-tapped transformer provides electrical isolation of the 5 V power supply. The primary winding of the transformer is excited with a pair of square waveforms that are 180° out of phase with each other. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP3330 linear voltage regulator provides a regulated power supply to the bus side circuitry (VISO) of the ADM3251E. Rev. E | Page 14 of 16 VCC 22µF SD OUT ADP3330 + 10µF ERR NR GND 78253 SD103C VCC VCC VISO ADM3251E GND GNDISO Figure 22. Isolated Power Supply Circuit 07388-022 ISOLATED POWER SUPPLY CIRCUIT ADM3251E OUTLINE DIMENSIONS 13.00 (0.5118) 12.60 (0.4961) 20 11 7.60 (0.2992) 7.40 (0.2913) 10 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) ⋅ 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 060706-A 1 Figure 23. 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 ADM3251EARWZ ADM3251EARWZ-REEL EVAL-ADM3251EEBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 20-Lead Standard Small Outline Package [SOIC_W] 20-Lead Standard Small Outline Package [SOIC_W] Evaluation Board Z = RoHS Compliant Part. Rev. E | Page 15 of 16 Package Option RW-20 RW-20 ADM3251E NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07388-0-5/10(E) Rev. E | Page 16 of 16