a FEATURES Complete Dual Matching ADCs Low Power Dissipation: 215 mW (+3 V Supply) Single Supply: 2.7 V to 5.5 V Differential Nonlinearity Error: 0.4 LSB On-Chip Analog Input Buffers On-Chip Reference Signal-to-Noise Ratio: 57.8 dB Over Nine Effective Bits Spurious-Free Dynamic Range: –73 dB No Missing Codes Guaranteed 28-Lead SSOP Dual Channel, 20 MHz 10-Bit Resolution CMOS ADC AD9201 FUNCTIONAL BLOCK DIAGRAM AVDD IINA "I" ADC IINB IREFB IREFT QREFB QREFT AVSS CLOCK I REGISTER AD9201 SLEEP SELECT ASYNCHRONOUS MULTIPLEXER VREF QINA DVSS REFERENCE BUFFER THREESTATE OUTPUT BUFFER DATA 10 BITS 1V REFSENSE QINB DVDD "Q" ADC Q REGISTER CHIP SELECT PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9201 is a complete dual channel, 20 MSPS, 10-bit CMOS ADC. The AD9201 is optimized specifically for applications where close matching between two ADCs is required (e.g., I/Q channels in communications applications). The 20 MHz sampling rate and wide input bandwidth will cover both narrowband and spread-spectrum channels. The AD9201 integrates two 10-bit, 20 MSPS ADCs, two input buffer amplifiers, an internal voltage reference and multiplexed digital output buffers. 1. Dual 10-Bit, 20 MSPS ADCs A pair of high performance 20 MSPS ADCs that are optimized for spurious free dynamic performance are provided for encoding of I and Q or diversity channel information. Each ADC incorporates a simultaneous sampling sample-andhold amplifier at its input. The analog inputs are buffered; no external input buffer op amp will be required in most applications. The ADCs are implemented using a multistage pipeline architecture that offers accurate performance and guarantees no missing codes. The outputs of the ADCs are ported to a multiplexed digital output buffer. 3. On-Chip Voltage Reference The AD9201 includes an on-chip compensated bandgap voltage reference pin programmable for 1 V or 2 V. The AD9201 is manufactured on an advanced low cost CMOS process, operates from a single supply from 2.7 V to 5.5 V, and consumes 215 mW of power (on 3 V supply). The AD9201 input structure accepts either single-ended or differential signals, providing excellent dynamic performance up to and beyond its 10 MHz Nyquist input frequencies. 2. Low Power Complete CMOS Dual ADC function consumes a low 215 mW on a single supply (on 3 V supply). The AD9201 operates on supply voltages from 2.7 V to 5.5 V. 4. On-chip analog input buffers eliminate the need for external op amps in most applications. 5. Single 10-Bit Digital Output Bus The AD9201 ADC outputs are interleaved onto a single output bus saving board space and digital pin count. 6. Small Package The AD9201 offers the complete integrated function in a compact 28-lead SSOP package. 7. Product Family The AD9201 dual ADC is pin compatible with a dual 8-bit ADC (AD9281) and has a companion dual DAC product, the AD9761 dual DAC. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9201–SPECIFICATIONS Parameter Symbol (AVDD = +3 V, DVDD = +3 V, FSAMPLE = 20 MSPS, VREF = 2 V, INB = 0.5 V, TMIN to TMAX, internal ref, differential input signal, unless otherwise noted) Min RESOLUTION Typ Max 10 CONVERSION RATE FS DC ACCURACY Differential Nonlinearity Integral Nonlinearity Differential Nonlinearity (SE) Integral Nonlinearity (SE) Zero-Scale Error, Offset Error Full-Scale Error, Gain Error Gain Match Offset Match ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Aperture Delay Match Input Bandwidth (–3 dB) Small Signal (–20 dB) Full Power (0 dB) ± 0.4 1.2 ± 0.5 ± 1.5 ± 1.5 ± 3.5 ± 0.5 ±5 DNL INL DNL INL EZS EFS AIN CIN tAP tAJ –0.5 Units Condition Bits 20 MHz ±1 ± 2.5 ± 3.8 ± 5.4 LSB LSB LSB LSB % FS % FS LSB LSB 2 4 2 2 AVDD/2 V pF ns ps ps 240 245 MHz MHz 1 ± 10 2 ± 15 V mV V mV mV mV REFT = 1 V, REFB = 0 V REFT = 1 V, REFB = 0 V BW INTERNAL REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2 V Mode) Output Voltage Tolerance (2 V Mode) Load Regulation (1 V Mode) Load Regulation (2 V Mode) POWER SUPPLY Operating Voltage VREF VREF ± 15 AVDD DRVDD IAVDD IDRVDD PD Supply Current Power Consumption Power-Down Power Supply Rejection 2.7 2.7 PSR 3 3 71.6 0.1 215 15.5 0.8 ± 28 5.5 5.5 245 1.3 V V mA mA mW mW % FS REFSENSE = VREF REFSENSE = GND 1 mA Load Current 1 mA Load Current AVDD – DVDD ≤ 2.3 V AVDD = 3 V AVDD = DVDD = 3 V STBY = AVDD, Clock = AVSS 1 DYNAMIC PERFORMANCE Signal-to-Noise and Distortion f = 3.58 MHz f = 10 MHz Signal-to-Noise f = 3.58 MHz f = 10 MHz Total Harmonic Distortion f = 3.58 MHz f = 10 MHz Spurious Free Dynamic Range f = 3.58 MHz f = 10 MHz Two-Tone Intermodulation Distortion2 Differential Phase Differential Gain Crosstalk Rejection SINAD 55.6 57.3 55.8 dB dB 55.9 57.8 56.2 dB dB SNR THD –69 –66.3 –63.3 dB dB SFDR –66 IMD DP DG –73 –70.5 –62 0.1 0.05 68 –2– dB dB dB Degree % dB f = 44.49 MHz and 45.52 MHz NTSC 40 IRE Mod Ramp FS = 14.3 MHz REV. D AD9201 Parameter Symbol Min Typ Max Units Condition 3 DYNAMIC PERFORMANCE (SE) Signal-to-Noise and Distortion f = 3.58 MHz Signal-to-Noise f = 3.58 MHz Total Harmonic Distortion f = 3.58 MHz Spurious Free Dynamic Range f = 3.58 MHz SINAD 52.3 dB 55.5 dB –55 dB –58 dB SNR THD SFDR DIGITAL INPUTS High Input Voltage Low Input Voltage DC Leakage Current Input Capacitance VIH VIL IIN CIN LOGIC OUTPUT (with DVDD = 3 V) High Level Output Voltage (IOH = 50 µA) Low Level Output Voltage (IOL = 1.5 mA) LOGIC OUTPUT (with DVDD = 5 V) High Level Output Voltage (IOH = 50 µA) Low Level Output Voltage (IOL = 1.5 mA) Data Valid Delay MUX Select Delay Data Enable Delay Data High-Z Delay CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency 2.4 V V µA pF 0.3 ±6 2 VOH 2.88 V VOL 0.095 V VOH 4.5 V VOL tOD tMD tED 0.4 11 7 13 V ns ns ns tDHZ 13 ns 3.0 ns ns Cycles tCH tCL 22.5 22.5 CL = 20 pF. Output Level to 90% of Final Value NOTES 1 AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V. 2 IMD referred to larger of two input signals. 3 SE is single ended input, REFT = 1.5 V, REFB = –0.5 V. Specifications subject to change without notice. tOD CLOCK INPUT ADC SAMPLE #1 SELECT INPUT ADC SAMPLE #2 ADC SAMPLE #3 SAMPLE #1-3 Q CHANNEL OUTPUT I CHANNEL OUTPUT ENABLED SAMPLE #1 Q CHANNEL OUTPUT SAMPLE #1-2 Q CHANNEL OUTPUT SAMPLE #1-1 I CHANNEL OUTPUT Figure 1. ADC Timing REV. D ADC SAMPLE #5 t MD Q CHANNEL OUTPUT ENABLED SAMPLE #1-1 Q CHANNEL OUTPUT DATA OUTPUT ADC SAMPLE #4 –3– SAMPLE #1 I CHANNEL OUTPUT SAMPLE #2 Q CHANNEL OUTPUT AD9201 ABSOLUTE MAXIMUM RATINGS* With Respect to Parameter AVDD AVSS DVDD DVSS AVSS DVSS AVDD DVDD CLK AVSS Digital Outputs DVSS AINA, AINB AVSS VREF AVSS REFSENSE AVSS REFT, REFB AVSS Junction Temperature Storage Temperature Lead Temperature 10 sec PIN FUNCTION DESCRIPTIONS Pin Min Max Units –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –1.0 –0.3 –0.3 –0.3 +6.5 +6.5 +0.3 +6.5 AVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 V V V V V V V V V V °C °C +300 °C –65 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ORDERING GUIDE Model AD9201ARS AD9201-EVAL Temperature Range Package Description Package Options* –40°C to +85°C 28-Lead SSOP RS-28 Evaluation Board *RS = Shrink Small Outline. PIN CONFIGURATION DVSS CHIP-SELECT DVDD INA-Q (LSB) D0 INB-Q D2 AD9201 D3 TOP VIEW (Not to Scale) Description 1 2 3 4 5 6 7 8 9 10 11 12 DVSS DVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Digital Ground Digital Supply Bit 0 (LSB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 (MSB) 13 14 15 SELECT CLOCK SLEEP Hi I Channel Out, Lo Q Channel Out Clock Hi Power Down, Lo Normal Operation 16 17 18 19 20 21 22 23 24 25 26 27 28 INA-I INB-I REFT-I REFB-I AVSS REFSENSE VREF AVDD REFB-Q REFT-Q INB-Q INA-Q CHIP-SELECT I Channel, A Input I Channel, B Input Top Reference Decoupling, I Channel Bottom Reference Decoupling, I Channel Analog Ground Reference Select Internal Reference Output Analog Supply Bottom Reference Decoupling, Q Channel Top Reference Decoupling, Q Channel Q Channel, B Input Q Channel, A Input Hi-High Impedance, Lo-Normal Operation REFB-Q DEFINITIONS OF SPECIFICATIONS AVDD INTEGRAL NONLINEARITY (INL) VREF Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB before the first code transition. “Full scale” is defined as a level 1 1/2 LSBs beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line. D5 REFSENSE D6 AVSS D7 REFB-I D8 REFT-I (MSB) D9 INB-I SELECT INA-I CLOCK Name REFT-Q D1 D4 No. DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) SLEEP An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. D AD9201 AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS AVSS AVSS DRVSS AVSS AVSS a. D0–D9, OTR AVSS b. Three-State, Standby c. CLK AVDD AVDD AVDD AVDD AVDD IN REFBS AVSS AVDD AVSS REFBF AVSS AVSS AVSS AVSS d. INA, INB e. Reference f. REFSENSE g. VREF Figure 2. Equivalent Circuits OFFSET ERROR The first transition should occur at a level 1 LSB above “zero.” Offset is defined as the deviation of the actual first code transition from that point. scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. GAIN MATCH The change in gain error between I and Q channels. OFFSET MATCH The change in offset error between I and Q channels. PIPELINE DELAY (LATENCY) EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N = (SINAD – 1.76)/6.02 The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every rising clock edge. MUX SELECT DELAY It is possible to get a measure of performance expressed as N, the effective number of bits. The delay between the change in SELECT pin data level and valid data on output pins. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. POWER SUPPLY REJECTION TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. APERTURE DELAY SPURIOUS FREE DYNAMIC RANGE (SFDR) SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO The difference in dB between the rms amplitude of the input signal and the peak spurious signal. GAIN ERROR The first code transition should occur for an analog value 1 LSB above nominal negative full scale. The last transition should occur for an analog value 1 LSB below the nominal positive full REV. D Aperture delay is a measure of the Sample-and-Hold Amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. –5– AD9201–Typical Characteristic Curves 1.5 65 1.0 60 –0.5dB 0.5 55 –6dB SNR – dB INL (AVDD = +3 V, DVDD = +3 V, FS = 20 MHz (50% duty cycle), 2 V input span from –0.5 V to +1.5 V, 2 V internal reference unless otherwise noted) 0 50 –0.5 45 –1.0 40 –1.5 0 128 256 384 512 640 CODE OFFSET 768 896 –20dB 35 1.00E+05 1024 1.00E+06 1.00E+07 INPUT FREQUENCY – Hz 1.00E+08 Figure 6. SNR vs. Input Frequency Figure 3. Typical INL (1 V Internal Reference) 1 65 60 –0.5dB 0.5 SINAD – dB DNL 55 0 –6dB 50 45 –0.5 –20dB 40 –1.0 0 128 256 384 512 640 CODE OFFSET 768 896 35 1.00E+05 1024 1.00E+08 Figure 7. SINAD vs. Input Frequency 1.00 –30 0.80 –35 0.60 –40 0.40 –45 0.20 –50 THD – dB IB – nA Figure 4. Typical DNL (1 V Internal Reference) 1.00E+06 1.00E+07 INPUT FREQUENCY – Hz 0.00 –0.20 –20dB –55 –6dB –60 –0.40 –65 –0.60 –70 –0.80 –75 –0.5dB –1.00 –1.0 –0.5 0 0.5 1.0 INPUT VOLTAGE – V 1.5 –80 1.00E+05 2.0 1.00E+06 1.00E+07 INPUT FREQUENCY – Hz 1.00E+08 Figure 8. THD vs. Input Frequency Figure 5. Input Bias Current vs. Input Voltage –6– REV. D AD9201 –75 1.20E+07 –70 1.00E+07 10000000 HITS THD – dB 8.00E+06 –65 6.00E+06 –60 4.00E+06 –55 2.00E+06 255100 –50 1.00E+06 1.00E+07 CLOCK FREQUENCY – Hz 0.00E+00 1.00E+08 Figure 9. THD vs. Clock Frequency (fIN = 1 MHz) N–1 150400 N CODE N+1 Figure 12. Grounded Input Histogram 1.012 0 –3 1.011 –6 –9 AMPLITUDE – dB VREF – V 1.010 1.009 1.008 –12 –15 –18 –21 –24 1.007 –27 1.006 –40 0 –20 20 40 60 TEMPERATURE – 8C 80 –30 1.00E+06 100 Figure 10. Voltage Reference Error vs. Temperature 1.00E+09 Figure 13. Full Power Bandwidth 220 60 –0.5dB 215 55 210 –6.0dB 205 SNR – dB POWER CONSUMPTION – mW 1.00E+07 1.00E+08 INPUT FREQUENCY – Hz 200 195 50 45 190 40 185 180 0 2 4 8 6 10 12 14 CLOCK FREQUENCY – MHz 16 18 35 1.00E+05 20 Figure 11. Power Consumption vs. Clock Frequency REV. D –20.0dB 1.00E+07 1.00E+06 INPUT FREQUENCY – Hz 1.00E+08 Figure 14. SNR vs. Input Frequency (Single Ended) –7– AD9201 The AD9201 also includes an on-chip bandgap reference and reference buffer. The reference buffer shifts the ground-referred reference to levels more suitable for use by the internal circuits of the converter. Both converters share the same reference and reference buffer. This scheme provides for the best possible gain match between the converters while simultaneously minimizing the channel-to-channel crosstalk. (See Figure 16.) 10 0 FUND –10 –20 I CHANNEL –30 –40 –50 –60 –70 2ND 3RD –80 5TH 4TH 9TH 6TH Each A/D converter has its own output latch, which updates on the rising edge of the input clock. A logic multiplexer, controlled through the SELECT pin, determines which channel is passed to the digital output pins. The output drivers have their own supply (DVDD), allowing the part to be interfaced to a variety of logic families. The outputs can be placed in a high impedance state using the CHIP SELECT pin. 7TH 8TH –90 –100 –110 –120 0.0E+0 1.0E+6 2.0E+6 3.0E+6 4.0E+6 5.0E+6 6.0E+6 7.0E+6 8.0E+6 9.0E+6 10.0E+6 10 0 The AD9201 has great flexibility in its supply voltage. The analog and digital supplies may be operated from 2.7 V to 5.5 V, independently of one another. FUND –10 Q CHANNEL –20 –30 ANALOG INPUT –40 Figure 16 shows an equivalent circuit structure for the analog input of one of the A/D converters. PMOS source-followers buffer the analog input pins from the charge kickback problems normally associated with switched capacitor ADC input structures. This produces a very high input impedance on the part, allowing it to be effectively driven from high impedance sources. This means that the AD9201 could even be driven directly by a passive antialias filter. –50 –60 –70 –80 2ND 4TH 3RD 5TH 6TH 7TH 8TH 9TH –90 –100 –110 –120 0.0E+0 1.0E+6 2.0E+6 3.0E+6 4.0E+6 5.0E+6 6.0E+6 7.0E+6 8.0E+6 9.0E+6 10.0E+6 Figure 15. Simultaneous Operation of I and Q Channels (Differential Input) IINA BUFFER THEORY OF OPERATION OUTPUT WORD ADC CORE SHA The AD9201 integrates two A/D converters, two analog input buffers, an internal reference and reference buffer, and an output multiplexer. For clarity, this data sheet refers to the two converters as “I” and “Q.” The two A/D converters simultaneously sample their respective inputs on the rising edge of the input clock. The two converters distribute the conversion operation over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the result from stage to stage. As a consequence of the distributed conversion, each converter requires a small fraction of the 1023 comparators used in a traditional flash-type 10-bit ADC. A sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the following stages continue to process previous samples. This results in a “pipeline processing” latency of three clock periods between when an input sample is taken and when the corresponding ADC output is updated into the output registers. +FS LIMIT IINB –FS LIMIT BUFFER +FS LIMIT = VREF +VREF/2 –FS LIMIT = VREF –VREF/2 VREF Figure 16. Equivalent Circuit for AD9201 Analog Inputs The source followers inside the buffers also provide a level-shift function of approximately 1 V, allowing the AD9201 to accept inputs at or below ground. One consequence of this structure is that distortion will result if the analog input approaches the positive supply. For optimum high frequency distortion performance, the analog input signal should be centered according to Figure 29. The capacitance load of the analog input Pin is 4 pF to the analog supplies (AVSS, AVDD). The AD9201 integrates input buffer amplifiers to drive the analog inputs of the converters. In most applications, these input amplifiers eliminate the need for external op amps for the input signals. The input structure is fully differential, but the SHA common-mode response has been designed to allow the converter to readily accommodate either single-ended or differential input signals. This differential structure makes the part capable of accommodating a wide range of input signals. Full-scale setpoints may be calculated according to the following algorithm (VREF may be internally or externally generated): –FS = (VREF – VREF/2) +FS = (VREF + VREF/2) VSPAN = VREF –8– REV. D AD9201 The AD9201 can accommodate a variety of input spans between 1 V and 2 V. For spans of less than 1 V, expect a proportionate degradation in SNR . Use of a 2 V span will provide the best noise performance. 1 V spans will provide lower distortion when using a 3 V analog supply. Users wishing to run with larger full-scales are encouraged to use a 5 V analog supply (AVDD). Single-Ended Inputs: For single-ended input signals, the signal is applied to one input pin and the other input pin is tied to a midscale voltage. This midscale voltage defines the center of the full-scale span for the input signal. EXAMPLE: For a single-ended input range from 0 V to 1 V applied to IINA, we would configure the converter for a 1 V reference (See Figure 17) and apply 0.5 V to IINB. 1V 0V 0.1mF INPUT MIDSCALE VOLTAGE = 0.5V IINA I OR QREFT IINB I OR QREFB 0.1mF 10mF AC Coupled Inputs If the signal of interest has no dc component, ac coupling can be easily used to define an optimum bias point. Figure 18 illustrates one recommended configuration. The voltage chosen for the dc bias point (in this case the 1 V reference) is applied to both IINA and IINB pins through 1 kΩ resistors (R1 and R2). IINA is coupled to the input signal through Capacitor C1, while IINB is decoupled to ground through Capacitor C2 and C3. Transformer Coupled Inputs Another option for input ac coupling is to use a transformer. This not only provides dc rejection, but also allows truly differential drive of the AD9201’s analog inputs, which will provide the optimal distortion performance. Figure 19 shows a recommended transformer input drive configuration. Resistors R1 and R2 define the termination impedance of the transformer coupling. The center tap of the transformer secondary is tied to the common-mode reference, establishing the dc bias point for the analog inputs. 10mF 0.1mF 0.1mF AD9201 5kV 5kV VREF REFSENSE QINA IINB QINB R2 AD9201 COMMON MODE VOLTAGE 0.1mF I OR QREFT 0.1mF 10mF 0.1mF IINA R1 10mF VREF I OR QREFB 0.1mF 10mF 0.1mF REFSENSE Figure 17. Example Configuration for 0 V–1 V SingleEnded Input Signal Note that since the inputs are high impedance, this reference level can easily be generated with an external resistive divider with large resistance values (to minimize power dissipation). A decoupling capacitor is recommended on this input to minimize the high frequency noise-coupling onto this pin. Decoupling should occur close to the ADC. Differential Inputs Use of differential input signals can provide greater flexibility in input ranges and bias points, as well as offering improvements in distortion performance, particularly for high frequency input signals. Users with differential input signals will probably want to take advantage of the differential input structure. Figure 19. Example Configuration for Transformer Coupled Inputs Crosstalk: The internal layout of the AD9201, as well as its pinout, was configured to minimize the crosstalk between the two input signals. Users wishing to minimize high frequency crosstalk should take care to provide the best possible decoupling for input pins (see Figure 20). R and C values will make a pole dependant on antialiasing requirements. Decoupling is also required on reference pins and power supplies (see Figure 21). IINA QINA AD9201 IINB 1.5V QINB 0.1mF ANALOG INPUT C1 C2 1.0mF REFT 0.5V IINA R1 1kV C3 0.1mF 0.1mF Figure 20. Input Loading 10mF REFB IINB 0.1mF V ANALOG V DIGITAL AD9201 AVDD VREF 10mF REFSENSE 0.1mF DVDD AD9201 0.1mF 10mF 0.1mF 10mF I OR QREFT Figure 18. Example Configuration for 0.5 V–1.5 V ac Coupled Single-Ended Inputs 0.1mF I OR QREFB 0.1mF Figure 21. Reference and Power Supply Decoupling REV. D –9– AD9201 REFERENCE AND REFERENCE BUFFER The reference and buffer circuitry on the AD9201 is configured for maximum convenience and flexibility. An illustration of the equivalent reference circuit is show in Figure 26. The user can select from five different reference modes through appropriate pin-strapping (see Table I below). These pin strapping options cause the internal circuitry to reconfigure itself for the appropriate operating mode. Externally Set Voltage Mode (Figure 24)—this mode uses the on-chip reference, but scales the exact reference level though the use of an external resistor divider network. VREF is wired to the top of the network, with the REFSENSE wired to the tap point in the resistor divider. The reference level (and input full scale) will be equal to 1 V × (R1 + R2)/R1. This method can be used for voltage levels from 0.7 V to 2.5 V. 1mF Table I. Table of Modes 0.1mF Mode Input Span REFSENSE Pin Figure 1V 2V Programmable External 1V 2V 1 + (R1/R2) = External Ref VREF AGND See Figure AVDD 1V + VREF +– – 22 23 24 25 R2 R1 1V 0V 0V IINA QINA IINB QINB 0.1mF AD9201 External Reference Mode (Figure 25)—in this mode, the onchip reference is disabled, and an external reference is applied to the VREF pin. This mode is achieved by tying the REFSENSE pin to AVDD. 1V AD9201 1V 0V 10mF 0.1mF I OR QREFT 0.1mF 0.1mF 5kV 1V EXT REFERENCE 10mF 2V 2V 0V 0V 5kV 0.1mF 5kV AD9201 VREF AD9201 0.1mF I OR QREFT 0.1mF AVDD 2 V Mode (Figure 23)—provides a 2 V reference and 2 V input full scale. Recommended for noise sensitive applications on 5 V supplies. The part is placed in 2 V reference mode by grounding (shorting to AVSS) the REFSENSE pin. QINB QINB 0.1mF 10mF I OR QREFB Figure 22. 0 V to 1 V Input IINB IINB VREF 10mF 0.1mF QINA QINA 0.1mF I OR QREFB IINA IINA 5kV VREF REFSENSE 10mF 0.1mF 0V 1V 10mF I OR QREFB Figure 24. Programmable Reference 0.1mF 5kV 10mF I OR QREFT VREF = 1 + R2 R1 5kV 10mF 0.1mF AVSS 1 V Mode (Figure 22)—provides a 1 V reference and 1 V input full scale. Recommended for applications wishing to optimize high frequency performance, or any circuit on a supply voltage of less than 4 V. The part is placed in this mode by shorting the REFSENSE pin to the VREF pin. 1V REFSENSE REFSENSE 0.1mF Figure 25. External Reference Reference Buffer—The reference buffer structure takes the voltage on the VREF pin and level-shifts and buffers it for use by various subblocks within the two A/D converters. The two converters share the same reference buffer amplifier to maintain the best possible gain match between the two converters. In the interests of minimizing high frequency crosstalk, the buffered references for the two converters are separately decoupled on the IREFB, IREFT, QREFB and QREFT pins, as illustrated in Figure 26. 0.1mF I OR QREFT 10mF 0.1mF 0.1mF 10mF I OR QREFB REFSENSE 0.1mF Figure 23. 0 V to 2 V Input –10– REV. D AD9201 VREF ADC CORE 0.1mF 10mF 22V QREFT IREFT 0.1mF 0.1mF 0.1mF 6 50V 1V IREFB 0.1mF QREFB 0.1mF 0.33mF 24V 16 22V 2 10pF 1kV 0.1mF 0.01mF VREF 10mF 17 ADC 3 10mF 10pF 1kV AD8051 1kV 10kV REFSENSE Figure 27. 10kV INTERNAL CONTROL LOGIC 10 FUND 0 AVSS AD9201 –10 –20 Figure 26. Reference Buffer Equivalent Circuit and External Decoupling Recommendation –30 –40 For best results in both noise suppression and robustness against crosstalk, the 4 capacitor buffer decoupling arrangement shown in Figure 26 is recommended. This decoupling should feature chip capacitors located close to the converter IC. The capacitors are connected to either IREFT/IREFB or QREFT/ QREFB. A connection to both sides is not required. –50 2ND 3RD –60 –70 4TH 7TH 6TH 8TH –80 5TH –90 –100 –110 DRIVING THE AD9201 –120 0.0E+0 Figure 27 illustrates the use of an AD8051 to drive the AD9201. Even though the AD8051 is specified with 3 V and 5 V power, the best results are obtained at ± 5 V power. The ADC input span is 2 V. REV. D 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 1.0E+6 3.0E+6 5.0E+6 7.0E+6 9.0E+6 Figure 28. AD8051/AD9201 Performance –11– AD9201 COMMON-MODE PERFORMANCE Inspection of the curves will yield the following conclusions: Attention to the common-mode point of the analog input voltage can improve the performance of the AD9201. Figure 29 illustrates THD as a function of common-mode voltage (center point of the analog input span) and power supply. 1. An AD9201 running with AVDD = 5 V is the easiest to drive. 2. Differential inputs are the most insensitive to common-mode voltage. 3. An AD9201 powered by AVDD = 3 V and a single ended input, should have a 1 V span with a common-mode voltage of 0.75 V. –10 –30 2V SPAN –35 –20 2V SPAN –40 –30 –50 THD – dB THD – dB –45 –55 –60 –40 –50 1V SPAN 1V SPAN –65 –60 –70 –70 –75 –80 –0.5 0 0.5 1.0 COMMON-MODE LEVEL – V –80 –0.5 1.5 a. Differential Input, 3 V Supplies 0 1.5 0.5 1.0 COMMON-MODE LEVEL – V c. Single-Ended Input, 3 V Supplies –30 –10 –35 –20 –40 2V SPAN –30 –50 THD – dB THD – dB –45 2V SPAN –55 –60 –65 –70 –40 –50 –60 1V SPAN –80 –0.5 1V SPAN –70 –75 0 1.5 0.5 1.0 COMMON-MODE LEVEL – V 2.0 –80 –0.5 2.5 b. Differential Input, 5 V Supplies 0 1.5 0.5 1.0 COMMON-MODE LEVEL – V 2.0 2.5 d. Single-Ended Input, 5 V Supplies Figure 29. THD vs. CML Input Span and Power Supply (Analog Input = 1 MHz) –12– REV. D AD9201 DIGITAL INPUTS AND OUTPUTS SELECT Each of the AD9201 digital control inputs, CHIP SELECT, CLOCK, SELECT and SLEEP are referenced to AVDD and AVSS. Switching thresholds will be AVDD/2. When the select pin is held LOW, the output word will present the “Q” level. When the select pin is held HIGH, the “I” level will be presented to the output word (see Figure 1). The format of the digital output is straight binary. A low power mode feature is provided such that for STBY = HIGH and the clock disabled, the static power of the AD9201 will drop below 22 mW. The AD9201’s select and clock pins may be driven by a common signal source. The data will change in 5 ns to 11 ns after the edges of the input pulse. The user must make sure the interface latches have sufficient hold time for the AD9201’s delays (see Figure 30). CLOCK INPUT The AD9201 clock input is internally buffered with an inverter powered from the AVDD pin. This feature allows the AD9201 to accommodate either +5 V or +3.3 V CMOS logic input signal swings with the input threshold for the CLK pin nominally at AVDD/2. The pipelined architecture of the AD9201 operates on both rising and falling edges of the input clock. To minimize duty cycle variations the logic family recommended to drive the clock input is high speed or advanced CMOS (HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 20 MSPS operation. Running the part at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, some slight performance improvements might be realized by clocking the AD9201 at slower clock rates. The power dissipated by the output buffers is largely proportional to the clock frequency; running at reduced clock rates provides a reduction in power consumption. DIGITAL OUTPUTS Each of the on-chip buffers for the AD9201 output bits (D0–D9) is powered from the DVDD supply pin, separate from AVDD. The output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy generated. In all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pF level. For DVDD = 5 V, the AD9201 output signal swing is compatible with both high speed CMOS and TTL logic families. For TTL, the AD9201 on-chip, output drivers were designed to support several of the high speed TTL families (F, AS, S). For applications where the clock rate is below 20 MSPS, other TTL families may be appropriate. For interfacing with lower voltage CMOS logic, the AD9201 sustains 20 MSPS operation with DVDD = 3 V. In all cases, check your logic family data sheets for compatibility with the AD9201’s Specification table. CLOCK CLOCK SOURCE I PROCESSING I LATCH SELECT CLK DATA DATA OUT DATA Q PROCESSING Q LATCH CLOCK Figure 30. Typical De-Mux Connection APPLICATIONS USING THE AD9201 FOR QAM DEMODULATION QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in both FDMA as well as spread spectrum (i.e., CDMA) based systems. A QAM signal is a carrier frequency which is both modulated in amplitude (i.e., AM modulation) and in phase (i.e., PM modulation). At the transmitter, it can be generated by independently modulating two carriers of identical frequency but with a 90° phase difference. This results in an inphase (I) carrier component and a quadrature (Q) carrier component at a 90° phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier or IF frequency. Figure 31 shows a typical analog implementation of a QAM modulator using a dual 10-bit DAC with 2× interpolation, the AD9761. A QAM signal can also be synthesized in the digital domain thus requiring a single DAC to reconstruct the QAM signal. The AD9853 is an example of a complete (i.e., DAC included) digital QAM modulator. IOUT DSP OR ASIC A 2 ns reduction in output delays can be achieved by limiting the logic load to 5 pF per output line. 10 AD9761 CARRIER FREQUENCY 0 90 TO MIXER QOUT THREE-STATE OUTPUTS NYQUIST FILTERS The digital outputs of the AD9201 can be placed in a high impedance state by setting the CHIP SELECT pin to HIGH. This feature is provided to facilitate in-circuit testing or evaluation. REV. D QUADRATURE MODULATOR Figure 31. Typical Analog QAM Modulator Architecture –13– AD9201 At the receiver, the demodulation of a QAM signal back into its separate I and Q components is essentially the modulation process explain above but in the reverse order. A common and traditional implementation of a QAM demodulator is shown in Figure 32. In this example, the demodulation is performed in the analog domain using a dual, matched ADC and a quadrature demodulator to recover and digitize the I and Q baseband signals. The quadrature demodulator is typically a single IC containing two mixers and the appropriate circuitry to generate the necessary 90° phase shift between the I and Q mixers’ local oscillators. Before being digitized by the ADCs, the mixed down baseband I and Q signals are filtered using matched analog filters. These filters, often referred to as Nyquist or PulseShaping filters, remove images-from the mixing process and any out-of-band. The characteristics of the matching Nyquist filters are well defined to provide optimum signal-to-noise (SNR) performance while minimizing intersymbol interference. The ADC’s are typically simultaneously sampling their respective inputs at the QAM symbol rate or, most often, at a multiple of it if a digital filter follows the ADC. Oversampling and the use of digital filtering eases the implementation and complexity of the analog filter. It also allows for enhanced digital processing for both carrier and symbol recovery and tuning purposes. The use of a dual ADC such as the AD9201 ensures excellent gain, offset, and phase matching between the I and Q channels. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD9201 in a solid ground plane. The power and ground return currents must be carefully managed. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. Transients between AVSS and DVSS will seriously degrade performance of the ADC. If the user cannot tie analog ground and digital ground together at the ADC, he should consider the configuration in Figure 33. AVDD A I ADC DSP OR ASIC D DIGITAL LOGIC ICs CSTRAY ANALOG CIRCUITS DIGITAL CIRCUITS B A A CARRIER FREQUENCY LO 90°C NYQUIST FILTERS IA FROM PREVIOUS STAGE QUADRATURE DEMODULATOR Figure 32. Typical Analog QAM Demodulator GROUNDING AND LAYOUT RULES As is the case for any high performance device, proper grounding and layout techniques are essential in achieving optimal performance. The analog and digital grounds on the AD9201 have been separated to optimize the management of return currents in a system. Grounds should be connected near the ADC. It is recommended that a printed circuit board (PCB) of at least four layers, employing a ground plane and power planes, be used with the AD9201. The use of ground and power planes offers distinct advantages: CSTRAY ID AVSS Q ADC DUAL MATCHED ADC A ADC IC VIN A = ANALOG D = DIGITAL LOGIC SUPPLY DVDD A GND DVSS DV A D Figure 33. Ground and Power Consideration Another input and ground technique is shown in Figure 34. A separate ground plane has been split for RF or hard to manage signals. These signals can be routed to the ADC differentially or single ended (i.e., both can either be connected to the driver or RF ground). The ADC will perform well with several hundred mV of noise or signals between the RF and ADC analog ground. RF GROUND ANALOG GROUND DIGITAL GROUND LOGIC ADC 1. The minimization of the loop area encompassed by a signal and its return path. AIN DATA BIN 2. The minimization of the impedance associated with ground and power paths. - 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. Figure 34. RF Ground Scheme –14– REV. D AD9201 EVALUATION BOARD The AD9201 evaluation board is shipped “ready to run.” Power and signal generators should be connected as shown in Figure 35. Then the user can observe the performance of the Q channel. If the user wants to observe the I channel, then he should install a jumper at JP22 Pins 1 and 2. If the user wants to toggle between I and Q channels, then a CMOS level pulse train should be applied to the “strobe” jack after appropriate jumper connections. +3V AGND SYNTHESIZER 20MHz 2Vp-p SYNTHESIZER 1MHz 1Vp-p ANTIALIAS FILTER +3V +5V AVDD DGND1 DVDD DGND2 DRVDD CLOCK AD9201 P1 Q IN Figure 35. Evaluation Board Connections REV. D –15– DSP EQUIPMENT AD9201 – 9201EB – +C5 C54 C4 R50 R51 C14 C50 C51 C20 C22 REV C29 C55 C35 +C36 C24 R52 R53 C52 C14 C17 C23 C27 C53 (NOT TO SCALE) Figure 36. Evaluation Board Solder-Side Silkscreen (NOT TO SCALE) Figure 37. Evaluation Board Component-Side Layout –16– REV. D AD9201 (NOT TO SCALE) Figure 38. Evaluation Board Ground Plane Layout (NOT TO SCALE) Figure 39. Evaluation Board Solder-Side Layout REV. D –17– AD9201 J1 AGND CLOCK DGND1 DGND2 DBVDD BJ6 BJ5 J6 C42 AVDD + L2 R38 L3 C38 R39 C41 JP22 R37 JP13 C33 R33 R31 T1 R1 JP3 JP21 R4 R11 R32 JP15 JP17 P1 R2 RN1 V1 C15 + JP20 R40 R35 C13 V2 TP5 + JP6 + C11 R6 C8 R7 R9 R8 V4 R14 R12 R10 C10 L5 C30 C19 C9 R24 JP4 C21 D1 Q_IN R17 C12 R30 C32 V6 R18 R16 DGND TP6 AGND C6 RN2 JP5 C24 + R34 C2 + C25 JP14 R23 JP19 TP7 4 JP12JP11 C31 + + C46 C47 C7 TP1 C34 L4 C48 TP4 4 TP2 C37 C44 V8 C1 JP2 JP1 JP7 C3 J3 JP9 JP10 T2 TP3 C45 JP16 + C43 R36 R13 J4 DVDD BJ3 BJ4 C40 BJ1 BJ2 J5 AVDD DBVDD AGND STROBE C49 + I_IN V3 (NOT TO SCALE) Figure 40. Evaluation Board Component-Side Silkscreen (NOT TO SCALE) Figure 41. Evaluation Board Power Plane Layout –18– REV. D REV. D R2 R-S 50V CH1IN 1 –19– Figure 42. Evaluation Board J4 BNC AVDD C32 0.1mF R35 R-S 1V R24 R-S 22V R10 R-S 10V R40 R-S 100V JUMPER TP5 CON1 T2 TRANSFORMER CT 4 3 2 6 1 P S JP12 JP11 C37 10_6V3 NOT TO SCALE JP10 R34 R-S 50V U6 AD822 + 8 C21 CAP_NP R17 15kV AVDD C11 10_6V3 C12 0.1kV U3 R7 15kV AD822 + 8 C8 CAP_NP C3 10_6V3 JUMPER C34 0.1mF C31 10_6V3 R16 5kV HDR3 3 CHOIN 2 1 R30 1.5kV R23 POT_10kV ADJ_REF R12 1.5kV R9 POT_10kV ADJ_REF TP3 CON1 DIODE_ZENER D1 R8 5.49kV AVDD MIDSCALE_I JP2 2 INB-1 C36 10_6V3 DCINO R_VREF R51 10V C15 CAP_P R50 10V AVDD STROBE C47 CAP_NP R53 10V C55 1000pF TP6 CON1 3 HDR3 1 JP6 2 R52 10V C25 CAP_P C27 0.1mF AVDD C45 CAP_NP 18 17 16 15 C53 10pF C52 10pF 28 27 26 C26 CAP_NP 25 24 23 22 21 20 C16 CAP_NP 19 C51 10pF C50 10pF R11 1kV 3 JP21 2 1 HDR3 C48 CAP_NP U4 DUTCLK DVSS DVDD AD9201 CHIP-SELECT INA-Q D0 D1 REFT-Q INB-Q D2 D3 D4 REFB-Q AVDD VREF D5 D6 D7 D8 D9 SELECT TESTCHIP REFSENSE AVSS REFB-1 REFT-1 INB-1 INA-1 R13 1kV 3 4 5 6 7 8 9 C29 CAP_NP D0 D1 D2 D3 D4 D5 D6 10 D7 D8 11 D4 12 D9 13 14 3 JP22 2 1 HDR3 DUTCLK AVDD DRVDD DGND DVDD SLEEP L4 DRVDD FERRITE BEAD DRVDD C44 CAP_NP L3 DVDD FERRITE BEAD DVDD 1 JP4 R14 2 R-S TBDV 3 C23 0.1mF R18 R-S TBDV C17 0.1mF C14 0.1mF C54 1000pF HDR3 INA-Q 3 JP14 INB-Q 1 2 4 HDR4 C35 0.1mF C24 10_10V JP9 JUMPER AVDD C20 0.1kV R_VREF 3 4 1 JP13 INA-1 C46 10_10V DPWRIN C43 10_10V DPWRIN C22 0.1kV C5 10_6V3 JUMPER JP5 JP7 JUMPER VREF C4 0.1V CON1 TP2 R_VREF BJ6 1 BANA BJ5 1 BANA BJ4 BANA 1 BJ3 BANA 1 DCIN1 AGND AVDD C19 10_10V R1 JUMPER TP1 JUMPER R-S TBDV C1 0.1mF CON1 R4 R-S 100V JP2 P S 1 C42 CAP_NP GND 3 C41 CAP_NP AVDD L2 FERRITE BEAD AVDD VCC T1 TRANSFORMER CT 4 3 2 6 1 R6 5kV HDR3 JP3 2 R37 R-S 49.9V STROBE C40 10_10V J3 MIDSCALE_IN J1 BNC BJ2 1 BANA J5 BNC BJ1 1 BANA APWRIN 14 D4 J6 BNC R38 R-S 50V ADC_CLK R32 POT_2kV C30 CAP_NP 13 22 23 R33 500V C33 0.1mF R31 500V C49 10_10V T/R 11 2 1 HDR3 U8A 2 3 U8B DRVDD C10 0.1mF 4 U8C 6 74AHC14DW 5 C38 0.1mF AVDD R39 R-S 50V TP7 CON1 74AHC14DW 74AHC14DW 1 HDR3 1 JP20 3 2 BD3 BD4 BD2 9 10 BD1 8 BD0 BCLK0 HDR3 1 JP17 2 3 7 6 3 4 5 GND3 12 GND2 1 JP15 2 3 C13 0.1mF A A A A VCCA 74LVXC4245 GND1 OE NC1 VCCB D4 D3 D2 D1 A A B D0 A A HDR3 1 JP19 2 3 DRVDD C6 0.1mF DRVDD BD9 BD8 7 BD7 6 BD6 BD5 5 4 3 GND2 11 GND3 12 B B U2 DVDD DRVDD AVDD C9 0.1mF 16 D3 24 17 D2 20 21 20 19 C7 0.1mF A A A A 9 8 A 10 1 VCCA T/R 2 74LVXC4245 13 GND1 18 L5 FERRITE_BEAD DVDD D[0...9] DUTDATA [0...9] B VCCB 23 NC1 22 OE 24 14 D1 D0 DRVDD C2 0.1mF CLK0 DVDD D9 18 B 17 B D8 B B A B 19 20 D6 A A B B U1 D7 21 D5 15 16 U8F 12 U8E 10 U8D 8 P1 DUTCLK TP4 CON1 1 JP16 R36 CLK0 2 3 R-S TBDV HDR3 74AHC14DW 9 74AHC14DW 11 74AHC14DW 13 14 1 RN1B 13 2 RN1C 13 31 30 11 4 2 29 9 28 12 3 3 RN1D 7 6 4 11 26 RN1E 24 5 22 5 CLK 10 8 RN1F OUT 1 10 9 6 12 RN2A 33 20 25 1 14 18 RN2B 23 27 2 13 16 RN2C 21 32 14 3 12 34 RN2D 19 33 4 11 40 RN2E 17 39 5 36 10 38 RN2F 15 37 6 9 CON40 RN1A RESISTOR 7PACK AD9201 AD9201 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 15 1 14 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 28 C3116d–0–8/99 0.407 (10.34) 0.397 (10.08) 0.07 (1.79) 0.066 (1.67) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 0.015 (0.38) 0.010 (0.25) SEATING 0.009 (0.229) PLANE 0.005 (0.127) 8° 0° 0.03 (0.762) 0.022 (0.558) PRINTED IN U.S.A. 0.078 (1.98) PIN 1 0.068 (1.73) –20– REV. D