ADS5220 ADS 522 0 SBAS261A – APRIL 2003 – REVISED MARCH 2004 12-Bit, 40MSPS Sampling, +3.3V ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● The ADS5220 is a pipeline, CMOS Analog-to-Digital Converter (ADC) that operates from a single +3.3V power supply. This converter can be operated with a single-ended input or differential input. The ADS5220 includes a 12-bit quantizer, high bandwidth track-and-hold, and an internal reference. It also allows the user to disable the internal reference and utilize external references which provide excellent gain and offset matching when used in multi-channel applications or in applications where full-scale range adjustment is required. ● ● ● ● HIGH SNR: 70dB HIGH SFDR: 88dBFS LOW POWER: 195mW INTERNAL/EXTERNAL REFERENCE OPTION SINGLE-ENDED OR FULLY DIFFERENTIAL ANALOG INPUT PROGRAMMABLE INPUT RANGE LOW DNL: 0.3LSB SINGLE +3.3V SUPPLY OPERATION TQFP-48 PACKAGE APPLICATIONS ● WIRELESS LOCAL LOOP ● COMMUNICATIONS ● MEDICAL IMAGING ● PORTABLE INSTRUMENTATION The ADS5220 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for medical imaging, communications, video, and test instrumentation. The ADS5220 offers power dissipation of 195mW and also provides two power-down modes. The ADS5220 is specified at a maximum sampling frequency of 40MSPS and a differential input range of 1V to 2V. The ADS5220 is available in a TQFP-48 package. CLK AVDD VDRV ADS5220 Timing/Duty Cycle Adjust Circuitry IN VIN S/H IN 12-Bit Pipelined ADC Error Correction Logic 3-State Output D0 • • • D11 OVR Internal Reference STPD QPD REFT REFB RSEL VREF OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2003-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) AVDD, DVDD, VDRV ........................................................................... +3.8V Analog Input ............................................................. –0.3V to (+VS + 0.3V) Logic Input ............................................................... –0.3V to (+VS + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5220 " TQFP-48 " PFB " –40°C to +85°C " ADS5220PFB " ADS5220PFBT ADS5220IPFBR Tape and Reel, 250 Tape and Reel, 2000 ADS5220 " QFN-48(2) " RGZ " –40°C to +85°C " ADS5220RGZ " ADS5220RGZ ADS5220IRGZR Rails, 52 Tape and Reel, 1000 PRODUCT NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. (2) This package available Q2 2004. ELECTRICAL CHARACTERISTICS: AVDD = 3.3V TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3, VDRV = 2.5V, –1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. ADS5220 PARAMETER CONDITIONS MIN RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Single-Ended Input Range Optional Single-Ended Input Range Differential Input Range Analog Input Bias Current Input Impedance Analog Input Bandwidth CONVERSION CHARACTERISTICS Sample Rate Data Latency Clock Duty Cycle DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 2.4MHz f = 9.7MHz No Missing Codes Integral Nonlinearity Error, f = 2.4MHz Spurious-Free Dynamic Range(1) f = 2.4MHz f = 9.7MHz f = 19.8MHz 2-Tone Intermodulation Distortion(3) f = 9.5MHz and 10.5MHz (–7dB each tone) Signal-to-Noise Ratio (SNR) f = 2.4MHz f = 9.7MHz f = 19.8MHz Signal-to-(Noise + Distortion) (SINAD) f = 2.4MHz f = 9.7MHz f = 19.8MHz Effective Number of Bits(4), f = 2.4MHz Output Noise Aperture Delay Time Aperture Jitter Over-Voltage Recovery Time Full-Scale Step Acquisition Time 2 Ambient Air 2VPP 1VPP 2VPP TYP MAX 12 Tested Bits –40 to +85 °C 0.5 1 1 2.5 2 2 V V V µA MΩ || pF MHz 40M Samples/s Clock Cycle % ±0.75 LSB LSB ±1.5 LSBs 1 1.25 || 5 300 Static, No Clock –3dBFS Input 1M 5 35 to 65 Mode Select Enabled UNITS ±0.3 ±0.35 Tested ±0.7 Referred to Full-Scale 83 88 88 76 dBFS(2) dBFS dBFS 86.3 dBc 70 70 69 dBFS dBFS dBFS 69 69 68 11.2 0.3 3 1.2 1.0 5 dBFS dBFS dBFS Bits LSBrms ns ps rms Clock Cycle ns Referred to Full-Scale 68.5 Referred to Full-Scale 68 Input Tied to Common-Mode ADS5220 www.ti.com SBAS261A ELECTRICAL CHARACTERISTICS: AVDD = 3.3V TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3, VDRV = 2.5V, –1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. ADS5220 PARAMETER DIGITAL INPUTS Logic Family Convert Command High Level Input Current(5) (VIN = 3VDD) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA to 1.5mA) High Output Voltage (IOH = 50µA to 0.5mA) 3-State Enable Time 3-State Disable Time Output Capacitance ACCURACY (Internal Reference, 2VPP, unless otherwise noted) Zero Error (referred to midscale) Zero Error Drift (referred to midscale) Gain Error(6) Gain Error Drift Power-Supply Rejection of Gain CONDITIONS MIN MAX CMOS-Compatible Rising Edge of Convert Clock 100 10 Start Conversion +1.7 +0.7 5 CMOS-Compatible Straight Offset Binary or BTC +0.1 VDRV = 2.5V +2.4 OE = H OE = L 20 2 5 40 10 fIN = 2.4MHz, at 25°C fIN = 2.4MHz at 25°C ±0.75 5 ±0.4 38 52 ±1.5 ∆ VS = ±5% INTERNAL VOLTAGE REFERENCE Output Voltage Error (1V) Load Regulation at 1mA Output Voltage Error (0.5V) Load Regulation at 0.5mA POWER-SUPPLY REQUIREMENTS Supply Voltage: AVDD, DVDD Driver Supply Voltage Supply Current: +IS Power Dissipation: VDRV = 2.5V VDRV = 3.3V Standard Power-Down Quasi-Power-Down Thermal Resistance, θJA TQFP-48 QFN-48 TYP ±3.0 ±10mV 0.15% ±5mV 0.1% Operating Operating (External Reference) +3.0 +2.3 +3.3 2.5 59 195 200 15 75 63.7 26.1 UNITS µA µA V V pF V V ns ns pF %FS ppm/°C %FS ppm/°C dB mV mV +3.6 +3.6 215 V V mA mW mW mW mW °C/W °C/W NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the twotone fundamental envelope. (4) Effective Number of Bits (ENOB) is defined by (SINAD – 1.76) /6.02. (5) A 50kΩ pull-down resistor is inserted internally on the OE pin. (6) Includes internal reference. ADS5220 SBAS261A www.ti.com 3 DVDD DVDD CLK DGND DGND DGND IN IN AGND AGND AGND AVDD PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 MSBI 1 36 AVDD OE 2 35 NC Mode Select 3 34 REFT STPD 4 33 NC QPD 5 32 REFB GDRV 6 GDRV 7 30 VREF VDRV 8 29 AGND VDRV 9 28 AGND D11 (MSB) 10 27 AGND 31 RSEL ADS5220 D4 D3 19 20 21 22 23 24 OVR 18 NC 17 NC 16 D0 (LSB) 15 D1 14 D2 13 D5 25 NC D6 D9 12 D7 26 NC D8 D10 11 PIN ASSIGNMENTS PIN I/O 1 4 DESCRIPTION MSBI Most Significant Bit Invert (HI = Binary Two’s Complement, LO = Straight Offset Binary) Tri-State (LO = Enabled, HI = Tri-State) Duty Cycle Stablilizer (HI = Enabled, LO = Normal Operation) Standard Power Down (LO = Normal Operation, HI = Enabled) Quasi Power Down (LO = Normal Operation, HI = Enabled) Output Driver Ground Output Driver Ground Output Driver Supply Output Driver Supply Data Bit 12 Data Bit 11 Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 No Internal Connection No Internal Connection Over-Range Indicator 2 3 OE Mode Select 4 STPD 5 QPD 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GDRV GDRV VDRV VDRV D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) NC NC OVR O O O O O O O O O O O O PIN NAME I/O NAME DESCRIPTION 25 NC No Internal Connection 26 NC No Internal Connection 27 AGND Analog Ground 28 AGND Analog Ground 29 AGND 30 VREF Internal Reference Voltage (1/2V Reference) 31 RSEL Reference Mode Select (see Table I for settings) 32 REFB 33 NC 34 REFT Top Reference Bypass 35 NC No Internal Connection 36 AVDD Analog Supply 37 AVDD Analog Supply 38 AGND Analog Ground 39 AGND Analog Ground 40 AGND 41 I 42 I Analog Ground Bottom Reference Bypass No Internal Connection Analog Ground IN Analog Input IN Complementary Analog Input 43 DGND Digital Ground 44 DGND Digital Ground 45 DGND Digital Ground 46 I CLK Convert Clock Input 47 I DVDD Digital Supply 48 I DVDD Digital Supply ADS5220 www.ti.com SBAS261A TIMING DIAGRAM N+2 N+1 Analog In N+4 N+3 N tD N+5 tL tCONV N+6 N+7 tH Clock 5 Clock Cycles t2 Data Out N–5 N–4 N–3 N–2 N–1 N Data Invalid SYMBOL tCONV tL tH tD t1 t2 N+2 t1 DESCRIPTION MIN Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 25 8.75 8.75 ADS5220 SBAS261A N+1 www.ti.com TYP MAX UNITS 1µs ns ns ns ns ns ns 12.5 12.5 3 3.9 12 5 TYPICAL CHARACTERISTICS: AVDD = 3.3V TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, –1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. SPECTRAL PERFORMANCE (Differential, 2VPP) SPECTRAL PERFORMANCE (Differential, 2VPP) 0 0 fIN = 2.4MHz (−1dBFS) SFDR = 88.2dBFS SNR = 70.0dBFS SINAD = 69.9dBFS −40 −60 −80 0 2 4 6 8 10 12 14 16 18 −80 0 20 2 4 6 8 10 12 14 Frequency (MHz) Frequency (MHz) SPECTRAL PERFORMANCE EXTERNAL REFERENCE (Differential, 2VPP) SPECTRAL PERFORMANCE PROGRAMMED REFERENCE (Differential, 1.5VPP) 0 16 18 20 0 fIN = 9.7MHz (−1dBFS) SFDR = 88.7dBFS SNR = 69.3dBFS SINAD = 69.1dBFS −20 −40 fIN = 2.4MHz (−1dBFS) SFDR = 88.8dBFS SNR = 70.0dBFS SINAD = 70.0dBFS −20 Amplitude (dB) Amplitude (dB) −60 −120 −120 −60 −80 −100 −40 −60 −80 −100 −120 −120 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 Frequency (MHz) Frequency (MHz) SPECTRAL PERFORMANCE (Differential, 1VPP) SPECTRAL PERFORMANCE (Single-Ended, 1VPP) 0 16 18 20 0 fIN = 9.7MHz (−1dBFS) SFDR = 84.9dBFS SNR = 67.4dBFS SINAD = 67.3dBFS −20 −40 fIN = 9.7MHz (−1dBFS) SFDR = 84.0dBFS SNR = 67.1dBFS SINAD = 66.9dBFS −20 Amplitude (dB) Amplitude (dB) −40 −100 −100 −60 −80 −100 −40 −60 −80 −100 −120 −120 0 2 4 6 8 10 12 14 16 18 20 0 Frequency (MHz) 6 fIN = 9.7MHz (−1dBFS) SFDR = 88.4dBFS SNR = 69.8dBFS SINAD = 69.7dBFS −20 Amplitude (dB) Amplitude (dB) −20 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ADS5220 www.ti.com SBAS261A TYPICAL CHARACTERISTICS: AVDD = 3.3V (Cont.) TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, –1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. SPECTRAL PERFORMANCE (Single-Ended, 2VPP) TWO-TONE INTERMODULATION DISTORTION 0 0 fIN = 9.7MHz (−1dBFS) SFDR = 80.2dBFS SNR = 69.6dBFS SINAD = 69.1dBFS −40 −60 −80 −40 −60 −80 −100 −100 −120 −120 0 2 4 6 8 10 12 14 16 0 20 18 2 4 6 10 12 14 Frequency (MHz) INTEGRAL LINEARITY ERROR INTEGRAL LINEARITY ERROR EXTERNAL REFERENCE 1.0 fIN = 9.7MHz 0.8 0.6 0.4 0.4 0.2 0.2 ILE (LSB) 0.6 0 –0.2 16 20 18 fIN = 9.7MHz 0.8 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 1024 2048 3072 0 4096 1024 DIFFERENTIAL LINEARITY ERROR EXTERNAL REFERENCE 1.0 3072 4096 DIFFERENTIAL LINEARITY ERROR 1.0 fIN = 9.7MHz 0.8 2048 Code Code fIN = 9.7MHz 0.8 0.6 0.6 0.4 0.4 0.2 0.2 DLE (LSB) DLE (LSB) 8 Frequency (MHz) 1.0 ILE (LSB) fIN = 9.5MHz (−7dBFS) fIN = 10.5MHz (−7dBFS) SFDR = 93.3dBFS −20 Amplitude (dB) Amplitude (dB) −20 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 1024 2048 3072 4096 Code 1024 2048 3072 4096 Code ADS5220 SBAS261A 0 www.ti.com 7 TYPICAL CHARACTERISTICS: AVDD = 3.3V (Cont.) TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, –1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. SWEPT POWER (SNR) EXTERNAL REFERENCE SFDR/SNR vs CLOCK DUTY CYCLE (DCA = Duty Cycle Adjust) 80 90 dBFS 70 SFDR: DCA off SFDR: DCA on 60 70 60 SNR: DCA off SNR: DCA on 50 SNR (dBc, dBFS) SFDR, SNR (dBFS) 80 50 40 30 20 10 dBc 0 40 −10 fIN = 9.7MHz −20 30 30 35 40 45 50 55 60 65 –80 70 –70 –60 SWEPT POWER (SFDR) –40 –30 0 85 dBFS 80 SNR, SFDR (dBFS) 80 70 60 50 40 30 dBc SFDR 75 70 65 SNR 60 55 20 10 50 fIN = 9.7MHz 0 45 –80 –70 –60 –50 –40 –30 –20 –10 0 1 100 10 Analog Input Level (dBFS) Frequency (MHz) DYNAMIC PERFORMANCE vs TEMPERATURE DYNAMIC PERFORMANCE vs TEMPERATURE 95 95 fIN = 2.4MHz fIN = 9.7MHz 90 90 85 SFDR, SNR (dBFS) SFDR, SNR (dBFS) –10 90 90 SFDR 80 75 70 65 SNR 85 SFDR 80 75 70 60 65 55 60 SNR −50 −25 0 25 50 75 100 Temperature (°C) 8 –20 SNR, SFDR vs INPUT FREQUENCY 100 SFDR (dBc, dBFS) –50 Analog Input Level (dBFS) Duty Cycle (%) −50 −25 0 25 50 75 100 Temperature (°C) ADS5220 www.ti.com SBAS261A TYPICAL CHARACTERISTICS: AVDD = 3.3V (Cont.) TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, –1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. OUTPUT NOISE HISTOGRAM (DC Output) 60000 50000 Counts 40000 30000 20000 10000 0 N–2 N–1 N N+1 N+2 Code APPLICATION INFORMATION THEORY OF OPERATION The ADS5220 is a 12-bit, 40MSPS, CMOS ADC designed with a fully differential pipeline architecture. The pipeline consists of three sections: a 3-bit quantizer, eight middle stages with a 1.5-bit quantizer for each stage, and a 4-bit flash. The output of each pipeline stage is processed and formed into 12-bit data in the digital error correction logic section to ensure good differential linearity of the ADC. The converter includes a high bandwidth track-and-hold amplifier in the input stage as shown in Figure 1. The rising edge of the input clock initiates the conversion process. Once the signal is captured by the input track-and-hold, the bits are sequentially encoded starting with the Most Significant Bit (MSB). This process results in a data latency of 5 clock cycles. The ADS5220 includes a high accuracy internal reference and also allows the use of an external reference. The input full-scale range is up to 2VPP and is selectable based on the reference voltage setting. For normal operation, both analog inputs (IN, IN) require an external commonmode voltage as a bias. The output data of the ADS5220 is available as a 12-bit parallel word, either coded in a Straight Offset Binary or Binary Two’s Complement format. The ADS5220 includes an on-chip duty-cycle adjust (DCA) circuit, controlled through the state of the Mode Select pin (3). When activated, this duty-cycle adjust circuit can accommodate for an incoming clock duty-cycle range of 35% to 65%, and re-time it to a 50% duty-cycle, which allows for optimum internal clock timing. The ADS5220 has low power dissipation in normal mode and has two power-down modes. The device operates from a single +3.3V power supply and has a separate digital output driver supply pin. S5 S3 VBIAS CIN S2 CIN IN T&H IN S4 S6 VBIAS Tracking Phase: S1, S2, S3, S4 closed; S5, S6 open Hold Phase: S1, S2, S3, S4 open; S5, S6 closed FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier of ADS5220. ADS5220 SBAS261A S1 www.ti.com 9 ANALOG INPUT INPUT COMMON-MODE VOLTAGE Depending on the application and the desired level of performance, the analog input of the ADS5220 can be configured in various ways and driven with different circuits. In any case, the analog interface requirements should be carefully examined before selecting the appropriate circuit configuration. The circuit definition should include considerations on the input frequency band and amplitude, as well as the available power supplies. The ADS5220 operates from a single +3.3V supply, and requires an external common-mode voltage. This allows a symmetrical signal swing while maintaining sufficient headroom to the supply rails. The common-mode voltage can be generated from an external DC voltage source (for example, an analog +3.3V supply with a simple resistor divider), or from the input signal source with DC-coupling. For a singleended input configuration, the common-mode voltage is typically +1.25V. When the input configuration is differential, the common-mode voltage is +1.5V. INPUT IMPEDANCE The input impedance of the ADS5220 is capacitive due to the input stray and sampling capacitors. These capacitors effectively result in a dynamic input impedance that is a function of the sampling and input frequency. Figure 2 depicts the differential input impedance of the ADS5220 as a function of the signal input frequency. For applications that use op amps to drive the ADC, it is recommended that a series resistor be added between the amplifier output and the converter inputs. This will isolate the capacitive input of the converter from the driving source and avoid gain peaking, or instability; furthermore, it will create a 1st-order, low-pass filter (LPF) in conjunction with the specified input capacitance of the ADS5220. The cutoff frequency of this LPF can be further adjusted by adding an external shunt capacitor. In any case, the use of the RC network is optional, but optimizing the values to adapt to the specific application is encouraged. INPUT FULL-SCALE RANGE The input full-scale range (FSR) of the ADS5220 is selectable from 1VPP to 2VPP and any value within this range, by the configuration of the reference select pin RSEL and reference voltage pin VREF (see Table I). The input FSR (differential) is always twice VREF (the voltage at the VREF pin) for all reference modes. By choosing different signal input ranges, trade-offs can be made between noise and distortion performance. For example, applications requiring the maximum signal-to-noise performance (SNR) will benefit from the 2VPP input range while lower distortion may be obtain with the reduced input range of 1VPP. Depending on the input driver configuration the 1VPP range may also relax the requirements for the driver, particularly for single-ended, single supply applications. DIFFERENTIAL INPUTS The ADS5220 input structure is designed to accept both a single-ended or differential analog signal. However, the ADS5220 will achieve its optimum performance when the analog inputs are driven differentially. DIFFERENTIAL INPUT IMPEDANCE 50k Differential operation of the ADS5220 requires that an input signal at the inputs (IN, IN) has the same amplitude and is 180 degrees out-of-phase. Differential signals offer a number of advantages: 40k Ω 30k 20k • The signal amplitude is half that required for the singleended operation, and is therefore less demanding to achieve, while maintaining good linearity performance from the signal source. 10k 100 1M 10M • The reduced signal swing allows for more headroom of the interface circuitry, and therefore also allows a wider selection of the most suitable driver amplifier. 100M Input Frequency (Hz) • Minimization of even-order harmonics. FIGURE 2. Differential Input Impedance vs Input Frequency. 10 • Improved noise immunity based on the common-mode input rejection of the converter. ADS5220 www.ti.com SBAS261A ANALOG INPUT DRIVEN BY TRANSFORMER The ADS5220 can be driven by a transformer, which provides signal AC-coupling and allows a signal conversion from single-ended input to differential output, or from single-ended input to single-ended output. Using a transformer offers a number of advantages. As a passive component, it does not add to the total noise and has better harmonics in wide frequency bands, compared to an op amp driver. By using a step-up transformer, further signal amplification can be realized; as a result, the signal swing from the source can be reduced. For transformer selection, it is important to carefully examine the application requirements and determine the correct model, the desired impedance ratio, and frequency characteristics. Furthermore, the appropriate model must support the targeted distortion level and should not exhibit any core saturation at full-scale voltage levels. A variety of miniature RF transformers from different manufacturers (such as Mini-Circuits, Coilcraft, or Trak) can be selected. 1:n 24.9Ω IN RS ADS5220 22pF 24.9Ω IN RT 0.1µF 1.7kΩ 3.3V 1.5V 1.5kΩ FIGURE 3. Transformer-Coupled Differential Input Configuration of ADS5220. Figure 3 shows a transformer-coupled input configuration of the ADS5220. The ADS5220 receives a differential AC signal from the output of the transformer and common-mode voltage of +1.5V from the center tap. A source termination resistor, RT , is required, which may be placed at the primary or secondary side of the transformer to satisfy the termination requirements of the source impedance, RS. The circuit also shows the use of an additional RC low-pass filter placed in series with each converter input to attenuate some of the wideband noise. The resistor values are typically in the range of 10Ω to 50Ω, and capacitors are in the range of 10pF to 100pF for individual application requirements. ANALOG INPUT DRIVEN BY AMPLIFIER The ADS5220 can be driven by an operational amplifier with DC or AC signal coupling, as shown in Figure 4 and Figure 5. In Figure 4, the THS4503, a differential amplifier, is used to convert a single-ended input into a differential output with a gain of 2. The THS4503 provides an output common-mode voltage set by VOCM pin, and is DC-coupled to the input of ADS5220. A low-pass filter can be created by adding small capacitors (for example, 10pF) in parallel with the feedback resistors of the THS4503 as needed for some applications. +5V 10pF(1) 392Ω 187Ω 24.9Ω IN 50Ω Source VOCM 60.4Ω THS4503 24.9Ω ADS5220 22pF IN 0.1µF 392Ω 215Ω 10pF(1) –5V 1.7kΩ 3.3V 1.5V 1.5kΩ NOTE: (1) optional. FIGURE 4. Using the THS4503 Differential Amplifier (Gain = 2) to Drive the ADS5220 in a DC-Coupled Configuration. ADS5220 SBAS261A www.ti.com 11 Due to the THS4503 driving a capacitive load, small series resistors in the output ensure stable operation. Further details of this and other functions of the THS4503 may be found in its product datasheet, located on the Texas Instruments web site (www.ti.com). In general, differential amplifiers provide a high-performance driver solution for applications that require DC signal coupling. 3.3V CMOS/TTL 0V CLK Clock Source 50Ω 50Ω ADS5220 Mode Select As shown in Figure 5, an AC-coupled, single-ended input configuration is realized with TI’s OPA695 for wideband applications. For narrowband applications, the OPA2822 can be used. In Figure 5, the OPA695 is configured for a single supply +5V and noninverting operation. The AC gain of the amplifier is 2 and the DC bias of the amplifier is +2.5V, set by the voltage divider from the op amp power supply. The OPA695 is a very high bandwidth, current-feedback op amp that combines 4200V/µs slew rate and low input voltage noise. The OPA695’s high slew-rate and output drive capability can support the maximum full-scale input range of the ADS5220 up to high input frequencies. A = DCA enabled B = DCA disabled DVDD A B FIGURE 6. General Input Clock Interface of ADS5220. The clock input of the ADS5220 is referenced to the digital supply (DVDD) and the applied logic levels should comply with the specified levels (LV-logic). To obtain the specified level of performance the clock signal applied to the ADS5220 should have as close of a 50% duty cycle as possible. This is particularly important when the ADS5220 is operated at its maximum sampling rate. Since this condition cannot always easily be met, the ADS5220 features an on-chip duty-cycle adjust (DCA) circuit that allows for additional design flexibility. The function of this duty cycle adjust circuit is controlled through the Mode Select pin. Its default configuration is for a logic low (internal pull-down) which has the DCA circuit disabled. Applying a logic high, the DCA circuit becomes activated. Now the incoming clock duty cycle can be in the range of 35% to 65% and the DCA circuit will adjust this to be 50% for the internal timing. There may be situations where Further details of the OPA695 can be found in the OPA695 data sheet. The common-mode voltage at the ADS5220 input is +1.25V, set by a voltage divider from +3.3V power supply. The +3.3V power supply must be decoupled, as shown in Figure 11. CLOCK INPUT The clock input of the ADS5220 is designed to operate with a single-ended pulse clock with CMOS/TTL level and DCcoupling. There is no external common-mode voltage requirement at the clock input pin (see Figure 6). +5V 0.1µF 6.8µF 1kΩ 1.6kΩ 806Ω 3.3V +5V 0.1µF 0.1µF 50Ω Source 57.6Ω 806Ω 30Ω IN OPA695 47pF 0.1µF 487Ω ADS5220 487Ω IN 0.1µF 1.6kΩ 3.3V 1.25V 47pF 1kΩ FIGURE 5. Single-Ended Input of ADS5220 Driven by OPA695 with Gain = 2. 12 ADS5220 www.ti.com SBAS261A the user may prefer to disable the DCA function; for example, during asynchronous clocking (that is, when the sampling period is purposely not constant). In any case, a very low jitter clock is fundamental to preserving the excellent AC performance of the ADS5220. Generally, as input frequency increases, clock jitter becomes more critical to maintain a good signal-to-noise ratio. The following equation can be used to calculate the achievable SNR for a given input frequency and clock jitter (tJA in ps rms): SNRJA = 20 log [1/(2 • π • fIN • tJA)] Here, the tJA is the rms aperture jitter from all jitter sources, such as clock edge, input signal and the device. The fIN is input frequency. The crystal oscillator has very low jitter, but if using a clock conditioning circuit (gate, divider, logic level converter, and so forth), the extra jitter and timing variation must be considered. In addition, the input clock is treated as an analog signal and its power supply should be separated from the power supply of the digital output driver to limit the digital noise. MINIMUM SAMPLING RATE The pipeline architecture of the ADS5220 uses a switchedcapacitor technique in its internal track-and-hold stages. The high sampling speed necessitates the use of very small capacitor values. In order to hold droop errors low, the capacitors require a minimum refresh rate. To maintain accuracy of the acquired sample charge, the sampling clock on the ADS5220 must not drop below the specified minimum of 1MSPS. REFERENCE The ADS5220 provides both an internal and an external reference mode through the configuration of pins RSEL and VREF (see Table 1). The input full-scale range (FSR) of the ADS5220 is always twice the voltage at the VREF pin. The REFT and REFB pins are internally buffered, and drive the ADC core for both the external and internal reference modes. When the internal reference mode is selected the voltage at VREF is generated by an internal 0.5V bandgap voltage through a VREF amplifier. This internal buffer amplifier can be used to supply up to 2mA to external circuitry. Selecting the external reference mode will power-down this reference amplifier, and the VREF pin becomes the input for the external reference voltage. In the power-down mode, the impedance of the VREF pin is approximately 6kΩ. remains the same for the internal or external reference modes. The bypassing should consist of two pairs of 2.2µF ceramic and 15µF tantalum capacitors, and a 10µF tantalum capacitor, as depicted in Figure 7. In addition to the bypassing the top- and bottom reference pin (REFT, REFB) require a pull-up and a pull-down resistor, respectively. As shown in Figure 7, the pull-up resistor should be connected from the REFT pin to the analog supply (+3.3V AVDD), while the pull-down resistor on the REFB pin should be connected to ground. For proper operation the value of those resistors should be maintained as shown, that is, 402Ω. Also, to ensure optimal settling of the internal reference amplifiers the external configuration must include two low value resistors located in series with each the REFT and REFB pins (see Figure 7). For best results, use small surface mount chip resistors and position them as close to the pins as possible. INTERNAL REFERENCE There are two internal fixed reference modes and one internal programmable reference mode as shown in Table I and Figure 7 through Figure 9. Setting RSEL to ground (or < 0.2V) provides an internal reference voltage of +1.0V at VREF pin, +2V at REFT, and +1V at REFB pin. In this case, the input FSR is +2V peak-to-peak. Connecting RSEL to the VREF pin provides an internal reference voltage of +0.5V at VREF, +1.75V at REFT, and +1.25V at REFB. In this case, the input FSR is +1V peak-to-peak. Setting the resistor divider as in Figure 9 provides an internal voltage between +0.5V and +1V at VREF, which is as follows: VREF = 0.5 • (1+R2/R1) In this case, the voltage at REFT and REFB and input FSR is calculated based on Table I. RSEL VREF 0.1µF 2.2µF 1V Output 402Ω ADS5220 +3.3V REFT 2Ω + 10µF 2.2µF + 15µF 2Ω REFB 402Ω Shown in Table I are the values for VREFT, VREFB, and VREF for the various modes and full-scale input ranges. The ADS5220 requires its reference pins to be bypassed as outlined in Figure 7 through Figure 10. The configuration + 2.2µF + 15µF FIGURE 7. Internal Reference Mode for VREF = 1V. SELECTED MODE RSEL PIN CONNECT TO VREF PIN (V) INPUT FSR (VPP) (Differential) REFT (V) REFB (V) Internal Fixed Internal Fixed Internal Program External GND to 0.2V VREF Pin 0.2V to VREF AVDD (3.3V) 1.0 0.5 0.5 • (1+R2/R1) Ext. 0.5V to 1V 2 1 2 • VREF 2 • VREF 2 1.75 VREF/2 + 1.5 VREF/2 + 1.5 1 1.25 1.5 – VREF/2 1.5 – VREF/2 TABLE I. Reference Configuration. ADS5220 SBAS261A www.ti.com 13 AVDD RSEL VREF + 0.1µF 0.5V Output 2.2µF RSEL 402Ω ADS5220 +3.3V + 2Ω 10µF 2.2µF + Input 0.5V to 1V VREF REFT 0.1µF + 2.2µF 15µF 402Ω ADS5220 +3.3V 2Ω REFT REFB 2.2µF 402Ω + 2Ω 15µF + 10µF 2.2µF + 15µF 2Ω REFB FIGURE 8. Internal Reference Mode for VREF = 0.5V. 2.2µF 402Ω + 15µF FIGURE 10. External Reference Configuration. RSEL R2 DIGITAL OUTPUTS VREF 0.1µF + 2.2µF R1 DATA OUTPUT FORMAT 402Ω ADS5220 +3.3V REFT 2Ω + 10µF 2.2µF + 15µF 2Ω REFB 402Ω 2.2µF + 15µF FIGURE 9. Internal Reference Mode for VREF = 0.5 • (1 + R2/R1). The ADS5220 makes two data output formats available, either the Straight Offset Binary (SOB) code or the Binary Two’s Complement (BTC) code. The selection of the output coding is controlled through the MSBI pin. Applying a logic high will enable the BTC coding, whereas a logic low will enable the SOB code. In its default configurations the MSBI pin assumes a logic low level (internal pull-down) and the ADS5220 will operate with the SOB output coding. The two code structures are identical with one exception: the MSB is inverted for the BTC format, as shown in Table II. If the input signal exceeds the FSR, the output code will remain at all 1s or all 0s. EXTERNAL REFERENCE For even more design flexibility, the ADS5220 can be operated with external references. Utilization of an external reference voltage may be considered for applications requiring higher accuracy, improved temperature stability, or flexible full-scale range. Particularly in multi-channel applications, the use of a common external reference offers the benefit of improving gain matching between converters. Setting RSEL to AVDD (+3.3V) provides an external reference mode for the ADS5220. In this case, the internal VREF amplifier is powered down, and the VREF pin requires an external reference voltage between +0.5V to +1V to provide an input full-scale range of 1VPP to 2VPP. The REFT and REFB will appear with the voltage as shown in Table I, and input FSR is always twice the voltage at the VREF pin. A voltage reference (REF1004 or TPS79225) and a single-supply amplifier (OPA2234 or OPA4227) can be used to generate a precision external reference. 14 STRAIGHT OFFSET BINARY (SOB) BINARY TWO’S COMPLEMENT (BTC) +FS – 1LSB (+FS: IN = 2V, IN = 1V) 1111 1111 1111 0111 1111 1111 +1/2 FS (IN = 1.75V, IN = 1.25V) 1100 0000 0000 0100 0000 0000 Bipolar Zero (IN = IN = 1.5V) 1000 0000 0000 0000 0000 0000 –1/2 FS ( IN = 1.75V, IN = 1.25V) 0100 0000 0000 1100 0000 0000 –FS ( IN = 2V, IN = 1V) 0000 0000 0000 1000 0000 0000 DIFFERENTIAL INPUT TABLE II. Coding Table for Differential Input Configuration with FSR of 2VPP. ADS5220 www.ti.com SBAS261A OUTPUT ENABLE (OE ) The digital outputs including the OVR pin of the ADS5220 can be set to output enable or output high impedance (tristate) by the OE pin. For normal operation, this pin must be at a logic low (default is internal pull-down), whereas a logic high disables the outputs or sets the output tri-state. data, when the input voltage changes from normal value to over FS or from over FS to normal value. The OVR signal remains high for as long as the input signal exceeds the input range limits of the ADS5220. The OVR pin is tri-stated by the use of the output enable pin (OE). TIMING OUTPUT LOADING It is recommended to keep the capacitive loading on the data output lines as low as possible, preferably below 10pF. Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. These high current surges can feed back to the analog portion of the ADC and adversely affect device performance. If necessary, external buffers or latches (for example, the SN74LVTH16374) close to the converter output pins can be used to minimize capacitive loading. Buffers or latches also provide the added benefit of isolating the ADS5220 from any digital activities on the bus to limit the high-frequency noise. The ADS5220 samples the analog signal at the rising edge of its input clock, and outputs the digital data at the rising edge of the input clock after a pipeline delay of 5 clocks. There is an aperture delay (typically 3ns) between the sampling edge and the actual sampling time. There is also a propagation delay between the rising edge of the clock and the time that data is valid on the data bus (see the timing diagram on page 5). The output data of the ADS5220 is latched data. POWER SUPPLIES AND POWER DISSIPATION OVER-RANGE INDICATOR ANALOG AND DIGITAL POWER SUPPLY The ADS5220 has control functions for the input voltage over full-scale that includes output data code control and overrange indication. The output data code control of over fullscale is shown in Table II. In SOB format, for example, when the input voltage is (+FS – 1 LSB) or above this value, the ADS5220 outputs all 1s at 12 data bits; when the input voltage is –FS or below this value, the ADS5220 outputs all 0s at 12 data bits. When the input voltage is 0 (mid-scale) or only the common-mode voltage at the input, the ADS5220 outputs 1 at MSB and 0s at the remaining 11 data bits. Another over-range control function of the ADS5220 is overrange indication, which is output by the OVR pin. The OVR pin is the function of the reference voltage and the output data bits, and has the same pipeline delay as the output data bits. OVR is at logic low if the input voltage is within the FSR, and is at logic high if the input voltage is over full-scale or under full-scale. OVR changes from logic low to high or logic high to low immediately following the change of the output The ADS5220 includes power-supply pins of AVDD, DVDD and VDRV. The analog supply AVDD and digital supply DVDD is +3.3V. The digital output driver supply, VDRV, can be set between +2.5V and +3.3V. AVDD, DVDD and VDRV are not tied together internally. Each of these supply pins must be bypassed separately with at least one 0.1µF ceramic chip capacitor. The analog supply (AVDD) and the digital supply (DVDD or VDRV) may be tied together externally with a ferrite bead or inductor between the supply pins. The ADS5220 is specified with the digital output driver supply, VDRV, set to +2.5V. It is highly recommended to consider linear supplies instead of switching types. Even with good filtering, switching supplies can radiate noise that could interfere with any highfrequency input signal and cause unwanted modulation products. The supply voltage should stay within the tolerance given in the specification table. A basic application configuration with the power supply decoupling is shown in Figure 11. ADS5220 SBAS261A www.ti.com 15 3.3V 30 31 24.9Ω 42 1.5VDC AVDD AVDD 36 0.10µF 37 0.10µF 48 10µF + DVDD 47 DVDD 5 Q PD 4 3 2 10µF + VREF NC RSEL NC OVR IN 22pF 15µF +3.3V (AVDD) 2.2µF 2Ω 10µF 34 33 32 402Ω + 15µF 2.2µF 2Ω 38 39 40 43 44 45 27 28 29 46 D11 (MSB) D10 REFT D9 NC D8 REFB D7 ADS5220 D6 AGND D5 AGND D4 AGND D3 DGND D2 DGND D1 DGND D0 (LSB) AGND 26 25 24 23 22 LATCH 10 11 12 13 14 15 16 17 18 19 20 21 SN74LVTH16374 AGND AGND CLK GNDRV + NC GNDRV 35 NC IN NC VDRV 41 VDRV 24.9Ω 1.5VDC 402Ω ST PD + 0.10µF Mode Select 2.2µF OE MSBI 1 3.3V – 7 6 49.9Ω 9 VPULSE 8 + 0.10µF 10µF + VDRV NC = No Connection. FIGURE 11. General Configuration for the ADS5220. POWER DISSIPATION POWER DOWN In normal operating mode (STPD = low and QPD = low), the typical total power dissipation of the ADS5220 is 195mW. The majority of the power consumption is due to biasing; therefore, this part of the total power dissipation is independent of the applied clock frequency. The current on the VDRV supply is directly related to the capacitive loading of the data output pins; care must be taken to minimize such loading. The ADS5220 provides two power-down modes for different application requirements. One is the Standard Power-Down (STPD); the second is the Quasi-Power-Down (QPD). Both pins will assume a logic low level (internal pull-down) and configure the ADS5220 for normal operation. Setting STPD to logic high (and QPD to logic low or high) will shut down the internal ADC core and power down the reference circuit. In 16 ADS5220 www.ti.com SBAS261A this case the power dissipation is typically 15mW. With 10µF external decoupling capacitor at REFT and REFB, it takes about 800µs to fully restore normal operation after the normal mode is enabled. Setting QPD to logic high (and STPD to logic low) will shut down the internal ADC core while the internal reference circuit power remains on. In this case, power dissipation is typically 75mW. It takes about 2µs to fully restore normal operation after the normal mode is enabled. During power-down, data in the converter pipeline will be lost and new valid data will be subject to the specified pipeline delay. LAYOUT AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for highfrequency designs. Achieving optimum performance with a fast sampling converter like the ADS5220 requires careful attention to the PC board layout in order to minimize the effect of board parasitics and optimize component placement. A multi-layer board usually ensures best results and allows convenient component placement. The ADS5220 must be treated as an analog component, and the AVDD pins connected to a clean analog supply. This ensures the most consistent results, because digital supplies often carry a high level of switching noise that could couple into the converter and degrade the performance. The driver supply pins (VDRV) must also be connected to a low-noise supply. Supplies of adjacent digital circuits can carry substantial current transients. The supply voltage must be thoroughly filtered before connecting to the VDRV supply of the converter. All ground connections on the ADS5220 are internally bonded to the metal flag (bottom of package) that forms a large ground plane. All ground pins must directly connect to an analog ground plane that covers the PC board area under the converter. Due to its high sampling frequency, the ADS5220 generates high frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. If not sufficiently bypassed, this adds noise to the conversion process. See Figure 11 for the recommended supply decoupling scheme for the ADS5220. All AVDD pins should be bypassed with a combination of 0.1µF ceramic chip capacitors (0805, low ESR) and a 10µF tantalum tank capacitor. A similar approach may be used on the digital supply pins DVDD and driver supply pins, VDRV. In order to minimize the lead and trace inductance, the capacitors must be located as close to the supply pins as possible. They are best placed directly under the package where double-sided component mounting is allowed. In addition, larger bipolar decoupling capacitors (2.2µF to 10µF), effective at lower frequencies, may also be used on the main supply pins. They can be placed on the PC board in close proximity (< 0.5 inches) to the ADC. If the analog inputs to the ADS5220 are driven differentially, it is especially important to optimize towards a highly symmetrical layout. Small trace length differences can create phase shifts compromising a good distortion performance. For this reason, the use of two single op amps rather than one dual amplifier enables a more symmetrical layout and a better match of parasitic capacitances. The pin orientation of the ADS5220 package follows a flow-through design with the analog inputs located on one side of the package, whereas the digital outputs are located on the opposite side of the quad-flat package. This provides a good physical isolation between the analog and digital connections. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog portion. Try to match trace length for the differential clock signal (if used) to avoid mismatches in propagation delays. Single-ended clock lines must be short and should not cross any other signal traces. Short circuit traces on the digital outputs will minimize capacitive loading. Trace length must be kept short to the receiving gate (< 2 inches) with only one CMOS gate connected to one digital output. If possible, the digital data outputs should be buffered (with the TI SN74LTH16374, for example). Dynamic performance can also be improved with the insertion of series resistors at each data output line. This sets a defined time constant and reduces the slew rate that would otherwise flow as the fast edge rate. The resistor value may be chosen to give a time constant of 15% to 25% of the used data. ADS5220 SBAS261A www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS5220PFBR ACTIVE TQFP PFB 48 2500 None CU NIPDAU Level-2-220C-1 YEAR ADS5220PFBT ACTIVE TQFP PFB 48 250 None CU NIPDAU Level-2-220C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. 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Addendum-Page 1 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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