TI TAS5000

TAS5000
Digital Audio PWM Processor
Data Manual
December 2000
Digital Audio
SLAS270
IMPORTANT NOTICE
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Copyright  2000, Texas Instruments Incorporated
Contents
Section
1
2
3
Title
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Suggested System Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Serial Audio Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
System Clocks – Master Mode and Slave Mode . . . . . . . . . . . . . . . . .
2.3
Oscillator/Sampling Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Phase Locked Loop (PLL)/Clock Generation . . . . . . . . . . . . . . . . . . . .
2.5
Digital Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Digital PWM Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7
Control, Status, and Operational Modes . . . . . . . . . . . . . . . . . . . . . . . .
2.7.1
Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.3
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.4
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.5
Double Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.6
De-Emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.7
Error Status Reporting (ERR pin) . . . . . . . . . . . . . . . . . . . . . .
2.8
Serial Interface Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1
MSB First Right Justified (for 16-, 20-, 24-bits) . . . . . . . . . .
2.8.2
IIS Compatible Serial Format (for 16-, 20-, 24-bits) . . . . . .
2.8.3
MSB Left Justified Serial Interface Format (for 16 bits) . . .
2.8.4
DSP Compatible Serial Interface Format (for 16 bits) . . . .
2.9
PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
Static Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
Digital Interpolation Filter and PWM Modulator . . . . . . . . . .
3.3.3
TAS5000/TAS5100 System Performance Measured at the
Speaker Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
1–1
1–1
1–2
1–3
1–5
1–5
1–6
2–1
2–1
2–1
2–1
2–1
2–2
2–2
2–2
2–2
2–3
2–3
2–3
2–4
2–4
2–4
2–4
2–5
2–5
2–6
2–6
2–6
3–1
3–1
3–1
3–2
3–2
3–2
3–2
3–2
iii
4
5
3.4.1
Serial Audio Ports Slave Mode . . . . . . . . . . . . . . . . . . . . . . .
3.4.2
Serial Audio Ports Master Mode . . . . . . . . . . . . . . . . . . . . . .
3.4.3
DSP Serial Interface Switching Characteristics . . . . . . . . .
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2
3–3
3–3
4–1
5–1
List of Illustrations
Figure
Title
Page
1–1 System #1: Stereo Configuration Using Two TAS5100 Amplifiers . . . . . . . . 1–3
1–2 System #2: Stereo Configuration With DSP . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1–3 System #3: 6-Channel Audio Playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
2–1 Power-Up Timing (RESET preceding PDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2–2 Power-Up Timing (PDN preceding (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
2–3 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
2–4 Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
2–5 De-Emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2–6 MSB First Right Justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2–7 IIS Compatible Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2–8 MSB Left Justified Serial Interface Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2–9 DSP Compatible Serial Interface Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
4–1 Right Justified, IIS, Left Justified Serial Protocol Timing . . . . . . . . . . . . . . . . 4–1
4–2 Right, Left, and IIS Serial Mode Timing Requirement . . . . . . . . . . . . . . . . . . 4–1
4–3 Serial Audio Ports Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4–4 DSP Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4–5 DSP Serial Port Expanded Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–6 DSP Absolute Timing Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
5–1 Connection Diagram, Slave Mode (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
List of Tables
Table
Title
Page
2–1 Oscillator, External Clock, and PLL Functions . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2–2 Mute Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2–3 De-Emphasis Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2–4 Hardware Selection of Serial Audio Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
iv
1 Introduction
The TAS5000 is an innovative, cost-effective, high-performance 24-bit stereo digital modulator based on Equibit
technology. This product converts input PCM serial digital audio data to an output PWM audio data stream. The
TAS5000 is designed to be connected to two TAS5100 mono true digital amplifiers for driving loudspeakers. This
all-digital audio system contains only two analog components in the signal chain—an L-C low-pass filter at the
speaker terminals. It can provide up to 90 dB SNR at the speaker terminals. It has a wide variety of serial input options
including right justified (16, 20, or 24-bit), IIS (16, 20, or 24-bit), left justified (16-bit), or DSP (16-bit) data formats. It
is fully compatible with AES standard sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz including providing
de-emphasis for 44.1 kHz, and 48 kHz sample rates. The TAS5000 and TAS5100 system can be used in a range of
products such as microcomponent systems, PC speakers, home theater in a box, convergence products, A/V
receivers, or TV sets.
1.1 Features
•
True Digital Audio Amplifier
•
High Quality Audio
•
16-, 20-, or 24 Bit Input Data
•
Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz
•
Supports Master and Slave Modes
•
90 dB SNR (EIAJ) and Dynamic Range at the Speaker Terminals
•
3.3 V Power Supply Operation
•
Economical 48-Pin TQFP Package
•
Digital De-Emphasis: 44.1 kHz and 48 kHz
•
High Power Efficiency
•
Clock Oscillator Circuit for Master Modes
•
Low Jitter Internal PLL
•
Mute
•
Good Phase Characteristics
•
Excellent PSRR
Equibit is the trademark of Texas Instruments.
1–1
PLL/Clock
Generator
OSC_CAP
XTL_OUT
XTL_IN
MCLK_OUT
ERR
MCLK_IN
PLL_FLT_RET
PLL_FLT_OUT
1.2 Functional Block Diagram
OSC
PWM_P_L
PWM_M_L
LRCLK
Serial
Audio
Port
SCLK
Digital
Interpolation
Filter
Equibit
Modulator
Buffer
SDIN
PWM_P_R
PWM_M_R
Control Section
1–2
DVDD1
DVSS1
DVDD2
DVSS2
DVDD3_L
DVSS3_L
DVDD3_R
DVSS3_R
AVDD1
AVSS1
AVDD2
AVSS2
FTEST
STEST
PTEST
DBSPD
M_S
PDN
RESET
MUTE
DEM_EN
MOD2
DEM_SEL
MOD1
MOD0
Audio Port
Configuration
1.3 Suggested System Block Diagrams
See application notes for more details.
Digital Audio
• USB
• IEEE 1394
• SPDIF
• ADC
• Automotive
MOST
Network
Left
TAS3001
IIC
Audio
Control
TAS5100
TAS5000
Right
TAS5100
• Digital Parametric EQ • Serial Audio Input Port
• Volume
• Internal PLL
• DRC
• 2 Mono H-Bridges
• Bass
• Treble
Figure 1–1. System #1: Stereo Configuration Using Two TAS5100 Amplifiers
Left
TAS5100
Digital Audio
• DSP
TAS5000
Right
TAS5100
• Volume
• Serial Audio Input Port
• EQ
• Internal PLL
• DRC
• 2 Mono H-Bridges
• Bass
• Treble
• Surround Processing
• AC-3 DTS Decode
Figure 1–2. System #2: Stereo Configuration With DSP
1–3
CH1
TAS5000
TAS5100
CH2
TAS5100
Home Theater
DVD 6-Channel
Encoded Digital
Audio Source
6
DSP 6-Channel
Decode
• Dolby AC-3
• DTS
• Volume
• EQ
• DRC
• Bass
• Treble
CH3
TAS5000
TAS5100
CH4
TAS5100
CH5
TAS5000
TAS5100
CH6
TAS5100
Figure 1–3. System #3: 6-Channel Audio Playback
1–4
1.4 Terminal Assignments
DEM_SEL
FTEST
STEST
DBSPD
MUTE
DVSS3_L
AVDD1
XTL_IN
XTL_OUT
OSC_CAP
AVSS1
DEM_EN
48-Pin TQFP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
MCLK_IN
AVDD2
PLL_FLT_OUT
PLL_FLT_RET
AVSS2
NC
RESET
PDN
PTEST
M_S
NC
DVDD1
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
DVDD3_L
PWM_P_L
PWM_M_L
NC
NC
DVDD2
DVSS2
PWM_P_R
PWM_M_R
NC
NC
DVDD3_R
DVSS1
DVDD1
DVSS1
MCLK_OUT
SCLK
LRCLK
SDIN
MOD2
MOD1
MOD0
ERR
DVSS3_R
13 14 15 16 17 18 19 20 21 22 23 24
NC – No internal connection
1.5 Ordering Information
TA
0°C to 70°C
PACKAGE
TAS5000PFB
1–5
1.6 Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVDD1
48
I
Analog supply for oscillator
AVDD2
2
I
Analog supply for PLL
AVSS1
44
I
Analog ground for oscillator
AVSS2
5
I
Analog ground for PLL
DBSPD
39
I
Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high
DEM_EN
43
I
De-emphasis enable, active high
DEM_SEL
42
I
De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz)
DVDD1
12, 14
I
Digital voltage supply for logic
DVDD2
31
I
Digital voltage supply for PWM reclocking
DVDD3_L
36
I
Digital voltage supply for PWM output (left)
DVDD3_R
25
I
Digital voltage supply for PWM output (right)
DVSS1
13, 15
I
Digital ground for Logic
DVSS2
30
I
Digital ground for PWM reclocking
DVSS3_L
37
I
Digital ground for PWM output (left)
DVSS3_R
24
I
Digital ground for PWM output (right)
ERR
23
O
System error flag, active low
FTEST
41
I
Tied to DVSS1 for normal operation
LRCLK
18
I/O
MCLK_IN
1
I
MCLK input
MCLK_OUT
16
O
Buffered system clock output if M_S = 1; otherwise set to 0
MOD0
22
I
Serial interface selection pin, bit 0
MOD1
21
I
Serial interface selection pin, bit 1
MOD2
20
I
Serial interface selection pin, bit 2 (MSB)
M_S
10
I
Master/slave, Master=1, Slave=0
MUTE
38
I
Muted signal = 0, Normal mode = 1
NC
6, 11, 26, 27,
32, 33
Left/right clock (input when M_S = 0; output when M_S = 1)
No connection
OSC_CAP
45
I
Oscillator cap return
PDN
8
I
Power down, active low
PTEST
9
I
Tied to DVSS1 for normal operation
PLL_FLT_OUT
3
O
Output terminal for external PLL filter
PLL_FLT_RET
4
I
Return for external PLL filter
PWM_M_L
34
O
PWM left output (differential –) Positive H-bridge side
PWM_M_R
28
O
PWM right output (differential –) Positive H-bridge side
PWM_P_L
35
O
PWM left output (differential +) Positive H-bridge side
PWM_P_R
29
O
PWM right output (differential +) Positive H-bridge side
RESET
7
I
Reset (active low)
SCLK
17
I/O
SDIN
19
I
Stereo serial audio data input
STEST
40
I
Tied to DVSS1 for normal operation
XTL_IN
47
I
Crystal or clock input (MCLK input)
XTL_OUT
46
O
Crystal output (not for external usage) NC when XTL_IN is MCLK input
1–6
Shift clock (input when M_S = 0, output when M_S = 1)
2 Functional Description
2.1 Serial Audio Port
The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and
a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 44.1 kHz, 48 kHz, 88.2 kHz,
or 96 kHz) stereo. See section 2.8 for Serial Interface Formats.
2.2 System Clocks – Master Mode and Slave Mode
The TAS5000 allows multiple system clocking schemes. In this document, master mode indicates that the TAS5000
provides system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 256Fs MCLK_OUT,
64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave mode indicates
that a system master other than the TAS5000 provides system clocks (LRCLK, SCLK, and MCLK_IN) to the TAS5000
(M_S = 0). The TAS5000 operates with LRCLK and SCLK synchronized to MCLK. TAS5000 does not require any
specific phase relationship between LRCLK and MCLK, but there must be synchronization. If the synchronization
between MCLK and LRCLK changes more than 10 MCLK periods during one sample period (LRCLK), the TAS5000
will initiate an internal reset. In the slave mode MCLK_OUT is driven low. Table 2–1 shows all the possible master
and slave modes.
2.3 Oscillator/Sampling Frequency
The sampling frequency is determined by the crystal (master mode) or master clock in (slave mode) which should
be either 11.2896 MHz (Fs = 44.1 kHz) or 12.288 MHz (Fs = 48 kHz). Twice the normal sampling frequency can be
selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz or Fs = 96 kHz. In the double-speed slave
mode (DBSPD = 1, M_S = 0), the external clock input is either 22.5796 MHz (Fs = 88.2 kHz) or 24.576 MHz
(Fs = 96 kHz). Table 2–1 explains the proper clock selection.
2.4 Phase Locked Loop (PLL)/Clock Generation
A low jitter PLL is incorporated for internal use. Connections for the PLL external loop filter are provided as
PLL_FLT_RET and PLL_FLT_OUT. See Figure 5–1 for a suggested external loop filter. If the PLL loses lock, the error
status pin (ERR) will go low. Note that ERR can go low for other conditions as well. See section 2.7.7 Error Status
Reporting.
2–1
Table 2–1. Oscillator, External Clock, and PLL Functions
DESCRIPTION
MCLK_IN
(MHz)‡
SCLK
(MHz)¶
LRCLK
(kHz)¶
11.2896
—
2.8224
44.1
0
12.288
48
12.288
—
5.6448
88.2
22.5792
1
1
—
—
22.5792§
24.576§
3.072
1
0
0
—
0
0
—
M_S
DBSPD
Master, normal speed
1
0
Master, normal speed
1
Master, double speed
1
Master, double speed
Slave, normal speed
Slave, normal speed
Slave, double speed
0
1
XTL_IN
(MHz)†
—
MCLK_OUT
(MHz)#
11.2896
6.144
96
24.576
11.2896§
12.288§
2.8224
44.1
Digital GND
3.072
48
Digital GND
22.5792§
24.576§
5.6448
88.2
Digital GND
6.144
96
Digital GND
Slave, double speed
0
1
—
† Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN.
‡ MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided.
§ External MCLK connected to MCLK_IN input
¶ SCLK and LRCLK are outputs when M_S=1, inputs when M_S=0.
# MCLK_OUT is driven low when M_S=0.
2.5 Digital Interpolation Filter
The 24-bit high performance linear phase FIR interpolation filter up-samples the input digital data at a rate of 4 times
(double speed mode = 88.2 kHz or 96 kHz) or 8 times (normal mode = 44.1 kHz or 48 kHz) the incoming sample rate.
This filter provides very low pass-band ripple and optimized time domain transient response for accurate music
reproduction.
2.6 Digital PWM Modulator
The interpolation filter output is sent to the modulator. This modulator consists of a high performance 4th order digital
noise shaper and a PCM to PWM converter. Following the noise shaper, the PCM signal is fed into a very low distortion
PCM to PWM conversion block, buffered and output from the chip. The modulation scheme is based on a 2-state
control of the H-bridge output.
2.7 Control, Status, and Operational Modes
The TAS5000 control section consists of several control-input pins. Three serial mode pins (MOD0, MOD1, and
MOD2) are provided to select various serial data formats. During normal operating conditions if any of the MOD0,
MOD1, or MOD2 pins changes state, a reset sequence is initiated (see paragraph 2.7.2). Also provided are separate
power-down (PDN), reset (RESET), and mute (MUTE) pins. The ERR pin indicates that an error has occurred.
2.7.1
Power Up
At power up the ERR pin is asserted low and the PWM outputs go to the hard mute state in which the P outputs are
held low and the M outputs are held high. Following initialization, the TAS5000 will come up in the operational state.
There are two cases of power-up timing. The first case is shown in Figure 2–1 with RESET preceding PDN. The
second case is shown in Figure 2–2 with PDN preceding RESET.
RESET
PDN
Initialization Time = 4224 LRCLK Periods
ERR
Figure 2–1. Power-Up Timing (RESET preceding PDN)
2–2
Greater Than 16 MCLK Periods
RESET
PDN
Initialization Time = 256 LRCLK Periods
ERR
Figure 2–2. Power-Up Timing (PDN preceding RESET)
2.7.2
Reset
The reset signal for the TAS5000 should be applied whenever toggling the M_S, DBSPD signal. This reset is
asynchronous. See Figure 2–3 for reset timing. To initiate the reset sequence the RESET pin is asserted low. As long
as the pin is held low the chip is in the reset state. During this reset time the PWM outputs are hard-muted (P-outputs
held low and M-outputs held high) and the ERR status pin is held low. Assuming PDN is high, the rising edge of the
reset pulse begins chip initialization. After 256 LRCLK periods the TAS5000 will begin normal operation.
RESET
Initialization
Normal
Operation
ERR
Normal Operation
PDN
Figure 2–3. Reset Timing
2.7.3
Power Down
When PDN is low (see Figure 2–4. Power-Down Timing) both the PLL and the oscillator are shut down. Note that
power down is an asynchronous operation. To place the device in total power-down mode, both RESET and PDN
must be held low. As long as these pins are held low, the chip is in the power-down state and the PWM outputs are
hard muted with the P outputs held low and the M outputs held high. To place the device back into normal mode, see
section 2.7.1 for power-up timing.
NOTE: In order for the dynamic logic to be properly powered down, the clocks should not be stopped before
the PDN pin goes low. Otherwise, the device may drain additional supply current.
Normal Operation
ERR
Normal
Operation
Initialization
Chip
Power-Down
PDN and
RESET
Figure 2–4. Power-Down Timing
2.7.4
Mute
The TAS5000 provides a mute function that is used when the MUTE pin is asserted low. See Table 2–2 for Mute
Description. This mute is a quiet mute; that is, the mute is accomplished by outputting a zero value waveform in which
both sides of the differential PWM outputs have a 50% duty cycle.
2–3
Table 2–2. Mute Description
2.7.5
MUTE
PWM_P
PWM_M
DESCRIPTION
0
50% Duty cycle
50% Duty cycle
Mute
1
DATA
DATA
Normal operation
Double Speed
Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. In order to put the TAS5000 in
double-speed mode with the device in normal operating conditions, the RESET pin must be held low while switching
the DBSPD pin high. After RESET pin is brought high again, a reset sequence takes place (see paragraph 2.7.2).
If the change is at power up, a power up sequence is originated (see paragraph 2.7.1).
2.7.6
De-Emphasis Filter
For audio sources that have been pre-emphasized, a precision 50 µs/15 µs de-emphasis filter is provided to support
the sampling rates of 44.1 kHz and 48 kHz. Pins DEM_SEL and DEM_EN select the de-emphasis functions. See
Figure 2–5 for a graph showing the de-emphasis filtering characteristics. See Table 2–3 for de-emphasis selection.
Response – dB
When the DEM_EN pin or the DEM_SEL pin change state, the PWM outputs go into the quiet mute state. After 128
LRCLK periods for initialization, the PWM outputs are driven to the normal (unmuted) mode.
0
De–emphasis
–10
3.18 (50 µs)
10.6 (15 µs)
f – Frequency – kHz
Figure 2–5. De-Emphasis Filter Characteristics
2.7.6.1 De-Emphasis Selection
De-emphasis selection is accomplished by using the DEM_SEL and DEM_EN pins. See Table 2–3 for de-emphasis
selection description.
Table 2–3. De-Emphasis Selection
2.7.7
DEM_SEL
DEM_EN
DESCRIPTION
X
0
De-emphasis disabled
0
1
De-emphasis enabled for Fs = 44.1 kHz
1
1
De-emphasis enabled for Fs = 48 kHz
Error Status Reporting (ERR pin)
The following is a list of the error conditions that will cause the ERR status pin to be asserted low:
•
No clocks
•
Clock phase errors
When any of the above conditions is met, the ERR will go low and the PWM outputs will go to the hard mute state.
If the error condition is removed, the TAS5000 is reinitialized and the ERR pin will be asserted high.
2.8 Serial Interface Formats
The TAS5000 is compatible with eight different serial interfaces. Available interface options are IIS, right justified, left
justified, and DSP Frame. Table 2–4 indicates how these options are selected using the MOD0, MOD1, and MOD2
pins.
2–4
Table 2–4. Hardware Selection of Serial Audio Modes
SERIAL INTERFACE
SDIN
MODE
MOD2 PIN
MOD1 PIN
MOD0 PIN
0
0
0
0
16 bit, MSB first; right justified
1
0
0
1
20 bit, MSB first; right justified
2
0
1
0
24 bit, MSB first; right justified
3
0
1
1
16 bit IIS
4
1
0
0
20 bit IIS
5
1
0
1
24 bit IIS
6
1
1
0
16 bit MSB first, left justified
7
1
1
1
16 bit DSP frame
The following figures illustrate the relationship between the SCLK, LRCLK and the serial data I/O for the different
interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with binary 0.
2.8.1
MSB First Right Justified (for 16-, 20-, 24-bits)
SCLK
LRCLK = Fs
SDIN
X
MSB
LSB
X
Left Channel
MSB
LSB
Right Channel
Figure 2–6. MSB First Right Justified
Note the following characteristics of this protocol.
•
•
•
•
•
2.8.2
Left channel is received when LRCLK is high.
Right channel is received when LRCLK is low.
The SDIN data is justified to the trailing edge of the LRCLK
SDIN is sampled at the rising edge of SCLK.
If LRCLK phase changes by more than 10 MCLKs, then the chip automatically resets.
IIS Compatible Serial Format ( for 16-, 20-, 24-bits)
SCLK
LRCLK = Fs
SDIN
X
MSB
LSB
Left Channel
X
MSB
LSB
Right Channel
Figure 2–7. IIS Compatible Serial Format
Note the following characteristics of this protocol.
2–5
•
•
•
2.8.3
Left channel is received when LRCLK is low.
Right channel is received when LRCLK is high.
SDIN is sampled with the rising edge of SCLK.
MSB Left Justified Serial Interface Format (for 16 bits)
SCLK
LRCLK = Fs
SDIN
MSB
LSB
MSB
LSB
Left Channel
Right Channel
Figure 2–8. MSB Left Justified Serial Interface Format
Note the following characteristics of this protocol.
•
Left channel is received when LRCLK is high.
•
Right channel is received when LRCLK is low.
•
The SDIN data is justified to the leading edge of the LRCLK.
•
SDIN is sampled with the rising edge of SCLK.
2.8.4
DSP Compatible Serial Interface Format (for 16 bits)
SCLK
LRCLK = Fs
SDIN
15
14
13
0
15
Left Channel
(MSB = 15)
14
13
0
Right Channel
(MSB = 15)
Figure 2–9. DSP Compatible Serial Interface Format
Note the following characteristics of this protocol.
• Serial data is sampled with the falling edge of SCLK.
2.9 PWM Outputs
Designed to be used with TAS5100.
2–6
3 Electrical Specifications
3.1 Absolute Maximum Ratings†
Analog supply voltage range, AVDD1, AVDD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.2 V
Digital power supply voltage, DVDD1, DVDD2, DVDD3_L, DVDD3_R . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.2 V
Digital input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDDX+0.3 V
Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. DVDD1, DVDD2, DVDD3_L, DVDD3_R
3.2 Recommended Operating Conditions
(TA = 25°C; DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ±10%, AVDD1 = AVDD2 = 3.3 V ±10%, Fs = 44.1 kHz)
Voltages at analog inputs and outputs are with respect to ground
MIN
Supply voltage
Digital
Supply current
Digital
Power dissipation
Digital
Supply voltage
Analog
Supply current
Analog
Power dissipation
Analog
DVDDX‡
3
Operating
2
Operating
Operating
Power down§
Operating
Power down§
3.3
MAX
3.6
18
Power down§
Power down§
AVDDX¶
TYP
V
mA
20
59.4
3
UNIT
µA
mW
6.6
72
µW
3.3
3.6
V
8
10
mA
100
26.4
33
µA
mW
360
µW
‡ DVDD1, DVDD2, DVDD3_L, DVDD3_R
§ If the clocks are turned off
¶ AVDD1, AVDD2
3–1
3.3 Electrical Characteristics
3.3.1
Static Digital Specifications
(TA = 25°C; DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ±10%, AVDD1 = AVDD2 = 3.3 V ±10%)
VIH
VIL
High-level input voltage
VOH
VOL
High-level output voltage, (IO = –1 mA)
Low-level input voltage
MAX
2
DVDD1
V
0
0.8
V
2.4
UNIT
V
Low-level output voltage, (IO = 4 mA)
Input leakage current
3.3.2
MIN
–10
0.4
V
10
µA
Digital Interpolation Filter and PWM Modulator
(TA = 25°C; DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ±10%, AVDD1 = AVDD2 = 3.3 V ±10%, Fs = 44.1 kHz)
All the terms characterized by frequency will scale with the normal mode sampling frequency, Fs.
MIN
Pass band
TYP
0
Pass band ripple
Stop band
Stop band attenuation (24.1 kHz to 152.3 kHz)
20
UNIT
kHz
±0.012
dB
24.1
kHz
50
dB
Group delay
700
PWM modulation index (gain)
0.93
3.3.3
MAX
µS
TAS5000/TAS5100 System Performance Measured at the Speaker Terminals
Reference section 4.4 in the TAS5100 Data Manual
3.4 Switching Characteristics
3.4.1
Serial Audio Ports Slave Mode
(TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = AVDD1 = AVDD2 = 3.3 V ±10%)
PARAMETER
MIN
f(SCLK)
SCLK frequency
tsu(SDIN)
th(SDIN)
SDIN setup time before SCLK rising edge
20
SDIN hold time from SCLK rising edge
10
F(LRCLK)
LRCLK frequency
44.1
3–2
UNIT
MHz
ns
48
50%
SCLK duty cycle
50%
LRCLK edge setup before SCLK rising edge
MAX
6.144
ns
MCLK duty cycle
LRCLK duty cycle
tsu(LRCLK)
TYP
96
kHz
50%
20
ns
3.4.2
Serial Audio Ports Master Mode
Load conditions: 50pF
(TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = AVDD1 = AVDD2 = 3.3 V ±10%)
PARAMETER
t(MSD)
t(MLRD)
MIN
MCLK to SCLK
0
MLCK to LRCLK
0
SCLK, LRCLK duty cycle
3.4.3
TYP
MAX
UNIT
5
ns
5
ns
50%
DSP Serial Interface Mode
(TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = AVDD1 = AVDD2 = 3.3 V ±10%)
PARAMETER
f(SCLK)
SCLK frequency
tW(FSHIGH)
tsu(SDIN),
tsu(LRCLK)
Pulse duration, sync
th(SDIN),
th(LRCLK)
MIN
TYP
1/(64×fs)
MAX
UNIT
6.144
MHz
ns
SDIN and LRCLK setup time before SCLK falling edge
20
ns
SDIN and LRCLK hold time from SCLK falling edge
10
ns
SCLK duty cycle
50%
3–3
3–4
4 Parameter Measurement Information
SCLK
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
tsu(SDIN)
SDIN
th(SDIN)
Figure 4–1. Right Justified, IIS, Left Justified Serial Protocol Timing
SCLK
tsu(LRCLK)
LRCLK
NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns)
Figure 4–2. Right, Left, and IIS Serial Mode Timing Requirement
SCLK
LRCLK
(Output)
t(MSD)
t(MLRD)
MCLK
(Output)
Figure 4–3. Serial Audio Ports Master Mode Timing
SCLK
th(LRCLK)
tsu(LRCLK)
LRCLK
tw(FSHIGH)
tsu(SDIN)
SDIN
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
th(SDIN)
Figure 4–4. DSP Serial Port Timing
4–1
SCLK
LRCLK
tw(FSHIGH)
64 fs
16-Bit Left Channel Data
SDIN
16-Bit Left Channel Data
32-Bit Ignore
16-Bit Left Channel Data
Figure 4–5. DSP Serial Port Expanded Timing
SCLK
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
tsu(SDIN) = 20 ns
SDIN
th(SDIN) = 10 ns
NOTE: Serial data is sampled with the falling edge of SCLK (setup time = 20 ns and hold time = 10 ns)
Figure 4–6. DSP Absolute Timing Requirement
4–2
5 Application Information
PLL_FLT_RET
C2†
C1†
PWM_P_L
PWM_M_L
TAS5100
H-Bridge
R1†
PLL_FLT_OUT
ERR
RESET
DEM_SEL
Audio
Source
Clock
Generator
3.3 V DIG
DEM_EN
DBSPD
SDIN
PWM_P_R
PWM_M_R
TAS5100
H-Bridge
LRCLK
SCLK
MCLK_IN
MOD0
MicroController
MOD1
MOD2
M_S
MUTE
PDN
XTL_IN
† See application note for values
Figure 5–1. Connection Diagram, Slave Mode (typical)
5–1
5–2