LINER LTC2611

LTC2601/LTC2611/LTC2621
16-/14-/12-Bit Rail-to-Rail
DACs in 10-Lead DFN
U
DESCRIPTIO
FEATURES
The LTC®2601/LTC2611/LTC2621 are single 16-, 14and 12-bit, 2.5V-to-5.5V rail-to-rail voltage output DACs
in a 10-lead DFN package. They have built-in high performance output buffers and are guaranteed monotonic.
Smallest Pin-Compatible Single DACs:
LTC2601: 16 Bits
LTC2611: 14 Bits
LTC2621: 12 Bits
Guaranteed Monotonic Over Temperature
Wide 2.5V to 5.5V Supply Range
Low Power Operation: 300µA at 3V
Power Down to 1µA, Max
High Rail-to-Rail Output Drive (±15mA, Min)
Double-Buffered Data Latches
Asynchronous DAC Update Pin
Tiny (3mm × 3mm) 10-Lead DFN Package
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These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive, and load regulation in single-supply,
voltage-output multiples.
The parts use a simple SPI/MICROWIRETM compatible
3-wire serial interface which can be operated at clock rates
up to 50MHz. Daisy-chain capability, hardware CLR and
asynchronous DAC update (LDAC) pins are included.
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APPLICATIO S
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The LTC2601/LTC2611/LTC2621 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
less than 10mV above zero scale; and after power-up, they
stay at zero scale until a valid write and update take place.
Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
U.S. patent number 5396245.
W
BLOCK DIAGRA
2
SDI
6
9
REF
VCC
Differential Nonlinearity (LTC2601)
1.0
3
VCC = 5V
VREF = 4.096V
0.8
SCK
0.6
5
1
INPUT
REGISTER
DAC
REGISTER
12-/14-/16-BIT DAC
VOUT
7
DNL (LSB)
0.4
32-BIT
SHIFT
REGISTER
0.2
0
–0.2
–0.4
CS/LD
–0.6
CONTROL
DECODE
LOGIC
–0.8
–1.0
SDO
LDAC
10
CLR
4
GND
8
2601 BD
0
16384
32768
CODE
49152
65535
2600 G02
2601f
1
LTC2601/LTC2611/LTC2621
W
U
U
W W
W
AXI U
U
ABSOLUTE
PACKAGE/ORDER I FOR ATIO
RATI GS
(Note 1)
Any Pin to GND ........................................... – 0.3V to 6V
Any Pin to VCC .............................................– 6V to 0.3V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LTC2601C/LTC2611C/LTC2621C .......... 0°C to 70°C
LTC2601I/LTC2611I/LTC2621I .......... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 125°C
Lead Temperature (Soldering, 10 sec)................ 300°C
ORDER PART
NUMBER
LTC2601CDD
LTC2601IDD
LTC2611CDD
LTC2611IDD
LTC2621CDD
LTC2621IDD
TOP VIEW
10 LDAC
SDO
1
SDI
2
SCK
3
CLR
4
7 VOUT
CS/LD
5
6 REF
9 VCC
11
8 GND
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
DD PART MARKING
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
LAGT
LBFQ
LBFS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC2621
TYP MAX
MIN
LTC2611
TYP MAX
MIN
LTC2601
TYP MAX
UNITS
DC Performance
Resolution
●
12
14
16
Bits
(Note 2)
●
12
14
16
Bits
Differential Nonlinearity (Note 2)
●
Integral Nonlinearity
(Note 2)
●
±0.8
Load Regulation
VREF = VCC = 5V, Midscale
IOUT = 0mA to 15mA Sourcing
IOUT = 0mA to 15mA Sinking
●
●
VREF = VCC = 2.5V, Midscale
IOUT = 0mA to 7.5mA Sourcing
IOUT = 0mA to 7.5mA Sinking
●
●
Monotonicity
DNL
INL
±0.5
±4
±1
±1
LSB
LSB
±3
±16
±13
±64
0.03 0.125
0.04 0.125
0.10
0.15
0.5
0.5
0.45
0.60
2
2
LSB/mA
LSB/mA
0.06
0.08
0.2
0.3
1
1
0.9
1.2
4
4
LSB/mA
LSB/mA
0.25
0.25
ZSE
Zero-Scale Error
Code = 0
●
1
9
1
9
1
9
mV
VOS
Offset Error
(Note 5)
●
±1.5
±9
±1.5
±9
±1.5
±9
mV
±5
VOS Temperature
Coefficient
GE
Gain Error
Gain Temperature
Coefficient
●
±0.03 ±0.7
±2
±5
±0.1
±2
±5
±0.7
±0.05 ±0.7
±2
µV/°C
%FSR
ppm/°C
2601f
2
LTC2601/LTC2611/LTC2621
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
PSR
Power Supply Rejection
VCC = 5V ±10%
VCC = 3V ±10%
LTC2601/LTC2611/LTC2621
MIN
TYP
MAX
UNITS
●
–80
–80
dB
dB
0.04
0.05
0.15
0.15
Ω
Ω
ROUT
DC Output Impedance
VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA
●
VREF = VCC = 2.5V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA ●
ISC
Short-Circuit Output Current
VCC = 5.5V, VREF = 5.5V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
●
●
15
15
35
39
60
60
mA
mA
VCC = 2.5V, VREF = 2.5V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
●
●
7.5
7.5
20
27
50
50
mA
mA
VCC
V
124
160
kΩ
Reference Input
Input Voltage Range
Resistance
Normal Mode
●
0
●
88
Capacitance
IREF
15
Reference Current, Power Down Mode DAC Powered Down
0.001
●
pF
1
µA
5.5
V
0.55
0.45
1
1
mA
mA
µA
µA
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
●
2.5
ICC
Supply Current
VCC = 5V (Note 3)
VCC = 3V (Note 3)
DAC Powered Down (Note 3) VCC = 5V
DAC Powered Down (Note 3) VCC = 3V
●
●
●
●
VIH
Digital Input High Voltage
VCC = 2.5V to 5.5V
VCC = 2.5V to 3.6V
●
●
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
●
●
VOH
Digital Output High Voltage
Load Current = –100µA
●
VOL
Digital Output Low Voltage
Load Current = +100µA
●
0.4
V
ILK
Digital Input Leakage
VIN = GND to VCC
●
±1
µA
CIN
Digital Input Capacitance
(Note 4)
●
8
pF
0.375
0.30
0.40
0.10
Digital I/O
2.4
2.0
V
V
0.8
0.6
VCC – 0.4
V
V
V
2601f
3
LTC2601/LTC2611/LTC2621
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded,
unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
LTC2621
TYP MAX
MIN
LTC2611
TYP MAX
MIN
LTC2601
TYP MAX
UNITS
AC Performance
tS
Settling Time (Note 6)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7
9
7
9
10
µs
µs
µs
Settling Time for 1LSB Step
(Note 7)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7
2.7
4.8
2.7
4.8
5.2
µs
µs
µs
Voltage Output Slew Rate
0.80
0.80
0.80
V/µs
Capacitive Load Driving
1000
1000
1000
pF
Glitch Impulse
At Midscale Transition
Multiplying Bandwidth
en
12
12
12
nV • s
180
180
180
kHz
Output Voltage Noise Density
At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
µVP-P
WU
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 4)
SYMBOL PARAMETER
VCC = 2.5V to 5.5V
t1
SDI Valid to SCK Setup
t2
SDI Valid to SCK Hold
t3
SCK High Time
t4
SCK Low Time
t5
CS/LD Pulse Width
t6
LSB SCK High to CS/LD High
t7
CS/LD Low to SCK High
t8
SDO Propagation Delay from SCK Falling Edge
t9
t10
t12
t13
CLR Pulse Width
CS/LD High to SCK Positive Edge
LDAC Pulse Width
CS/LD High to LDAC High or Low Transition
SCK Frequency
LTC2601/LTC2611/LTC2621
MIN
TYP
MAX
CONDITIONS
●
●
●
●
●
●
●
CLOAD = 10pF
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
●
●
●
50% Duty Cycle
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: Digital inputs at 0V or VCC.
Note 4: Guaranteed by design and not production tested.
4
4
9
9
10
7
7
●
ns
ns
ns
ns
ns
ns
ns
20
45
●
●
●
UNITS
20
7
15
200
50
ns
ns
ns
ns
ns
ns
MHz
Note 5: Inferred from measurement at code KL = 0.016(2N/VREF) and at
full scale.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
2601f
4
LTC2601/LTC2611/LTC2621
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2601
Integral Nonlinearity (INL)
32
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VREF = 4.096V
24
INL vs Temperature
32
VCC = 5V
VREF = 4.096V
0.8
VCC = 5V
VREF = 4.096V
24
0.6
16
0.4
0
–8
0.2
INL (LSB)
8
DNL (LSB)
INL (LSB)
16
0
–0.2
INL (POS)
8
0
–8
INL (NEG)
–0.4
–16
–0.6
–24
–32
–16
–24
–0.8
16384
0
32768
CODE
49152
–1.0
65535
0
16384
32768
CODE
49152
–10 10
30
50
TEMPERATURE (°C)
70
32
VCC = 5V
VREF = 4.096V
90
2601 G03
INL vs VREF
DNL vs Temperature
0.8
–30
2600 G02
2601 G01
1.0
–32
–50
65535
DNL vs VREF
1.5
VCC = 5.5V
24
VCC = 5.5V
1.0
0.6
16
0
–0.2
0
–8
DNL (NEG)
0.5
INL (POS)
8
DNL (LSB)
DNL (POS)
0.2
INL (LSB)
DNL (LSB)
0.4
INL (NEG)
DNL (POS)
0
DNL (NEG)
–0.5
–0.4
–16
–0.6
–1.0
–50
–1.0
–24
–0.8
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
–32
0
1
2601 G04
2
3
VREF (V)
4
5
–1.5
0
1
2
3
VREF (V)
2601 G05
Settling to ±1LSB
4
5
2601 G06
Settling of Full-Scale Step
VOUT
100µV/DIV
VOUT
100µV/DIV
9.7µs
CS/LD
2V/DIV
12.3µs
CS/LD
2V/DIV
2µs/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
2601 G07
5µs/DIV
2601 G08
SETTLING TO ±1LSB
VCC = 5V, VREF = 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
2601f
5
LTC2601/LTC2611/LTC2621
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2611
Integral Nonlinearity (INL)
8
1.0
VCC = 5V
VREF = 4.096V
6
Settling to ±1LSB
Differential Nonlinearity (DNL)
VCC = 5V
VREF = 4.096V
0.8
0.6
4
0.4
DNL (LSB)
INL (LSB)
2
0
–2
VOUT
100µV/DIV
0.2
0
CS/LD
2V/DIV
–0.2
–0.4
8.9µs
–4
–0.6
–6
–8
4096
0
8192
CODE
12288
–1.0
16383
2601 G11
2µs/DIV
–0.8
0
4096
8192
CODE
12288
2601 G09
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
16383
2601 G10
LTC2621
Integral Nonlinearity (INL)
2.0
1.0
VCC = 5V
VREF = 4.096V
1.5
Settling to ±1LSB
Differential Nonlinearity (DNL)
VCC = 5V
VREF = 4.096V
0.8
0.6
1.0
6.8µs
DNL (LSB)
INL (LSB)
0.4
0.5
0
–0.5
VOUT
1mV/DIV
0.2
0
CS/LD
2V/DIV
–0.2
–0.4
–1.0
–0.6
–1.5
–2.0
0
1024
2048
CODE
3072
–1.0
4095
2601 G14
2µs/DIV
–0.8
0
1024
2048
CODE
3072
2601 G12
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
4095
2601 G13
LTC2601/LTC2611/LTC2621
Current Limiting
0.06
∆VOUT (V)
0.04
CODE = MIDSCALE
VREF = VCC = 5V
–0.06
0.4
VREF = VCC = 3V
0.2
0
–0.2
VREF = VCC = 5V
–0.4
VREF = VCC = 5V
VREF = VCC = 3V
–0.6
20
30
40
2601 G17
–1.0
–35
1
0
–1
–2
–0.8
–0.08
–0.10
10
–40 –30 –20 –10 0
IOUT (mA)
2
0.6
VREF = VCC = 3V
0
–0.04
CODE = MIDSCALE
0.8
0.02
–0.02
Offset Error vs Temperature
3
OFFSET ERROR (mV)
0.08
Load Regulation
1.0
∆VOUT (mV)
0.10
–25
–15
–5
5
IOUT (mA)
15
25
35
2601 G18
–3
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
2601 G19
2601f
6
LTC2601/LTC2611/LTC2621
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2601/LTC2611/LTC2621
Zero-Scale Error vs Temperature
Gain Error vs Temperature
0.4
3
3
0.3
2.0
1.5
1.0
2
0.2
OFFSET ERROR (mV)
GAIN ERROR (%FSR)
2.5
ZERO-SCALE ERROR (mV)
Offset Error vs VCC
0.1
0
–0.1
0
–1
–0.2
0.5
–2
–0.3
0
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
–0.4
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
–3
90
2.5
3.5
3
4
VCC (V)
4.5
5
2601 G21
2601 G20
Gain Error vs VCC
5.5
2601 G22
ICC Shutdown vs VCC
0.4
Large-Signal Response
450
0.3
400
0.2
350
0.1
300
ICC (nA)
GAIN ERROR (%FSR)
1
0
–0.1
VOUT
0.5V/DIV
250
200
VREF = VCC = 5V
1/4-SCALE TO 3/4-SCALE
150
–0.2
100
–0.3
2.5µs/DIV
50
–0.4
2.5
3
3.5
4
VCC (V)
4.5
5
5.5
0
2.5
3
3.5
4
VCC (V)
4.5
5
2601 G23
2601 G25
5.5
2601 G24
Headroom at Rails
vs Output Current
Power-On Reset Glitch
Midscale Glitch Impulse
5.0
5V SOURCING
4.5
4.0
VOUT
10mV/DIV
3.5
VOUT (V)
VCC
1V/DIV
12nV-s TYP
4mV PEAK
CS/LD
5V/DIV
VOUT
10mV/DIV
2.5µs/DIV
2601 G26
3V SOURCING
3.0
2.5
2.0
1.5
5V SINKING
1.0
250µs/DIV
3V SINKING
2601 G27
0.5
0
0
1
2
3
4 5 6
IOUT (mA)
7
8
9
10
2601 G28
2601f
7
LTC2601/LTC2611/LTC2621
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2601/LTC2611/LTC2621
Supply Current vs Logic Voltage
2.4
Hardware CLR
VCC = 5V
SWEEP SCK, SDI
AND CS/LD
0V TO VCC
2.3
2.2
VOUT
1V/DIV
ICC (mA)
2.1
2.0
1.9
CLR
5V/DIV
1.8
1.7
1.5
2601 G31
1µs/DIV
1.6
0.5
0
1
1.5 2 2.5 3 3.5
LOGIC VOLTAGE (V)
4
4.5
5
2601 G29
Output Voltage Noise,
0.1Hz to 10Hz
Multiplying Bandwidth
0
–3
–6
–9
–12
VOUT
10µV/DIV
dB
–15
–18
–21
–24
–27
–30
–33
–36
VCC = 5V
VREF (DC) = 2V
VREF (AC) = 0.2VP-P
CODE = FULL SCALE
1k
0
1
2
3
4 5 6
SECONDS
8
9
10
2601 G33
1M
10k
100k
FREQUENCY (Hz)
7
2601 G32
Short-Circuit Output Current vs
VOUT (Sourcing)
Short-Circuit Output Current vs
VOUT (Sinking)
10mA/DIV
10mA/DIV
0mA
0mA
VCC = 5.5V
VREF = 5.6V
CODE = 0
VOUT SWEPT 0V TO VCC
1V/DIV
VCC = 5.5V
VREF = 5.6V
CODE = FULL SCALE
VOUT SWEPT VCC TO 0V
2601 G18
1V/DIV
2600 G19
2601f
8
LTC2601/LTC2611/LTC2621
U
U
U
PIN FUNCTIONS
SDO (Pin 1): Serial Interface Data Output. The serial
output of the shift register appears at the SDO pin. The data
transferred to the device via the SDI pin is delayed 32 SCK
rising edges before being output at the next falling edge.
This pin is used for daisy-chain operation.
SDI (Pin 2): Serial Interface Data Input. Data is applied to
SDI for transfer to the device at the rising edge of SCK
(Pin␣ 3). The LTC2601 accepts input word lengths of either
24 or 32 bits.
SCK (Pin 3): Serial Interface Clock Input. CMOS and TTL
compatible.
CLR (Pin 4): Asynchronous Clear Input. A logic low at this
level-triggered input clears all registers and causes the
DAC voltage outputs to drop to 0V. CMOS and TTL
compatible.
CS/LD (Pin 5): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on SDI
into the register. When CS/LD is taken high, SCK is
disabled and the specified command (see Table 1) is
executed.
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT (Pin 7): DAC Analog Voltage Output. The output
range is 0V to VREF.
GND (Pin 8): Analog Ground.
VCC (Pin 9): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V.
LDAC (Pin 10): Asynchronous DAC Update Pin. If CS/LD
is high, a falling edge on LDAC immediately updates the
DAC register with the contents of the input register (similar to a software update). If CS/LD is low when LDAC goes
low, the DAC register is updated after CS/LD returns high.
A low on the LDAC pin powers up the DAC. A software
power down command is ignored if LDAC is low.
Exposed Pad (Pin 11): Ground. Must be soldered to PCB
ground.
2601f
9
LTC2601/LTC2611/LTC2621
W
BLOCK DIAGRA
2
3
SDI
1
9
VCC
SCK
32-BIT
SHIFT
REGISTER
5
6
REF
INPUT
REGISTER
DAC
REGISTER
12-/14-/16-BIT DAC
VOUT
7
CS/LD
CONTROL
DECODE
LOGIC
SDO
LDAC
CLR
4
10
GND
8
2601 BD
W
UW
TI I G DIAGRA S
t1
t2
SCK
t3
1
t6
t4
2
3
23
24
t10
SDI
t5
t7
CS/LD
t8
SDO
t13
t12
LDAC
2601 F01a
Figure 1a
CS/LD
t13
LDAC
2601 F01b
Figure 1b
2601f
10
LTC2601/LTC2611/LTC2621
U
OPERATIO
Power-On Reset
The LTC2601/LTC2611/LTC2621 clear the outputs to zero
scale when power is first applied, making system initialization consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2601/
LTC2611/LTC2621 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
Transfer Function
The digital-to-analog transfer function is:
 k
VOUT(IDEAL) =  N  VREF
2 
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and VREF is the voltage at REF
(Pin 6).
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then 4 don’t
care bits; and finally the 16-bit data word. The data word
comprises the 16-, 14- or 12-bit input code, ordered MSBto-LSB, followed by 0, 2 or 4 don’t care bits (LTC2601,
LTC2611 and LTC2621 respectively). Data can only be
transferred to the device when the CS/LD signal is low.The
rising edge of CS/LD ends the data transfer and causes the
device to execute the command specified in the 24-bit
input word. The complete sequence is shown in Figure 2a.
The command (C3-C0) assignments are shown in Table 1.
The first four commands in the table consist of write and
update operations. A write operation loads a 16-bit data
word from the 32-bit shift register into the input register
of the DAC. In an update operation, the data word is copied
from the input register to the DAC register and converted
to an analog voltage at the DAC output. The update
operation also powers up the DAC if it had been in powerdown mode. The data path and registers are shown in the
Block Diagram.
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b
shows the 32-bit sequence. The 32-bit word is required for
daisy-chain operation, and is also available to accommodate microprocessors which have a minimum word width
of 16 bits (2 bytes).
Daisy-Chain Operation
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge.
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a “daisy chain” series is configured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire chain.
Table 1.
COMMAND*
C3 C2 C1 C0
0
0
0
0
Write to Input Register
0
0
0
1
Update (Power Up) DAC Register
0
0
1
1
Write to and Update (Power Up)
0
1
0
0
Power Down
1
1
1
1
No Operation
*Command codes not shown are reserved and should not be used.
2601f
11
LTC2601/LTC2611/LTC2621
U
OPERATIO
INPUT WORD (LTC2601)
COMMAND
C3
C2
C1 C0
DON’T CARE BITS
X
X
X
X
DATA (16 BITS)
D15 D14 D13 D12 D11 D10 D9
D8 D7 D6 D5
D4
D3
D2
D1 D0
MSB
LSB
2601 TBL01
INPUT WORD (LTC2611)
COMMAND
C3
C2
C1 C0
DON’T CARE BITS
X
X
X
X
DATA (14 BITS + 2 DON’T CARE BITS)
D13 D12 D11 D10 D9
D8 D7 D6 D5
D4
D3
D2
D1 D0
MSB
X
X
LSB
2601 TBL02
INPUT WORD (LTC2621)
COMMAND
C3
C2
C1 C0
DON’T CARE BITS
X
X
X
X
DATA (12 BITS + 4 DON’T CARE BITS)
D11 D10 D9
D8 D7 D6 D5
MSB
D4
D3
D2
D1 D0
X
X
X
X
LSB
2601 TBL03
Because of this, the devices can be addressed and controlled individually by simply concatenating their input
words; the first instruction addresses the last device in the
chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
REF rises accordingly becoming a high impedance input
(typically > 1GΩ).
In use, CS/LD is first taken low. Then the concatenated
input data is transferred to the chain, using SDI of the first
device as the data input. When the data transfer is complete, CS/LD is taken high, which executes the commands
specified for each of the devices simultaneously. A single
device can be controlled by using the no-operation command (1111) for the other devices in the chain.
Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1
or performing an asynchronous update (LDAC) as described in the next section. The DAC is powered up as its
voltage output is updated. When the DAC in powereddown state is powered up and updated, normal settling is
delayed. The main bias generation circuit block has been
automatically shut down in addition to the DAC amplifier
and reference input and so the power up delay time is 12µs
(for VCC = 5V) or 30µs (for VCC = 3V).
Power-Down Mode
Asynchronous DAC Update Using LDAC
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DAC output is not needed. When in power-down, the
buffer amplifier, bias circuit and reference input is disabled and draws essentially zero current. The DAC output
is put into a high impedance state, and the output pin is
passively pulled to ground through 90k resistors. Inputand DAC-register contents are not disturbed during powerdown.
In addition to the update commands shown in Table 1, the
LDAC pin asynchronously updates the DAC register with
the contents of the input register.
The DAC can be put into power-down mode by using
command 0100b. The 16-bit data word is ignored. The
supply and reference currents are reduced to almost zero
when the DAC is powered down; the effective resistance at
If CS/LD is high, a low on the LDAC pin causes the DAC
register to be updated with the contents of the input
register.
If CS/LD is low, a low going pulse on the LDAC pin before
the rising edge of CS/LD powers up the DAC but does not
cause the output to be updated. If LDAC remains low after
the rising edge of CS/LD, then LDAC is recognized, the
command specified in the 24-bit word just transferred is
executed and the DAC output is updated.
2601f
12
LTC2601/LTC2611/LTC2621
U
OPERATIO
The DAC is powered up when LDAC is taken low, independent of the state of CS/LD.
careful thought should be given to the grounding scheme
and board layout in order to ensure rated performance.
If LDAC is low at the time CS/LD goes high, it inhibits any
software power-down command that was specified in the
input word.
The PC board should have separate areas for the analog and
digital sections of the circuit. This keeps digital signals away
from sensitive analog signals and facilitates the use of
separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each other.
Voltage Outputs
The rail-to-rail amplifier contained in these parts has
guaranteed load regulation when sourcing or sinking up to
15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifier’s DC output
impedance is 0.05Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
25Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25Ω • 1mA = 25mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics section.
The amplifier is stable driving capacitive loads of up to
1000pF.
Board Layout
The excellent load regulation of these devices is achieved
in part by keeping “signal” and “power” grounds separated internally and by reducing shared internal resistance.
The GND pin functions both as the node to which the
reference and output voltages are referred and as a return
path for power currents in the device. Because of this,
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star ground
should be as low as possible. Resistance here will add
directly to the effective DC output impedance of the device
(typically 0.05Ω). Note that the LTC2601/LTC2611/
LTC2621 are no more susceptible to these effects than other
parts of their type; on the contrary, they allow layout-based
performance improvements to shine rather than limiting
attainable performance with excessive internal resistance.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur near full scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 3c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
2601f
13
14
X
X
SDI
SDO
SCK
CS/LD
1
X
X
2
X
X
3
4
X
5
X
X
DON’T CARE
X
C3
SDI
C2
2
C1
3
X
X
6
X
X
7
C0
X
6
X
7
4 DON’T CARE BITS
X
5
X
8
D15
9
D14
10
D12
12
D11
13
D10
14
24-BIT INPUT WORD
D13
11
D9
15
D7
17
DATA WORD
D8
16
D6
18
C3
C3
C2
10
C1
11
C2
C1
COMMAND WORD
9
C0
C0
X
14
X
15
X
X
X
4 DON’T CARE BITS
X
13
X
X
16
17
D15
D15
PREVIOUS 32-BIT INPUT WORD
12
D14
D14
18
SDO
SDI
SCK
D13
D13
19
D12
D12
20
t3
17
D10
D10
22
t2
t8
D9
D9
t4
18
D7
PREVIOUS D14
D14
D8
DATA WORD
D6
D5
D4
29
D3
D3
24
D0
28
D4
23
D1
27
D5
22
D2
26
D6
21
D3
25
D7
20
D4
24
D8
19
D5
23
PREVIOUS D15
D15
t1
D11
D11
21
Figure 2a. LTC2601 24-Bit Load Sequence (Minimum Input Word).
LTC2611 SDI Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;
LTC2621 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits
4
Figure 2b. LTC2601 32-Bit Load Sequence (Required for Daisy-Chain Operation).
LTC2611 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;
LTC2621 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t-Care Bits
X
X
8
COMMAND WORD
1
SCK
CS/LD
D2
D2
30
2601 F02a
D1
D1
31
2601 F02b
CURRENT
32-BIT
INPUT WORD
D0
D0
32
LTC2601/LTC2611/LTC2621
U
OPERATIO
2601f
LTC2601/LTC2611/LTC2621
U
OPERATIO
POSITIVE
FSE
VREF = VCC
VREF = VCC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0
0V
NEGATIVE
OFFSET
32, 768
INPUT CODE
(a)
2601 F03
65, 535
INPUT CODE
(b)
Figure 3. Effects of Rail-to-Rail Operation On the DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 ± 0.10
10
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
0.25 ± 0.05
0.200 REF
0.50
BSC
2.38 ±0.05
(2 SIDES)
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
2601f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC2601/LTC2611/LTC2621
U
TYPICAL APPLICATIO
Demo Circuit DC777 Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters
5V
5V
VREF
1V TO 5V
0.1µF
10
4
2
3
5
1
9
6
LDAC VCC VREF
CLR
SDI
LTC2601 VOUT
SCK
CS/LD
SDO GND
SPI
BUS
8
0.1µF
2
FSSET
7
100Ω
7.5k
3
VIN
1
VCC
LTC2421
100pF
DAC
OUTPUT
9
SCK
8
SDO
7
CS
10
FO
ZSSET GND
5
6
2601 TA01
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1654
Dual 14-Bit Rail-to-Rail VOUT DAC
Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA
LTC1655/LTC1655L
Single 16-Bit VOUT DACs with Serial Interface in SO-8
VCC = 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L
Parrallel 5V/3V 16-Bit VOUT DACs
Low Power, Deglitched, Rail-to-Rail VOUT
LTC1660/LTC1665
Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1661
Dual 10-Bit VOUT DAC 8-Lead MSOP
Micropower Rail-to-Rail Output, 3-Wire Interface
LTC1662
Dual 10-Bit VOUT DAC 8-Lead MSOP
Ultralow Power, Rail-to-Rail Output
LTC1663
Single 10-Bit VOUT DAC in SOT-23
SMBus Interface, Pin-for-Pin Compatible with LTC1669
LTC1664
Quad 10-Bit VOUT DAC 16-Lead SSOP
Micropower Rail-to-Rail Output, 3-Wire Interface
LTC1669
Single 10-Bit VOUT DAC 5-Lead SOT-23
Pin-for-Pin Compatible with LTC1663
LTC1821
Parallel 16-Bit Voltage Output DAC
Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610
LTC2620
Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output
LTC2602/LTC2612
LTC2622
Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP
300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output
LTC2604/LTC2614
LTC2624
Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output
2601f
16 Linear Technology Corporation
LT/TP 0404 1K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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 LINEAR TECHNOLOGY CORPORATION 2004