a FEATURES Current Conditioning Complete Vector Transformation on Silicon Three-Phase 120° and Orthogonal 90° Signal Transformation Three-Phase Balance Diagnostic–Homopolar Output DQ Manipulation Real-Time Filtering APPLICATIONS AC Induction Motor Control Spindle Drive Control Pump Drive Control Compressor Drive Control and Diagnostics Harmonic Measurement Frequency Analysis Three-Phase Power Measurement GENERAL DESCRIPTION The AD2S105 performs the vector rotation of three-phase 120 degree or two-phase 90 degree sine and cosine signals by transferring these inputs into a new reference frame which is controlled by the digital input angle φ. Two transforms are included in the AD2S105. The first is the Clarke transform which computes the sine and cosine orthogonal components of a three-phase input. These signals represent real and imaginary components which then form the input to the Park transform. The Park transform relates the angle of the input signals to a reference frame controlled by the digital input port. The digital input port on the AD2S105 is a 12-bit/parallel natural binary port. If the input signals are represented by Vds and Vqs, respectively, where Vds and Vqs are the real and imaginary components, then the transformation can be described as follows: Vds' = Vds Cosφ – Vqs Sinφ Vqs' = Vds Sinφ + Vqs Cosφ Where Vds' and Vqs' are the output of the Park transform and Sinφ, and Cosφ are the trigonometric values internally calculated by the AD2S105 from the binary digital data φ. The input section of the device can be configured to accept either three-phase inputs, two-phase inputs of a three-phase system, or two 90 degree input signals. The homopolar output indicates an imbalance of a three-phase input only at a userspecified level. The digital input section will accept a resolution of up to 12 bits. An input data strobe signal is required to synchronize the position data and load this information into the device counters. Three-Phase Current Conditioner AD2S105 FUNCTIONAL BLOCK DIAGRAM INPUT DATA STROBE Cos θ Sinθ Cos θ Cos ( θ + 120 °) Cos ( θ + 240 °) Sinθ CONV1 CONV2 IS1 SECTOR MULTIPLIER SINE AND COSINE MULTIPLIER SECTOR MULTIPLIER SINE AND COSINE MULTIPLIER Vds IS2 φ POSITION PARALLEL DATA 12 BITS BUSY Cos θ + φ Vds' 3φ-2 φ IS3 Vqs DECODE Vqs' Sin θ + φ Ia + Ib + Ic 3 HOMOPOLAR OUTPUT HOMOPOLAR REFERENCE +5V GND –5V A two-phase rotated output facilitates the implementation of multiple rotation blocks. The AD2S105 is fabricated on LC2MOS and operates on ± 5 volt power supplies. PRODUCT HIGHLIGHTS Current Conditioning The AD2S105 transforms the analog stator current signals (Is1, Is2, Is3) using the digital angular signal (reference frame) into dc values which represent direct current (Ids) and quadrature current (Iqs). This transformation of the ac signals into dc values simplifies the design of the analog-to-digital (A/D) conversion scheme. The A/D conversion scheme is simplified as the bandwidth sampling issues inherent in ac signal processing are avoided and in most drive designs, simultaneous sampling of the stator currents may not be necessary. Hardware Peripheral for Standard Microcontroller and DSP Systems The AD2S105 off-loads the time consuming Cartesian transformations from digital processors and benchmarks show a significant speed improvement over single processor designs. AD2S105 transformation time = 2 µs. Field Oriented Control of AC Motors The AD2S105 accommodates all the necessary functions to provide a hardware solution for current conditioning in variable speed control of ac synchronous and asynchronous motors. Three-Phase Imbalance Detection The AD2S105 can be used to sense imbalances in a three-phase system via the homopolar output. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 (VDD = +5 V ± 5%; VSS = –5 V ± 5% AGND = DGND = O V; AD2S105–SPECIFICATIONS T = –40°C to +85°C, unless otherwise noted) A Parameter SIGNAL INPUTS PH/IP1, 2, 3, 4 Voltage Level PH/IPH1, 2, 3 Voltage Level Input Impedance PH/IP1, 2, 3 PH/IPH1, 2, 3 PH/IP1, 4 Gain PH/IP1, 2, 3, 4 PH/IPH1, 2, 3 Min 7.5 13.5 0.95 VECTOR PERFORMANCE 3-Phase Input-Output Radius Error (Any Phase) Angular Error1, 2 PH/IP PH/IPH Differential Nonlinearity Full Power Bandwidth Small Signal Bandwidth STROBE Write Max Update Rate BUSY Pulse Width VOH VOL DIGITAL INPUTS DB1–DB12 VIH VIL Input Current, IIN Input Capacitance, CIN CONV MODE (CONV1, CONV2) VIH VIL Input Current Input Capacitance Max Units Conditions ± 2.8 ± 3.3 ± 4.25 V p-p V p-p DC to 50 kHz DC to 50 kHz 10 18 1 kΩ kΩ MΩ 1.05 ± 0.4 ±1 % DC to 600 Hz 15 30 30 ±1 arc min arc min LSB kHz kHz DC to 600 Hz DC to 600 Hz ± 3.3 10 V p-p mV V/µs µs ± 2.8 2 2 1 3.0 2 Mode 1 Only (2 Phase) Sin & Cos 1 0.56 50 200 ANALOG SIGNAL OUTPUTS PH/OP1, 4 Output Voltage3 Offset Voltage Slew Rate Small Signal Step Response Output Impedance Output Drive Current Resistive Load Capacitive Load Typ PH/IP, PH/IPH INPUTS DC to 50 kHz Inputs = 0 V 1° Input to Settle to ± 1 LSB (Input to Output) 50 Ω mA kΩ pF ns kHz Positive Pulse 366 µs V dc V dc Conversion in Process IOH = 0.5 mA IOL = 0.5 mA 15 4.0 100 1.7 2.5 4 1 3.5 1.5 ± 10 V dc V dc µA pF 1.5 100 V dc V dc µA pF 10 3.5 10 –2– Outputs to AGND Internal 50 kΩ Pull-Up Resistor REV. 0 AD2S105 Parameter Min HOMOPOLAR OUTPUT HPOP–OUTPUT VOH VOL HPREF–REFERENCE 4 POWER SUPPLY VDD VSS IDD ISS Typ Max Units Conditions 1 V dc V dc V dc IOH = 0.5 mA IOL = 0.5 mA Homopolar Output-Internal ISOURCE = 25 µA and 20 kΩ to AGND 5.25 –4.75 10 10 V dc V dc mA mA 0.5 4.75 –5.25 5 –5 4 4 Quiescent Current Quiescent Current NOTES 1 Angular accuracy includes offset and gain errors, measured with a stationary digital input and maximum analog frequency inputs. 2 The angular error does not include the additional error caused by the phase delay as a function of input frequency. For example, if f INPUT = 600 Hz, the contribution to the error due to phase delay is: 650 ns × fINPUT × 60 × 360 = 8.4 arc minutes. 3 Output subject to input voltage and gain. Specifications subject to change without notice. RECOMMENDED OPERATING CONDITIONS ORDERING GUIDE Power Supply Voltage (+VDD, –VSS) . . . . . . . . . ± 5 V dc ± 5% Analog Input Voltage (PH/IP1, 2, 3, 4) . . . . . . 2 V rms ± 10% Analog Input Voltage (PH/IPH1, 2, 3) . . . . . . 3 V rms ± 10% Ambient Operating Temperature Range Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Model AD2S105AP Temperature Range –40°C to +85°C Accuracy Option* 30 arc min P-44A *P = Plastic Leaded Chip Carrier. ABSOLUTE MAXIMUM RATINGS (TA = +25°C) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V dc VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V dc AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V dc Analog Input Voltage to AGND . . . . . . . . . . . . . . . VSS to VDD Digital Input Voltage to DGND . . . . –0.3 V to VDD + 0.3 V dc Digital Output Voltage to DGND . . . . . . –0.3 V to VDD + V dc Analog Output Voltage to AGND . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V dc Analog Output Load Condition (PH/OP1, 4 Sinθ, Cosθ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kΩ Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mW Operating Temperature Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C CAUTION 1. Absolute Maximum Ratings are those values beyond which damage to the device will occur. 2. Correct polarity voltages must be maintained on the +VDD and –VSS pins CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD2S105 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD2S105 PIN DESIGNATIONS1, 2, 3 41 42 44 VDD DGND BUSY STROBE NC NC BUSY NC DGND VDD NC 42 41 40 7 39 NC 8 38 DB1 NC 9 37 DB2 AGND 10 36 DB3 PH/IP4 11 AD2S105 35 DB4 PH/IPH3 12 TOP VIEW (NOT TO SCALE) 34 DB5 PH/IP3 13 33 DB6 PH/IPH2 14 32 DB7 PH/IP2 15 31 DB8 PH/IPH1 16 30 DB9 PH/IP1 17 29 DB10 18 19 20 21 22 23 24 25 26 27 28 DB11 COS SIN DB12 to DB1 43 DB12 25 26 27–38 44 SIN CONV2 1 COS 24 2 CONV2 PH/IP2 PH/IPH1 PH/IP1 VSS HPREF HPOP HPFILT CONV1 3 CONV1 15 16 17 19 20 21 22 23 4 HPFILT PH/IP3 PH/IPH2 NC 5 HPOP 13 14 PH/OP1 6 HPREF Begin Conversion Positive Power Supply Negative Power Supply Sin (θ + φ) Cos (θ + φ) Analog Ground Sin θ Input High Level Cos (θ + 240°) Input Cos (θ + 240°) Input High Level Cos (θ + 120°) Input Cos (θ + 120°) Input High Level Cos θ Input Cos (θ) Input Negative Power Supply Homopolar Reference Homopolar Output Homopolar Filter Select Analog Input Format Select Analog Input Format Cos Output Sin Output (DB1 = MSB, DB12 = LSB Parallel Input Data) Positive Power Supply Digital Ground Internal Logic Setup Time VSS STROBE VDD VSS PH/OP4 PH/OP1 AGND PH/IP4 PH/IPH3 VDD 3 4 5 6 7 10 11 12 PH/OP4 Description NC Mnemonic VSS Pin PIN CONFIGURATION NC = NO CONNECT. NOTES 1 90° orthogonal signals = Sin θ, Cos θ (Resolver) = PH/IP4 and PH/IP1. 2 Three phase, 120°, three-wire signals = Cos θ, Cos (θ + 120°), Cos (θ + 240°). = PH/IP1, PH/IP2, PH/IP3 High Level = PH/IPH1, PH/IPH2, PH/IPH3. 3 Three Phase, 120°, two-wire signals = Cos (θ + 120°), Cos (θ + 240°) = PH/IP2, PH/IP3. In all cases where any of the input Pins 11 through 17 are not used, they must be left unconnected. –4– REV. 0 AD2S105 To relate these stator current to the reference frame the rotor currents assume the same rectangular coordinates, but are now rotated by the operator ejf, where ejf = Cos f + jSin f. THEORY OF OPERATION A fundamental requirement for high quality induction motor drives is that the magnitude and position of the rotating air-gap rotor flux be known. This is normally carried out by measuring the rotor position via a position sensor and establishing a rotor oriented reference frame. Here the term vector rotator comes into play where the stator current vector can be represented in rotor-based coordinates or vice versa. To generate a flux component in the rotor, stator current is applied. A build-up of rotor flux is concluded which must be maintained by controlling the stator current, ids, parallel to the rotor flux. The rotor flux current component is the magnetizing current, imr. The AD2S105 uses ejf as the core operator. In terms of the mathematical function, it rotates the orthogonal ids and iqs components as follows: Torque is generated by applying a current component which is perpendicular to the magnetizing current. This current is normally called the torque generating current, iqs. where ids', iqs' = stator currents in the rotor reference frame. And ids' + jiqs' = (Ids + jIqs) ejf ejf = Cos f + jSin f = (Ids + jIqs)(Cos f + jSin f) To orient and control both the torque and flux stator current vectors, a coordinate transformation is carried out to establish a new reference frame related to the rotor. This complex calculation is carried out by the AD2S105. The output from the AD2S105 takes the form of: ids' = Ids Cos f – Iqs Sin f iqs' = Ids Sin f + Iqs Cos f To expand upon the vector operator a description of a single vector rotation is of assistance. If it is considered that the moduli of a vector is OP and that through the movement of rotor position by f, we require the new position of this vector it can be deduced as follows: The matrix equation is: [ ] [ ids' iqs' Let original vector OP = A (Cos u + jSIN u) where A is a constant; if OQ = OP ejF = Cos f – Sin f Sin f Cos f ] [ ] Ids Iqs and it is shown in Figure 2. (1) φ and: ejF = Cos f + jSin f OQ = A (Cos (u + f) + jSin (u + f)) = A [Cos u Cos φ – Sin u Sin φ + jSin u Cos φ + jCos u Sin φ] = A [(Cos u + jSin u) (Cos f + jSin f)] Ids (2) Ids' jφ e a Iqs Q Iqs' θ+φ P φ Figure 2. AD2S105 Vector Rotation Operation θ INPUT CLARK d O COSθ COSθ + 120° COS θ + 240° SIN θ 3φ TO 2φ TRANSFORMATION Figure 1. Vector Rotation in Polar Coordinate LATCH The complex stator current vector can be represented as is = ias DIGITAL φ j 2π j 4π and a2 = e . This can be re3 3 placed by rectangular coordinates as + aibs + a2ics where a = e is = ids + jiqs COS ( θ + φ) SINE AND COSINE MULTIPLIER (DAC) SIN ( θ + φ) LATCH LATCH (3) PARK In this equation ids and iqs represent the equivalent of a twophase stator winding which establishes the same magnitude of MMF in a three-phase system. These inputs can be seen after the three-phase to two-phase transformation in the AD2S105 block diagram. Equation (3) therefore represents a three-phase to two-phase conversion. REV. 0 SINE AND COSINE MULTIPLIER (DAC) Figure 3. Converter Operation Diagram –5– AD2S105 CONVERTER OPERATION ANALOG SIGNAL INPUT AND OUTPUT CONNECTIONS Input Analog Signals The architecture of the AD2S105 is illustrated in Figure 3. The AD2S105 is configured in the forward transformation which rotates the stator coordinates to the rotor reference frame. All analog signal inputs to AD2S105 are voltages. There are two different voltage levels of three-phase (0°, 120°, 240°) signal inputs. One is the nominal level, which is ± 2.8 V dc or 2 V rms and the corresponding input pins are PH/IP1 (Pin 17), PH/IP2 (Pin 15), PH/IP3 (Pin 13) and PH/IP4 (Pin 11). Vector Rotation Position data, f, is loaded into the input latch on the positive edge of the strobe pulse. (For detail on the timing, please refer to the “timing diagram.”) The negative edge of the strobe signifies that conversion has commenced. A busy pulse is subsequently produced as data is passed from the input latches to the Sin and Cos multipliers. During the loading of the multiplier, the busy pulse remains high preventing further updates of f in both the Sin and Cos registers. The high level inputs can accommodate voltages from nominal up to a maximum of ± VDD/VSS. The corresponding input pins are PH/IPH1 (Pin 16), PH/IPH2 (Pin 14) and PH/IPH3 (Pin 12). The homopolar output can only be used in the three-phase connection mode. The converter can accept both two-phase format and threephase format input signals. For the two-phase format input, the two inputs must be orthogonal to each other. For the threephase format input, there is the choice of using all three inputs or using two of the three inputs. In the latter case, the third input signal will be generated internally by using the information of other two inputs. The high level input mode, however, can only be selected with three-phase/three-input format. All these different conversion modes, including nominal/high input level and two/three-phase input format can be selected using two select pins (Pin 23, Pin 24). The functions are summarized in Table I. The negative edge of the busy pulse signifies that the multipliers are set up and the orthogonal analog inputs are then multiplied real time. The resultant two outputs are accessed via the PH/OP1 (Pin 7) and PH/OP4 (Pin 6). For other configurations, please refer to “Transformation Configuration.” CONNECTING THE CONVERTER Power Supply Connection The power supply voltages connected to VDD and VSS pins should be +5 V dc and –5 V dc and must not be reversed. Pin 4 (VDD) and Pin 41 (VDD) should both be connected to +5 V; similarly, Pin 5 (VSS) and Pin 19 (VSS) should both be connected to –5 V dc. Table I. Conversion Mode Selection It is recommended that decoupling capacitors, 100 nF (ceramic) and 10 µF (tantalum) or other high quality capacitors, are connected in parallel between the power line VDD, VSS and AGND adjacent to the converter. Separate decoupling capacitors should be used for each converter. The connections are shown in Figure 4. Mode Description CONV1 (Pin 23) MODE1 2-Phase Orthogonal with 2 Inputs NC Nominal Input Level MODE2 3-Phase (0°, 120°, 240°) with 3 Inputs DGND Nominal/High Input Level* MODE3 3-Phase (0°, 120°, 240°) with 2 Inputs VDD Nominal Input Level +5V CONV2 (Pin 24) DGND VDD VDD VDD VSS VDD *The high level input mode can only be selected with MODE2. 1 MODE1: 2-Phase/2 Inputs with Nominal Input Level 100nF + In this mode, PH/IP1 and PH/IP4 are the inputs and the Pins 12 through 16 must be left unconnected. 10µF AGND GND AD2S105 TOP VIEW + 100nF 12 VSS 10µF MODE2: 3-Phase/3 Inputs with Nominal/High Input Level In this mode, either nominal or high level inputs can be used. For nominal level input operation, PH/IP1, PH/IP2 and PH/IP3 are the inputs, and there should be no connections to PH/IPH1, PH/IPH2 and PH/IPH3; similarly, for high level input operation, the PH/IPH1, PH/IPH2 and PH/IPH3 are the inputs, and there should be no connections to PH/IP1, PH/IP2 and PH/IP3. In both cases, the PH/IP4 should be left unconnected. For high level signal input operation, select MODE2 only. 34 23 –5V MODE3: 3-Phase/2 Inputs with Nominal Input Level Figure 4. AD2S105 Power Supply Connection In this mode, PH/IP2 and PH/IP3 are the inputs and the third signal will be generated internally by using the information of other two inputs. It is recommended that PH/IP1, PH/IPH1, PH/IPH2, PH/IP4 and PH/IPH3 should be left unconnected. –6– REV. 0 AD2S105 Output Analog Signals Example: From the equivalent circuit, it can be seen that the inclusion of a 20 kΩ resistor will reduce Vts to ± 0.25 V dc. This corresponds to an imbalance of ± 0.75 V dc in the inputs. There are two sets of analog output from the AD2S105. Sin/Cos orthogonal output signals are derived from the Clark/ three-to-two-phase conversion before the Park angle rotation. These signals are available on Pin 25 (Cos u) and Pin 26 (Sin u), and occur before Park angle rotation. Homopolar Filtering The equation VSUM = Cosu + Cos (u + 120°) + Cos (u + 240°) = 0 denotes an imbalance when VSUM ≠ 0. There are conditions, however, when an actual imbalance will occur and the conditions as defined by VSUM will be valid. For example, if the first phase was open circuit when u = 90° or 270°, the first phase is valid at 0 V dc. VSUM is valid, therefore, when Cosu is close to 0. In order to detect an imbalance u has to move away from 90° or 270°, i.e., when on a balanced line Cos u ≠ 0. Two-Phase (Sin (u + f), Cos (u + f)) Signals These represent the output of the coordinate transformation. These signals are available on Pin 6 (PH/OP4, Sin (u + f)) and Pin 7 (PH/OP1, Cos (u + f)). HOMOPOLAR OUTPUT HOMOPOLAR Reference Line imbalance is detected as a function of HPREF, either set by the user or internally set at ± 0.5 V dc. This corresponds to a dead zone when f = 90° or 270° ± 30°, i.e., VSUM = 0, and, therefore, no indicated imbalance. If an external 20 kΩ resistor is added, this halves Vts and reduces the zone to ± 15°. Note this example only applies if the first phase is detached. In a three-phase ac system, the sum of the three inputs to the converter can be used to indicate whether or not the phases are balanced. If VSUM = PH/IP1 + PH/IP2 + PH/IP3 (or PH/IPH1 + PH/ IPH2 + PH/IPH3) this can be rewritten as VSUM = [Cosu, + Cos (u + 120°) + Cos (u + 240°)] = 0. Any imbalances in the line will cause the sum VSUM ≠ 0. The AD2S105 homopolar output (HPOP) goes high when VSUM > 3 × Vts. The voltage level at which the HPOP indicates an imbalance is determined by the HPREF threshold, Vts. This is set internally at ± 0.5 V dc (± 0.1 V dc). The HPOP goes high when In order to prevent this false triggering an external capacitor needs to be placed from HPFILT to ground, as shown in Figure 5. This averages out the perceived imbalance over a complete cycle and will prevent the HPOP from alternatively indicating balance and imbalance over u = 0° to 360°. For (Cosθ + Cos(θ + 120° ) + Cos(θ + 240° )) V ts < ×V 3 dθ = 1000 rpm C EXT = 220 nF dt dθ = 100 rpm C EXT = 2.2 µF dt where V is the nominal input voltage. With no external components VSUM must exceed ± 1.5 V dc in order for HPOP to indicate an imbalance. The sensitivity of the threshold can be reduced by connecting an external resistor between HPOP and ground in Figure 5 where V ts = Note: The slower the input rotational speed, the larger the time constant required over which to average the HPOP output. Use of the homopolar output at slow rotational speeds becomes impractical with respect to the increased value for CEXT. 0.5 REXT REXT + 20,000 34 REXT is in Ω. DGND AD2S105 TOP VIEW 1 25µA 23 CEXT 220nF HPFILT HOMOPOLAR REFERENCE HPOP HPOP HPREF TO TRIGGER AGND HPREF 20kΩ 12 REXT EXTERNAL RESISTOR GND Figure 6. AD2S105 Homopolar Output Connections Figure 5. The Equivalent Homopolar Reference Input Circuitry REV. 0 –7– AD2S105 TIMING DIAGRAMS Busy Output TYPICAL CIRCUIT CONFIGURATION Figure 8 shows a typical circuit configuration for the AD2S105 in a three phase, nominal level input mode (MODE2). TWO PHASE OUTPUT The width of the positive STROBE pulse should be at least 100 ns, in order to successfully start the conversion. The maximum frequency of STROBE input is 366 kHz, i.e., there should be at least 2.73 µs from the negative edge of one STROBE pulse to the next rising edge. This is illustrated by the following timing diagram and table. t2 BUSY t1 t2 t3 t4 tr 100 ns 30 ns 1.7 µs 2.5 µs 100 ns 20 ns 150 ns tf 10 ns 120 ns Cos(θ + 240°) COS SIN HPFILT LSB GND 10µF REVERSE TRANSFORMATION AD2S105 Cos(θ + φ) +jφ Cosθ Cos(θ + 120°) 30 27 The AD2S105 can perform both forward and reverse transformations. The section “Theory of Operation” explains how the chip operates with the core operator e+jf, which performs a forward transformation. The reverse transformation, e–jf, is performed by providing a negative angle φ. Figure 9 shows two different phase input/output connections for AD2S105 reverse transformation operation. STROBE Pulse Width STROBE ↓ to BUSY ↑ BUSY Pulse Width BUSY ↓ to STROBE ↑ BUSY Pulse Rise Time with No Load BUSY Pulse Rise Time with 68 pF Load BUSY Pulse Fall Time with No Load BUSY Pulse Fall Time with 68 pF Load Cosθ 3 PHASE – 2 PHASE 23 APPLICATIONS Transformation Configuration Condition Sinθ HPREF HPOP PH/IP2 16 PH/IP1 FORWARD TRANSFORMATION AD2S105 2 PHASE – 2 PHASE 34 TOP VIEW Figure 8. Typical Circuit Configuration Table II. AD2S105 Timing Table Max MSB PH/IP3 100nF t3 Typ 12 –5V Note: Digital data should be stable 25 ns before and after positive strobe edge. Min 38 +5V DIGITAL ANGLE INPUT THREE PHASE INPUT tf Figure 7. AD2S105 Timing Diagram Parameter 41 AD2S105 PH/IP4 STROBE tr 1 AGND t4 t1 PH/OP1 BUSY Strobe Input 10µF 100nF STROBE The BUSY output will go HI at the negative edge of the STROBE input. This is used to synchronize digital input data and load the digital angular rotation information into the device counter. The BUSY output will remain HI for 2 µs, and go LO until the next strobe negative edge occurs. e Sin(θ + φ) Cos(θ + φ) +jφ e Sin(θ + φ) Cos(θ – φ) Cosθ –jφ Sinθ Cosθ Cos(θ + 120°) Cos(θ + 240°) e Sin(θ – φ) Cos(θ – φ) –jφ e Sin(θ – φ) –1 Figure 9. Forward and Reverse Transformation Connections –8– REV. 0 AD2S105 phases are balanced or not. For more details about this application, refer to the related application note listed in the bibliography. MEASUREMENT OF HARMONICS In ac power systems, the quality of the electrical supply can be affected by harmonic voltages injected into the power main by loads, such as variable speed drive systems and computer power supplies. These harmonics are injected into other loads through the point of common coupling of the supply. This produces extra losses in power factor correction capacitors, power supplies and other loads which may result in failure. It also can result in tripping and failure of computer systems and other sensitive equipment. In ac machines the resultant harmonic currents and flux patterns produce extra motor losses and torque pulsations, which can be damaging to the load. Field Oriented Control of AC Induction Motors In ac induction motors, torque is produced through interaction between the rotating air gap field and currents induced in the rotor windings. The stator currents consist of two components, the flux component which drives the air gap field, and the torque component which is reflected from the rotor windings. A successful field oriented control strategy must independently control the flux component of current, referred to as direct current (Ids), and the torque producing component of stator current, referred to as quadrature current (Iqs). The AD2S105 can be used to monitor and detect the presence and magnitude of a particular harmonic on a three-phase line. Figure 10 shows the implementation of such a scheme using the AD2S105, where Va, Vb, Vc are the scaled line voltages. The control architecture in Figure 11 is referred to as field oriented because the control algorithms performed on the ADSP2105 processor operate on decoupled flux and torque current components in a reference frame relative to the rotor flux of the motor. The control algorithms provide fast torque response at any speed which results in superior dynamic performance, and consequently, load variations have minimal effect on speed or position control. AD2S105 Va Vb Vc Vd 1 Vd THREE -TO-TWO CLARK TRANSFORMATION HOMOPOLAR OUTPUT Vq jφ e PARK TRANSFORMATION 12-BIT UP/DOWN COUNTER LOW PASS FILTER ak Vq 1 The AD2S90 resolver-to-digital converter is used to convert the modulated resolver position signals into a 12-bit digital position value. This value is brought into the ADSP-2105 via the serial port where the control algorithms calculate the rotor flux angle. The rotor flux angle is the sum of the rotor position and the slip angle. The relationship between the stator current frequency and the slip frequency can be summarized by the following formula: PULSE INPUTS DIRECTION Figure 10. Harmonics Measurement Using AD2S105 Selecting a harmonic is achieved by synchronizing the rotational frequency of the park digital input, f, with the frequency of the fundamental component and the integer harmonic selected. The update rate, r, of the counters is determined by: r = 4096 × fstat = (vm × (p/2)) + fslip where: fstat = Stator Current Frequency (Hz) vm = Mechanical Speed of the Motor ( revs/sec ) p = Number of poles fslip = Slip Frequency (Hz) n×ω . 2π The rotor flux angle is fed into the 12-bit position input of the AD2S105. The AD2S105 transforms the three ac stator currents using the digital rotor flux angle into dc values representing direct current (Ids) and quadrature current (Iqs). The transformation of the ac signals into dc values simplifies the design of the A/D converter as it avoids the bandwidth sampling issues inherent in ac signal processing and in most cases eliminates the need for a simultaneous sampling A/D converter. Here, r = input clock pulse rate (pulses/second); n = the order of harmonics to be measured; v = fundamental angular frequency of the ac signal. The magnitude of the n-th harmonic as well as the fundamental component in the power line is represented by the output of the low-pass filter, ak. In concert with magnitude of the harmonic the AD2S105 homopolar output will indicate whether the three Ids I STATOR s1 CURRENT Is2 SIGNALS I s3 AD2S105 Iqs 2 CHANNEL 12 Bit A/D CONVERTER ADSP-2105 ROTOR FLUX MODEL INV + PWM MOTOR RESOLVER SPORT ROTOR POSITION DATA ROTOR FLUX ANGLE Figure 11. Field Oriented Control of AC Induction Motors REV. 0 –9– AD2S90 R/D CONVERTER AD2S105 MULTIPLE POLE MOTORS For multi-pole motor applications where a single speed resolver is used, the AD2S105 input has to be configured to match the electrical cycle of the resolver with the phasing of the motor windings. The input to the AD2S105 is the output of a resolverto-digital converter, e.g., AD2S80A series. The parallel output of the converter needs to be multiplied by 2n–1, where n = the number of pole pairs of the motor. In practice this is implemented by shifting the parallel output of the converter left relative to the number of pole pairs. This will work for motors with a binary number of pole pairs. Figure 13 shows the AD2S80A configured for use with a four pole motor, where n = 2. Using the formula described the MSB is shifted left once. (MSB) MSB MSB-1 MSB BIT2 MSB-1 . . . . . BIT13 (LSB) AD2S105 n = POLES BIT1 . Figure 12 shows the generic configuration of the AD2S80A with the AD2S105 for a motor with n pole pairs. The MSB of the AD2S105 is connected to MSB–(n–1) bit of the AD2S80A digital output, MSB-1 bit to MSB–(n–2) bit, etc. AD2S80A AD2S105 AD2S80A BIT14 . . . . . . . . . . . . . LSB 14-BIT RESOLUTION MODE MSB MSB-1 . Figure 13. Connecting of R/D Converter AD2S80A and AD2S105 for Four-Pole Motor Application MSB-2 . . . . MSB – (n–1) . . . . . . . . . . . . 12,14 OR 16-BIT RESOLUTION MODE Figure 12. A General Consideration in Connecting R/D Converter and AD2S105 for Multiple Pole Motors APPLICATION NOTES LIST 1. “Vector Control Using a Single Vector Rotation Semiconductor for Induction and Permanent Magnet Motors,” by F.P. Flett, Analog Devices. 2. “Silicon Control Algorithms for Brushless Permanent Magnet Synchronous Machines,” by F.P. Flett. 3. “Single Chip Vector Rotation Blocks and Induction Motor Field Oriented Control,” by A.P.M. Van den Bossche and P.J.M. Coussens. 4. “Three Phase Measurements with Vector Rotation Blocks in Mains and Motion Control,” P.J.M. Coussens, et al. 5. “A Tutorial in AC Induction and Permanent Magnet Synchronous Motors–Vector-Control with Digital Signal Processors.” –10– REV. 0 AD2S105 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Leaded Chip Carrier (P-44A) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 6 0.025 (0.63) 0.015 (0.38) 40 PIN 1 IDENTIFIER 7 0.048 (1.21) 0.042 (1.07) 0.180 (4.57) 0.165 (4.19) 39 0.021 (0.53) 0.013 (0.33) 0.63 (16.00) 0.59 (14.99) 0.032 (0.81) 0.026 (0.66) TOP VIEW 0.050 (1.27) BSC 29 17 18 0.020 (0.50) R 28 0.040 (1.01) 0.025 (0.64) 0.656 (16.66) SQ 0.650 (16.51) 0.110 (2.79) 0.085 (2.16) 0.695 (17.65) SQ 0.685 (17.40) REV. 0 –11– –12– PRINTED IN U.S.A. C1938–18–7/94