TI CD74HCT132

[ /Title
(CD74
HC132
,
CD74
HCT13
2)
/Subject
(High
Speed
CMOS
Logic
Quad
2-Input
NAND
Schmit
CD74HC132,
CD74HCT132
Data sheet acquired from Harris Semiconductor
SCHS145
High Speed CMOS Logic
Quad 2-Input NAND Schmitt Trigger
August 1997
Features
at VCC = 5V
• Typical Propagation Delay: 10ns at VCC = 5V,
CL = 15pF, TA = 25oC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Related Literature
- CD54HC132F3A and CD54HCT132F3A Military
Data Sheet, Document Number 3778
• Unlimited Input Rise and Fall Times
• Exceptionally High Noise Immunity
• Wide Operating Temperature Range . . . -55oC to 125oC
Description
• Balanced Propagation Delay and Transition Times
The Harris CD74HC132, CD74HCT132 each contain four
2-input NAND Schmitt Triggers in one package. This logic
device utilizes silicon gate CMOS technology to achieve
operating speeds similar to LSTTL gates with the low power
consumption of standard CMOS integrated circuits. All
devices have the ability to drive 10 LSTTL loads. The 74HCT
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 37%, NIH = 51% of VCC
Pinout
CD74HC132, CD74HCT132
(PDIP, SOIC)
TOP VIEW
1A 1
14 VCC
1B 2
13 4B
1Y 3
12 4A
2A 4
11 4Y
2B 5
10 3B
2Y 6
9 3A
GND 7
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number
1649.1
CD74HC132, CD74HCT132
Functional Diagram
1
14
2
13
1A
4B
1B
1Y
2A
2B
2Y
GND
VCC
3
12
4
11
5
10
6
9
7
8
4A
4Y
3B
3A
3Y
TRUTH TABLE
INPUTS
OUTPUT
nA
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
NOTE: H = High Voltage Level, L = Low Voltage Level
Logic Symbol
nA
nY
nB
2
CD74HC132, CD74HCT132
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VT+
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
0.7
-
1.5
0.7
1.5
0.7
1.5
V
4.5
1.7
-
3.15
1.7
3.15
1.7
3.15
V
6
2.1
-
4.2
2.1
4.2
2.1
4.2
V
2
0.3
-
1
0.3
1
0.3
1
V
4.5
0.9
-
2.2
0.9
2.2
0.9
2.2
V
6
1.2
-
3
1.2
3
1.2
3
V
2
0.2
-
1
0.2
1
0.2
1
V
4.5
0.4
-
1.4
0.4
1.4
0.4
1.4
V
6
0.6
-
1.6
0.6
1.6
0.6
1.6
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
HC TYPES
Input Switch Points
(Note 6)
V T-
-
-
-
VH
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
VOH
VT+ or
V T-
3
CD74HC132, CD74HCT132
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output
Voltage
CMOS Loads
SYMBOL
VI (V)
VOL
VT+ or
V T-
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
2
-
20
-
40
µA
VT+
-
-
4.5
1.2
-
1.9
1.2
1.9
1.2
1.9
V
5.5
1.4
-
2.1
1.4
2.1
1.4
2.1
V
4.5
0.5
-
1.2
0.5
1.2
0.5
1.2
V
5.5
0.6
-
1.4
0.6
1.4
0.6
1.4
V
4.5
0.4
-
1.4
0.4
1.4
0.4
1.4
V
5.5
0.4
-
1.5
0.4
1.5
0.4
1.5
V
-
4.5
4.4
-
-
4.4
-
4.4
-
V
-
4.5
3.98
-
-
3.84
-
3.7
-
V
-4
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.26
-
0.33
-
0.4
V
HCT TYPES
Input Switch Points
(Note 6)
V T-
VH
High Level Output
Voltage
CMOS Loads
-
-
-
VT+ or
V T-
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage CMOS Loads
VOL
VT+ or
V T-
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
-
-
II
VCC
and
GND
4
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
2
-
20
-
40
µA
∆ICC
VCC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTES:
4. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
5. Die for this part number is available which meets all electrical specifications.
6. Hysteresis definition, characteristic and test setup see Test Circuits and Waveforms:
4
CD74HC132, CD74HCT132
HCT Input Loading Table
INPUT
UNIT LOADS
nA, nB
0.6
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
VCC
-40oC TO 85oC -55oC TO 125oC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
125
-
156
-
188
ns
4.5
-
-
25
-
31
-
38
ns
6
-
-
21
-
27
-
32
ns
HC TYPES
Propagation Delay
A, B to Y (Figure 1)
Propagation Delay
A, B to Y
tTLH, tTHL
CL = 15pF
5
-
10
-
-
-
-
-
pF
Transition Times (Figure 1)
tTLH, tTHL
CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 7, 8)
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
30
-
-
-
-
-
pF
HCT TYPES
Propagation Delay
A, B to Y
(Figure 2)
tPHL, tPHL
CL = 50pF
4.5
-
-
33
-
41
-
50
ns
Propagation Delay
A, B to Y
tPLH, tPHL
CL = 15pF
5
-
13
-
-
-
-
-
pF
Transition Times (Figure 2)
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 7, 8)
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
30
-
-
-
-
-
pF
NOTES:
7. CPD is used to determine the dynamic power consumption, per gate.
8. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
5
CD74HC132, CD74HCT132
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
tPHL
tf = 6ns
tr = 6ns
VCC
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
VH
VO
+
VH = V T - V T
Vl
VT
+
VT
+
VT
VT
VCC
Vl
VH
GND
VCC
VCC
VO
GND
Vl
VO
FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SET-UP
6
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