[ /Title (CD74H C14, CD74H CT14) /Subject (High Speed CMOS Logic Hex Invert- CD74HC14, CD74HCT14 Data sheet acquired from Harris Semiconductor SCHS129 High Speed CMOS Logic Hex Inverting Schmitt Trigger January 1998 Features at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH • Unlimited Input Rise and Fall Times • Exceptionally High Noise Immunity • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC Description • Balanced Propagation Delay and Transition Times The Harris CD74HC14, CD74HCT14 each contain 6 inverting Schmitt Triggers in one package. • Significant Power Reduction Compared to LSTTL Logic ICs Ordering Information • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC PART NUMBER TEMP. RANGE (oC) PACKAGE -55 to 125 14 Ld CERDIP CD54HCT14F PKG. NO. F14.3 Pinout CD54HC14, CD54HCT14, CD74HC14, CD74HCT14 (PDIP, CERDIP, SOIC) TOP VIEW 1A 1 14 VCC 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 8 4Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 1 File Number 1781.1 CD74HC14, CD74HCT14 Functional Diagram 1A 2A 3A 4A 5A 6A 1 2 3 4 5 6 9 8 11 10 13 12 1Y 2Y 3Y 4Y 5Y 6Y GND = 7 VCC = 14 TRUTH TABLE INPUT (A) OUTPUT (Y) L H H L NOTE: H= High Level L = Low Level Logic Diagram nA nY 2 CD74HC14, CD74HCT14 VH VO VH = VT+ - VTVI VT- VT+ V T+ VT - VCC VH VI GND VCC VO GND FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP 3 CD74HC14, CD74HCT14 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 CERDIP Package . . . . . . . . . . . . . . . . 130 55 SOIC Package . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time, tr, tf 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VT+ - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 2 0.7 1.5 0.7 1.5 0.7 1.5 V 4.5 1.7 3.15 1.7 3.15 1.7 3.15 V 6 2.1 4.2 2.1 4.2 2.1 4.2 V 2 0.3 1.0 0.3 1.0 0.3 1.0 V 4.5 0.9 2.2 0.9 2.2 0.9 2.2 V 6 1.2 3.0 1.2 3.0 1.2 3.0 V HC TYPES Input Switch Points VT- VH High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads VOH - - VT- or VT+ - - - 2 0.2 1.0 0.2 1.0 0.2 1.0 V 4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 6 0.6 1.6 0.6 1.6 0.6 1.6 V -0.02 2 1.9 - 1.9 - 1.9 - V -0.02 4.5 4.4 - 4.4 - 4.4 - V -0.02 6 5.9 - 5.9 - 5.9 - V - - - - - - - - V -4 4.5 3.98 - 3.84 - 3.7 - V -5.2 6 5.48 - 5.34 - 5.2 - V 4 CD74HC14, CD74HCT14 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER SYMBOL VI (V) Low Level Output Voltage CMOS Loads VOL VIH or VIL IO (mA) VCC (V) Quiescent Device Current -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 0.02 2 - 0.1 - 0.1 - 0.1 V 0.02 4.5 - 0.1 - 0.1 - 0.1 V 0.02 6 - 0.1 - 0.1 - 0.1 V - - - - - - - - V 4 4.5 - 0.26 - 0.33 - 0.4 V 5.2 6 - 0.26 - 0.33 - 0.4 V Low Level Output Voltage TTL Loads Input Leakage Current 25oC II VCC or GND - 6 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - 2 - 20 - 40 µA VT+ - - 4.5 1.2 1.9 1.2 1.9 1.2 1.9 V 5.5 1.4 2.1 1.4 2.1 1.4 2.1 V 4.5 0.5 1.2 0.5 1.2 0.5 1.2 V 5.5 0.6 1.4 0.6 1.4 0.6 1.4 V 4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 5.5 0.4 1.5 0.4 1.5 0.4 1.5 V -0.02 4.5 4.4 - 4.4 - 4.4 - V -4 4.5 3.98 - 3.84 - 3.7 - V 0.02 4.5 - 0.1 - 0.1 - 0.1 V 4 4.5 - 0.26 - 0.33 - 0.4 V HCT TYPES Input Switch Points VT- VH High Level Output Voltage CMOS Loads VOH VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 2 - 20 - 40 µA ∆ICC (Note 4) VCC - 2.1 - 4.5 to 5.5 - 360 - 450 - 490 µA NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS nA 0.6 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 5 Switching Specifications Input tr, tf = 6ns PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 135 - 170 - 205 ns CL = 50pF 4.5 - - 27 - 34 - 41 ns CL = 15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 23 - 29 - 35 ns CL = 50pF 2 - - 75 - 95 18 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns HC TYPES Propagation Delay, A to Y Output Transition Times tTLH, tTHL Input Capacitance Power Dissipation Capacitance (Notes 5, 6) CI - - - - 10 - 10 - 10 pF CPD - 5 - 20 - - - - - pF CL = 50pF 4.5 - - 38 - 48 - 57 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 4.5 - - 15 - 19 - 22 ns HCT TYPES Propagation Delay, A to Y tPLH, tPHL Output Transition Times tTLH, tTHL Input Capacitance Power Dissipation Capacitance (Notes 5, 6) CI - - - - 10 - 10 - 10 pF CPD - 5 - 20 - - - - - pF NOTES: 5. CPD is used to determine the dynamic power consumption, per inverter. 6. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 4. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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