PD - 94547A IRLR7833 IRLU7833 ® HEXFET Power MOSFET Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use VDSS RDS(on) max 4.5m: 30V Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current D-Pak IRLR7833 Qg 33nC I-Pak IRLU7833 Absolute Maximum Ratings Parameter Max. Units 30 V VDS Drain-to-Source Voltage VGS Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V ± 20 140 99 IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current PD @TC = 25°C Maximum Power Dissipation 140 ID @ TC = 25°C ID @ TC = 100°C c PD @TC = 100°C g Maximum Power Dissipation g TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range f f A 560 W 71 0.95 -55 to + 175 Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw W/°C °C 300 (1.6mm from case) x x 10 lbf in (1.1N m) Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) RθJA Junction-to-Ambient g Typ. Max. ––– 1.05 ––– 50 ––– 110 Units °C/W Notes through are on page 11 www.irf.com 1 3/19/04 IRLR/U7833 Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions BVDSS ∆ΒVDSS/∆TJ RDS(on) Drain-to-Source Breakdown Voltage 30 ––– ––– Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance ––– ––– 19 3.6 ––– 4.5 VGS(th) ∆VGS(th)/∆TJ IDSS Gate Threshold Voltage ––– 1.4 4.4 ––– 5.5 2.3 Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current ––– ––– -6.0 ––– ––– 1.0 IGSS Gate-to-Source Forward Leakage ––– ––– ––– ––– 150 100 nA VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V Gate-to-Source Reverse Leakage Forward Transconductance ––– 66 ––– ––– -100 ––– S VGS = -20V VDS = 15V, ID = 12A Total Gate Charge Pre-Vth Gate-to-Source Charge ––– ––– 33 8.7 50 ––– Post-Vth Gate-to-Source Charge Gate-to-Drain Charge ––– ––– 2.1 13 ––– ––– Qgodr Qsw Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– ––– 9.9 15 ––– ––– Qoss td(on) Output Charge Turn-On Delay Time ––– ––– 22 14 ––– ––– tr td(off) Rise Time Turn-Off Delay Time ––– ––– 6.9 23 ––– ––– tf Ciss Fall Time Input Capacitance ––– ––– 15 4010 ––– ––– Coss Crss Output Capacitance Reverse Transfer Capacitance ––– ––– 950 470 ––– ––– gfs Qg Qgs1 Qgs2 Qgd V VGS = 0V, ID = 250µA mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 15A f = 12A f V VGS = 4.5V, ID VDS = VGS, ID = 250µA mV/°C µA VDS = 24V, VGS = 0V VDS = 16V nC VGS = 4.5V ID = 12A See Fig. 16 nC ns VDS = 16V, VGS = 0V VDD = 15V, VGS = 4.5V f ID = 12A Clamped Inductive Load VGS = 0V pF VDS = 15V ƒ = 1.0MHz Avalanche Characteristics EAS IAR Parameter Single Pulse Avalanche Energy Avalanche Current EAR Repetitive Avalanche Energy c d c Typ. ––– ––– Max. 530 20 Units mJ A ––– 14 mJ Diode Characteristics Parameter Min. Typ. Max. Units 140 f Conditions IS Continuous Source Current ––– ––– ISM (Body Diode) Pulsed Source Current ––– ––– 560 VSD (Body Diode) Diode Forward Voltage ––– ––– 1.0 V p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V trr Qrr Reverse Recovery Time Reverse Recovery Charge ––– ––– 39 37 58 55 ns nC TJ = 25°C, IF = 12A, VDD = 15V di/dt = 100A/µs ton Forward Turn-On Time 2 ch MOSFET symbol A showing the integral reverse D G S f f Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) www.irf.com IRLR/U7833 1000 1000 100 BOTTOM 10 VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.25V 1 2.25V 0.1 TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 100 BOTTOM 10 2.25V 20µs PULSE WIDTH Tj = 175°C 20µs PULSE WIDTH Tj = 25°C 0.01 1 0.1 1 10 100 1000 0.1 VDS, Drain-to-Source Voltage (V) 1 10 100 1000 VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.0 T J = 175°C 100.00 10.00 T J = 25°C 1.00 VDS = 25V 20µs PULSE WIDTH ID = 30A VGS = 10V 1.5 (Normalized) RDS(on) , Drain-to-Source On Resistance 1000.0 ID, Drain-to-Source Current (Α) VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.25V 1.0 0.5 0.10 2.0 3.0 4.0 5.0 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 6.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRLR/U7833 100000 6.0 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd VGS , Gate-to-Source Voltage (V) ID= 12A C, Capacitance(pF) Coss = Cds + Cgd 10000 Ciss Coss 1000 Crss VDS= 24V VDS= 15V 5.0 4.0 3.0 2.0 1.0 0.0 100 1 10 0 100 30 40 50 10000 100.00 ID, Drain-to-Source Current (A) 1000.00 ISD, Reverse Drain Current (A) 20 Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 T J = 175°C 100 10.00 T J = 25°C 1.00 100µsec 10 1msec Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 10msec 1 0.10 0.0 0.5 1.0 1.5 2.0 VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 10 Q G Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) 2.5 1 10 100 1000 VDS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRLR/U7833 2.5 150 VGS(th) Gate threshold Voltage (V) LIMITED BY PACKAGE 125 ID , Drain Current (A) 100 75 50 25 2.0 ID = 250µA 1.5 1.0 0.5 0.0 0 25 50 75 100 125 150 175 -75 -50 -25 ° TC, Case Temperature (°C) 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature (Z thJC) 10 1 Thermal Response D = 0.50 0.20 P DM 0.10 0.1 0.05 0.02 0.01 t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 t1/ t 2 J = P DM x Z thJC +TC 0.1 1 t1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U7833 15V + V - DD IAS 20V VGS A 0.01Ω tp EAS , Single Pulse Avalanche Energy (mJ) 10000 D.U.T RG ID 8.2A 14A BOTTOM 20A TOP 12500 DRIVER L VDS 15000 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 7500 5000 2500 0 25 50 75 100 125 150 Starting T J , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS VDS Fig 12b. Unclamped Inductive Waveforms VGS RG Current Regulator Same Type as D.U.T. RD D.U.T. + -V DD V GS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 50KΩ 12V .2µF Fig 14a. Switching Time Test Circuit .3µF D.U.T. + V - DS VDS 90% VGS 3mA IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit 6 10% VGS td(on) tr t d(off) tf Fig 14b. Switching Time Waveforms www.irf.com IRLR/U7833 D.U.T Driver Gate Drive + - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer D= Period P.W. + + Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage - Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRLR/U7833 Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput Q + oss × Vin × f + (Qrr × Vin × f ) 2 This can be expanded and approximated by; *dissipated primarily in Q1. Ploss = (Irms 2 × Rds(on ) ) Qgd +I × × Vin × ig Qgs 2 f + I × × Vin × f ig + (Qg × Vg × f ) + Qoss × Vin × f 2 This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRLR/U7833 TO-252AA (D-Pak) Package Outline Dimensions are shown in millimeters (inches) 2.38 (.094) 2.19 (.086) 6.73 (.265) 6.35 (.250) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 10.42 (.410) 9.40 (.370) 1.02 (.040) 1.64 (.025) 1 2 1 - GATE 1.52 (.060) 1.15 (.045) 3X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) 2 - DRAIN 0.51 (.020) MIN. -B- 2X LEAD ASSIGNMENTS 3 3 - SOURCE 4 - DRAIN 0.58 (.023) 0.46 (.018) M A M B NOTES: 2.28 (.090) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4.57 (.180) 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). TO-252AA (D-Pak) Part Marking Information 5 ) 5 , 1 $ 6 , 6 , + 7 ( / 3 5 ( % / $ 1 2 , 7 $ 1 5 ( 7 1 , ( ' 5 $ ( < 2 * 2 / . ( ( : $ ( 1 , / < / % 0 ( 6 6 $ ( + 7 1 , $ 8 ) ,5 5 ( , ) , 7 & ( 5 : : 1 2 ' ( / % 0 ( 6 6 $ 2 & ( 7 $ ' < / % 0 ( ( 6 ' 6 $ 2 & + 7 7 , 2 : / 0 8 1 7 5 $ 3 0 $ ; ( $ ( 1 , / < / % 0 ( 6 6 $ ( ' 2 & 7 2 / www.irf.com 9 IRLR/U7833 I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) 2.38 (.094) 2.19 (.086) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.52 (.060) 1.15 (.045) 1 2 2.28 (.090) 1.91 (.075) 1.14 (.045) 0.76 (.030) 2.28 (.090) 2X 3 - SOURCE 4 - DRAIN 3 -B- 3X 1 - GATE 2 - DRAIN 3X 9.65 (.380) 8.89 (.350) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 0.89 (.035) 0.64 (.025) 1.14 (.045) 0.89 (.035) 0.25 (.010) M A M B 0.58 (.023) 0.46 (.018) I-Pak (TO-251AA) Part Marking Information 10 www.irf.com IRLR/U7833 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Notes: Repetitive rating; pulse width limited by Calculated continuous current based on maximum allowable max. junction temperature. Starting TJ = 25°C, L = 2.6mH, RG = 25Ω, IAS = 20A. Pulse width ≤ 400µs; duty cycle ≤ 2%. When mounted on 1" square PCB (FR-4 or G-10 Material). junction temperature. Package limitation current is 30A. For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.03/04 www.irf.com 11