PD - 94650A IRLR3715Z IRLU3715Z ® HEXFET Power MOSFET Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use VDSS RDS(on) max : 11m 20V Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current D-Pak IRLR3715Z Qg 7.2nC I-Pak IRLU3715Z Absolute Maximum Ratings Parameter Max. Units 20 V Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V ± 20 49 A 35 IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current PD @TC = 25°C Maximum Power Dissipation 40 PD @TC = 100°C Maximum Power Dissipation 20 TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range VDS Drain-to-Source Voltage VGS ID @ TC = 25°C ID @ TC = 100°C c f f 200 W 0.27 -55 to + 175 Soldering Temperature, for 10 seconds W/°C °C 300 (1.6mm from case) Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) RθJA Junction-to-Ambient g Typ. Max. Units ––– 3.75 °C/W ––– 50 ––– 110 Notes through are on page 11 www.irf.com 1 04/02/03 IRLR/U3715Z Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions BVDSS Drain-to-Source Breakdown Voltage 20 ––– ––– ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 13 ––– RDS(on) Static Drain-to-Source On-Resistance ––– 8.8 11 mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 15A ––– 12.4 15.5 VGS = 4.5V, ID = 12A V VGS = 0V, ID = 250µA VGS(th) Gate Threshold Voltage 1.65 2.1 2.55 V ∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -4.8 ––– mV/°C IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA VDS = 16V, VGS = 0V ––– ––– 150 IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V Gate-to-Source Reverse Leakage ––– ––– -100 gfs Qg Forward Transconductance 33 ––– ––– e e VDS = VGS, ID = 250µA VDS = 16V, VGS = 0V, TJ = 125°C VGS = -20V S VDS = 10V, ID = 12A Total Gate Charge ––– 7.2 11 Qgs1 Pre-Vth Gate-to-Source Charge ––– 2.3 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 0.90 ––– Qgd Gate-to-Drain Charge ––– 2.6 ––– ID = 12A Qgodr ––– 1.4 ––– See Fig. 16 Qsw Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– 3.5 ––– Qoss Output Charge ––– 3.8 ––– td(on) Turn-On Delay Time ––– 7.8 ––– VDD = 10V, VGS = 4.5V tr Rise Time ––– 13 ––– ID = 12A td(off) Turn-Off Delay Time ––– 10 ––– tf Fall Time ––– 4.3 ––– Ciss Input Capacitance ––– 810 ––– Coss Output Capacitance ––– 270 ––– Crss Reverse Transfer Capacitance ––– 150 ––– VDS = 10V nC nC ns VGS = 4.5V VDS = 10V, VGS = 0V e Clamped Inductive Load VGS = 0V pF VDS = 10V ƒ = 1.0MHz Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy c d c Typ. Max. Units ––– 19 mJ ––– 12 A ––– 4.0 mJ Diode Characteristics Parameter Min. Typ. Max. Units f Conditions IS Continuous Source Current ––– ––– 49 ISM (Body Diode) Pulsed Source Current ––– ––– 200 showing the integral reverse VSD (Body Diode) Diode Forward Voltage ––– ––– 1.0 V p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V trr Reverse Recovery Time ––– 11 17 ns Qrr Reverse Recovery Charge ––– 3.5 5.3 nC ton Forward Turn-On Time 2 c MOSFET symbol A D G S e TJ = 25°C, IF = 12A, VDD = 10V di/dt = 100A/µs e Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) www.irf.com IRLR/U3715Z 10000 1000 1000 100 BOTTOM VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V 2.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 10 1 2.5V 0.1 100 BOTTOM VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V 2.5V 10 2.5V 1 20µs PULSE WIDTH Tj = 175°C 20µs PULSE WIDTH Tj = 25°C 0.01 0.1 0.1 1 10 0.1 Fig 1. Typical Output Characteristics 10 Fig 2. Typical Output Characteristics 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) 1000 ID, Drain-to-Source Current (Α) 1 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) T J = 175°C 100 10 TJ = 25°C 1 ID = 30A VGS = 10V 1.5 1.0 0.5 0.1 0 2 4 6 8 10 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 12 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRLR/U3715Z VGS Ciss Crss Coss 1000 6.0 = 0V, f = 1 MHZ = C gs + Cgd , C ds SHORTED = C gd = C ds + Cgd ID= 12A VGS, Gate-to-Source Voltage (V) C, Capacitance(pF) 10000 Ciss Coss Crss 100 VDS= 16V VDS= 10V 5.0 4.0 3.0 2.0 1.0 0.0 10 1 10 100 0 2 4 6 8 10 QG Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 1000 1000.00 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100.00 T J = 175°C 10.00 1.00 TJ = 25°C 10 100µsec 1msec 1 10msec Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.1 0.10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRLR/U3715Z 50 2.5 VGS(th) Gate threshold Voltage (V) Limited By Package ID, Drain Current (A) 40 30 20 10 2.0 ID = 250µA 1.5 1.0 0 25 50 75 100 125 150 -75 -50 -25 175 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) T C , Case Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature Thermal Response ( Z thJC ) 10 D = 0.50 1 R1 R1 0.20 τJ 0.10 0.05 R3 R3 τC τ τ1 τ2 τ2 τ3 τ3 τ4 τi (sec) Ri (°C/W) R4 R4 τ4 Ci= τi/Ri Ci i/Ri 0.02 0.01 0.1 τJ τ1 R2 R2 1.1512 0.000082 2.2284 0.000897 0.3256 0.053599 0.0448 0.074119 P DM t1 SINGLE PULSE ( THERMAL RESPONSE ) t2 Notes: 1. Duty factor D = 2. Peak T t 1/ t 2 J = P DM x Z thJC +T C 0.01 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U3715Z 15V D.U.T RG + V - DD IAS 20V VGS A 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS , Single Pulse Avalanche Energy (mJ) DRIVER L VDS 80 ID 4.2A 6.9A BOTTOM 12A 70 TOP 60 50 40 30 20 10 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy vs. Drain Current I AS LD VDS Fig 12b. Unclamped Inductive Waveforms VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF .3µF D.U.T. + V - DS Fig 14a. Switching Time Test Circuit VDS 90% VGS 3mA IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit 10% VGS td(on) tr td(off) tf Fig 14b. Switching Time Waveforms 6 www.irf.com IRLR/U3715Z D.U.T Driver Gate Drive + + P.W. - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer D= Period V DD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRLR/U3715Z Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput Q + oss × Vin × f + (Qrr × Vin × f ) 2 This can be expanded and approximated by; *dissipated primarily in Q1. Ploss = (Irms 2 × Rds(on ) ) Qgd +I × × Vin × ig Qgs 2 f + I × × Vin × f ig + (Qg × Vg × f ) + Qoss × Vin × f 2 This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRLR/U3715Z D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 2.38 (.094) 2.19 (.086) 6.73 (.265) 6.35 (.250) 1.14 (.045) 0.89 (.035) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 0.58 (.023) 0.46 (.018) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 10.42 (.410) 9.40 (.370) LEAD ASSIGNMENTS 1 - GATE 3 0.51 (.020) MIN. -B1.52 (.060) 1.15 (.045) 2X 2 - DRAIN 3 - SOURCE 4 - DRAIN 0.89 (.035) 3X 0.64 (.025) 1.14 (.045) 0.76 (.030) 0.25 (.010) 0.58 (.023) 0.46 (.018) M A M B NOTES: 2.28 (.090) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 4.57 (.180) 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). D-Pak (TO-252AA) Part Marking Information Notes : T his part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 9U1P INT ERNATIONAL RECTIFIER LOGO IRFU120 016 9U 1P DAT E CODE YEAR = 0 WEEK = 16 ASS EMBLY LOT CODE Notes : T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN T HE AS SEMBLY LINE "A" INT ERNATIONAL RECTIFIER LOGO IRFU120 12 ASS EMBLY LOT CODE www.irf.com PART NUMBER 916A 34 DATE CODE YEAR 9 = 1999 WEEK 16 LINE A 9 IRLR/U3715Z I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) 2.38 (.094) 2.19 (.086) -A- 0.58 (.023) 0.46 (.018) 1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) LEAD ASSIGNMENTS 4 1 - GATE 2 - DRAIN 6.45 (.245) 5.68 (.224) 1 2 3 -B2.28 (.090) 1.91 (.075) 3X 3 - SOURCE 4 - DRAIN 6.22 (.245) 5.97 (.235) 1.52 (.060) 1.15 (.045) 1.14 (.045) 0.76 (.030) 2.28 (.090) 3X 9.65 (.380) 8.89 (.350) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 0.89 (.035) 0.64 (.025) 1.14 (.045) 0.89 (.035) 0.25 (.010) M A M B 2X 0.58 (.023) 0.46 (.018) I-Pak (TO-251AA) Part Marking Information Notes : T his part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 9U1P INTERNATIONAL RECT IFIER LOGO IRFU120 016 9U 1P DAT E CODE YEAR = 0 WEEK = 16 AS SEMBLY LOT CODE Notes : T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 5678 AS SEMBLED ON WW 19, 1999 IN T HE ASS EMBLY LINE "A" INTERNATIONAL RECT IFIER LOGO ASS EMBLY LOT CODE 10 PART NUMBER IRFU120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A www.irf.com IRLR/U3715Z D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Notes: Repetitive rating; pulse width limited by Calculated continuous current based on maximum allowable max. junction temperature. Starting TJ = 25°C, L = 0.27mH, RG = 25Ω, IAS = 12A. Pulse width ≤ 400µs; duty cycle ≤ 2%. When mounted on 1" square PCB (FR-4 or G-10 Material). junction temperature. Package limitation current is 30A. For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 04/03 www.irf.com 11 Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/