a CMOS 12-Bit Buffered Multiplying DAC AD7545A FUNCTIONAL BLOCK DIAGRAM FEATURES Improved Version of AD7545 Fast Interface Timing All Grades 12-Bit Accurate 20-Lead DIP and Surface Mount Packages Low Cost GENERAL DESCRIPTION The AD7545A, a 12-bit CMOS multiplying DAC with internal data latches, is an improved version of the industry standard AD7545. This new design features a WR pulse width of 100 ns, which allows interfacing to a much wider range of fast 8-bit and 16-bit microprocessors. It is loaded by a single 12-bit-wide word under the control of the CS and WR inputs; tying these control inputs low makes the input latches transparent, allowing unbuffered operation of the DAC. PIN CONFIGURATIONS DIP/SOIC LCCC PLCC REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD7545A–SPECIFICATIONS (V REF = ⴞ10 V, VOUT1 = O V, AGND = DGND unless otherwise noted) Version VDD = +5 V Limits TA = + 25ⴗC TMIN –TMAX1 VDD = +15 V Limits TA = + 25ⴗC TMIN –TMAX1 Units All K, B, T L, C, U All 12 ± 1/2 ± 1/2 ±1 12 ± 1/2 ± 1/2 ±1 12 ± 1/2 ± 1/2 ±1 12 ± 1/2 ± 1/2 ±1 Bits LSB max LSB max LSB max K, B, T L, C, U All All ±3 ±1 ±5 ±2 ±4 ±2 ±5 ±2 ±3 ±1 ±5 ±2 ±4 ±2 ±5 ±2 LSB max LSB max ppm/°C max ppm/°C typ All K, L B, C T, U 0.002 10 10 10 0.004 50 50 200 0.002 10 10 10 0.004 50 50 200 % per % max nA max nA max nA max ∆VDD = ± 5% DB0–DB11 = 0 V; WR, CS = 0 V All 1 1 1 1 µs max To 1/2 LSB. OUT1 Load = 100 Ω, CEXT = 13 pF. DAC Output Measured from Falling Edge of WR, CS = 0 V. Propagation Delay 2 (from Digital Input Change to 90% of Final Analog Output) Digital-to-Analog Glitch Impulse All All 200 5 – – 150 5 – – ns max nV sec typ OUT1 Load = 100 Ω, CEXT = 13 pF3 VREF = AGND. OUT1 Load = 100 Ω, Alternately Loaded with All 0s and 1s. AC Feedthrough 2, 4 At OUT1 All 5 5 5 5 mV p-p typ VREF = ± 10 V, 10 kHz Sine Wave All 10 20 10 20 10 20 10 20 kΩ min kΩ max Input Resistance TC = –300 ppm/°C typ Typical Input Resistance = 15 kΩ All 70 150 70 150 70 150 70 150 pF max pF max DB0–DB11 = 0 V, WR, CS = 0 V DB0–DB11 = VDD, WR, CS = 0 V All 2.4 2.4 13.5 13.5 V min All 0.8 0.8 1.5 1.5 V max All ±1 ± 10 ±1 ± 10 µA max All 8 8 8 8 pF max K, B, L, C T, U 100 100 130 170 75 75 85 95 ns min ns min All K, B, L, C T, U 0 100 100 0 130 170 0 75 75 0 85 95 ns min ns min ns min All 100 150 60 80 ns min All 5 5 5 5 ns min All All 5 2 100 10 5 2 100 10 15 2 100 10 15 2 100 10 V mA max µA max µA typ Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Temperature Coefficient 2 ∆Gain/∆Temperature DC Supply Rejection 2 ∆Gain/∆VDD Output Leakage Current at OUT1 DYNAMIC PERFORMANCE Current Settling Time 2 REFERENCE INPUT Input Resistance (Pin 19 to GND) ANALOG OUTPUTS Output Capacitance 2 COUT1 COUT1 DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Current5 IIN Input Capacitance2 DB0–DB11, WR, CS SWITCHING CHARACTERISTICS 2 Chip Select to Write Setup Time tCS Chip Select to Write Hold Time tCH Write Pulse Width tWR Data Setup Time tDS Data Hold Time tDH POWER SUPPLY VDD IDD Test Conditions/Comments Endpoint Measurement All Grades Guaranteed 12-Bit Monotonic Over Temperature Measured Using Internal RFB. DAC Register Loaded with All 1s. VIN = 0 or VDD See Timing Diagram tCS ≥ tWR, TCH ≥ 0 ± 5% For Specified Performance All Digital Inputs VIL or VIH All Digital Inputs 0 V or V DD All Digital Inputs 0 V or V DD NOTES 1 Temperature range as follows: K, L Versions = 0°C to +70°C; B, C Versions = –25°C to +85°C; T, U Versions = –55°C to +125°C. 2 Sample tested to ensure compliance. 3 DB0–DB11 = 0 V to VDD or VDD to 0 V. 4 Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND. 6 Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA. Specifications subject to change without notice. –2– REV. C AD7545A WRITE CYCLE TIMING DIAGRAM Operating Temperature Range Commercial (KN, LN, KP, LP) Grades . . . 0°C to +70°C Industrial (BQ, CQ, BE, CE) Grades . . . . –25°C to +85°C Extended (TQ, UQ, TE, UE) Grades . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C ABSOLUTE MAXIMUM RATINGS* (TA = + 25°C unless otherwise noted) VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD +0.3 V VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V VPIN1 to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model1 Temperature Range Relative Gain Accuracy Error TMIN –TMAX TMIN –TMAX Package Options2 AD7545AKN AD7545ALN AD7545AKR AD7545AKP AD7545ALP AD7545ABQ AD7545ACQ AD7545ABE AD7545ACE AD7545ATQ AD7545AUQ AD7545ATE AD7545AUE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –25°C to +85°C –25°C to +85°C –25°C to +85°C –25°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 ± 1/2 N-20 N-20 R-20 P-20A P-20A Q-20 Q-20 E-20A E-20A Q-20 Q-20 E-20A E-20A ±4 ±2 ±4 ±4 ±2 ±4 ±2 ±4 ±2 ±4 ±2 ±4 ±2 NOTES 1 To order MIL-STD-883, Class B process parts, add /883B to part number. Contact local sales office for military data sheet. 2 E = Leadless Ceramic Chip Carrier (LCCC); N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC. REV. C –3– AD7545A input buffers operate in their linear region and draw current from the power supply. To minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails (VDD and DGND) as is practically possible. CIRCUIT INFORMATION—D/A CONVERTER SECTION Figure 1 shows a simplified circuit of the D/A converter section of the AD7545A, and Figure 2 gives an approximate equivalent circuit. Note that the ladder termination resistor is connected to AGND. R is typically 15 kΩ. The AD7545A may be operated with any supply voltage in the range 5 ≤ VDD ≤ 15 volts. With VDD = +15 V the input logic levels are CMOS compatible only, i.e., 1.5 V and 13.5 V. The binary weighted currents are switched between the OUT1 bus line and AGND by N-channel switches, thus maintaining a constant current in each ladder leg independent of the switch state. BASIC APPLICATIONS Figures 4 and 5 show simple unipolar and bipolar circuits using the AD7545A. Resistor R1 is used to trim for full scale. The L, C, U grades have a guaranteed maximum gain error of ± 1 LSB at +25°C, and in many applications it should be possible to dispense with gain trim resistors altogether. Capacitor C1 provides phase compensation and helps prevent overshoot and ringing when using high speed op amps. Note that all the circuits of Figures 4, 5 and 6 have constant input impedance at the VREF terminal. The circuit of Figure 4 can either be used as a fixed reference D/A converter so that it provides an analog output voltage in the range 0 to –VIN (note the inversion introduced by the op amp) or VIN can be an ac signal in which case the circuit behaves as an attenuator (2-Quadrant Multiplier). VIN can be any voltage in the range –20 ≤ VIN ≤ +20 volts (provided the op amp can handle such voltages) since VREF is permitted to exceed VDD. Table II shows the code relationship for the circuit of Figure 4. Figure 1. Simplified D/A Circuit of AD7545A The capacitance at the OUT1 bus line, COUT1, is codedependent and varies from 70 pF (all switches to AGND) to 150 pF (all switches to OUT1). One of the current switches is shown in Figure 2. The input resistance at VREF (Figure 1) is always equal to R. Since RIN at the VREF pin is constant, the reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. (If a current source is used, a low temperature coefficient external RFB is recommended to define scale factor.) Figure 4. Unipolar Binary Operation Table I. Recommended Trim Resistor Values vs. Grades Figure 2. N-Channel Current Steering Switch CIRCUIT INFORMATION—DIGITAL SECTION Trim Resistor K/B/T L/C/U R1 R2 200 Ω 68 Ω 100 Ω 33 Ω Figure 3 shows the digital structure for one bit. Table II. Unipolar Binary Code Table for Circuit of Figure 4 The digital signals CONTROL and CONTROL are generated from CS and WR. Binary Number in DAC Register Analog Output 1111 1111 1111 4095 –VIN 4096 1000 0000 0000 2048 –VIN 4096 = –1/2 VIN 0000 0000 0001 0000 0000 0000 1 –VIN 4096 0 Volts Figure 3. Digital Input Structure The input buffers are simple CMOS inverters designed such that when the AD7545A is operated with VDD = 5 V, the buffers convert TTL input levels (2.4 V and 0.8 V) into CMOS logic levels. When VIN is in the region of 2.0 volts to 3.5 volts, the –4– REV. C AD7545A Figure 5 and Table III illustrate the recommended circuit and code relationship for bipolar operation. The D/A function itself uses offset binary code and inverter U1 on the MSB line converts twos complement input code to offset binary code. If appropriate, inversion of the MSB may be done in software using an exclusive –OR instruction and the inverter omitted. R3, R4 and R5 must be selected to match within 0.01%, and they should be the same type of resistor (preferably wire-wound or metal foil), so that their temperature coefficients match. Mismatch of R3 value to R4 causes both offset and full-scale error. Mismatch of R5 to R4 and R3 causes full-scale error. Figure 6. 12-Bit Plus Sign Magnitude Converter Table IV. 12-Bit Plus Sign Magnitude Code Table for Circuit of Figure 6 Sign Bit Binary Numbers in DAC Register 0 1111 1111 1111 0 1 0000 0000 0000 0000 0000 0000 1 1111 1111 1111 Figure 5. Bipolar Operation (Twos Complement Code) Analog Output 4095 + VIN × 4096 0 Volts 0 Volts 4095 – VIN × 4096 Note: Sign bit of “0” connects R3 to GND. Table III. Twos Complement Code Table for Circuit of Figure 5 Data Input APPLICATIONS HINTS Output Offset: CMOS D/A converters such as Figures 4, 5 and 6 exhibit a code dependent output resistance which, in turn, can cause a code dependent error voltage at the output of the amplifier. The maximum amplitude of this error, which adds to the D/A converter nonlinearity, depends on VOS, where VOS is the amplifier input offset voltage. To maintain specified accuracy with VREF at 10 V, it is recommended that VOS be no greater than 0.25 mV, or (25 × 10–6 ) (VREF), over the temperature range of operation. Suitable op amps are AD517 and AD711. The AD517 is best suited for fixed reference applications with low bandwidth requirements: it has extremely low offset (150 µV max for lowest grade) and in most applications will not require an offset trim. The AD711 has a much wider bandwidth and higher slew rate and is recommended for multiplying and other applications requiring fast settling. An offset trim on the AD711 may be necessary in some circuits. Analog Output 0111 1111 1111 2047 +VIN × 2048 0000 0000 0001 0000 0000 0000 1 +VIN × 2048 0 Volts 1111 1111 1111 1 –VIN × 2048 1000 0000 0000 2048 –VIN × 2048 General Ground Management: AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7545A. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7545A AGND and DGND pins (1N914 or equivalent). Figure 6 and Table IV show an alternative method of achieving bipolar output. The circuit operates with sign plus magnitude code and has the advantage that it gives 12-bit resolution in each quadrant compared with 11-bit resolution per quadrant for the circuit of Figure 5. The AD7592 is a fully protected CMOS change-over switch with data latches. R4 and R5 should match each other to 0.01% to maintain the accuracy of the D/A converter. Mismatch between R4 and R5 introduces a gain error. Refer to Reference 1 (supplemental application material) for additional information on these circuits. REV. C –5– AD7545A Invalid Data: When WR and CS are both low, the latches are transparent and the D/A converter inputs follow the data inputs. In some bus systems, data on the data bus is not always valid for the whole period during which WR is low, and as a result invalid data can briefly occur at the D/A converter inputs during a write cycle. Such invalid data can cause unwanted signals or glitches at the output of the D/A converter. The solution to this problem, if it occurs, is to retime the write pulse, WR, so it only occurs when data is valid. The loading on the reference voltage source is code-dependent and the response time of the circuit is often determined by the behavior of the reference voltage with changing load conditions. To maintain linearity, the voltages at OUT1 and AGND should remain within 2.5 volts of each other, for a VDD of 15 volts. If VDD is reduced from 15 V, or the differential voltage between OUT1 and AGND is increased to more than 2.5 V, the differential nonlinearity of the DAC will increase and the linearity of the DAC will be degraded. Figures 8 and 9 show typical curves illustrating this effect for various values of reference voltage and VDD. If the output voltage is required to be offset from ground by some value, then OUT1 and AGND may be biased up. The effect on linearity and differential nonlinearity will be the same as reducing VDD by the amount of the offset. Digital Glitches: Digital glitches result due to capacitive coupling from the digital lines to the OUT1 and AGND terminals. This should be minimized by screening the analog pins of the AD7545A (Pins 1, 2, 19, 20) from the digital pins by a ground track run between Pins 2 and 3 and between Pins 18 and 19 of the AD7545A. Note how the analog pins are at one end (DIP) or side (LCC and PLCC) of the package and separated from the digital pins by VDD and DGND to aid screening at the board level. On-chip capacitive coupling can also give rise to crosstalk from the digitalto-analog sections of the AD7545A, particularly in circuits with high currents and fast rise and fall times. This type of crosstalk is minimized by using VDD = +5 volts. However, great care should be taken to ensure that the +5 V used to power the AD7545A is free from digitally induced noise. Temperature Coefficients: The gain temperature coefficient of the AD7545A has a maximum value of 5 ppm/°C and a typical value of 2 ppm/°C. This corresponds to worst case gain shifts of 2 LSBs and 0.8 LSBs respectively over a 100°C temperature range. When trim resistors R1 and R2 (such as in Figure 4) are used to adjust full-scale range, the temperature coefficient of R1 and R2 should also be taken into account. The reader is referred to Analog Devices Application Note “Gain Error and Gain Temperature Coefficient to CMOS Multiplying DACs,” Publication Number E630c–5–3/86. Figure 8. Differential Nonlinearity vs. VDD for Figure 7 Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows Range of Values of Differential Nonlinearity that Typically Occur for all Grades. SINGLE SUPPLY OPERATION The ladder termination resistor of the AD7545A (Figure 1) is connected to AGND. This arrangement is particularly suitable for single supply operation because OUT1 and AGND may be biased at any voltage between DGND and VDD. OUT1 and AGND should never go more than 0.3 volts less than DGND or an internal diode will be turned on and a heavy current may flow that will damage the device. (The AD7545A is, however, protected from the SCR latchup phenomenon prevalent in many CMOS devices.) Figure 7 shows the AD7545A connected in a voltage switching mode. OUT1 is connected to the reference voltage and AGND is connected to DGND. The D/A converter output voltage is available at the VREF pin and has a constant output impedance equal to R. RFB is not used in this circuit and should be tied to OUT1 to minimize stray capacitance effects. Figure 9. Differential Nonlinearity vs. Reference Voltage for Figure 7 Circuit. VDD = 15 Volts. Shaded Area Shows Range of Values of Differential Nonlinearity that Typically Occur for all Grades. Figure 7. Single Supply Operation Using Voltage Switching Mode –6– REV. C AD7545A The circuits of Figures 4, 5 and 6 can all be converted to single supply operation by biasing AGND to some voltage between VDD and DGND. Figure 10 shows the 2s Complement Bipolar circuit of Figure 5 modified to give a range from +2 V to +8 V about a “pseudo-analog ground” of 5 V. This voltage range would allow operation from a single VDD of +10 V to +15 V. The AD584 pin-programmable reference fixes AGND at +5 V. VIN is set at +2 V by means of the series resistors R1 and R2. Figure 12 shows an alternative approach for use with 8-bit processors which have a full 16-bit wide address bus such as 6800, 8080, Z80. This technique uses the 12 lower address lines of the processor address bus to supply data to the DAC, thus each AD7545A connected in this way uses 4k bytes of address locations. Data is written to the DAC using a single memory write instruction. The address field of the instruction is organized so that the lower 12 bits contain the data for the DAC and the upper 4 bits contain the address of the 4k block at which the DAC resides. There is no need to buffer the VREF input to the AD7545A with an amplifier because the input impedance of the D/A converter is constant. Note, however, that since the temperature coefficient of the D/A reference input resistance is typically –300 ppm/°C, applications which experience wide temperature variations may require a buffer amplifier to generate the +2.0 V at the AD7545A VREF pin. Other output voltage ranges can be obtained by changing R4 to shift the zero point and (R1 + R2) to change the slope, or gain of the D/A transfer function. VDD must be kept at least 5 V above OUT1 to ensure that linearity is preserved. Figure 12. Connecting the AD7545A to 8-Bit Processors via the Address Bus SUPPLEMENTAL APPLICATION MATERIAL For further information on CMOS multiplying D/A converters the reader is referred to the following texts: Figure 10. Single Supply "Bipolar" 2s Complement D/A Converter Reference 1 CMOS DAC Application Guide available from Analog Devices, Publication Number G872a-15-4/86. MICROPROCESSOR INTERFACING OF THE AD7545A The AD7545A can interface directly to both 8- and 16-bit microprocessors via its 12-bit wide data latch using standard CS and WR control signals. Reference 2 Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs – Application Note, Publication Number E630c–5–3/86. A typical interface circuit for an 8-bit processor is shown in Figure 11. This arrangement uses two memory addresses, one for the lower 8 bits of data to the DAC and one for the upper 4 bits of data into the DAC via the latch. Reference 3 Analog-Digital Conversion Handbook (Third Edition) available from Prentice-Hall. Figure 11. 8-Bit Processor to AD7545 Interface REV. C –7– AD7545A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead SOIC (R-20) 20-Lead Plastic DIP (N-20) 1 10 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45° 0.0098 (0.25) 8° 0.0500 0.0192 (0.49) 0° (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 20-Lead Cerdip (Q-20) 20-Terminal Leadless Ceramic Chip Carrier (E-20A) 20-Terminal Plastic Leadless Chip Carrier (P-20A) PRINTED IN U.S.A. PIN 1 C1022–0–3/00 (rev. C) 11 0.4193 (10.65) 0.3937 (10.00) 20 0.2992 (7.60) 0.2914 (7.40) 0.5118 (13.00) 0.4961 (12.60) –8– REV. C