19-0168; Rev 3; 7/95 +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC ________________________Applications Battery-Powered Data-Conversion Products Minimum Component-Count Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Arbitrary Function Generators Automatic Test Equipment Microprocessor-Controlled Calibration ________________Functional Diagram REFOUT 18 REFIN 13 ROFS 22 AGND 20 17 A0 A1 12-BIT DAC LATCH 8 9 CS 11 WR 10 LDAC MAX530 15 CONTROL LOGIC NBL INPUT LATCH ♦ ♦ ♦ ♦ ______________Ordering Information PART TEMP. RANGE PIN-PACKAGE ERROR (LSB) MAX530ACNG 0°C to +70°C 24 Narrow Plastic DIP ±1/2 MAX530BCNG 0°C to +70°C 24 Narrow Plastic DIP MAX530ACWG 0°C to +70°C 24 Wide SO MAX530BCWG 0°C to +70°C 24 Wide SO MAX530ACAG 0°C to +70°C 24 SSOP MAX530BCAG 0°C to +70°C 24 SSOP MAX530BC/D 0°C to +70°C Dice* Ordering Information continued on last page. * Dice are tested at TA = +25°C, DC parameters only. ±1 ±1/2 ±1 ±1/2 ±1 ±1 __________________Pin Configuration D1/D9 1 24 D0/D8 D2/D10 2 23 VDD D3/D11 3 22 ROFS D4 4 23 POWER-ON RESET CLR VOUT DAC LATCH 14 ♦ ♦ Buffered Voltage Output Internal 2.048V Voltage Reference Operates from Single +5V or Dual ±5V Supplies Low Power Consumption: 250µA Operating Current 40µA Shutdown-Mode Current SSOP Package Saves Space Relative Accuracy: ±1/2 LSB Max Over Temperature Guaranteed Monotonic Over Temperature 4-Quadrant Multiplication with No External Components Power-On Reset Double-Buffered Parallel Logic Inputs TOP VIEW 21 RFB 2.048V REFERENCE REFGND ____________________________Features ♦ ♦ ♦ ♦ NBM INPUT LATCH 16 24 1 2 3 4 5 6 7 D4 D6 D0/D8 D2/D10 D1/D9 D3/D11 D5 D7 NBH INPUT LATCH 12 19 VDD D5 5 21 RFB MAX530 20 VOUT DGND D6 6 19 VSS VSS D7 7 18 REFOUT A0 8 17 REFGND A1 9 16 LDAC WR 10 15 CLR CS 11 14 AGND DGND 12 13 REFIN DIP/SO/SSOP ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. 1 MAX530 _______________General Description The MAX530 is a low-power, 12-bit, voltage-output digital-to-analog converter (DAC) that uses single +5V or dual ±5V supplies. This device has an on-chip voltage reference plus an output buffer amplifier. Operating current is only 250µA from a single +5V supply, making it ideal for portable and battery-powered applications. In addition, the SSOP (Shrink-Small-Outline-Package) measures only 0.1 square inches, using less board area than an 8-pin DIP. 12-bit resolution is achieved through laser trimming of the DAC, op amp, and reference. No further adjustments are necessary. Internal gain-setting resistors can be used to define a DAC output voltage range of 0V to +2.048V, 0V to +4.096V, or ±2.048V. Four-quadrant multiplication is possible without the use of external resistors or op amps. The parallel logic inputs are double buffered and are compatible with 4-bit, 8-bit, and 16-bit microprocessors. For DACs with similar features but with a serial data interface, refer to the MAX531/MAX538/MAX539 data sheet. MAX530 +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC ABSOLUTE MAXIMUM RATINGS VOUT to AGND (Note 1) .............................................. VSS, VDD Continuous Current, Any Input ........................................±20mA Continuous Power Dissipation (TA = +70°C) Narrow Plastic DIP (derate 13.33mW/°C above +70°C)......1067mW Wide SO (derate 11.76mW/°C above +70°C) .......... 941mW SSOP (derate 8.00mW/°C above +70°C) ..................640mW Operating Temperature Ranges: MAX530_C_ _ ...................................................0°C to +70°C MAX530_E_ _ ................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +165°C Lead Temperature (soldering, 10sec ) .......................... +300°C VDD to DGND and VDD to AGND ................................-0.3V, +6V VSS to DGND and VSS to AGND .................................-6V, +0.3V VDD to VSS ............................................................... -0.3V, +12V AGND to DGND........................................................-0.3V, +0.3V REFGND to AGND........................................-0.3V, (VDD + 0.3V) Digital Input Voltage to DGND ................... -0.3V, (VDD + 0.3V) REFIN .................................................(VSS - 0.3V), (VDD + 0.3V) REFOUT .............................................(VSS - 0.3V), (VDD + 0.3V) REFOUT to REFGND ................................... -0.3V, (VDD + 0.3V) RFB ...................................................(VSS - 0.3V), (VDD + 0.3V) ROFS .................................................(VSS - 0.3V), (VDD + 0.3V) Note 1: The output may be shorted to VDD, VSS, DGND, or AGND if the continuous package power dissipation and current ratings are not exceeded. Typical short-circuit currents are 20mA. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—Single +5V Supply (VDD = 5V ±10%, VSS = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, CREFOUT = 33µF, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 12 Relative Accuracy INL VDD = 5V (Note 2) Differential Nonlinearity DNL Guaranteed monotonic Unipolar Offset Error VOS VDD = 5V Unipolar Offset Temperature Coefficient TCVOS Unipolar Offset-Error Power-Supply Rejection PSRR Gain Error (Note 2) GE ±0.5 MAX530BC/BE ±1 MAX530_C/E 0 1 4.5V ≤ VDD ≤ 5.5V (Note 3) DAC latch = all 1s, VOUT < VDD - 0.4V (Note 2) 0.4 MAX530_C/E LSB 8 LSB ppm/°C 1 LSB/V ±1 LSB 1 PSRR 4.5V ≤ VDD ≤ 5.5V (Note 3) 0.4 LSB ±1 3 Gain-Error Temperature Coefficient Gain-Error Power-Supply Rejection Bits MAX530AC/AE ppm/°C 1 LSB/V DAC VOLTAGE OUTPUT (VOUT) Output Voltage Range 0 VOUT = 2V, load regulation ≤ ±1LSB Resistive Load DC Output Impedance Short-Circuit Current VDD - 0.4 2 ISC V kΩ 0.2 Ω 20 mA REFERENCE INPUT (REFIN) Reference Input Range 0 Reference Input Resistance Code dependent, minimum at code 555hex 40 Reference Input Capacitance Code dependent (Note 4) 10 AC Feedthrough (Note 5) 2 VDD - 2 V kΩ 50 -80 _______________________________________________________________________________________ pF dB +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC (VDD = 5V ±10%, VSS = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, CREFOUT = 33µF, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX TA = +25°C 2.024 2.048 2.072 MAX530BC 2.017 2.079 MAX530BE 2.013 2.083 UNITS REFERENCE OUTPUT (REFOUT) Reference Tolerance VREFOUT Reference Output Resistance RREFOUT Power-Supply Rejection Ratio PSRR Noise Voltage en Temperature Coefficient Minimum Required External Capacitor VDD = 5.0V (Note 8) 4.5V ≤ VDD ≤ 5.5V 0.1Hz to 10kHz 400 MAX530AC/AE 30 MAX530BC/BE 30 CMIN V 2 Ω 300 µV/V µVp-p 50 3.3 ppm/°C µF DYNAMIC PERFORMANCE Voltage Output Slew Rate TA = +25°C Voltage Output Settling Time To ±0.5LSB, VOUT = 2V 25 µs Digital Feedthrough WR = VDD, digital inputs all 1s to all 0s 5 nV-s Unity gain (Note 5) 68 Gain = 2 (Note 5) 68 Signal-to-Noise Plus Distortion Ratio SINAD 0.15 0.25 V/µs dB DIGITAL INPUTS (D0-D7, LDAC, CLR, CS, WR, A0, A1) Logic High Input VIH Logic Low Input VIL Digital Leakage Current 2.4 V VIN = 0V or VDD Digital Input Capacitance 0.8 V ±1 µA 8 pF POWER SUPPLIES Positive Supply-Voltage Range VDD (Note 6) Positive Supply Current IDD Outputs unloaded, all digital inputs = 0V or VDD 4.5 250 5.5 V 400 µA SWITCHING CHARACTERISTICS Address to WR Setup tAWS 5 ns Address to WR Hold tAWH 5 ns CS to WR Setup tCWS 0 ns CS to WR Hold 0 ns Data to WR Setup tCWH tDS 45 ns Data to WR Hold tDH 0 ns WR Pulse Width tWR 45 ns tLDAC 45 ns tCLR 45 LDAC Pulse Width CLR Pulse Width Internal Power-On Reset Pulse Width tPOR (Note 4) ns 1.3 10 µs _______________________________________________________________________________________ 3 MAX530 ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued) MAX530 +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (VDD = 5V ±10%, VSS = -5V ±10%, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, CREFOUT = 33µF, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 12 Relative Accuracy INL VDD = 5V, VSS = -5V Differential Nonlinearity DNL Guaranteed monotonic Bipolar Offset Error VOS VDD = 5V, VSS = -5V Bipolar Offset Temperature Coefficient TCVOS Bipolar Offset-Error Power-Supply Rejection PSRR Gain Error Bits MAX530AC/AE ±0.5 MAX530BC/BE ±1.5 MAX530_C/E 0 0.4 MAX530_C/E Gain-Error Temperature Coefficient TC Gain-Error Power-Supply Rejection PSRR ±1 LSB ±8 LSB 3 4.5V ≤ VDD ≤ 5.5V -5.5V ≤ VSS ≤ -4.5V (Note 3) ppm/°C 1 ±1 1 4.5V ≤ VDD ≤ 5.5V, -5.5V ≤ VSS ≤ -4.5V (Note 3) 0.4 LSB LSB/V LSB ppm/°C 1 LSB/V DAC VOLTAGE OUTPUT (VOUT) Output Voltage Range VSS + 0.4 VOUT = 2V, load regulation ≤ ±1LSB Resistive Load DC Output Impedance Short-Circuit Current VDD - 0.4 2 ISC V kΩ 0.2 Ω 20 mA REFERENCE INPUT (REFIN) Reference Input Range VSS + 2 Reference Input Resistance Code dependent, minimum at code 555hex 40 Reference Input Capacitance Code dependent (Note 4) 10 AC Feedthrough (Note 5) VDD - 2 V kΩ 50 -80 pF dB REFERENCE OUTPUT (REFOUT)—Specifications are identical to those under Single +5V Supply DYNAMIC PERFORMANCE—Specifications are identical to those under Single +5V Supply DIGITAL INPUTS (D0-D7, LDAC, CLR, CS, WR, A0, A1)—Specifications are identical to those under Single +5V Supply POWER SUPPLIES Positive Supply Voltage VDD (Note 6) 4.5 5.5 Negative Supply Voltage VSS (Note 7) -5.5 -4.5 V Positive Supply Current IDD Outputs unloaded, all digital inputs = 0V or VDD 250 400 µA Negative Supply Current ISS Outputs unloaded, all digital inputs = 0V or VDD 150 200 µA SWITCHING CHARACTERISTICS—Specifications are identical to those under Single +5V Supply 4 _______________________________________________________________________________________ V +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC MAX530 ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (continued) (VDD = 5V ±10%, VSS = -5V ±10%, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, CREFOUT = 33µF, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) Note 2: In single supply, INL and GE are calculated from code 11 to code 4095. Note 3: Zero Code, Bipolar and Gain Error PSRR are input referred specifications. In Unity Gain, the specification is 500µV. In Gain = 2 and Bipolar modes, the specification is 1mV. Note 4: Guaranteed by design. Note 5: REFIN = 1kHz, 2.0Vp-p. Note 6: For specified performance, VDD = 5V ±10% is guaranteed by PSRR tests. Note 7: For specified performance, VSS = -5V ±10% is guaranteed by PSRR tests. Note 8: Tested at IOUT = 100µA. The reference can typically source up to 5mA (see Typical Operating Characteristics). __________________________________________Typical Operating Characteristics (TA = +25°C, single supply (+5V), unity gain, code = all 1s, unless otherwise noted). INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (11–4095) 14 -1.00 -1.25 -0.25 -0.50 SINGLE SUPPLY 2 6 4 8 10 4 2 0 512 1024 1536 2048 2560 3072 3584 4095 0.2 0.4 0.6 0.8 DIGITAL INPUT CODE (DECIMAL) OUTPUT PULL-DOWN VOLTAGE (V) OUTPUT SOURCE CAPABILITY vs. OUTPUT PULL-UP VOLTAGE ANALOG FEEDTHROUGH vs. FREQUENCY REFERENCE VOLTAGE vs. TEMPERATURE -110 MAX531-4 7 -100 ANALOG FEEDTHROUGH (dB) OUTPUT SOURCE CAPABILITY (mA) 6 DIGITAL INPUT CODE (DECIMAL) 8 6 5 4 3 2 1 -90 -80 -70 REFIN = 2Vp-p -60 -50 -40 -30 2 3 4 OUTPUT PULL-UP VOLTAGE (V) 5 2.050 CODE = ALL 0s, DUAL SUPPLIES (±5V) 2.045 0 1 2.055 1.0 -20 -10 0 0 8 0 11 12 12 10 MAX531-6 0 0 MAX531-5 0 REFERENCE VOLTAGE (V) INTEGRAL NONLINEARITY (LSB) DUAL SUPPLIES OUTPUT SINK CAPABILITY (mA) 16 MAX530-1 0.25 0.25 MAX531-3 OUTPUT SINK CAPABILITY vs. OUTPUT PULL-DOWN VOLTAGE INTEGRAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (0–11) 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) _______________________________________________________________________________________ 5 +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC MAX530 ____________________________Typical Operating Characteristics (continued) (TA = +25°C, single supply (+5V), unity gain, code = all 1s, unless otherwise noted). -2 270 260 -4 -6 -8 250 DUAL SUPPLIES (±5V) -10 240 REFIN = 4Vp-p SIGNAL-TO-NOISE RATIO (dB) 0 280 80 MAX531-8 MAX530-7 REFIN = 4Vp-p 2 GAIN (dB) -20 0 20 40 60 80 100 TEMPERATURE (°C) MAX530-10 180 100 1k 10k 10 100k 0 0 PHASE -100 150 REFGND = VDD 50 -200 100k 2.0480 2.0475 200 100 10k REFERENCE OUTPUT VOLTAGE vs. REFERENCE LOAD CURRENT REFGND = AGND GAIN 1k 100 FREQUENCY (Hz) 250 SUPPLY CURRENT (µA) GAIN (dB) -100 DUAL SUPPLIES (±5V) SUPPLY CURRENT vs. REFIN PHASE SHIFT (Degrees) (G = 2) (G = 1) 30 20 FREQUENCY (Hz) GAIN AND PHASE vs. FREQUENCY -200 50 40 0 1 REFERENCE OUTPUT (V) -40 -14 MAX530-14 -60 60 10 -12 230 70 MAX530-15 SUPPLY CURRENT (µA) 290 AMPLIFIER SIGNAL-TO- NOISE RATIO GAIN vs. FREQUENCY 4 MAX531-9 SUPPLY CURRENT vs. TEMPERATURE 300 2.0470 2.0465 2.0460 2.0455 REFIN = EXTERNAL -180 -300 1 10 100 800 0 2.0450 0 FREQUENCY (kHz) 50 100 150 200 250 300 350 400 450 500 REFIN (mV) DIGITAL FEEDTHROUGH 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE LOAD CURRENT (mA) SETTLING TIME (RISING) SETTLING TIME (FALLING) A A A B B B 2µs/div A: D0...D7 = 100kHz, 4Vp-p B: VOUT, 10mV/div LDAC = CS = HIGH 6 5µs/div A: DIGITAL INPUTS RISING EDGE, B: VOUT, NO LOAD, 1V/div DUAL SUPPLY (±5V) LDAC = LOW BIPOLAR CONFIGURATION VREFIN = 2V 5µs/div A: DIGITAL INPUTS FALLING EDGE, 5V/div B: VOUT, NO LOAD, 1V/div DUAL SUPPLY (±5V) LDAC = LOW BIPOLAR CONFIGURATION VREFIN = 2V _______________________________________________________________________________________ +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC PIN NAME FUNCTION 1 D1/ D9 D1 Input Dta, when A0 = 0 and A1 = 1, or D9 Input when A0 = A1 = 1* 2 D2/ D10 D2 Input Dta, when A0 = 0 and A1 = 1, or D10 Input when A0 = A1 = 1* 3 D3/ D11 D3 Input Dta, when A0 = 0 and A1 = 1, or D11 (MSB) Input when A0 = A1 =1* 4 D4 D4 Input Dta, or tie to D0 and multiplex when A0 = 1 and A1 = 0* 5 D5 D5 Input Dta, or tie to D1 and multiplex when A0 = 1 and A1 = 0* 6 D6 D6 Input Dta, or tie to D2 and multiplex when A0 = 1 and A1 = 0* 7 D7 D7 Input Dta, or tie to D3 and multiplex when A0 = 1 and A1 = 0* 8 A0 Address Line A0. With A1, used to multiplex 4 of 12 data lines to load low (NBL), middle (NBM), and high (NBH) 4-bit nibbles. (12 bits can also be loaded as 8+4.) 9 A1 Address Line A1. Set A0 = A1 = 0 for NBL and NBM, A0 = 0 and A1 = 1 for NBL, A0 = 1 and A1 = 0 for NBM, or A0 = A1 = 1 for NBH. See Table 2 for complete input latch addressing. 10 WR Write Input (active low). Used with CS to load data into the input latch selected by A0 and A1. 11 CS Chip Select (active low). Enables addressing and writing to this chip from common bus lines. 12 DGND Digital Ground 13 REFIN Reference Input. Input for the R-2R DAC. Connect an external reference to this pin or a jumper to REFOUT (pin 18) to use the internal 2.048V reference. 14 AGND Analog Ground 15 CLR 16 LDAC Load DAC Input (active low). Driving this asynchronous input low transfers the contents of the input latch to the DAC latch and updates VOUT. 17 REFGND Reference Ground must be connected to AGND when using the internal reference. Connect to VDD to disable the internal reference and save power. 18 REFOUT Reference Output. Output of the internal 2.048V reference. Tie to REFIN to drive the R-2R DAC. 19 VSS 20 VOUT 21 RFB 22 ROFS 23 VDD 24 D0/D8 Clear (active low). A low on CLR resets the DAC latches to all 0s. Negative Power Supply. Usually ground for single-supply or -5V for dual-supply operation. Voltage Output. Op-amp buffered DAC output. Feedback Pin. Op-amp feedback resistor. Always connect to VOUT. Offset Resistor Pin. Connect to VOUT for G = 1, to AGND for G = 2, or to REFIN for bipolar output. Positive Power Supply (+5V) D0 (LSB) Input Dta when A0 = 0 and A1 = 1, or D8 Input when A0 = A1= 1* * This applies to 4 + 4 + 4 input loading mode. See Table 2 for 8 + 4 input loading mode. _______________________________________________________________________________________ 7 MAX530 ______________________________________________________________Pin Description MAX530 +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC ________________Detailed Description The MAX530 consists of a parallel-input logic interface, a 12-bit R-2R ladder, a reference, and an op amp. The Functional Diagram shows the control lines and signal flow through the input data latch to the DAC latch, as well as the 2.048V reference and output op amp. Total supply current is typically 250µA with a single +5V supply. This circuit is ideal for battery-powered, microprocessor-controlled applications where high accuracy, no adjustments, and minimum component count are key requirements. R-2R Ladder The MAX530 uses an “inverted” R-2R ladder network with a BiCMOS op amp to convert 12-bit digital data to analog voltage levels. Figure 1 shows a simplified diagram of the R-2R DAC and op amp. Unlike a standard DAC, the MAX530 uses an “inverted” ladder network. Normally, the REFIN pin is the current output of a standard DAC and would be connected to the summing junction, or virtual ground, of an op amp. In this standard DAC configura- tion, however, the output voltage would be the inverse of the reference voltage. The MAX530’s topology makes the ladder output voltage the same polarity as the reference input, which makes the device suitable for single-supply operation. The BiCMOS op amp is then used to buffer, invert, or amplify the ladder signal. Ladder resistors are nominally 80kΩ to conserve power and are laser trimmed for gain and linearity. The input impedance at REFIN is code dependent. When the DAC register is all 0s, all rungs of the ladder are grounded and REFIN is open or no load. Maximum loading (minimum REFIN impedance) occurs at code 010101... or 555hex. Minimum reference input impedance at this code is guaranteed to be not less than 40kΩ. The REFIN and REFOUT pins allow the user to choose between driving the R-2R ladder with the on-chip reference or an external reference. REFIN may be below analog ground when using dual supplies. See the External Reference and Four-Quadrant Multiplication sections for more information. Internal Reference 2R 2R MAX530 R 2R * 2R RFB R 2R ROFS R 2R LSB 2R VOUT OUTPUT BUFFER MSB R = 80kΩ REFIN AGND REFOUT LSB DAC LATCH MSB NBL INPUT LATCH NBM INPUT LATCH NBH INPUT LATCH CLR 2.048V REFGND D4 D6 D0/D8 D2/D10 D1/D9 D5 D7 D3/D11 *SHOWN FOR ALL 1s The on-chip reference is laser trimmed to generate 2.048V at REFOUT. The output stage can source and sink current so REFOUT can settle to the correct voltage quickly in response to code-dependent loading changes. Typically source current is 5mA and sink current is 100µA. REFOUT connects the internal reference to the R-2R DAC ladder at REFIN. The R-2R ladder draws 50µA maximum load current. If any other connection is made to REFOUT, ensure that the total load current is less than 100µA to avoid gain errors. A separate REFGND pin is provided to isolate reference currents from other analog and digital ground currents. To achieve specified noise performance, connect a 33µF capacitor from REFOUT to REFGND (see Figure 2). Using smaller capacitance values increases noise, and values less than 3.3µF may compromise the reference’s stability. For applications requiring the lowest noise, insert a buffered RC filter between REFOUT and REFIN. When using the internal reference, REFGND must be connected to AGND. In applications not requiring the internal reference, connect REFGND to VDD, which shuts down the reference and saves typically 100µA of VDD supply current. Figure 1. Simplified MAX530 DAC Circuit 8 _______________________________________________________________________________________ +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC TOTAL REFERERNCE NOISE CS CREFOUT REFERENCE NOISE (µVRMS) 250 1.6 CREFOUT = 3.3µF 1.4 200 1.2 1.0 150 0.8 100 0.6 0.4 50 CREFOUT = 47µF 0 0.1 1 10 100 REFERENCE NOISE (mVp-p) 1.8 SINGLE POLE ROLLOFF MAX531-FIG02 TEK 7A22 300 0.2 0.0 1000 FREQUENCY (kHz) Figure 2. Reference Noise vs. Frequency Output Buffer The output amplifier uses a folded cascode input stage and a type AB output stage. Large output devices with low series resistance allow the output to swing to ground in single-supply operation. The output buffer is unity-gain stable. Input offset voltage and supply current are laser trimmed. Settling time is 25µs to 0.01% of final value. The output is short-circuit protected and can drive a 2kΩ load with more than 100pF of load capacitance. The op amp may be placed in unity-gain (G = 1), in a gain of two (G = 2), or in a bipolar-output mode by using the ROFS and RFB pins. These pins are used to define a DAC output voltage range of 0V to +2.048V, 0V to +4.096V or ±2.048V, by connecting ROFS to VOUT, GND, or REFIN. RFB is always connected to VOUT. Table 1 summarizes ROFS usage. Table 1. ROFS Usage ROFS CONNECTED TO: DAC OUTPUT RANGE OP-AMP GAIN VOUT 0V to 2.048V G=1 AGND 0V to 4.096V G=2 REFIN -2.048V to +2.048V Bipolar An external reference in the range (V SS + 2V) to (VDD - 2V) may be used with the MAX530 in dual-supply, unity-gain operation. In single-supply, unity-gain operation, the reference must be positive and may not exceed (VDD - 2V). The reference voltage determines the DAC’s full-scale output. Because of the codedependent nature of reference input impedances, a high-quality, low-output-impedance amplifier (such as the MAX480 low-power, precision op amp) should be used to drive REFIN. If an upgrade to the internal reference is required, the 2.5V MAX873A is ideal: ±15mV initial accuracy, 7ppm/°C (max) temperature coefficient. Power-On Reset An internal power-on reset (POR) circuit forces the DAC register to reset to all 0s when VDD is first applied. The POR pulse is typically 1.3µs; however, it may take 2ms for the internal reference to charge its large filter capacitor and settle to its trimmed value. In addition to POR , a clear (CLR) pin, when held low, sets the DAC register to all 0s. CLR operates asynchronously and independently from chip select (CS). With the DAC input at all 0s, the op-amp output is at zero for unity-gain and G = 2 configurations, but it is at -VREF for the bipolar configuration. Shutdown Mode The MAX530 is designed for low power consumption. Understanding the circuit allows power consumption management for maximum efficiency. In single-supply mode (VDD = +5V, VSS = GND) the initial supply current is typically only 160µA, including the reference, op amp, and DAC. This low current occurs when the power-on reset circuit clears the DAC to all 0s and forces the op-amp output to zero (unipolar mode only). See the Supply Current vs. REFIN graph in the Typical Operating Characteristics. Under this condition, there is no internal load on the reference (DAC = 000hex, REFIN is open circuit) and the op amp operates at its minimum quiescent current. The CLR signal resets the MAX530 to these same conditions and can be used to control a power-saving mode when the DAC is not being used by the system. Note: Assumes RFB = VOUT and REFIN = REFOUT = 2.048V _______________________________________________________________________________________ 9 MAX530 External Reference RS REFOUT MAX530 +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC REFOUT REFIN ROFS 33µF 2.048V REFERENCE RFB REFGND VOUT 2N7002 AGND DGND DAC POWER-ON RESET MAX530 VDD 12-BIT DAC LATCH CLR +5V VSS NBL INPUT LATCH A0 A1 CONTROL LOGIC NBM INPUT LATCH NBH INPUT LATCH CS WR LDAC D4 D6 D0/D8 D2/D10 D1/D9 D5 D7 D3/D11 Figure 3. Low-Current Shutdown Mode An additional 110µA of supply current can be saved when the internal reference is not used by connecting REFGND to VDD. A low on resistance N-channel FET, such as the 2N7002, can be used to turn off the internal reference to create a shutdown mode with minimum current drain (Figure 3). When CLR is high, the transistor pulls REFGND to AGND and the reference and DAC operate normally. When CLR goes low, REFGND is pulled up to VDD and the reference is shut down. At the same time, CLR resets the DAC register to all 0s, and the op-amp output goes to 0V for unity-gain and G = 2 Table 2. Input Latch Addressing CLR CS WR LDAC X X A0 X A1 X H X H X X No Operation X H H X X No Operation H L L H H H NBH (D8-D11) H L L H H L NBM (D4-D7) H L L H L H NBL (D0-D3) H H H L X X Update DAC Only H H L L L L X L L H L H DAC NOT UPDATED NBH and Update DAC L X H H 10 DATA UPDATED Reset DAC Latches modes. This reduces the total single-supply operating current from 250µA (400µA max) to typically 40µA in shutdown mode. A small error voltage is added to the reference output by the reference current flowing through the N-channel pull-down transistor. The switch’s on resistance should be less than 5Ω. A typical reference current of 100µA would add 0.5mV to REFOUT. Since the reference current and on resistance increase with temperature, the overall temperature coefficient will degrade slightly. As data is loaded into the DAC and the output moves above GND, the op-amp quiescent current increases to its nominal value and the total operating current averages 250µA. Using dual supplies (±5V), the op amp is fully biased continuously, and the VDD supply current is more constant at 250µA. The VSS current is typically 150µA. The MAX530 logic inputs are compatible with TTL and CMOS logic levels. However, to achieve the lowest power dissipation, drive the digital inputs with rail-to-rail CMOS logic. With TTL logic levels, the power requirement increases by a factor of approximately 2. ______________________________________________________________________________________ +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC MAX530 ADDRESS BUS VALID VIH A0-A1 VIL tAWH CS tCWS tCWH WR tAWS tWR tDS DATA BITS (8-BIT BYTE OR 4-BIT NIBBLE) CLR tDH VIH VIL DATA BUS VALID tCLR LDAC NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS VIH + VIL 2 tLDAC Figure 4. MAX530 Write-Cycle Timing Diagram Parallel Logic Interface Designed to interface with 4-bit, 8-bit, and 16-bit microprocessors (µPs), the MAX530 uses 8 data pins and double-buffered logic inputs to load data as 4 + 4 + 4 or 8 + 4. The 12-bit DAC latch is updated simultaneously through the control signal LDAC. Signals A0, A1, WR, and CS select which input latches to update. The 12-bit data is broken down into nibbles (NB); NBL is the enable signal for the lowest 4 bits, NBM is the enable for the middle 4 bits, and NBH is the enable for the highest and most significant 4 bits. Table 2 lists the address decoding scheme. Refer to Figure 4 for the MAX530 write-cycle timing diagram. Figure 5 shows the circuit configuration for a 4-bit µP application. Figure 6 shows the corresponding timing sequence. The 4 low bits (D0-D3) are connected in parallel to the other 4 bits (D4-D7) and then to the µP bus. Address lines A0 and A1 enable the input data latches for the high, middle, or low data nibbles. The µP sends chip select (CS) and write (WR) signals to latch in each of three nibbles in three cycles when the data is valid. Figure 7 shows a typical interface to an 8-bit or a 16-bit µP. Connect 8 data bits from the data bus to pins D0-D7 on the MAX530. With LDAC held high, the user can load NBH or NBL + NBM in any order. Figure 8a shows the corresponding timing sequence. For fastest throughput, use Figure 8b’s sequence. Address lines A0 and A1 are tied together and the DAC is loaded in 2 cycles as 8 + 4. In this scheme, with LDAC held low, the DAC latch is transparent. Always load NBL and NBM first, followed by NBH. LDAC is asynchronous with respect to WR. If LDAC is brought low before or at the same time WR goes high, LDAC must remain low for at least 50ns to ensure the correct data is latched. Data is latched into DAC registers on LDAC’s rising edge. ______________________________________________________________________________________ 11 MAX530 +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC D0-D3 DATA BUS D0-D3 D0-D3 FROM SYSTEM RESET D0-D3 CLR D4-D7 A0, A1 MC6800 D0-D7 DATA BUS D0-D7 FROM SYSTEM RESET CLR MAX530 MAX530 A0-A1 MC6809 CS LDAC WR D0-D7 02 CS LDAC WR E EN R/W ADDRESS BUS A0-A15 A0, A1 DECODER R/W EN A0-A15 ADDRESS BUS A13-A15 A0 DECODER A13-A15 Figure 7. 8-Bit and 16-Bit µP Interface Figure 5. 4-Bit µP Interface A0 = 1, A1 = 1 NBH NBM A0 = 1, A1 = 0 NBL A0 = 0, A1 = 1 CS WR LDAC DAC UPDATE Figure 6. 4-Bit µP Timing Sequence NBH A0 = A1 = 1 NBL & NBM A0 = A1 = 0 CS WR LDAC DAC UPDATE Figure 8a. 8-Bit and 16-Bit µP Timing Sequence Using LDAC 12 ______________________________________________________________________________________ +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC MAX530 A0 = A1 = 0 NBL & NBM A0 = A1 = 1 NBH CS WR LDAC = 0 (DAC LATCH IS TRANSPARENT) DAC UPDATE Figure 8b. 8-Bit and 16-Bit µP Timing Sequence with LDAC = 0 Unipolar Configuration The MAX530 is configured for a 0V to +2.048V unipolar output range by connecting ROFS and RFB to VOUT (Figure 9). The converter operates from either single or dual supplies in this configuration. See Table 3 for the DAC-latch contents (input) vs. the analog VOUT (output). In this range, 1LSB = REFIN (2 -12). A 0V to 4.096V unipolar output range is set up by connecting ROFS to AGND and RFB to VOUT (Figure 10). Table 4 shows the DAC-latch contents vs. VOUT. The MAX530 operates from either single or dual supplies in this mode. In this range, 1LSB = (2)(REFIN)(2 -12) = (REFIN)(2 -11). +5V REFIN +5V VDD REFIN ROFS REFOUT VDD REFOUT 33µF 33µF MAX530 AGND MAX530 ROFS RFB RFB AGND DGND VOUT VOUT REFGND VOUT DGND VOUT REFGND VSS G=1 0V TO -5V Figure 9. Unipolar Configuration (0V to +2.048V Output) VSS G=2 0V TO -5V Figure 10. Unipolar Configuration (0V to +4.096V Output) ______________________________________________________________________________________ 13 MAX530 +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC Table 3. Unipolar Binary Code Table (0V to VREFIN Output), Gain = 1 OUTPUT INPUT OUTPUT INPUT 1111 1111 1111 (VREFIN) 4095 4096 1111 1111 1111 +2 (VREFIN) 4095 4096 1000 0000 0001 (VREFIN) 2049 4096 1000 0000 0001 +2 (VREFIN) 2049 4096 1000 0000 0000 1000 0000 0000 +2 (VREFIN) 2048 = +VREFIN 4096 0111 1111 1111 (VREFIN) 2047 4096 0111 1111 1111 +2 (VREFIN) 2047 4096 0000 0000 0001 (VREFIN) 1 4096 0000 0000 0001 +2 (VREFIN) 1 4096 0000 0000 0000 0000 0000 0000 (VREFIN) 2048 = +VREFIN/2 4096 OV Bipolar Configuration A -VREFIN to +VREFIN bipolar range is set up by connecting ROFS to REFIN and RFB to VOUT, and operating from dual (±5V) supplies (Figure 11). Table 5 shows the DAC-latch contents (input) vs. VOUT (output). In this range, 1 LSB = REFIN (2 -11). Four-Quadrant Multiplication The MAX530 can be used as a four-quadrant multiplier by connecting ROFS to REFIN and RFB to VOUT and, using (1) an offset binary digital code, (2) bipolar power supplies, and (3) a bipolar analog input at REFIN within the range VSS + 2V to VDD - 2V, as shown in Figure 12. In general, a 12-bit DAC’s output is (D)(V REFIN)(G), where “G” is the gain (1 or 2) and “D” is the binary representation of the digital input divided by 212 or 4,096. This formula is precise for unipolar operation. However, for bipolar, offset binary operation, the MSB is really a polarity bit. No resolution is lost, because there is the same number of steps. The output voltage, however, has been shifted from a range of, for example, 0V to 4.096V (G = 2) to a range of -2.048V to +2.048V. Keep in mind that when using the DAC as a four-quadrant multiplier, the scale is skewed. The negative full scale is -VREFIN, while the positive full scale is +VREFIN - 1LSB. 14 Table 4. Unipolar Binary Code Table (0V to 2VREFIN Output), Gain = 2 OV Table 5. Bipolar (Offset Binary) Code Table (-VREFIN to +VREFIN Output) OUTPUT INPUT 1111 1111 1111 (+VREFIN) 2047 2048 1000 0000 0001 (+VREFIN) 1 2048 1000 0000 0000 0111 1111 1111 (-VREFIN) 1 2048 0000 0000 0001 (-VREFIN) 2047 2048 0000 0000 0000 (-VREFIN) 2048 = -VREFIN 2048 0V ______________________________________________________________________________________ +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC +5V VDD REFIN REFIN ROFS REFOUT MAX530 +5V REFIN ROFS REFGND 33µF MAX530 RFB AGND MAX530 RFB AGND DGND VOUT VOUT DGND VOUT VOUT REFGND VSS -5V Figure 11. Bipolar Configuration (-2.048V to +2.048V Output) __________Applications Information Single-Supply Linearity As with any amplifier, the MAX530’s output op amp offset can be positive or negative. When the offset is positive, it is easily accounted for. However, when the offset is negative, the output cannot follow linearly when there is no negative supply. In that case, the amplifier output (VOUT) remains at ground until the DAC voltage is sufficient to overcome the offset and the output becomes positive. The resulting transfer function is shown in Figure 13. Normally, linearity is measured after allowing for zero error and gain error. Since, in single-supply operation, the actual value of a negative offset is unknown, it cannot be accounted for during test. In the MAX530, linearity and gain error are measured from code 11 to code 4095 (see Note 2 under Electrical Characteristics). The output amplifier offset does not affect monotonicity, and these DACs are guaranteed monotonic starting with code zero. In dual-supply operation, linearity and gain error are measured from code 0 to 4095. Power-Supply Bypassing and Ground Management Best system performance is obtained with printed circuit boards that use separate analog and digital ground planes. Wire-wrap boards are not recommended. The two ground planes should be connected together at the low-impedance power-supply source. AGND and REFGND should be connected together, and then to DGND at the chip. For single-supply appli- -5V Figure 12. Four-Quadrant Multiplying Circuit cations, connect VSS to AGND at the chip. The best ground connection may be achieved by connecting the AGND, REFGND, and DGND pins together and connecting that point to the system analog ground plane. If DGND is connected to the system digital ground, digital noise may get through to the DAC’s analog portion. Bypass V DD (and V SS in dual-supply mode) with a 0.1µF ceramic capacitor connected between VDD and AGND (and between V SS and AGND). Mount the capacitors with short leads close to the device. AC Considerations Digital Feedthrough High-speed data at any of the digital input pins may couple through the DAC package and cause internal stray capacitance to appear as noise at the DAC output, even though LDAC and CS are held high (see Typical Operating Characteristics ). This digital feedthrough is tested by holding LDAC and CS high and toggling the data inputs from all 1s to all 0s. Analog Feedthrough Because of internal stray capacitance, higher-frequency analog input signals at REFIN may couple to the output, even when the input digital code is all 0s, as shown in the Typical Operating Characteristics graph Analog Feedthrough vs. Frequency. It is tested by setting CLR to low (which sets the DAC latches to all 0s) and sweeping REFIN. ______________________________________________________________________________________ 15 ___________________Chip Topography D3/D11 D1/D9 POSITIVE OFFSET OUTPUT (LSBs) MAX530 +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC 4 3 2 1 0 D4 D2/D10 D0/D8 V DD RFB ROFS NEGATIVE OFFSET 1 2 3 4 5 6 7 VOUT 8 D5 0.133" (3.378mm) DAC CODE (LSBs) D6 V SS D7 Figure 13. Single-Supply DAC Transfer Function REFOUT A0 _Ordering Information (continued) PIN-PACKAGE ERROR (LSB) MAX530AENG -40°C to +85°C 24 Narrow Plastic DIP ±1/2 MAX530BENG MAX530AEWG MAX530BEWG MAX530AEAG MAX530BEAG 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO 24 SSOP 24 SSOP ±1 ±1/2 ±1 ±1/2 ±1 PART TEMP. RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C REFGND LDAC A1 WR CS AGND DGND CLR REFIN 0.087" (2.210mm) TRANSISTOR COUNT: 913; SUBSTRATE CONNECTED TO VDD. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.