AD SMP08FP

Octal Sample-and-Hold
with Multiplexed Input
SMP08*
a
FEATURES
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
FUNCTIONAL BLOCK DIAGRAM
INPUT
(LSB)
A
B
(MSB)
C
INH
3
11
10
9
6
8 DGND
1 OF 8 DECODER
16 VDD
SW
APPLICATIONS
Multiple Path Timing Deskew for ATE
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
SW
SW
SW
SW
SW
SW
GENERAL DESCRIPTION
The SMP08 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP08 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
± 1/2 LSB in less than 7 microseconds. The SMP08’s output
swing includes the negative supply in both single and dual supply operation.
The SMP08 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP08 ideal for
calibration requirements that have previously required an
ASIC, or high cost multiple D/A converters.
SW
13 CH0OUT
14 CH1OUT
15 CH2OUT
12 CH3OUT
1
CH4OUT
5
CH5OUT
2
CH6OUT
4 CH7OUT
HOLD CAPS
(INTERNAL)
7 VSS
SMP08
The SMP08 is also ideally suited for a wide variety of sampleand-hold applications including amplifier offset or VCA gain
adjustments. One or more SMP08s can be used with single or
multiple DACs to provide multiple set points within a system.
The SMP08 offers significant cost and size reduction over discrete designs. It is available in a 16-pin plastic DIP, or surfacemount SOIC package.
*Protected by U.S. Patent No. 4,739,281.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
SMP08–SPECIFICATIONS(@ V
ELECTRICAL CHARACTERISTICS
Parameter
Linearity Error
Buffer Offset Voltage
Symbol
Hold Step
VHS
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
∆VCH/∆t
ISOURCE
ISINK
VOS
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
Acquisition Time3
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
Capacitive Load Stability
Analog Crosstalk
VINH
VINL
IIN
DD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP08F,
unless otherwise noted)
Conditions
–3 V ≤ VIN ≤ +3 V
TA = +25°C, VIN = 0 V
–40°C ≤ TA ≤ +85°C, VIN = 0 V
VIN = 0 V, TA = +25°C to +85°C
VIN = 0 V, TA = –40°C
TA = +25°C, VIN = 0 V
VIN = 0 V1
VIN = 0 V1
RL = 20 kΩ
Min
Typ
0.01
2.5
3.5
2.5
2
1.2
0.5
–3.0
Max
+3.0
Units
%
mV
mV
mV
mV
mV/s
mA
mA
V
0.8
1
V
V
µA
10
20
4
5
20
2.4
VIN = 2.4 V
0.5
TA = +25°C, –3 V to +3 V to 0.1%
To ± 1 mV of Final Value
3.6
1
90
45
90
3
500
–72
2
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
tAQ
tH
tCH
tDCS
tIR
SR
<30% Overshoot
–3 V to +3 V Step
PSRR
IDD
ELECTRICAL CHARACTERISTICS
Parameter
Linearity Error
Buffer Offset Voltage
Symbol
Hold Step
VHS
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
∆VCH/∆t
ISOURCE
ISINK
VOS
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
DYNAMIC PERFORMANCE2
Acquisition Time3
tAQ
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
Capacitive Load Stability
Analog Crosstalk
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
tH
tCH
tDCS
tIR
SR
PSRR
IDD
VS = ± 5 V to ± 6 V
TA = +25°C
–40°C ≤ TA ≤ +85°C
60
75
4
5
7
7.5
9.5
µs
µs
ns
ns
ns
V/µs
pF
dB
dB
mA
mA
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP08F,
unless otherwise noted)
Conditions
60 mV ≤ VIN ≤ 10 V
TA = +25°C, VIN = 6 V
–40°C ≤ TA ≤ +85°C, VIN = 6 V
VIN = 6 V, TA = +25°C to +85°C
VIN = 6 V, TA = –40°C
TA = +25°C, VIN = 6 V
VIN = 6 V1
VIN = 6 V1
RL = 20 kΩ
RL = 10 kΩ
Min
Typ
0.01
2.5
3.5
2.5
2
1.2
0.5
0.06
0.06
Max
10.0
9.5
Units
%
mV
mV
mV
mV
mV/s
mA
mA
V
V
0.8
1
V
V
µA
10
20
4
5
20
2.4
VIN = 2.4 V
0.5
TA = +25°C, 0 V to 10 V to 0.1%
–40°C ≤ TA ≤ +85°C
To ± 1 mV of Final Value
3.5
3.75
1
90
45
90
4
500
–72
RL = 20 kΩ4
<30% Overshoot
0 V to 10 V Step
3
10.8 V ≤ VDD ≤ 13.2 V
TA = +25°C
–40°C ≤ TA ≤ +85°C
60
75
6.0
8.0
4.25
6.00
8.0
10.0
µs
µs
µs
ns
ns
ns
V/µs
pF
dB
dB
mA
mA
NOTES
1
Outputs are capable of sinking and sourcing over 20 mA but offset is guaranteed at specified load levels.
2
All input control signals are specified with t r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3
This parameter is guaranteed without test.
4
Slew rate is measured in the sample mode with 0 V to 10 V step from 20% to 80%.
Specifications subject to change without notice.
–2–
REV. D
SMP08
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
VOUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
(Not Short-Circuit Protected)
Operating Temperature Range
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Package Type
uJA*
uJC
Units
16-Pin Plastic DIP (P)
16-Pin SOIC (S)
76
92
33
27
°C/W
°C/W
Model
Temperature
Range
Package
Description
Package
Option
SMP08FP
SMP08FS
–40°C to +85°C
–40°C to +85°C
Plastic DIP
SO-16
N-16
R-16A
PIN CONNECTIONS
CH4OUT 1
16 VDD
CH6OUT 2
15 CH2OUT
SMP08
13 CH0OUT
TOP VIEW
CH5OUT 5 (Not to Scale) 12 CH3OUT
CH7OUT 4
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for plastic DIP package; θJA is specified for device soldered to printed
circuit board for SO package.
INH 6
11 A CONTROL
VSS 7
10 B CONTROL
DGND 8
9 C CONTROL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP08 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. D
14 CH1OUT
INPUT 3
–3–
WARNING!
ESD SENSITIVE DEVICE
SMP08–Typical Performance Characteristics
100
10
1
0.1
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE – °C
Figure 1. Droop Rate vs. Temperature
2
1600
1
0
–1
VDD = +12V
VSS = 0V
–2
TA = +25°C
NO LOAD
–3
2 3
4
5
6 7
8
0 1
INPUT VOLTAGE – Volts
1200
1000
800
600
9
0
10
0
–1
–2
–3
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
Figure 3. Droop Rate vs. Input Voltage
7
VSS = 0V
T A = +25 °C
NO LOAD
6
SLEW RATE – V/µs
HOLD STEP – mV
NO LOAD
TA = +125°C
NO LOAD
VDD = +12V
VSS = 0V
V I N = +5V
NO LOAD
1
TA = +25°C
VDD = +12V
VSS = 0V
1400
2
VDD = +12V
VSS = 0V
1
0
–1
–2
–SR
5
+SR
4
–3
–4
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
Figure 4. Hold Step vs. Input Voltage
4
–4
–55
10
20
∞
TA = +25°C
NO LOAD
–2
–4
RL = 20kΩ
RL = 10kΩ
–6
–8
NO LOAD
5
RL =
0
∞
–5
RL = 10kΩ
RL = 20kΩ
–10
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
Figure 7. Offset Voltage vs. Input
Voltage
13
14
15
VDD – Volts
16
17
18
Figure 6. Slew Rate vs. VDD
VDD = +12V
VSS = 0V
0
RL =
∞
TA = –40°C
NO LOAD
RL = 20kΩ
–2
RL = 10kΩ
–4
–6
–8
–20
0
12
2
TA = +85°C
10
11
4
–15
–10
3
10
85
65
VDD = +12V
VSS = 0V
15
OFFSET VOLTAGE – mV
RL =
0
–15
5
25
45
TEMPERATURE – °C
Figure 5. Hold Step vs. Temperature
VDD = +12V
VSS = 0V
2
–35
OFFSET VOLTAGE – mV
HOLD STEP – mV
1800
Figure 2. Droop Rate vs. Input Voltage
2
OFFSET VOLTAGE – mV
3
DROOP RATE – mV/s
VDD = +12V
VSS = 0V
V I N = +5V
RL = 10kΩ
DROOP RATE – mV/s
DROOP RATE – mV/s
1000
–10
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
Figure 8. Offset Voltage vs. Input
Voltage
–4–
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
Figure 9. Offset Voltage vs. Input
Voltage
REV. D
Typical Performance Characteristics–SMP08
14
–2
V I N = +5V
RL = 10kΩ
90
VSS = 0V
NO LOAD
12
–3
–4
–5
–6
10
+85°C
8
+25°C
6
–40°C
4
–7
25
45
65
85 105 125
4
TEMPERATURE – °C
Figure 10. Offset Voltage vs.
Temperature
VDD = +12V
VSS = 0V
1
TA = +25°C
NO LOAD
0
GAIN – dB
8
10
12
VDD – Volts
35
45
30
–45
PHASE
–90
–2
–135
–3
GAIN
–180
–4
1k
10k
100k
FREQUENCY – Hz
1M
25
NO LOAD
–PSRR
40
30
20
0
10
18
100
1k
10k
100k
FREQUENCY – Hz
VDD = +12V
VSS = 0V
TA = +25°C
NO LOAD
15
10
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 14. Output Impedance vs.
Frequency
60
VDD = +6V
VSS = –6V
50
TA = +25°C
NO LOAD
9
6
3
+PSRR
40
VDD = +12V
30 VSS = 0V
TA = +25°C
20 NO LOAD
10 HOLD CAPACITORS
REFERENCED TO VSS
0
–PSRR
0
10k
1M
100k
FREQUENCY – Hz
–10
10
10M
Figure 15. Maximum Output Voltage
vs. Frequency
REV. D
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 16. Hold Mode Power Supply
Rejection
–5–
1M
Figure 12. Sample Mode Power
Supply Rejection
20
0
10
REJECTION RATIO – dB
PEAK-TO-PEAK OUTPUT – Volts
50
V I N = +6V
TA = +25°C
60
5
–225
10M
Figure 13. Gain, Phase Shift vs.
Frequency
12
16
90
0
–1
15
14
Figure 11. Supply Current vs. VDD
2
–5
100
6
OUTPUT IMPEDANCE – Ω
5
+PSRR
70
10
2
PHASE SHIFT – Degrees
–8
–55 –35 –15
VDD = +12V
VSS = 0V
80
REJECTION RATIO – dB
–1
VDD = +12V
VSS = 0V
SUPPLY CURRENT – mA
OFFSET VOLTAGE – mV
0
SMP08
VCC
R3
6.5kΩ
R4
1kΩ
+15V
D1
C1
10µF
+
C2
1µF
R1
10Ω
1
16
2
15
3
14
SMP08
4
R2
10kΩ
R2
10kΩ
R2
10kΩ
R2
10kΩ
13
5
12
6
11
7
10
8
9
R2
10kΩ
R2
10kΩ
R2
10kΩ
R2
10kΩ
Figure 17. Burn-In Circuit
APPLICATIONS INFORMATION
OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)
The SMP08, a multiplexed octal S/H, minimizes board space in
systems requiring cycled calibration or an array of control voltages. When used in conjunction with a low cost 16-bit D/A, the
SMP08 can easily be integrated into microprocessor based systems. Since the SMP08 features break-before-make switching
and an internal decoder, no external logic is required. The
SMP08 has an internally regulated TTL supply so that TTL/
CMOS compatibility is maintained over the full supply range.
See Figure 18 for channel decode address information.
The buffer offset specification is 10 mV; this is less than 1/2 LSB
of an 8-bit DAC with 10 V full scale. The hold step (magnitude of step caused in the output voltage when switching from
sample-to-hold mode, also referred to as the pedestal error or
sample-to-hold offset), is about 2.5 mV with little variation
over the full output voltage range, TA = +25°C to +85°C. The
droop rate of a held channel is 2 mV/s typical and 20 mV/s
maximum.
The buffers are designed to drive loads connected to ground.
The outputs can source more than 20 mA, over the full voltage
range, but have limited current sinking capability near VSS. In
split supply operation, symmetrical output swings can be obtained by restricting the output range to 2 V from either supply.
POWER SUPPLIES
The SMP08 is capable of operating with either single or dual
supplies, over a voltage range of 7 volts to 15 volts. Based on the
supply voltages chosen, VDD and VSS establish the input and
output voltage range, which is:
On-chip SMP08 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with capacitive loads up to 500 pF. However, since the SMP08’s
buffer outputs are not short-circuit protected, care should be
taken to avoid shorting any output to the supplies or ground.
(VSS +0.06 V) ≤ VOUT/IN ≤ (VDD –2 V)
Note that several specifications, including acquisition time, offset and output voltage compliance, will degrade for supply voltages of less than 7 V.
If split supplies are used, the negative supply should be bypassed
with a 0.1 µF capacitor in parallel with a 10 µF to ground. The
internal hold capacitors are connected to this supply pin and any
noise will appear at the outputs.
In single supply applications, it is extremely important that the
VSS (negative supply) pin is connected to a clean ground. The
hold capacitors are internally tied to the VSS (negative) rail. Any
ground noise or disturbance will directly couple to the output of
the sample-and-hold, degrading the signal-to-noise performance. The analog and digital ground traces on the circuit
board should be physically separated to reduce digital switching
noise from entering the analog circuitry.
SIGNAL INPUT (Pin 3)
The signal input should be driven from a low impedance voltage source such as the output of an op amp. The op amp
should have a high slew rate and fast settling time if the
SMP08’s acquisition time characteristics are to be maintained.
As with all CMOS devices, all input voltages should be kept
within range of the supply rails (VSS < VIN < VDD) to avoid the
possibility of latchup. If single supply operation is desired, op
amps such as the OP183 or AD820 that have input and output
voltage compliances including ground, can be used to drive the
inputs. Split supplies, such as ± 7.5 V, can be used with the
SMP08.
APPLICATION TIPS
POWER SUPPLY SEQUENCING
All unused digital inputs should be connected to logic LOW
and unused analog inputs connected to analog ground. For
connector-driven analog inputs that may become temporarily
disconnected, a resistor to VDD, VSS or analog ground should
be used with a value ranging from 200 kΩ to 1 MΩ.
VDD should be applied to the SMP08 before the logic input signals. The SMP08 has been designed to be immune to latchup,
but standard precautions should still be taken.
–6–
REV. D
SMP08
+12V
SMP08
13 CH0
REF02
+12V
+5V
DIGITAL
INPUTS
4
17
VREFA
VDD
CS
16
15
14 CH1
VOA 3
DAC8228
WR
VSS
3
VSS
VZ
1
GND
15 CH2
5
VSS
WR
ADDRESS
BUS
A
B
ADDRESS
DECODE
C
CHANNEL DECODING
12 CH3
11
VSS
10
9
1
CH4
5
CH5
2
CH6
4
CH7
VSS
DGND
8
VSS
INH
PIN 9
C
PIN 10
B
PIN 11
A
PIN 6
INH
CH
PIN
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
1
0
1
2
3
4
5
6
7
NONE
13
14
15
12
1
5
2
4
–
VSS
6
VSS
16
7
+12V
0.1µF
Figure 18. 8-Channel Multiplexed D/A Converter
Do not apply signals to the SMP08 with power off unless the
input current is limited to less than 10 mA.
TYPICAL APPLICATIONS
AN 8-CHANNEL MULTIPLEXED D/A CONVERTER
Figure 18 illustrates a typical demultiplexing function of the
SMP08. It is used to sample-and-hold eight different output
voltages corresponding to eight different digital codes from a
D/A converter. The SMP08’s droop rate of 20 mV/s requires a
refresh once every 500 ms, before the voltage drifts beyond
REV. D
1/2 LSB accuracy (1 LSB of an 8-bit DAC is equivalent to
19.5 mV out of a full-scale voltage of 5 V). For a 10-bit DAC
the refresh rate must be less than 120 ms, and, for a 12-bit
system, 31 ms. This implementation is very cost effective compared to using multiple DACs as the number of output channels
increases.
–7–
SMP08
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C2192–2–10/96
16-Lead Plastic DIP
(N-16)
0.840 (21.33)
0.745 (18.93)
16
9
1
8
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
PIN 1
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.015 (0.38)
0.210 (5.33)
MAX
0.160 (4.06)
0.130
(3.30)
MIN
0.115 (2.93)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.015 (0.381)
0.070 (1.77) SEATING
0.045 (1.15) PLANE
0.008 (0.204)
16-Lead SOIC (Narrow Body)
(SO-16)
0.3937 (10.00)
0.3859 (9.80)
0.1574 (4.00)
0.1497 (5.80)
16
9
1
8
PIN 1
0.0098 (0.25)
0.2550 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0196 (0.50)
0.0532 (1.35)
0.0099 (0.25)
x 45°
0.0040 (0.10)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
8°
0.0099 (0.25) 0° 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
PRINTED IN U.S.A.
SEATING
PLANE
–8–
REV. D