19-1469; Rev 0; 7/99 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input Features The MAX5165 contains four 1-to-8 multiplexers and 32 sample/hold amplifiers. A single analog input connects to all four internal 1-to-8 multiplexers. The sample/hold amplifiers are organized into four octal sample/holds with independent TTL/CMOS-compatible track/hold enables for each octal set. Additional 3-bit TTL/CMOScompatible address logic selects the 1-to-8 multiplexer channel. Clamping diodes on each output allow clamping between two external reference voltages. The MAX5165 is available with an output impedance of 50Ω, 500Ω, or 1kΩ, allowing output filtering. The MAX5165 operates with +10V and -5V supplies and a separate +5V digital logic supply. Manufactured with a proprietary BiCMOS process, it provides high accuracy, fast acquisition time, low droop rate, and a low hold step. The device acquires 8V step input signals to 0.01% accuracy in 2.5µs. Transitions from sample mode to hold mode result in only a 0.5mV error. While in hold mode, the output voltage slowly droops at a rate of 1mV/sec. The MAX5165 is available in a 48-pin TQFP package. ♦ 32-Channel Sample/Hold ♦ Output Clamping ♦ 0.01% Accuracy of Acquired Signal ♦ 0.01% Linearity Error ♦ Fast Acquisition Time: 2.5µs ♦ Low Droop Rate: 1mV/sec ♦ Low Hold Step: 0.25mV ♦ Wide Output Voltage Range: +7V to -4V Ordering Information Applications Automatic Test Equipment (ATE) Industrial Process Controls PART TEMP. RANGE PINPACKAGE MAX5165LCCM 0°C to +70°C ROUT (Ω) 48 TQFP 50 MAX5165MCCM 0°C to +70°C MAX5165NCCM 0°C to +70°C MAX5165LECM -40°C to +85°C 48 TQFP 48 TQFP 48 TQFP 500 1k 50 MAX5165MECM -40°C to +85°C MAX5165NECM -40°C to +85°C 48 TQFP 48 TQFP 500 1k Arbitrary Function Generators Avionics Equipment 37 38 39 40 41 42 43 44 45 46 47 48 A1 A0 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 Pin Configuration A2 M0 1 36 2 35 M1 M2 M3 3 34 4 33 5 32 VL 6 31 DGND VSS 7 8 29 AGND IN 9 28 10 27 11 26 12 25 OUT17 OUT16 VDD OUT15 OUT14 OUT13 OUT12 OUT11 24 23 22 21 20 19 18 17 16 15 14 30 OUT19 OUT18 N.C. OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 13 CH CL MAX5165 OUT21 OUT20 TQFP ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX5165 General Description MAX5165 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input ABSOLUTE MAXIMUM RATINGS VDD to AGND.......................................................-0.3V to +11.0V VSS to AGND .........................................................-6.0V to +0.3V VDD to VSS ......................................................................+15.75V VL to DGND...........................................................-0.3V to +6.0V VL to AGND ...........................................................-0.3V to +6.0V DGND to AGND.....................................................-0.3V to +2.0V IN to AGND .................................................................VSS to VDD A_, M_ to DGND ....................................................-0.3V to +6.0V CH, CL to AGND .................................................-6.0V to +11.0V Maximum Current into Output Pin ....................................±10mA Maximum Current into A_, M_ ..........................................±20mA Continuous Power Dissipation (TA = +70°C) 48-pin TQFP (derate 12.5mW/°C above +70°C).........1000mW Operating Temperature Ranges MAX5165_CCM ...................................................0°C to +70°C MAX5165_ECM.................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Maximum Current into CH, CL, PIN..................................±80mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +10V, VSS = -5V, VL = +5V ±5%, AGND = DGND, RL = 5kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -4V < VIN < +7V, RL = ∞ 0.01 0.08 % IN = AGND 0.25 1.00 mV 1 40 mV/sec -5 30 mV 20 40 µV/°C VDD 2.4 V ANALOG SECTION Linearity Error Hold Step Droop Rate Offset Voltage Output Voltage Range VHS ∆VOUT_ VOS VOUT_ DC Output Impedance Output Source Current IN = AGND, TA = +25°C -30 +15°C ≤ TA ≤ +65°C (Note 1) VSS + 0.75 RL = ∞ 8V step with 500ns rising edge (Note 1) Analog Crosstalk Input Capacitance IN = AGND, TA = +25°C MAX5165L, CL = 250pF -72 -76 MAX5165M, CL = 10nF -72 -76 MAX5165N, CL = 10nF -72 -76 MAX5165L 35 MAX5165M 350 500 650 MAX5165N 700 1000 1300 CIN ROUT_ RL = ∞, CL = 250pF ISOURCE dB 10 20 50 65 2 pF Ω mA Output Sink Current ISINK 2 Output Clamp High VCH VSS VDD mA V Output Clamp Low VCL VSS VDD V TIMING PERFORMANCE Acquisition Time tAQ 8V step to 0.08%, RL = ∞, Figure 2 (Note 2) 2.5 TA = +25°C, 100mV step to ±1mV, RL = ∞, Figure 2 (Note 2) 1 1 4 µs Hold-Mode Settling Time tH To ±1mV of final value, Figure 2 (Note 1) Aperture Delay tAP Figure 2 (Note 1) Inhibit Pulse Width tPW Figure 2 (Note 1) 200 ns Data Hold Time tDH Figure 2 (Note 1) 150 ns Data Setup Time tDS Figure 2 (Note 1) 50 ns 2 _______________________________________________________________________________________ 2 µs 200 ns 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input (VDD = +10V, VSS = -5V, VL = +5V ±5%, AGND = DGND, RL = 5kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS Input Voltage High VIH Input Voltage Low VIL Input Current II 2.0 A_ = DGND or VL, M_ = DGND or VL V -1 0.8 V +1 µA POWER SUPPLIES Positive Analog Supply Voltage VDD (Note 3) 9.5 10 10.5 V Negative Analog Supply Voltage VSS (Note 3) -4.75 -5.0 -5.45 V Digital Logic Supply Voltage VL 4.75 5 5.25 V Positive Analog Supply Current IDD RL = ∞ 36 mA Negative Analog Supply Current ISS RL = ∞ 36 mA Digital Logic Supply Current IL A0–A3 = DGND or VL; M0, M1, M2 = DGND or VCC 0.5 mA Digital Logic Supply Current IL A0–A3 = 0.8V or 2V; M0, M1, M2 = 0.8V or 2V 5 mA Power-Supply Rejection Ratio PSRR For both VDD and VSS in sample mode, VIN = 0 -60 -75 dB Note 1: Guaranteed by design. Note 2: Only one M_ input may be asserted low at a time, so only one channel is selected (see Single vs. Simultaneous Sampling). Note 3: Do not exceed the absolute maximum rating for VDD to VSS of +15.75V (see Absolute Maximum Ratings). _______________________________________________________________________________________ 3 MAX5165 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = +10V, VSS = -5V, VL = +5V, IN = GND, RL = ∞, CL = 0, AGND = DGND, VCH = VDD, VCL = VSS, TA = +25°C, unless otherwise noted.) 10 8 -80 1.40 -70 1.35 1.30 1.25 1.20 -50 -40 1.15 -30 4 1.10 -20 2 1.05 -10 6 1.00 0 -20 0 20 40 60 80 0 -5.0 -3.5 -2.0 -0.5 1.0 2.5 4.0 5.5 7.0 8.5 10.0 100 1 10 INPUT VOLTAGE (V) TEMPERATURE (°C) POWER-SUPPLY REJECTION RATIO (SAMPLE MODE) HOLD STEP vs. TEMPERATURE -80 10k HOLD STEP vs. INPUT VOLTAGE 90 80 -70 -50 -SUPPLY -40 -30 50 HOLD STEP (µV) HOLD STEP (µV) +SUPPLY -60 25 70 60 50 40 30 -20 20 -10 10 0 0 0 10 100 10k 1k -40 -20 0 20 40 60 80 -5.0 -3.0 TEMPERATURE (°C) FREQUENCY (kHz) 1.0 -3.6 OFFSET VOLTAGE (mV) -3.7 -3.0 -3.5 -4.0 -3.8 -3.9 -4.0 -4.1 -4.2 -4.3 -4.5 -4.4 -4.5 -5.0 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 3.0 OFFSET VOLTAGE vs. INPUT VOLTAGE -3.5 MAX5165-05 -2.5 -1.0 INPUT VOLTAGE (V) OFFSET VOLTAGE vs. TEMPERATURE -2.0 OFFSET VOLTAGE (mV) 100 MAX5165-08 1 4 1k 100 MAX5165-04 75 MAX5165-03 -90 100 FREQUENCY (kHz) MAX5165-07 -40 +SUPPLY -SUPPLY -60 PSRR (dB) 12 MAX5165-02 1.45 DROOP RATE (mV/sec) 14 -90 MAX5165-06 16 DROOP RATE (mV/sec) 1.50 MAX5165-01 18 POWER-SUPPLY REJECTION RATIO (HOLD MODE) DROOP RATE vs. INPUT VOLTAGE DROOP RATE vs. TEMPERATURE PSRR (dB) MAX5165 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input 100 -5.0 -3.0 -1.0 1.0 3.0 5.0 7.0 INPUT VOLTAGE (V) _______________________________________________________________________________________ 5.0 7.0 CL CH A0 A2 A1 M0 M1 M2 MAX5165 M3 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input D0 D0 D31 D31 MAX5165 3-TO-8 DECODER 8 1-TO-8 MULTIPLEXER 8 AND0 AND7 OUTPUT CLAMPING EN OUT0 IN OUT7 SAMPLE-AND-HOLD 1-TO-8 MULTIPLEXER 8 OUT8 EN IN OUT15 SAMPLE-AND-HOLD 1-TO-8 MULTIPLEXER 8 IN OUT16 EN IN OUT23 SAMPLE-AND-HOLD 1-TO-8 MULTIPLEXER 8 OUT24 EN IN OUT31 DGND VL AGND VDD VCC SAMPLE-AND-HOLD Figure 1. Functional Diagram _______________________________________________________________________________________ 5 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165 Pin Description PIN NAME FUNCTION 1, 47, 48 A2, A0, A1 Address Inputs. The input of a 3-to-8 decoder, which controls channel selection for all four 1-to-8 multiplexers simultaneously. Selects which output channels are connected to the input during sample mode (Tables 1, 2). 2–5 M0–M3 Mode-Selection/Multiplexer-Enable Inputs 0 to 3. Independent controls for each of the four 1-to-8 multiplexers. A logic low enables sample mode by connecting the selected channel (via address inputs A2, A1, A0) to IN. A logic high selects hold mode (Tables 1, 2). 6 VL 7 DGND 8 VSS 9 AGND 10 IN Analog Input. Connects to the input of all four internal 1-to-8 multiplexers. 11 CH Clamp High Input. Clamps VOUT to (VCH + 0.7V). 12 CL Clamp Low Input. Clamps VOUT to (VCL - 0.7V). 13 N.C. 14–29 OUT0–OUT15 30 VDD 31–46 OUT16–OUT31 Positive Digital Logic Power-Supply Input Digital Ground Negative Analog Power-Supply Input Analog Ground No Connection. Not internally connected. Sample/Hold Outputs 0 to 15 Positive Analog Power-Supply Input Sample/Hold Outputs 16 to 31 _______________Detailed Description The MAX5165 connects a single analog input to the inputs of four internal 1-to-8 analog multiplexers. Each multiplexer channel connects to a buffered sample/hold circuit and a series output resistor, creating a singleinput device with 32 sample/hold output channels. Three multiplexer channel-address inputs and four mode-select inputs (one for each multiplexer) control channel selection and sample/hold functions (Figure 1 and Tables 1, 2). Digital Interface Sample/Hold The MAX5165 contains 32 buffered sample/hold circuits with internal hold capacitors. Internal hold capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. The value of the hold capacitor affects acquisition time and droop rate. Lower capacitance allows faster acquisition times but increases the droop rate. Higher values increase hold time and acquisition time. The hold capacitor used in the MAX5165 provides fast 2.5µs (typ) acquisition time while maintaining a low 1mV/sec (typ) droop rate, making the sample/hold ideal for high-speed sampling. Three address pins and 3-to-8 address decoder logic select the channel for all four internal analog multiplexers. The mode-select inputs (M3–M0) independently control the sample/hold functions for each multiplexer (Tables 1, 2). 6 _______________________________________________________________________________________ 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165 Table 1. Output Selection ADDRESS OUTPUT SELECTED A2 A1 A0 MUX0 MUX1 MUX2 MUX3 0 0 0 OUT0 OUT8 OUT16 OUT24 0 0 1 OUT1 OUT9 OUT17 OUT25 0 1 0 OUT2 OUT10 OUT18 OUT26 0 1 1 OUT3 OUT11 OUT19 OUT27 1 0 0 OUT4 OUT12 OUT20 OUT28 1 0 1 OUT5 OUT13 OUT21 OUT29 1 1 0 OUT6 OUT14 OUT22 OUT30 1 1 1 OUT7 OUT15 OUT23 OUT31 0 = Logic Low, 1 = Logic High Table 2. Mode Selection MODE-SELECT INPUTS (M3–M0) ACTION 0 Sample mode enabled on selected analog multiplexer and channel (Table 1). 1 Hold mode enabled on selected analog multiplexer and channel (Table 1). 0 = Logic Low, 1 = Logic High * Only one M_ input asserted low; all others must be logic high to meet the timing specification (see Single vs. Simultaneous Sampling section). Sample Mode Driving M3–M0 low (one at a time) selects sample mode (Tables 1, 2). During sample mode, the selected multiplexer channel connects to IN, allowing the hold capacitor to acquire the input signal. To guarantee an accurate sample, maintain sample mode for at least 4µs. The output of the S/H amplifier tracks the input after 4µs. Only the addressed channel on the selected multiplexer samples the input; all other channels remain in hold mode. Hold Mode Driving M3–M0 high selects hold mode. Hold mode disables the multiplexer and disconnects all eight channels on the 1-to-8 multiplexer from the input. When a channel is disconnected, the hold capacitor maintains the sampled voltage at the output with a 1mV/sec droop rate (towards VDD). Hold Step When switching between sample mode and hold mode, the voltage of the hold capacitor changes due to charge injection from stray capacitance. This voltage change, called hold step, is minimized by limiting the amount of stray capacitance seen by the hold capacitor. The MAX5165 limits the hold step to 0.25mV (typ). An output capacitor to ground can be used to filter out this small hold-step error. Output The MAX5165 contains an output buffer for each multiplexer channel (32 total), so the hold capacitor sees a high-impedance input, reducing the droop rate. The capacitor droops at a 1mV/sec (typ) rate while in hold mode. The buffer also provides a low output impedance; however, the device contains output resistors in series with the buffer output (Figure 1) for selected output filtering. To provide greater design flexibility, the MAX5165 is available with an RO of 50Ω, 500Ω, or 1kΩ. Note: Output loads increase the analog supply current (IDD and ISS). Excessive loading of the output(s) damages the device by consuming more power than the device will dissipate (see Absolute Maximum Ratings). The resistor-divider formed by the output resistor (ROUT) and load impedance (RL) scales the sampled voltage (VSAMP). Determine the output voltage (VOUT_) as follows: Voltage Gain = AV = RL / (RL + ROUT) VOUT_ = VSAMP · AV The maximum output voltage range depends on the analog supply voltages available, and the scaling factor used: (VSS + 0.75V) · AV ≤ VOUT_ ≤ (VDD - 2.4V) · AV when RL = ∞, then AV = 1 and this equation becomes: (VSS + 0.75V) ≤ VOUT ≤ (VDD - 2.4V) _______________________________________________________________________________________ 7 MAX5165 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input Output Clamp __________Applications Information The MAX5165 clamps the output between two externally applied reference voltages. Internal diodes connect all outputs to the clamping voltages, restricting the output voltage to: VCH + 0.7V ≤ VOUT_ ≤ VCL - 0.7V Control-Line Reduction The MAX5165 contains four separate 1-to-8 multiplexers and individual mode selectors for each multiplexer. Configure the device to sample only one channel at a time or up to four channels (with the same address, see Table 1) simultaneously. When sampling one channel at a time, use an external 2-to-4 decoder (with activelow outputs) to reduce the number of digital control lines from seven to five (Figure 3). When the clamping voltage exceeds the maximum output voltage, the maximum output voltage will be the limiting factor. To disable output clamping, connect CH to VDD and CL to VSS to set the clamping voltages beyond the maximum output voltage range. The clamping diodes allow the MAX5165 to be used with other devices requiring restricted input voltages. Single vs. Simultaneous Sampling Individually control the four mode/multiplexer-select pins to simultaneously sample on four channels, the same channel for each multiplexer (Figure 4). Each mode-select pin controls sampling on one of the 1-to-8 multiplexers, while the 3-bit address selects one of the eight channels on all the multiplexers (Tables 1, 2). Setting any combination of the mode-select pins low enables sampling on the addressed channels for the selected multiplexers. Timing Definitions Acquisition time (t AQ ) is the amount of time the MAX5165 must remain in sample mode for the hold capacitor to acquire an accurate sample. The holdmode settling time (tH) is the amount of time necessary for the output voltage to settle to its final value. Aperture delay (tAP) is the time interval required to disconnect the input from the hold capacitor. The inhibit pulse width (tPW) is the amount of time the MAX5165 must remain in hold mode while the address is changed. The data setup time (tDS) is the amount of time an address must be maintained before the address becomes valid. The data hold time (tDH) is the amount of time that an address must be maintained after mode select has gone from low to high (Figure 2). Simultaneously sampling two or more channels reduces offset voltage but increases acquisition time. Multiply the single-channel acquisition time by the number of channels sampling. tPW MODE SELECT tDS ADDRESS (A0–A2) tDH OUTPUT HOLD STEP tH INPUT tAQ tAP Figure 2. Timing Performance 8 _______________________________________________________________________________________ 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input 1/16 MAX5165 3 5 MAX5165 CHANNEL ADDRESS A0–A2 3 ADDRESS DECODER 2 M0 M1 M2 M3 MODE SELECTOR DECODER OUT0 AGND INPUT SIGNAL OUT8 IN AGND Figure 3. Control-Line Reduction ADDRESS 1/16 MAX5165 3 A0–A2 3 ADDRESS DECODER MODE/MULTIPLEXER SELECTION M0 M1 M2 M3 OUT0 AGND INPUT SIGNAL OUT8 IN AGND Figure 4. Simultaneous Sampling _______________________________________________________________________________________ 9 MAX5165 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input Multiplexed DAC Powering the MAX5165 Figure 5 shows a typical demultiplexer application. Different digital codes are converted by the digital-toanalog converter (DAC) and then stored on 32 different channels of the MAX5165. The 100mV/sec (max) droop rate requires refreshing the hold capacitors every 100ms before the voltage drops by 1/2LSB for an 8-bit DAC with a 5V full-scale voltage. The MAX5165 does not require a special power-up sequence to avoid latchup. The device requires three separate supply voltages for operation; however, when one or two of the voltages are not available, DC-DC charge-pump (switched-capacitor) converters provide a simple, efficient solution. The MAX860 provides voltage doubling or inversion, ideal for conversions from +5V to +10V or from +5V to -5V. The MAX860 also functions as a voltage divider to provide conversion from +10V to +5V. ADDRESS 3 5 1/16 MAX5165 A0–A2 3 ADDRESS DECODER 2 MODE SELECTOR DECODER M0 M1 M2 M3 OUT0 AGND DIGITAL INPUTS DAC OUT8 IN AGND Figure 5. Multiplexing a DAC Chip Information TRANSISTOR COUNT: 5077 10 ______________________________________________________________________________________ 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input TQFPPO.EPS ______________________________________________________________________________________ 11 MAX5165 Package Information MAX5165 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.