a CMOS Complete DDS AD9830 FEATURES +5 V Power Supply 50 MHz Speed On-Chip SINE Look-Up Table On-Chip 10-Bit DAC Parallel Loading Power-Down Option 72 dB SFDR 250 mW Power Consumption 48-Pin TQFP GENERAL DESCRIPTION APPLICATIONS DDS Tuning Digital Demodulation A power-down pin allows external control of a power-down mode. The part is available in a 48-pin TQFP package. This DDS device is a numerically controlled oscillator employing a phase accumulator, a sine look-up table and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation and frequency modulation. Clock rates up to 50 MHz are supported. Frequency accuracy can be controlled to one part in 4 billion. Modulation is effected by loading registers through the parallel microprocessor interface. FUNCTIONAL BLOCK DIAGRAM AVDD AGND REFOUT DVDD DGND MCLK ON-BOARD REFERENCE FSELECT FREQ0 REG MUX FREQ1 REG PHASE ACCUMULATOR (32-BIT) Σ 12 SIN ROM PHASE0 REG FS ADJUST REFIN FULL SCALE CONTROL COMP IOUT 10-BIT DAC IOUT AD9830 PHASE1 REG MUX PHASE2 REG PHASE3 REG SLEEP PARALLEL REGISTER TRANSFER CONTROL RESET MPU INTERFACE D0 D15 WR A0 A1 A2 PSEL0 PSEL1 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD9830–SPECIFICATIONS1 R(V DD SET Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate (fMAX) IOUT Full Scale Output Compliance DC Accuracy Integral Nonlinearity Differential Nonlinearity = +5 V 6 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT; = 1 kV; RLOAD = 51 V for IOUT and IOUT unless otherwise noted) AD9830A Units Test Conditions/Comments 10 50 20 1 Bits MSPS max mA max V max ±1 ± 0.5 LSB typ LSB typ DDS SPECIFICATIONS2 Dynamic Specifications Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range (SFDR)3 Narrow Band (± 50 kHz) (± 200 kHz) Wide Band (± 2 MHz) Clock Feedthrough Wake Up Time Power-Down Option 50 –53 dB min dBc max –72 –68 –50 –55 1 Yes dBc min dBc min dBc min dBc typ ms typ VOLTAGE REFERENCE Internal Reference @ +25°C TMIN to TMAX REFIN Input Impedance Reference TC REFOUT Impedance 1.21 1.21 ± 7% 10 100 300 Volts typ Volts min/max MΩ typ ppm/°C typ Ω typ LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance VDD–0.9 0.9 10 10 V min V max µA max pF max 4.75/5.25 4.75/5.25 25 6 + 0.5/MHz 60 0.25 1 V min/V max V min/V max mA max mA typ mA max mA typ mA max POWER SUPPLIES AVDD DVDD IAA IDD IAA + IDD4 Low Power Sleep Mode5 fMCLK = fMAX , fOUT = 2 MHz fMCLK = fMAX , fOUT = 2 MHz fMCLK = 6.25 MHz, fOUT = 2.11 MHz fOUT = 2 MHz NOTES 1 Operating temperature range is as follows: A Version: –40°C to +85°C. 2 All dynamic specifications are measured using IOUT. 100% production tested. 3 fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz. 4 Measured with the digital inputs static and equal to 0 V or DVDD. 5 The Low Power Sleep Mode current is 2 mA typically when a 1 MΩ resistor is not tied from REFOUT to AGND. The AD9830 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated. For example, a 10 MHz output signal will be attenuated by 3 dB when the load capacitance equals 250 pF. Specifications subject to change without notice. 1 MΩ Resistor Tied Between REFOUT and AGND RSET 1kΩ 10nF REFOUT REFIN ON-BOARD REFERENCE FS ADJUST FULL-SCALE CONTROL AVDD 10nF COMP IOUT 12 SIN ROM 10-BIT DAC 51Ω IOUT 51Ω 50pF 50pF Figure 1. Test Circuit with Which Specifications Are Tested –2– REV. A AD9830 TIMING CHARACTERISTICS (V DD = +5 V 6 5%; AGND = DGND = 0 V, unless otherwise noted) Parameter Limit at TMIN to TMAX (A Version) Units Test Conditions/Comments t1 t2 t3 t4 1 t4A1 t5 t6 t7 t8 t9 1 t9A1 t10 20 8 8 8 8 8 t1 5 3 8 8 t1 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min MCLK Period MCLK High Duration MCLK Low Duration WR Rising Edge Before MCLK Rising Edge WR Rising Edge After MCLK Rising Edge WR Pulse Width Duration Between Consecutive WR Pulses Data/Address Setup Time Data/Address Hold Time FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge RESET Pulse Duration NOTES 1 See Pin Description section. Guaranteed by design, but not production tested. t1 MCLK t2 t4 t3 t5 t4A WR t6 Figure 2. WR–MCLK Relationship t6 t5 WR t8 t7 A0, A1, A2 DATA VALID DATA VALID DATA Figure 3. Writing to a Phase/Frequency Register MCLK t9A t9 FSELECT PSEL0, PSEL1 RESET VALID DATA VALID DATA t10 Figure 4. Control Timing REV. A –3– VALID DATA AD9830 Maximum Junction Temperature . . . . . . . . . . . . . . . . TQFP θJA Thermal Impedance . . . . . . . . . . . . . . . . . Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C +150°C 75°C/W +215°C +220°C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model Temperature Range AD9830AST –40°C to +85°C Package Option* ST-48 *ST = Thin Quad Flatpack (TQFP). AVDD NC AGND AGND NC AVDD NC IOUT AGND IOUT COMP FS ADJUST PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 REFIN 1 REFOUT 2 PIN 1 IDENTIFIER SLEEP 3 DVDD 4 DVDD 5 DGND 6 AD9830 MCLK 7 TOP VIEW (Not to Scale) WR 8 DVDD 9 36 AGND 35 RESET 34 33 A0 A1 32 A2 31 DB0 30 DB1 29 DGND 28 DB2 FSELECT 10 27 DB3 PSEL0 11 26 DB4 PSEL1 12 25 DVDD DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DGND 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT –4– REV. A AD9830 PIN DESCRIPTION Mnemonic Function POWER SUPPLY AVDD Positive power supply for the analog section. A 0.1 µF capacitor should be connected between AVDD and AGND. AVDD has a value of +5 V ± 5%. AGND Analog Ground. DVDD Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDD and DGND. DVDD has a value of +5 V ± 5%. DGND Digital Ground. ANALOG SIGNAL AND REFERENCE IOUT, IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND. IOUT should be either tied directly to AGND or through an external load resistor to AGND. FS ADJUST Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows: IOUTFULL-SCALE = 16 VREFIN/RSET VREFIN = 1.21 V nominal, RSET = 1 kΩ typical REFIN Voltage Reference Input. The AD9830 can be used with either the on-board reference, which is available from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9830 accepts a reference of 1.21 V nominal. REFOUT Voltage Reference Output. The AD9830 has an on-board reference of value 1.21 V nominal. The reference is made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND. COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic capacitor should be connected between COMP and AVDD. DIGITAL INTERFACE AND CONTROL MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an MCLK rising edge occurs. If FSELECT changes value when an MCLK rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge. WR Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9830. The data is loaded into the AD9830 on the rising edge of the WR pulse. This data is then loaded into the destination register on the MCLK rising edge. The WR pulse rising edge should not coincide with the MCLK rising edge as there will be an uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The WR rising edge should occur before an MCLK rising edge. The data will then be transferred into the destination register on the MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the destination register will be loaded on the next MCLK rising edge. D0–D15 Data Bus, Digital Inputs for destination registers. A0–A2 Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to be written. PSEL0, PSEL1 Phase Select Input. The AD9830 has four phase registers. These registers can be used to alter the value being input to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, the AD9830 samples the PSEL0 and PSEL1 inputs on the MCLK rising edge. Therefore, these inputs should be in steady state at the MCLK rising edge or, there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase register. SLEEP Low Power Control, active low digital input. SLEEP puts the AD9830 into a low power mode. Internal clocks are disabled and the DAC’s current sources and REFOUT are turned off. The AD9830 is re-enabled by taking SLEEP high. RESET Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog output of midscale. REV. A –5– AD9830 TERMINOLOGY Output Compliance Integral Nonlinearity The output compliance refers to the maximum voltage which can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compliance are generated, the AD9830 may not meet the specifications listed in the data sheet. For the AD9830, the maximum voltage which can be generated by the DAC is 1V. This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 LSB above the last code transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs. Spurious Free Dynamic Range Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between two adjacent codes in the DAC. Signal to (Noise + Distortion) Signal to (Noise + Distortion) is measured signal to noise at the output of the DAC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fMCLK/2) but excluding the dc component. Signal to (Noise + Distortion) is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical Signal to (Noise + Distortion) ratio for a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB where N is the number of bits. Thus, for an ideal 10-bit converter, Signal to (Noise + Distortion) = 61.96 dB. Along with the frequency of interest, harmonics of the fundamental frequency and images of the MCLK frequency will be present at the output of a DDS device. The spurious free dynamic range (SFDR) refers to the largest spur or harmonic which is present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the bandwidth ± 2 MHz about the fundamental frequency. The narrowband SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ± 200 kHz and ± 50 kHz about the fundamental frequency. Clock Feedthrough There will be feedthrough from the MCLK input to the analog output. The clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the AD9830’s output spectrum. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9830, THD is defined as 2 THD = 20log 2 2 2 2 (V 2 +V 3 +V 4 +V 5 +V 6 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonic. –6– REV. A Typical Performance Characteristics–AD9830 –35 60 50MHz –40 SFDR (0–MCLK/2) – dB TOTAL CURRENT – mA 55 AVDD = DVDD = +5V TA = +25°C fOUT = 200kHz 50 45 40 –45 30MHz –50 10MHz –55 –60 35 AVDD = DVDD = +5V 30 10 –65 20 30 40 MCLK FREQUENCY – MHz 0 50 0.05 0.1 0.15 0.2 fOUT/fMCLK 0.25 0.3 0.35 Figure 8. WB SFDR vs. fOUT/fMCLK for Various MCLK Frequencies Figure 5. Typical Current Consumption vs. MCLK Frequency 60 –50 AVDD = DVDD = +5V fOUT/fMCLK = 1/3 AVDD = DVDD = +5V fOUT = fMCLK/3 –55 SNR – dB SFDR (±200kHz) - dB 55 –60 –65 50 –70 45 –75 –80 10 20 30 40 MCLK FREQUENCY – MHz 40 10 50 30 40 MCLK FREQUENCY – MHz 50 Figure 9. SNR vs. MCLK Frequency Figure 6. Narrow Band SFDR vs. MCLK Frequency –40 –45 20 60 AVDD = DVDD = +5V AVDD = DVDD = +5V fOUT/fMCLK = 1/3 10MHz –50 SNR – dB SFDR (±2MHz) – dB 55 –55 30MHz 50 50MHz 45 –60 –65 10 40 20 30 40 MCLK FREQUENCY – MHz 50 0.1 0.2 fOUT/fMCLK 0.3 Figure 10. SNR vs. fOUT/fMCLK for Various MCLK Frequencies Figure 7. Wide Band SFDR vs. MCLK Frequency REV. A 0 –7– 0.4 0 0 –10 –10 –20 –20 –30 –30 10dB/DIV 10dB/DIV AD9830 –40 –50 –60 –70 –70 –80 –80 VBW 3kHz –90 START 0Hz RBW 1kHz STOP 25MHz ST 50 SEC Figure 11. fMCLK = 50 MHz, fOUT = 2.1 MHz, Frequency Word = ACO8312 0 0 –10 –10 –20 –20 –30 –30 –40 –50 –50 –60 –70 –70 –80 –80 VBW 3kHz –90 START 0Hz RBW 1kHz STOP 25MHz ST 50 SEC Figure 12. fMCLK = 50 MHz, fOUT = 3.1 MHz, Frequency Word = FDF3B64 0 –10 –20 –20 –30 –30 10dB/DIV 0 –40 –50 STOP 25MHz ST 50 SEC –40 –50 –60 –60 –70 –70 –80 –80 VBW 3kHz VBW 3kHz Figure 15. fMCLK = 50 MHz, fOUT = 11.1 MHz, Frequency Word = 38D4FDF4 –10 –90 START 0Hz RBW 1kHz STOP 25MHz ST 50 SEC –40 –60 –90 START 0Hz RBW 1kHz VBW 3kHz Figure 14. fMCLK = 50 MHz, fOUT = 9.1 MHz, Frequency Word = 2E978D50 10dB/DIV 10dB/DIV –50 –60 –90 START 0Hz RBW 1kHz 10dB/DIV –40 –90 START 0Hz RBW 1kHz STOP 25MHz ST 50 SEC Figure 13. fMCLK = 50 MHz, fOUT = 7.1 MHz, Frequency Word = 245A1CAC VBW 3kHz STOP 25MHz ST 50 SEC Figure 16. fMCLK = 50 MHz, fOUT = 13.1 MHz, Frequency Word = 43126E98 –8– REV. A AD9830 0 –10 –20 10dB/DIV –30 –40 –50 –60 –70 –80 –90 START 0Hz RBW 1kHz STOP 25MHz ST 50 SEC VBW 3kHz Figure 17. fMCLK = 50 MHz, fOUT = 16.5 MHz, Frequency Word = 547AE148 Register Size Description A2 A1 A0 Destination Register FREQ0 REG 32 Bits FREQ1 REG 32 Bits PHASE0 REG 12 Bits Frequency Register 0. This defines the output frequency, when FSELECT = 0, as a fraction of the MCLK frequency. Frequency Register 1. This defines the output frequency, when FSELECT = 1, as a fraction of the MCLK frequency. Phase Offset Register 0. When PSEL0 = PSEL1 = 0, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 1. When PSEL0 = 1 and PSEL1 = 0, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 2. When PSEL0 = 0 and PSEL1 = 1, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 3. When PSEL0 = PSEL1 = 1, the contents of this register are added to the output of the phase accumulator. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 FREQ0 REG 16 LSBs FREQ0 REG 16 MSBs FREQ1 REG 16 LSBs FREQ1 REG 16 MSBs PHASE0 REG PHASE1 REG PHASE2 REG PHASE3 REG PHASE1 REG PHASE2 REG PHASE3 REG 12 Bits 12 Bits 12 Bits Figure 19. Addressing the Control Registers D0 MSB LSB Figure 20. Frequency Register Bits D15 D14 D13 D12 D11 D0 X LSB X X X MSB X = Don't Care Figure 21. Phase Register Bits Figure 18. AD9830 Control Registers REV. A D15 –9– AD9830 CIRCUIT DESCRIPTION Numerical Controlled Oscillator + Phase Modulator The AD9830 provides an exciting new level of integration for the RF/Communications system designer. The AD9830 combines the Numerical Controlled Oscillator (NCO), SINE Look-Up table, Frequency and Phase Modulators, and a Digital-to-Analog Converter on a single integrated circuit. The internal circuitry of the AD9830 consists of three main sections. These are: Numerical Controlled Oscillator (NCO) + Phase Modulator SINE Look-Up Table Digital-to-Analog Converter This consists of two frequency select registers, a phase accumulator and four phase offset registers. The main component of the NCO is a 32-bit phase accumulator which assembles the phase component of the output signal. Continuous time signals have a phase range of 0 to 2π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9830 is implemented with 32 bits. Therefore, in the AD9830, 2π = 232. Likewise, the ∆Phase term is scaled into this range of numbers 0 < ∆Phase < 232 –1. Making these substitutions into the equation above The AD9830 is a fully integrated Direct Digital Synthesis (DDS) chip. The chip requires one reference clock, two low precision resistors and eight decoupling capacitors to provide digitally created sine waves up to 25 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain allowing accurate and simple realization of complex modulation algorithms using DSP techniques. f = ∆Phase × fMCLK/232 where 0 < ∆Phase < 232 With a clock signal of 50 MHz and a phase word of 051EB852 hex f = 51EB852 × 50 MHz/232 = 1.000000000931 MHz The input to the phase accumulator (i.e., the phase step) can be selected either from the FREQ0 Register or FREQ1 Register and this is controlled by the FSELECT pin. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. More complex frequency modulation schemes can be implemented by updating the contents of these registers. This facilitates complex frequency modulation schemes, such as GMSK. THEORY OF OPERATION Sine waves are typically thought of in terms of their magnitude form a (t) = sin (ωt). However, these are nonlinear and not easy to generate except through piece wise construction. On the other hand, the angular information is linear in nature. That is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of ω = 2πf Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit PHASE Registers. The contents of this register are added to the most significant bits of the NCO. The AD9830 has four PHASE registers. The resolution of the phase registers equals 2π/4096. MAGNITUDE +1 Sine Look-Up Table (LUT) To make the output useful, the signal must be converted from phase information into a sinusoidal value. Since phase information maps directly into amplitude, a ROM LUT converts the phase information into amplitude. To do this, the digital phase information is used to address a sine ROM LUT. Although the NCO contains a 32-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary as this would require a look-up table of 232 entries. 0 –1 2π PHASE 0 Figure 22. Sine Wave Knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined. ∆Phase = ωδt Solving for ω It is necessary only to have sufficient phase resolution in the LUTs such that the dc error of the output waveform is dominated by the quantization error in the DAC. This requires the look-up table to have two more bits of phase resolution than the 10-bit DAC. Digital-to-Analog Converter ω = ∆Phase/δt = 2πf Solving for f and substituting the reference clock frequency for the reference period (1/fMCLK = δt) f = ∆Phase × fMCLK/2π The AD9830 builds the output based on this simple equation. A simple DDS chip can implement this equation with three major subcircuits. The AD9830 includes a high impedance current source 10-bit DAC, capable of driving a wide range of loads at different speeds. Full-scale output current can be adjusted, for optimum power and external load requirements, through the use of a single external resistor (RSET). The DAC can be configured for single or differential ended operation. IOUT can be tied directly to AGND for single ended operation or through a load resistor to develop an output voltage. The load resistor can be any value required, as long as the –10– REV. A AD9830 FSELECT, PSEL0 and PSEL1 are sampled on the MCLK rising edge. Again, these inputs should be valid when an MCLK rising edge occurs as there will be an uncertainty of one MCLK cycle introduced otherwise. When these inputs change value, there will be a pipeline delay before control is transferred to the selected register—there will be a pipeline delay before the analog output is controlled by the selected register. Similarly, there is a delay when a new word is written to a register. PSEL0, PSEL1, FSELECT and WR have latencies of six MCLK cycles. full-scale voltage developed across it does not exceed the voltage compliance range. Since full-scale current is controlled by RSET, adjustments to RSET can balance changes made to the load resistor. However, if the DAC full-scale output current is significantly less than 20 mA, the linearity of the DAC may degrade. DSP and MPU Interfacing The AD9830 has a parallel interface, with 16 bits of data being loaded during each write cycle. The frequency or phase registers are loaded by asserting the WR signal. The destination register for the 16-bit data is selected using the address inputs A0, A1 and A2. The phase registers are 12 bits wide so, only the 12 LSBs need to be valid—the 4 MSBs of the 16 bit word do not have to contain valid data. Data is loaded into the AD9830 by pulsing WR low, the data being latched into the AD9830 on the rising edge of WR. The values of inputs A0, A1 and A2 are also latched into the AD9830 on the WR rising edge. The appropriate register is updated on the next MCLK rising edge. To ensure that the AD9830 contains valid data at the rising edge of MCLK, the rising edge of the WR pulse should not coincide with the rising MCLK edge. The WR pulse must occur several nanoseconds before the MCLK rising edge. If the WR rising edge occurs at the MCLK rising edge, there is an uncertainty of one MCLK cycle regarding the loading of the destination register—the destination register may be loaded with the new data immediately or the destination register may be updated on the next MCLK rising edge. To avoid any uncertainty, the times listed in the specifications should be complied with. The flow chart in Figure 23 shows the operating routine for the AD9830. When the AD9830 is powered up, the part should be reset using RESET. This will reset the phase accumulator to zero so that the analog output is at midscale. RESET does not reset the phase and frequency registers. These registers will contain invalid data and, therefore, should be set to zero by the user. The registers to be used should be loaded, the analog output being fMCLK/232 × FREG where FREG is the value contained in the selected frequency register. This signal will be phase shifted by an amount 2π/4096 × PHASEREG where PHASEREG is the value contained in the selected phase register. When FSELECT, PSEL0 and PSEL1 are programmed, there will be a pipeline delay of approximately 6 MCLK cycles before the analog output reacts to the change on these inputs. RESET DATA WRITE FREG<0, 1> = 0 PHASEREG<0, 1, 2, 3> = 0 DATA WRITE FREG<0> = fOUT0/fMCLK*232 FREG<1> = fOUT1/fMCLK*232 PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3> SELECT DATA SOURCES SET FSELECT SET PSEL0, PSEL1 WAIT 6 MCLK CYCLES DAC OUTPUT VOUT = VREFIN*8*ROUT/RSET*(1 + SIN(2π(FREG*fMCLK*t/232 + PHASEREG/212))) CHANGE PHASE? YES NO NO NO CHANGE FSELECT CHANGE FOUT? YES NO CHANGE PHASEREG? CHANGE FREG? CHANGE PSEL0, PSEL1 YES YES Figure 23. Flow Chart for AD9830 Initialization and Operation REV. A –11– AD9830 APPLICATIONS The AD9830 contains functions which make it suitable for modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9830. In a FSK application, the two frequency registers of the AD9830 are loaded with different values, one frequency will represent the space frequency while the other will represent the mark frequency. The digital data stream is fed to the FSELECT pin which will cause the AD9830 to modulate the carrier frequency between the two values. The AD9830 has four phase registers which enable the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount which is related to the bit stream being input to the modulator. The presence of four shift registers eases the interaction needed between the DSP and the AD9830. The frequency and phase registers can be written to continuously, if required. The maximum update rate equals the frequency of the MCLK. However, if a selected register is loaded with a new word, there will be a delay of 6 MCLK cycles before the analog output will change accordingly. The AD9830 is also suitable for signal generator applications. With its low current consumption, the part is suitable for mobile applications in which it can be used as a local oscillator. Figure 24 shows the interface between the AD9830 and AD6459 which is a down converter used on the receive side of mobile phones or basestations. AD9830 RSET 10 BITS 1kΩ FILTER 51Ω 51Ω 0.1µF LOIP IRxP AD6459 RFHI IRxN MXOP IFIP ANTENNA 0° RFLO MXOM BANDPASS FILTER FREF PLL 90° FLTR IFIM QRxP MIDPOINT BIAS GENERATOR QRxN GAIN TC COMPENSATION VPS1 VPS2 GAIN GREF BIAS CIRCUIT PRUP COM1 COM2 Figure 24. AD9830 and AD6459 Receiver Circuit –12– REV. A AD9830 Grounding and Layout AD9830 Evaluation Board The printed circuit board that houses the AD9830 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD9830 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9830. If the AD9830 is in a system where multiple devices require AGND to DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9830. The AD9830 Evaluation Board allows designers to evaluate the high performance AD9830 DDS Modulator with a minimum of effort. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD9830 to avoid noise coupling. The power supply lines to the AD9830 should use as large a track as is possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. Good decoupling is important. The analog and digital supplies to the AD9830 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND respectively with 0.1 µF ceramic capacitors in parallel with 10 µF tantalum capacitors. To achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD of the AD9830, it is recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD9830 and AGND and the recommended digital supply decoupling capacitors between the DVDD pins and DGND. REV. A To prove that this device will meet the user’s waveform synthesis requirements, the user only requires a +5 V power supply, an IBM-compatible PC and a spectrum analyzer along with the evaluation board. The evaluation setup is shown below. The DDS Evaluation kit includes a populated, tested AD9830 printed circuit board along with software which controls the AD9830 in a Windows environment. IBM COMPATIBLE PC PARALLEL PORT CENTRONICS PRINTER CABLE AD9830.EXE AD9830 EVALUATION BOARD Figure 25. AD9830 Evaluation Board Setup Using the AD9830 Evaluation Board The AD9830 Evaluation kit is a test system designed to simplify the evaluation of the AD9830. Provisions to control the AD9830 from the printer port of an IBM-compatible PC are included along with the necessary software. An application note is also available with the evaluation board which gives information on operating the evaluation board. Prototyping Area An area is available on the evaluation board where the user can add additional circuits to the evaluation test set. Users may want to build custom analog filters for the outputs or add buffers and operational amplifiers which are to be used in the final application. XO vs. External Clock The AD9830 can operate with master clocks up to 50 MHz. A 50 MHz oscillator is included on the evaluation board. However, this oscillator can be removed and an external CMOS clock connected to the part, if required. Power Supply Power to the AD9830 evaluation board must be provided externally through the pin connections. The power leads should be twisted to reduce ground loops. –13– AD9830 DVDD AVDD 0.1µF C1, C2, C3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0.1µF C4, C5 AVDD DVDD LATCH D0 D1 D2 D3 D4 D5 D6 D7 DVDD 4, 5, 9, 25 U2 0.1µF C13 VDD J1 14 74HC574 PC INTERFACE 21 CK WR RESET LATCH LOAD D7 D8 REFIN VDD REFOUT 22 31 32 FSADJUST MCLK 51Ω R6 FSELECT 7 DVDD DVDD 44 PSEL0 SMB7 MCLK IOUT SLEEP DGND SW 10µF C11 SMB6 IOUT 3 LOAD 0.1µF C10 AVDD 1kΩ R5 PSEL1 10 LK3 0.1µF C8 J3 RESET 11 LK2 SMB2 J2 47 WR 12 LK1 DVDD 10µF C9 U1 A0 35 RESET AD9830 A2 8 WR 2 10nF C7 D0 34 SMB1 SMB5 1 D7 CK LATCH R3 10kΩ 10nF C6 48 LK5 0.1µF C14 RESET SMB3 COMP U3 D0 R2 10kΩ D15 LOAD DVDD 74HC574 R1 10kΩ AVDD 38, 43 6,13, 29 AGND 45 51Ω R7 36, 39, 41, 46 LK4 SMB4 WR R4 50Ω DVDD C12 0.1µF U4 DVDD OUT XTAL1 DGND Figure 26. Evaluation Board Layout COMPONENT LIST Integrated Circuits U1 U2, U3 XTAL1 Capacitors C9, C11 C8, C10, C12–C14 C1–C5 C6, C7 Links AD9830 (48-Pin TQFP) 74HC574 Latches OSC XTAL 50 MHz 10 µF Tantalum Capacitor 0.1 µF Ceramic Capacitor 0.1 µF Ceramic Chip Capacitor 10 nF Ceramic Capacitor Resistors R5 R6, R7 R4 R1–R3 1 kΩ Resistor 51 Ω Resistor 50 Ω Resistor 10 kΩ Resistor LK5 LK1, LK2, LK3, LK4 Two Pin Link Three Pin Link Switch SW End Stackable Switch (SDC Double Throw) Sockets SMB1–SMB7 Sub-Miniature BNC Connector Connectors J2, J3 J1 –14– PCB Mounting Terminal Block 36-Pin Edge Connector REV. A AD9830 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead TQFP (ST-48) 0.063 (1.60) MAX 0.276 (7.0) BSC 0.276 (7.0) BSC 37 36 48 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.006 (0.15) 0.002 (0.05) 0° – 7° REV. A 0° MIN 0.007 (0.18) 0.004 (0.09) 12 13 0.019 (0.5) BSC –15– 25 24 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) BSC 0.030 (0.75) 0.018 (0.45) 0.354 (9.00) BSC 0.030 (1.45) (0.75) 0.057 0.018 (1.35) (0.45) 0.053 –16– PRINTED IN U.S.A. C2142a–10–9/96