AD SSM2602

Low Power Audio Codec
SSM2602
Preliminary Technical Data
FEATURES
GENERAL DESCRIPTION
Stereo, 24-bit analog-to-digital and digital-to-analog converters
DAC SNR: 98 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
Highly efficient headphone amplifier
Complete stereo/mono or microphone/line interface
Low power
7 mW stereo playback (1.8 V/1.8 V supplies)
14 mW record and playback (1.8 V/1.8 V supplies)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital core: 1.8 V to 3.6 V
Digital I/O: 1.8 V/3.6 V
256 fS/384 fS or USB master clock rate: 12 MHz, 24 MHz
Audio sample rates: 8 kHz,16 kHz, 32 kHz, 44.1 kHz, 48 kHz,
88.2 kHz, and 96 kHz
28-lead, 5 mm × 5 mm LFCSP (QFN) package
The SSM2602 is a low power, high quality stereo audio codec
for portable digital audio applications with stereo programmable
gain amplifier (PGA) line and monaural microphone inputs. It
features two 24-bit analog-to-digital converter (ADC) channels
and two 24-bit digital-to-audio (DAC) converter channels.
The SSM2602 can operate as a master or a slave. It offers
various master clock frequencies, including 12 MHz or 24 MHz
for USB devices; standard 256 fS rates, such as 12.288 MHz and
24.576 MHz; and many common audio-sampling rates, such as
96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 16 kHz, and 8 kHz.
The SSM2602 can operate at power supplies as low as 1.8 V for
the analog circuitry and 1.5 V for the digital circuitry. The
maximum voltage supply is 3.6 V for all supplies.
The SSM2602 software-programmable output options provide
the user with many application options, such as speaker driver,
headphone driver, or both. Its volume control functions provide
a large range of gain control of the audio signal.
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The SSM2602 is specified over the industrial temperature range
of −40°C to +85°C. It is available in a 28-lead, 5 mm × 5 mm
lead frame chip scale package (LFCSP).
FUNCTIONAL BLOCK DIAGRAM
AVDD
VMID AGND
DBVDD DGND DCVDD
MICBIAS
ATTEN
ATTEN
–34.5dB~+33dB,
1.5dB STEP
HPVDD PGND
BYPASS/MUTE 3dB STEP
SSM2602
6dB~15dB/MUTE 3dB STEP
–73dB~+6dB,
1dB STEP
RHPOUT
RLINEIN
MUX
ADC
DAC
ROUT
DIGITAL
PROCESSOR
MICIN
LOUT
14dB/34dB
MUX
LLINEIN
ADC
DAC
LHPOUT
ATTEN
ATTEN
CLK
MCLK/ XTO CLKOUT
XTI
–73dB~+6dB,
1dB STEP
6dB~15dB/MUTE 3dB STEP
BYPASS/MUTE 3dB STEP
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
DACDAT ADCDAT BCLK DACLRC ADCLRC MODE CSB
SDIN SCLK
06858-001
–34.5dB~+33dB,
1.5dB STEP
Figure 1.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
SSM2602
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Software Control Interface........................................................ 13
Applications....................................................................................... 1
Applications..................................................................................... 14
General Description ......................................................................... 1
Typical Application Circuits ......................................................... 15
Functional Block Diagram .............................................................. 1
Register Map ................................................................................... 17
Revision History ............................................................................... 2
Register Map Details ...................................................................... 18
Specifications..................................................................................... 3
Left-Channel ADC Input Volume, Address 0x00.................. 18
Recommended Operating Conditions ...................................... 4
Right-Channel ADC Input Volume, Address 0x01 ............... 19
Digital Filter Characteristics ....................................................... 4
Left-Channel DAC Volume, Address 0x02............................. 20
Timing Characteristics ................................................................ 5
Right-Channel DAC Volume, Address 0x03 .......................... 20
Timing Diagrams.......................................................................... 5
Analog Audio Path, Address 0x04 ........................................... 21
Absolute Maximum Ratings............................................................ 6
Digital Audio Path Control, Address 0x05 ............................. 21
Thermal Resistance ...................................................................... 6
Power Management, Address 0x06.......................................... 22
ESD Caution.................................................................................. 6
Power Consumption .................................................................. 22
Pin Configuration and Function Descriptions............................. 7
Digital Audio I/F, Address 0x07 ............................................... 23
Typical Performance Characteristics ............................................. 8
Sampling Rate, Address 0x08.................................................... 23
Converter Filter Response........................................................... 8
ACTIVE, Address 0x09 ............................................................. 25
Digital De-Emphasis Characteristics......................................... 9
RESET, Address 0x0F................................................................. 25
Theory of Operation ...................................................................... 10
ALC Control 1, Address 0x10................................................... 25
ADC High-Pass Filter ................................................................ 10
ALC Control 2, Address 0x11................................................... 26
Automatic Level Control (ALC)............................................... 10
Noise Gate, Address 0x12.......................................................... 26
Analog Interface ......................................................................... 11
Outline Dimensions ....................................................................... 27
Digital Audio Interface .............................................................. 11
Ordering Guide .......................................................................... 27
REVISION HISTORY
9/07—Revision PrB: Preliminary Version
Rev. PrB | Page 2 of 28
Preliminary Technical Data
SSM2602
SPECIFICATIONS
TA = 25°C, AVDD = DVDD = 3.3 V, PVDD = 3.3 V, 1 kHz signal, fS = 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted.
Table 1.
Parameter
OPERATING CONDITIONS
Analog Voltage Supply (AVDD)
Digital Power Supply
Ground (AGND, PGND, DGND)
POWER CONSUMPTION
Power-Up
Stereo Record (1.8 V)
Stereo Record (3.3 V)
Stereo Playback (1.8 V)
Stereo Playback (3.3 V)
Power-Down
LINE INPUT
Input Signal Level (0 dB)
Input Impedance
Input Capacitance
Signal-to-Noise Ratio (A-weighted)
Min
Typ
Max
Unit
1.8
1.5
3.3
3.3
0
3.6
3.6
V
V
V
7
22
7
22
40
85
Total Harmonic Distortion (THD)
Channel Separation
Programmable Gain
Gain Step
Mute Attenuation
MICROPHONE INPUT
Input Signal Level
Signal-to-Noise Ratio (A-weighted)
Total Harmonic Distortion
Power Supply Rejection Ratio
Mute Attenuation
Input Resistance
Input Capacitance
MICROPHONE BIAS
Bias Voltage
Bias Current Source
Noise in the Signal Bandwidth
LINE OUTPUT
DAC
Full-Scale Output
Signal-to-Noise Ratio (A-Weighted)
THD + N
Power Supply Rejection Ratio
Channel Separation
−34.5
1 × AVDD/3.3
200
10
480
10
90
87
−80
−75
80
0
1.5
−80
33.5
1
85
−70
50
80
10
10
mW
mW
mW
mW
μW
V rms
kΩ
kΩ
kΩ
pF
dB
dB
dB
dB
dB
dB
dB
dB
V rms
dB
dB
dB
dB
kΩ
pF
0.75 × AVDD
3
40
Conditions
V
mA
nV/√Hz
PGA gain = 0 dB
PGA gain = +33 dB
PGA gain = −34.5 dB
PGA gain = 0 dB, AVDD = 3.3 V
PGA gain = 0 dB, AVDD = 1.8 V
−1 dBFS input, AVDD = 3.3 V
−1 dBFS input, AVDD = 1.8 V
Microphone gain = 0 dB (RSOURCE = 40 kΩ)
0 dBFS input, 0 dB gain
20 Hz to 20 kHz
−1 dBFS input DAC + line output
1 × AVDD/3.3
100
98
−80
−75
50
80
Rev. PrB | Page 3 of 28
V rms
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
SSM2602
Parameter
HEADPHONE OUTPUT
Full-Scale Output Voltage
Maximum Output Power
Signal-to-Noise Ratio (A-Weighted)
THD + N
Power Supply Rejection Ratio
Mute Attenuation
LINE INPUT TO LINE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
Total Harmonic Distortion
Power Supply Rejection
MICROPHONE INPUT TO
HEADPHONE OUTPUT
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
Power Supply Rejection Ratio
Programmable Attenuation
Gain Step
Mute Attenuation
Preliminary Technical Data
Min
92
Typ
Max
Unit
1 × AVDD/3.3
30
60
100
−50
−55
50
80
V rms
mW
mW
dB
dB
dB
dB
dB
1 × AVDD/3.3
96
−80
50
V rms
dB
dB
dB
1 × AVDD/3.3
98
50
V rms
dB
dB
dB
dB
dB
6
15
3
80
Conditions
RL = 32 Ω
RL = 16 Ω
POUT = 10 mW
POUT = 20 mW
RECOMMENDED OPERATING CONDITIONS
Table 2.
Parameter
Analog Voltage Supply (AVDD)
Digital Power Supply
Ground (AGND, PGND, DGND
Min
1.8
1.5
Typ
3.3
3.3
0
Max
3.6
3.6
Unit
V
V
V
Typ
Max
Unit
Conditions
0.445 fS
Hz
Hz
dB
Hz
dB
Hz
Hz
Hz
±0.04 dB
−6 dB
DIGITAL FILTER CHARACTERISTICS
Table 3.
Parameter
ADC FILTER
Pass Band
Min
0
0.5 fS
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
High-Pass Filter Corner Frequency
DAC FILTER
Pass Band
±0.04
0.555 fS
−60
3.7
10.4
21.6
0
0.445 fS
0.5 fS
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
±0.04
0.555 fS
−58
Rev. PrB | Page 4 of 28
Hz
Hz
dB
Hz
dB
f > 0.567 fS
−3 dB
−0.5 dB
−0.1 dB
±0.03 dB
−6 dB
f > 0.565 fS
4
Preliminary Technical Data
SSM2602
TIMING CHARACTERISTICS
Table 4.
Parameter
fSCLK
tSCLKPL
tSCLKPH
tSCH
tSCS
tDS
tSDIN-SCLKR
tSDIN-SCLKF
tHCS
tDH
tMIN
0
1.3
600
600
600
100
Limit
tMAX
550
300
300
600
900
Unit
kHz
μs
ns
ns
ns
ns
ns
ns
ns
ns
Description
SCLK frequency
SCLK low pulse width
SCLK high pulse width
Hold time (start condition)
Setup time (start condition)
Data setup time
SDIN, SCLK rise time
SDIN, SCLK fall time
Setup time (hold condition)
Data hold time
TIMING DIAGRAMS
TBD
Rev. PrB | Page 5 of 28
SSM2602
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
At 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 5.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Supply Voltage
Input Voltage
Common-Mode Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
5V
VDD
VDD
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
Table 6. Thermal Resistance
Package Type
28-Lead, 5 mm × 5 mm LFCSP
θJA
TBD
θJC
TBD
Unit
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. PrB | Page 6 of 28
6
Preliminary Technical Data
SSM2602
28
27
26
25
24
23
22
SCLK
SDIN
CSB
MODE
LLINEIN
RLINEIN
MICIN
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
PIN 1
INDICATOR
SSM2602
TOP VIEW
(Not to Scale)
21
20
19
18
17
16
15
MICBIAS
VMID
AGND
AVDD
ROUT
LOUT
PGND
06858-002
DACDAT
DACLRC
ADCDAT
ADCLRC
HPVDD
LHPOUT
RHPOUT
8
9
10
11
12
13
14
MCLK/XTI
XTO
DCVDD
DGND
DBVDD
INT/CLKOUT
BCLK
Figure 2. Pin Configuration of SSM2602
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
Mnemonic
MCLK/XTI
XTO
DCVDD
DGND
DBVDD
CLKOUT
BCLK
DACDAT
DACLRC
Type
Digital Input
Digital Output
Digital Supply
Digital Ground
Digital Supply
Digital Output
Digital Input/Output
Digital Input
Digital Input/Output
10
11
ADCDAT
ADCLRC
Digital Output
Digital Input/Output
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
HPVDD
LHPOUT
RHPOUT
PGND
LOUT
ROUT
AVDD
AGND
VMID
MICBIAS
MICIN
RLINEIN
LLINEIN
MODE
CSB
Analog Supply
Analog Output
Analog Output
Analog Ground
Analog Output
Analog Output
Analog Supply
Analog Ground
Analog Output
Analog Output
Analog Input
Analog Input
Analog Input
Digital Input
Digital Input
27
28
SDIN
SCLK
Digital Input/Output
Digital Input
Description
Master Clock Input/Crystal Input
Crystal Output
Digital Core Supply
Digital Ground
Digital I/O Supply
Buffered Clock Output
Digital Audio Bit Clock. This pin is pulled down when the ACTIVE register is set to 0.
DAC Digital Audio Data Input
DAC Sample Rate Clock (from Left and Right Channels). This pin is pulled down
when the ACTIVE register is set to 0.
ADC Digital Audio Data Output
ADC Sample Rate Clock (from Left and Right Channels). This pin is pulled down
when the ACTIVE register is set to 0.
Headphone Supply
Left-Channel Headphone Output
Right-Channel Headphone Output
Headphone Ground
Left-Channel Line Output
Right-Channel Line Output
Analog Supply
Analog Ground
Middle Voltage Decoupling Capacitor
Microphone Bias
Microphone Input Signal
Right-Channel Line/Microphone Input
Left-Channel Line/Microphone Input
Control Interface Selection to Select I2C®/SPI
3-Wire MPU Chip Select/2-Wire MPU Interface Address Selection, Active Low. This pin is
pulled up when the ACTIVE register is set to 0.
3-Wire MPU Data Input/2-Wire MPU Data Input/Output
3-Wire MPU Clock Input/2-Wire MPU Clock Input
Rev. PrB | Page 7 of 28
SSM2602
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
–40
–50
–60
–70
–70
–80
–80
–90
–100
0.5
1.0
1.5
2.0
2.5
FREQUENCY (fS)
3.0
0
0.03
0.03
0.02
0.02
MAGNITUDE (dB)
0.04
0.01
0
–0.01
2.0
2.5
3.0
0.01
0
–0.01
–0.02
–0.02
–0.03
–0.03
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (fS)
06858-005
MAGNITUDE (dB)
1.5
Figure 5. DAC Digital Filter Frequency Response
0.04
0
1.0
FREQUENCY (fS)
Figure 3. ADC Digital Filter Frequency Response
–0.04
0.5
–0.04
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (fS)
06858-006
0
06858-003
–90
–100
06858-004
MAGNITUDE (dB)
MAGNITUDE (dB)
CONVERTER FILTER RESPONSE
Figure 6. DAC Digital Filter Ripple
Figure 4. ADC Digital Filter Ripple
Rev. PrB | Page 8 of 28
8
Preliminary Technical Data
SSM2602
DIGITAL DE-EMPHASIS CHARACTERISTICS
0
0.20
–1
0.15
–2
0.10
MAGNITUDE (dB)
MAGNITUDE (dB)
–3
–4
–5
–6
0.05
0
–0.05
–7
–0.10
–8
2
0
4
6
8
10
FREQUENCY (kHz)
12
14
16
–0.20
06858-007
–10
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
Figure 7. De-Emphasis Frequency Response (32 kHz)
06858-011
–0.15
–9
Figure 10. De-Emphasis Error (44.1 kHz)
0
0.20
–1
0.15
–2
0.10
MAGNITUDE (dB)
MAGNITUDE (dB)
–3
0.05
0
–0.05
–4
–5
–6
–7
–0.10
–8
–0.15
4
6
8
FREQUENCY (kHz)
10
12
14
–10
0
2
4
6
8
10
12
14
16
18
20
22
FREQUENCY (kHz)
Figure 8. De-Emphasis Error (32 kHz)
06858-008
2
0
06858-010
–0.20
–9
Figure 11. De-Emphasis Frequency Response (48 kHz)
0
0.20
–1
0.15
–2
0.10
MAGNITUDE (dB)
–4
–5
–6
0.05
0
–0.05
–7
–0.10
–8
–10
0
2
4
6
8
10
12
14 16
FREQUENCY (kHz)
18
20
22
24
Figure 9. De-Emphasis Frequency Response (44.1 kHz)
–0.20
0
2
4
6
8
10
12
14
FREQUENCY (kHz)
Figure 12. De-Emphasis Error (48 kHz)
Rev. PrB | Page 9 of 28
16
18
20
06858-012
–0.15
–9
06858-009
MAGNITUDE (dB)
–3
SSM2602
Preliminary Technical Data
THEORY OF OPERATION
ADC HIGH-PASS FILTER
Decay (Gain Ramp-Up) Time
DC offset can be removed by using the SSM2602 adjustable
digital high-pass filter (see Table 3 for characteristics).
The ADC and DAC employ separate digital filters.
This is the time for the PGA gain to ramp up through 90% of its
range. The time for the recording level to return to its target value
therefore depends on both the decay time and the gain adjustment
required. If the gain adjustment is small, the time to return to
the target value will be less than the decay time.
AUTOMATIC LEVEL CONTROL (ALC)
Attack (Gain Ramp-Down) Time
Codec has an automatic level control that aims to keep a constant
recording volume irrespective of the input signal level. This is
achieved by continuously adjusting the PGA gain so that the
signal level at the ADC input remains constant. A digital peak
detector monitors the ADC output and changes the PGA gain if
necessary.
This is the time for the PGA gain to ramp down through 90% of
its range. The time for the recording level to return to its target
value therefore depends on both the attack time and the gain
adjustment required. If the gain adjustment is small, the time
to return to the target value will be less than the attack time.
Digital Filter Characteristics
INPUT SIGNAL
PGA
SIGNAL
AFTER
ALC
DECAY TIME
ATTACK TIME
Figure 13. PGA and ALC Decay Time and Attack Time Definitions
Rev. PrB | Page 10 of 28
06858-021
ALC TARGET
VALUE
Preliminary Technical Data
SSM2602
ANALOG INTERFACE
DIGITAL AUDIO INTERFACE
Microphone Input
The digital audio input can support various communication
protocols:
High impedance input MIC
•
•
•
•
TBD
Headphone Output
TBD
Sidetone Insertion
Right justified
Left justified
I2S mode
Digital-signal processor (DSP) mode
The mode selection is performed by writing to the FORMAT [1:0]
bits of the digital audio interface register (Register R7). All
modes are MSB first and operate with data of 16 to 32 bits.
TBD
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
ADCDAT/
DACDAT
1
2
3
4
N
1
2
3
06858-013
BCLK
N
Figure 14. Left-Justified Audio Interface
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
ADCDAT/
DACDAT
N
4
3
2
1
N
4
3
1
2
06858-014
BCLK
Figure 15. Right-Justified Audio Interface
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
ADCDAT/
DACDAT
1
2
3
4
N
Figure 16. I2S Audio Interface
Rev. PrB | Page 11 of 28
1
2
3
N
06858-015
BCLK
SSM2602
Preliminary Technical Data
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
ADCDAT/
DACDAT
1
2
3
N
1
2
06858-016
BCLK
N
3
Figure 17. DSP/Pulse Code Modulation (PCM) Mode Audio Interface Submode 1 (SM1) [Bit LRP = 0]
1/fS
LEFT CHANNEL
ADCLRC/
DACLRC
RIGHT CHANNEL
FALLING EDGE CAN OCCUR ANY WHERE IN THIS AREA
ADCDAT/
DACDAT
1
2
3
N
1
2
3
Figure 18. DSP/PCM Mode Audio Interface Submode 2 (SM2) [Bit LRP = 1]
Rev. PrB | Page 12 of 28
N
06858-017
BCLK
Preliminary Technical Data
SSM2602
In 3-wire (SPI) mode, SDIN is used for the program data, SCLK
is used to clock in the program data, and CSB is used to latch in
the program data. In 2-wire (I2C) mode, SDIN is used for serial
data, SCLK is used for the serial clock, and the state of the CSB
pin allows the user to select one of two addresses (see Table 9).
SOFTWARE CONTROL INTERFACE
The software control interface can be operated with a 3-wire (SPI)
or 2-wire (I2C) interface. Selection of the interface format is
achieved by setting the state of the MODE pin.
Table 8. Selecting the Interface Format
MODE Pin Setting
0
1
Table 9. Selecting the Address
Interface
2-wire (I2C) interface
3-wire (SPI) interface
CSB Pin Setting
0
1
Address
0011010
0011011
CSB
CCLK
B14
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
9
1–7
8
ACK
DATA
B01
B0
06858-018
B15
SDIN
NOTES
1. B15 TO B9 ARE REGISTER MAP ADDRESS.
2. B8 TO B0 ARE REGISTER DATA.
Figure 19. SPI Serial Interface
SCLOCK
S
1–7
8
9
START
ADDR
R/W
ACK
1–7
8
SUBADDRESS
9
P
ACK
STOP
06858-019
SDATA
Figure 20. SSM2602 2-Wire I2C Generalized Clocking Diagram
WRITE
SEQUENCE
S
A7
...
A1
A0
A(S)
B15 ...
B9
B8
A(S)
B7
...
B0
P
A(S)
0
DEVICE
ADDRESS
READ
SEQUENCE
S
A7
...
A1
REGISTER
ADDRESS
A0
A(S)
B15
...
B9
REGISTER
DATA
0
A(S)
S
A7
...
A1
0
DEVICE
ADDRESS
A0
A(S)
B7
...
B0
A(M)
0
...
0
B8
A(M)
P
1
REGISTER
ADDRESS
DEVICE
ADDRESS
06858-022
S/P = START/STOP BIT.
A0 = I2C R/W BIT.
A(S) = ACKNOWLEGE BY SLAVE.
A(M) = ACKNOWLEGE BY MASTER.
A(M) = ACKNOWLEGE BY MASTER.
REGISTER
DATA
(SLAVE DRIVE)
Figure 21. SSM2602 I2C Write and Read Sequences
Rev. PrB | Page 13 of 28
SSM2602
Preliminary Technical Data
APPLICATIONS
TBD
Rev. PrB | Page 14 of 28
Preliminary Technical Data
SSM2602
TYPICAL APPLICATION CIRCUITS
AVDD
VMID
AVSS
DBVDD DVSS DCVDD
HPVDD
SSM2602
HPVSS
PWRPD
REF
ATTEN
MICBIAS
ATTEN
MICBPD
ADCPD
DACPD
RHPOUT
RLINEIN
MUX
LINPD
ADC
DAC
LHPPD
ROUT
LADCPD
MICIN
DIGITAL
PROCESSOR
LDACPD
OUTPD
MICPD
LOUT
MUX
LLINEIN
DAC
LHPOUT
RINPD
RADCPD
RDACPD
RHPPD
ATTEN
ATTEN
OSCPD
CLKOUTPD
OSC
MCLK/XTI
CLK GEN
XTO
CLKOUT
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
DACDAT ADCDAT BCLK DACLRC ADCLRC MODE CSB SDINS CLK
Figure 22. SSM2602 Power Management Functional Location Diagram
Rev. PrB | Page 15 of 28
06858-020
LINEPD
ADC
SSM2602
Preliminary Technical Data
+3.3V_VAA
L2
FB
L1
FB
C23
0.1uF
C21
10uF +
C20
0.1uF
+
C22
10uF
+3,3V_VDD
3
5
C24
0.1uF
+
C25
10uF
1uF
C4
220PF
24
L_LINE_IN
ROUT
R_LINE_IN
LOUT
J4
C12
1uF
R11
100
17
BNC
J5
1uF
MIC_IN
2
DACLRC
DACDAT
ADCDAT
ADCLRC
BCLK
R6 NC
CSB
SDIN
SCLK
R8
25
26
27
28
2
INT/CLKOUT
6
R14
47K
MODE
CSB
SDIN
SCLK
VMID
0
1
220PF
20
PHONEJACK STEREO SW
C6
0.1uF
MCLK/XTI
R13
47K
1
2
3
4
5
+
C3
10uF
2
12.288MHz
C7
22pF
C8
22pF
POR/XTO
DVSS
Y1
4
1uF
R10
47K
J6
C27
220PF
AVSS
HPVSS
C11
220PF
R9
47K
220uF
SPI[0..2]
R15
47K
220uF
14
C26
R5 100K
1
C10
9
8
10
11
7
19
15
MIC_IN
RHP_OUT
SSM2602KCPZ
DACLRC
DACDAT
ADCDAT
ADCLRC
BCLK
+3.3V_VAA
R7
680
13
+
22
I2S[0..4]
J7
LHP_OUT
C15
C5
220PF
NC
R
MIC_BIAS
+
21
R4
1
R12
100
C13
1uF
C14
1
2
16
2
R3
0
+
BNC
23
J2
1
Connection under chip
Figure 23. SSM2602 Typical Application Circuit
Rev. PrB | Page 16 of 28
06858-023
NC
L
+
C2
R2
2
U1
DBVDD
1
12
18
C1
DCVDD
R1
0
C19
0.1uF
AVDD
J1
+
HPVDD
C18
10uF
Preliminary Technical Data
SSM2602
REGISTER MAP
Table 10. Register Map
Reg. Address Name
D8
R0 0x00
Left-Channel
LRINBOTH
ADC Input Volume
D7
LINMUTE
D6
0
R1
0x01
Right-Channel
RLINBOTH
ADC Input Volume
RINMUTE
0
R2
0x02
Left-Channel
DAC Volume
LRHPBOTH
LZCEN
LHPVOL [6:0]
001111001
R3
0x03
Right-Channel
DAC Volume
RLHPBOTH
RZCEN
RHPVOL [6:0]
001111001
R4
0x04
MICBOOST2
R5
0x05
Analog
Audio Path
Digital
Audio Path
0
0
0
R6
0x06
0
PWROFF
R7
0x07
0
BCLKINV
R8
0x08
0
CLKODIV2 CLKDIV2
R9
0x09
Power
Management
Digital
Audio I/F
Sampling
Rate
Active
0
0
R15 0x0F
R16 0x10
R17 0x11
R18 0x12
Software
Reset
ALC
Control 1
ALC
Control 2
Noise Gate
D5
D4
D3
D2
LINVOL [5:0]
D0
RINVOL [5:0]
SIDETONE_ATT [1:0]
SIDETONE_EN DACSEL BYPASS
HPOR
DACMU
CLKOUTPD OSCPD
OUTPD
DACPD
MS
LRP
0
D1
0
LRSWAP
0
010010111
INSEL
MUTEMIC MICBOOST 000001010
DEEMPH [1:0]
ADCPD
MICPD
WL [1:0]
SR [3:0]
0
0
0
ADCHPD
000001000
LINEINPD
010011111
FORMAT [1:0]
0
0
MAXGAIN [2:0]
DCY [3:0]
NGTH [4:0]
Rev. PrB | Page 17 of 28
000001010
BOSR
USB
000000000
0
ACTIVE
000000000
RESET [8:0]
ALCSEL [1:0]
Default
010010111
000000000
ALCL [3:0]
001111011
ATK [3:0]
000110010
NGG [1:0]
NGAT
000000000
SSM2602
Preliminary Technical Data
REGISTER MAP DETAILS
LEFT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x00
Table 11. Left-Channel ADC Input Volume Register Bit Map
D8
LRINBOTH
D7
LINMUTE
D6
0
D5
D4
D3
D2
LINVOL [5:0]
D1
Table 12. Descriptions of Left-Channel ADC Input Volume Register Bits
Bit Name
LRINBOTH
Description
Left-channel line input volume update
LINMUTE
Left-channel input mute
LINVOL [5:0]
Left-channel PGA volume control
Settings
0 = store LINVOL in intermediate latch (default)
1 = update left- and right-channel gains
0 = disable mute
1 = enable mute (default)
00 0000 = 34.5 dB
… 1.5 dB step down
01 0111 = 0 dB (default)
… 1.5 dB step down
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 = 33 dB
11 1111 to 10 1101 = 33 dB
Rev. PrB | Page 18 of 28
D0
Preliminary Technical Data
SSM2602
RIGHT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x01
Table 13. Right-Channel Input Volume Register Bit Map
D8
RLINBOTH
D7
RINMUTE
D6
0
D5
D4
D3
D2
RINVOL [5:0]
D1
Table 14. Descriptions of Right Input Volume Register Bits
Bit Name
RLINBOTH
Description
Right-channel line input volume update
RINMUTE
Right-channel input mute
RINVOL [5:0]
Right-channel PGA volume control
Settings
0 = store RINVOL in intermediate latch (default)
1 = update left- and right-channel gains
0 = disable mute
1 = enable mute (default)
00 0000 = 34.5 dB
… 1.5 dB step down
01 0111 = 0 dB (default)
… 1.5 dB step down
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 = 33 dB
11 1111 to 10 1101 = 33 dB
Rev. PrB | Page 19 of 28
D0
SSM2602
Preliminary Technical Data
LEFT-CHANNEL DAC VOLUME, ADDRESS 0x02
Table 15. Left-Channel DAC Volume Register Bit Map
D8
LRHPBOTH
D7
LZCEN
D6
D5
D4
D3
D2
LHPVOL [6:0]
D1
D0
Table 16. Descriptions of Left-Channel DAC Volume Register Bits
Bit Name
LRHPBOTH
Description
Right-channel headphone volume update
LZCEN
Left-channel zero cross detect enable
LHPVOL [6:0]
Left-channel headphone volume control
Settings
0 = store LHPVOL in intermediate latch (default)
1 = update left- and right-channel gains
0 = disable (default)
1 = enable
000 0000 to 010 1111 = mute
011 0000 = −73 dB
…
111 1001 = 0 dB (default)
… 1 dB steps down to
111 1111 = +6 dB
RIGHT-CHANNEL DAC VOLUME, ADDRESS 0x03
Table 17. Right-Channel DAC Volume Register Bit Map
D8
RLHPBOTH
D7
RZCEN
D6
D5
D4
D3
D2
RHPVOL [6:0]
D1
D0
Table 18. Descriptions of Right-Channel DAC Volume Register Bits
Bit Name
RLHPBOTH
Description
Right-channel headphone volume update
RZCEN
Right-channel zero cross detect enable
RHPVOL [6:0]
Right-channel headphone volume control
Rev. PrB | Page 20 of 28
Settings
0 = store RHPVOL in intermediate latch (default)
1 = update left- and right-channel gains
0 = disable (default)
1 = enable
000 0000 to 010 1111 = mute
011 0000 = −73 dB
…
111 1001 = 0 dB (default)
… 1 dB steps down to
111 1111 = +6 dB
Preliminary Technical Data
SSM2602
ANALOG AUDIO PATH, ADDRESS 0x04
Table 19. Analog Audio Path Register Bit Map
D8
MICBOOST2
D7
D6
SIDETONE_ATT [1:0]
D5
SIDETONE_EN
D4
DACSEL
D3
BYPASS
D2
INSEL
D1
MUTEMIC
D0
MICBOOST
Table 20. Descriptions of Analog Audio Path Register Bits
Bit Name
MICBOOST2
Description
Additional microphone amplifier gain booster control
SIDETONE_ATT [1:0]
Microphone sidetone gain control
SIDETONE_EN
DACSEL
DAC select
BYPASS
Line input bypass to line output
INSEL
Microphone/line level boost
MUTEMIC
Microphone mute control
MICBOOST
Primary microphone amplifier gain booster control
Settings
0 = 0 dB (default)
1 = 20 dB
00 = −6 dB (default)
01 = −9 dB
10 = −12 dB
11 = −15 dB
0 = sidetone disable (default)
1 = sidetone enable
0 = do not select DAC (default)
1 = select DAC
0 = bypass disable
1 = bypass enable (default)
0 = microphone input select to ADC (default)
1 = line input select to ADC
0 = mute disable
1 = mute enable (default)
0 = 0 dB (default)
1 = 20 dB
DIGITAL AUDIO PATH CONTROL, ADDRESS 0x05
Table 21. Digital Audio Path Control Register Bit Map
D8
0
D7
0
D6
0
D5
0
D4
HPOR
D3
DACMU
D2
D1
DEEMPH [1:0]
D0
ADCHPD
Table 22. Descriptions of Digital Audio Path Control Register Bits
Bit Name
HPOR
Description
Store dc offset when high-pass filter is disabled
DACMU
DAC digital mute
DEEMPH [1:0]
De-emphasis control
ADCHPD
ADC high-pass filter control
Rev. PrB | Page 21 of 28
Settings
0 = store offset disable (default)
1 = store offset enable
0 = no mute (signal active)
1 = mute (default)
00 = no de-emphasis (default)
01 = 32 kHz sampling rate
10 = 44.1 kHz sampling rate
11 = 48 kHz sampling rate
0 = ADC high-pass filter disable (default)
1 = ADC high-pass filter enable
SSM2602
Preliminary Technical Data
POWER MANAGEMENT, ADDRESS 0x06
Table 23. Power Management Register Bit Map
D8
0
D7
PWROFF
D6
CLKOUTPD
D5
OSCPD
D4
OUTPD
D3
DACPD
D2
ADCPD
D1
MICPD
D0
LINEINPD
Table 24.
Bit Name
PWROFF
Description
Whole chip power-down control
CLKOUTPD
Clock output power-down control
OSCPD
Crystal power-down control
OUTPD
Output power-down control
DACPD
DAC power-down control
ADCPD
ADC power-down control
MICPD
Microphone input power-down control
LINEINPD
Line input power-down control
Settings
0 = power up
1 = power down (default)
0 = power up (default)
1 = power down
0 = power up (default)
1 = power down
0 = power up
1 = power down (default)
0 = power up
1 = power down (default)
0 = power up
1 = power down (default)
0 = power up
1 = power down (default)
0 = power up
1 = power down (default)
POWER CONSUMPTION
Table 25.
Mode
Record and
Playback
Playback Only
Oscillator
Enabled
External Clock
Record Only
Line Clock
Line Oscillator
Microphone 1
Microphone 2
Sidetone
(Microphone to
Headphone
Output)
External Clock
Internally
Generated
Clock
Analog Bypass
(Line Input or
Line Output)
External Line
Internally
Generated
Line
Power-Down
External Clock
Oscillator
PWROFF
0
CLKOUTPD
0
OSCPD
0
OUTPD
0
DACPD
0
ADCPD
0
MICPD
0
LINEINPD
0
AVDD
(3.3 V)
8.36
HPVDD
(3.3 V)
1.7
DCVDD
(1.5 V)
TBD
DBVDD
(1.5 V)
TBD
Unit
mA
0
0
0
0
0
1
1
1
3.1
1.7
TBD
TBD
mA
0
1
1
0
0
1
1
1
3.1
1.7
TBD
TBD
mA
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
3.15
3.15
3.45
3.45
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
2.24
2.24
1.7
1.7
TBD
TBD
TBD
TBD
mA
mA
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1.94
1.94
1.7
1.7
TBD
TBD
TBD
TBD
mA
mA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Rev. PrB | Page 22 of 28
Preliminary Technical Data
SSM2602
DIGITAL AUDIO I/F, ADDRESS 0x07
Table 26. Digital Audio I/F Register Bit Map
D8
0
D7
BCLKINV
D6
MS
D5
LRSWAP
D4
LRP
D3
D2
WL [1:0]
D1
D0
FORMAT [1:0]
Table 27. Descriptions of Digital Audio I/F Register Bits
Bit Name
BCLKINV
Description
BCLK inversion control
MS
Master mode enable
LRSWAP
Swap DAC data control
LRP
Polarity control for clocks in right justified, left justified, and
I2S modes
WL [1:0]
Data-word length control
FORMAT [1:0]
Digital audio input format control
Settings
0 = BCLK not inverted (default)
1 = BCLK inverted
0 = enable slave mode (default)
1 = enable master mode
0 = output left- and right-channel data as normal
(default)
1 = swap left- and right-channel DAC data in audio
interface
0 = normal DACLRC and ADCLRC (default), or DSP
Submode 1
1 = invert DACLRC and ADCLRC polarity, or DSP
Submode 2
00 = 16 bits
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
00 = right justified
01 = left justified
10 = I2S format (default)
11 = DSP mode
SAMPLING RATE, ADDRESS 0x08
Table 28. Sampling Rate Register Bit Map
D8
0
D7
CLKODIV2
D6
CLKDIV2
D5
D4
D3
SR [3:0]
D2
Table 29. Descriptions of Sampling Rate Register Bits
Bit Name
CLKODIV2
Description
CLKOUT divider select
CLKDIV2
Core clock divide select
SR [3:0]
BOSR
Clock setting condition
Base oversampling rate
USB
USB mode select
Settings
0 = CLKOUT is core clock (default)
1 = CLKOUT is core clock divided by 2
0 = core clock is MCLK (default)
1= core clock is MCLK divided by 2
See Table 30 and Table 31.
USB mode:
0 = 250 fS (default)
1 = 272 fS
Normal mode:
0 = 256 fS (default)
1 = 384 fS
0 = USB mode disable (default)
1 = USB mode enable
Rev. PrB | Page 23 of 28
D1
BOSR
D0
USB
SSM2602
Preliminary Technical Data
Table 30. Sampling Rate Lookup Table, USB Disabled
Sampling Rate Register Setting
BOSR
SR3
SR2
SR1
SR0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
1
1
1
0
1
0
1
1
1
1
1
Normal/USB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MCLK (MHz)
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
ADC Sampling Rate (kHz)
48
DAC Sampling Rate (kHz)
48
48
8
8
48
8
8
12
12
16
16
32
32
96
96
44.1
44.1
44.1
8.02
8.02
44.1
8.02
8.02
11
11
22
22
24
24
88.2
88.2
MCLK (MHz)
12
12
12
12
12
12
12
12
12
12
12
12
12
ADC Sampling Rate (kHz)
48
44.1
48
44.1
8
8.02
8
8.02
12
16
11
22
24
DAC Sampling Rate (kHz)
48
44.1
8
8.02
48
44.1
8
8.02
12
16
11
22
24
Table 31. Sampling Rate Lookup Table, USB Enabled
Sampling Rate Register Setting
BOSR
SR3
SR2
SR1
SR0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
1
1
0
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
0
0
0
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
Normal/USB
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. PrB | Page 24 of 28
Preliminary Technical Data
Sampling Rate Register Setting
BOSR
SR3
SR2
SR1
SR0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
SSM2602
Normal/USB
1
1
1
MCLK (MHz)
12
12
12
ADC Sampling Rate (kHz)
32
96
88.2
DAC Sampling Rate (kHz)
32
96
88.2
ACTIVE, ADDRESS 0x09
Table 32. Active Register Bit Map
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
ACTIVE
Table 33. Descriptions of Active Register Bit
Bit Name
ACTIVE
Description
Digital core activation control
Settings
0 = disable digital core (default)
1 = activate digital core
RESET, ADDRESS 0x0F
Table 34. Reset Register Bit Map
D8
D7
D6
D5
D4
D3
D2
D1
D0
D1
ALCL [[3:0]
D0
RESET [8:0]
Table 35. Descriptions of Reset Register Bits
Bit Name
RESET [8:0]
Description
Write to RESET register to set all control registers to default
setting.
Settings
0 = reset (default)
ALC CONTROL 1, ADDRESS 0x10
Table 36. ALC Control 1 Register Bit Map
D8
D7
ALCSEL [1:0]
D6
D5
D4
MAXGAIN [2:0]
D3
D2
Table 37. Descriptions of ALC Control 1 Register Bits
Bit Name
ALCSEL [1:0]
Description
ALC selection
MAXGAIN [2:0]
PGA maximum gain
ALCL [3:0]
ALC target level
Settings
00: ALC disabled (default)
01: ALC enabled, right channel only
10: ALC enabled, left channel only
11: N/A
000: −12 dB
001: −6 dB
… 6 dB steps up to
111: 30 dB (default)
0000: −28.5 dBFS
0001: −27 dBFS
…
1011: −12 dBFS (default)
… 1.5 dB steps up to
1111: −6 dBFS
Rev. PrB | Page 25 of 28
SSM2602
Preliminary Technical Data
ALC CONTROL 2, ADDRESS 0x11
Table 38. ALC Control 2 Register Bit Map
D8
0
D7
D6
D5
DCY [3:0]
D4
D3
D2
D1
ATK [3:0]
D0
Table 39. Descriptions of ALC Control 2 Register Bits
Bit Name
DCY [3:0]
Description
Decay (release) time control
ATK [3:0]
ALC attack time control
Settings
0000: 24 ms
0001: 48 ms
0010: 96 ms
0011: 192 ms (default)
… 24 ms steps up to
1010: 24.576 sec
0000: 6 ms
0001: 12 ms
0010: 24 ms (default)
… 6 ms steps up to
1010: 6.144 sec
NOISE GATE, ADDRESS 0x12
Table 40. Noise Gate Register Bit Map
D8
0
D7
D6
D5
NGTH [4:0]
D4
D3
D2
D1
NGG [1:0]
Table 41. Descriptions of Noise Gate Register Bits
Bit Name
NGTH [4:0]
Description
Noise gate threshold
NGG [1:0]
Noise gate type
NGAT
Noise enable
1
Settings
00000: −76.5 dBFS (default)
00001: −75 dBFS
… 1.5 dB steps up to
11110: −31.5 dBFS
11111: −30 dBFS
X0: hold PGA gain constant (default) 1
01: mute output
11: reserved
0: noise disable (default)
1: noise enable
X = don’t care.
Rev. PrB | Page 26 of 28
D0
NGAT
Preliminary Technical Data
SSM2602
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
22
21
0.50
BSC
TOP
VIEW
1.00
0.85
0.80
PIN 1
INDICATOR
3.45
3.30 SQ
3.15
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.75
0.60
0.50
1
15
14
7
8
0.25 MIN
3.00 REF
0.80 MAX
0.65 TYP
12° MAX
SEATING
PLANE
0.30
0.23
0.18
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-1
122106-A
PIN 1
INDICATOR
28
Figure 24. 28-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-28-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
SSM2602CPZ-R2 1
SSM2602CPZ-REEL1
SSM2602CPZ-REEL71
SSM2602-EVALZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
28-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
28-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
28-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. PrB | Page 27 of 28
Package Option
CP-28-4
CP-28-4
CP-28-4
SSM2602
Preliminary Technical Data
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06858-0-9/07(PrB)
Rev. PrB | Page 28 of 28