MOTOROLA Order this document by MCM62110/D SEMICONDUCTOR TECHNICAL DATA MCM62110 32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker • Single 5 V ± 10% Power Supply • Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility • Fast Access and Cycle Times: 15/17/20 ns Max • Self–Timed Write Cycles • Clock Controlled Output Latches • Address, Chip Enable, and Data Input Registers • Common Data Inputs and Data Outputs • Dual I/O for Separate Processor and Memory Buses • Separate Output Enable Controlled Three–State Outputs • Odd Parity Checker During Reads • Open Drain Output on Data Parity Error (DPE) Allowing Wire–ORing of Outputs • High Output Drive Capability: 85 pF/Output at Rated Access Time • High Board Density 52 Lead PLCC Package • Active High and Low Chip Enables for Easy Memory Depth Expansion • Can be used as Separate I/O x9 FN PACKAGE PLASTIC CASE 778–02 SIE PIE SOE POE W K VCC VSS DPE A6 A4 A2 A0 PIN ASSIGNMENT 7 6 5 4 3 2 1 52 51 50 49 48 47 8 46 9 45 10 44 11 43 12 42 13 41 14 40 15 39 16 38 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33 A8 A7 A5 A3 A1 E2 E1 PDQ7 SDQ7 VSSQ PDQ5 SDQ5 VCCQ PDQ3 SDQ3 VSSQ PDQ1 SDQ1 A14 A13 A12 A11 A10 VSS VCC A9 The MCM62110 is a 294,912 bit synchronous static random access memory organized as 32,768 words of 9 bits, fabricated using Motorola’s high–performance silicon–gate CMOS technology. The device integrates a 32K x 9 SRAM core with advanced peripheral circuitry consisting of address registers, two sets of input data registers, two sets of output latches, active high and active low chip enables, and a parity checker. The RAM checks odd parity during RAM read cycles. The data parity error (DPE) output is an open drain type output which indicates the result of this check. This device has increased output drive capability supported by multiple power pins. In addition, the output levels can be either 3.3 V or 5 V TTL compatible by choice of the appropriate output bus power supply. The device has both asynchronous and synchronous inputs. Asynchronous inputs include the processor output enable (POE), system output enable (SOE), and the clock (K). The address (A0 – A14) and chip enable (E1 and E2) inputs are synchronous and are registered on the falling edge of K. Write enable (W), processor input enable (PIE) and system input enable (SIE) are registered on the rising edge of K. Writes to the RAM are self–timed. All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP have input data registers triggered by the rising edge of the clock. These pins also have three–state output latches which are transparent during the high level of the clock and latched during the low level of the clock. This device has a special feature which allows data to be passed through the RAM between the system and processor ports in either direction. This streaming is accomplished by latching in data from one port and asynchronously output enabling the other port. It is also possible to write to the RAM while streaming. Additional power supply pins have been utilized for maximum performance. The output buffer power (VCCQ) and ground pins (VSSQ) are electrically isolated from VSS and VCC, and supply power and ground only to the output buffers. This allows connecting the output buffers to 3.3 V instead of 5.0 V if desired. If 3.3 V output levels are chosen, the output buffer impedance in the ‘‘high’’ state is approximately equal to the impedance in the ‘‘low’’ state thereby allowing simplified transmission line terminations. The MCM62110 is available in a 52–pin plastic leaded chip carrier (PLCC). This device is ideally suited for pipelined systems and systems with multiple data buses and multiprocessing systems, where a local processor has a bus isolated from a common system bus. PIN NAMES A0 – A14 . . . . . . . . . . . . . . . Address Inputs K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input W . . . . . . . . . . . . . . . . . . . . . . . Write Enable E1 . . . . . . . . . . . . . Active Low Chip Enable E2 . . . . . . . . . . . . . Active High Chip Enable PIE . . . . . . . . . . . . . Processor Input Enable SIE . . . . . . . . . . . . . . . System Input Enable POE . . . . . . . . . . Processor Output Enable SOE . . . . . . . . . . . . . System Output Enable DPE . . . . . . . . . . . . . . . . . . Data Parity Error PDQ0 – PDQ7 . . . . . . . Processor Data I/O PDQP . . . . . . . . . . . Processor Data Parity SDQ0 – SDQ7 . . . . . . . . . System Data I/O SDQP . . . . . . . . . . . . . System Data Parity VCC . . . . . . . . . . . . . . . + 5 V Power Supply VCCQ . . . . . . Output Buffer Power Supply VSSQ . . . . . . . . . . . . Output Buffer Ground VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground All power supply and ground pins must be connected for proper operation of the device. VCC ≥ VCCQ at all times including power up. REV 3 5/95 Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM62110 1 PDQP SDQP VSSQ PDQ6 SDQ6 VCCQ PDQ4 SDQ4 PDQ2 SDQ2 VSSQ PDQ0 SDQ0 BLOCK DIAGRAM DATA REGISTER K PARITY CHECK A0 – A14 9 DATA REGISTER DATA LATCH WRITE DRIVER REGISTER 32K × 9 ARRAY SENSE AMPLIFIER W POE PDQ0 – PDQ7, PDQP CONTROL DPE 9 DATA REGISTER DATA LATCH E1 E2 9 PIE SOE SDQ0 – SDQ7, SDQP SIE FUNCTIONAL TRUTH TABLE (See Notes 1 and 2) W PIE SIE POE SOE Mode Memory Subsystem Cycle PDQ0 – PDQ7, PDQP Output SDQ0 – SDQ7, SDQP Output DPE Notes 1 1 1 0 1 Read Processor Read Data Out High–Z Parity Out 3, 4 1 1 1 1 0 Read Copy Back High–Z Data Out Parity Out 3, 4 1 1 1 0 0 Read Dual Bus Read Data Out Data Out Parity Out 3, 4 1 X X 1 1 Read NOP High–Z High–Z 1 X 0 0 X X N/A NOP High–Z High–Z 1 2, 5 0 0 1 1 1 Write Processor Write Hit Data In High–Z 1 2, 6 0 1 0 1 1 Write Allocate High–Z Data In 1 2 0 0 1 1 0 Write Write Through Data In Stream Data 1 2, 7 0 1 0 0 1 Write Allocate With Stream Stream Data Data In 1 2, 7 1 0 1 1 0 N/A Cache Inhibit Write Data In Stream Data 1 2, 7 1 1 0 0 1 N/A Cache Inhibit Read Stream Data Data In 1 2, 7 0 1 1 X X N/A NOP High–Z High–Z 1 5 X 0 1 0 0 N/A Invalid Data In Stream 1 2, 8 X 0 1 0 1 N/A Invalid Data In High–Z 1 2, 8 X 1 0 0 0 N/A Invalid Stream Data In 1 2, 8 X 1 0 1 0 N/A Invalid High–Z Data In 1 2, 8 NOTES: 1. A ‘0’ represents an input voltage ≤ VIL and a ‘1’ represents an input voltage ≥ VIH. All inputs must satisfy the specified setup and hold times for the falling or rising edge of K. Some entries in this truth table represent latched values. This table assumes that the chip is selected (i.e., E1 = 0 and E2 = 1) and VCC current is equal to ICCA. If this is not true, the chip will be in standby mode, the VCC current will equal ISB1 or ISB2 DPE will default to 1 and all RAM outputs will be in High–Z. Other possible combinations of control inputs not covered by this note or the table above are not supported and the RAM’s behavior is not specified. 2. If either IE signal is sampled low on the rising edge of clock, the corresponding OE is a don’t care, and the corresponding outputs are High–Z. 3. A read cycle is defined as a cycle where data is driven on the internal data bus by the RAM. 4. DPE is registered on the rising edge of K at the beginning of the following clock cycle 5. No RAM cycle is performed. 6. A write cycle is defined as a cycle where data is driven onto the internal data bus through one of the data I/O ports (PDQ0 – PDQ7 and PDQP or SDQ0 – SDQ7 and SPDQ), and written into the RAM. 7. Data is driven on the internal data bus by one I/O port through its data input register and latched into the data output latch of the other I/O port. 8. Data contention will occur. MCM62110 2 MOTOROLA FAST SRAM PARITY CHECKER Parity Scheme DPE E1 = VIH and/or E2 = VIL RAMP = RAM0 ⊕ RAM1 ⊕ . . . ⊕ RAM7 1 1 0 RAMP ≠ RAM0 ⊕ RAM1 ⊕ . . . ⊕ RAM7 NOTE: RAMP, RAM0, RAM1 . . . , refer to the data that is present on the RAMs internal bus, not necessarily data that resides in the RAM array. DPE is always delayed one clock, and is registered on the rising edge of K at the beginning of the following clock cycle (see AC CHARACTERISTICS). ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = VSSQ = 0 V) Rating Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 20 mA Power Dissipation PD 1.2 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to +70 °C Power Supply Voltage Relative to VSS/VSSQ for Any Pin Except VCC and VCCQ Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Storage Temperature MOTOROLA FAST SRAM This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. MCM62110 3 DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = VSSQ = 0 V) Parameter Symbol Min Max Unit VCC 4.5 5.5 V VCCQ 4.5 3.0 5.5 3.6 V Input High Voltage VIH 2.2 VCC + 0.3 V Input Low Voltage VIL – 0.5* 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ± 1.0 µA Output Leakage Current (POE, SOE = VIH) Ilkg(O) — ± 1.0 µA — — — 190 190 190 Supply Voltage (Operating Voltage Range) Output Buffer Supply Voltage (5.0 V TTL Compatible) (3.3 V 50 Ω Compatible) * VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter AC Supply Current (All Inputs = VIL or VIH,VIL = 0.0 V and VIH ≥ 3.0 V, Iout = 0 mA, Cycle Time ≥ tKHKH min) MCM62110–15: tKHKH = 15 ns MCM62110–17: tKHKH = 17 ns MCM62110–20: tKHKH = 20 ns ICCA TTL Standby Current (VCC = Max, E1 = VIH or E2 = VIL) ISB1 — 40 mA CMOS Standby Current (VCC = Max, f = 0 MHz, E1 = VIH or E2 = VIL, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V) ISB2 — 30 mA Output Low Voltage (IOL = + 8.0 mA, DPE: IOL = + 23.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Symbol Typ Max Unit Cin 2 3 pF Cout 6 7 pF Cout(DPE) 6 7 pF mA CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance (All Pins Except I/Os) Input/Output Capacitance (PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, SDQP) Data Parity Error Output Capacitance (DPE) AC SPEC LOADS +5V RL = 50 Ω DQ 480 Ω DQ 255 Ω Z0 = 50 Ω +5V 200 Ω DPE 5 pF 50 pF VL = 1.5 V Figure 1A MCM62110 4 Figure 1B Figure 1C MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted READ CYCLE (See Note 1) MCM62110–15 Parameter MCM62110–17 MCM62110–20 Symbol Min Max Min Max Min Max Unit Notes Read Cycle Time Clock High to Clock High tKHKH 15 — 17 — 20 — ns 1, 2 Clock Low Pulse Width tKLKH 5 — 5 — 5 — ns Clock High Pulse Width tKHKL 7 — 7 — 7 — ns Clock High to DPE Valid tKHDPEV — 7 — 8 — 10 ns 5 Clock High to Output Valid tKHQV — 7 — 7.5 — 10 ns 4, 3 Clock (K) High to Output Low Z After Write tKHQX1 8 — 8 — 8 — ns Output Hold from Clock High tKHQX2 5 — 5 — 5 — ns 4, 6 tKHQZ — 8 — 9 — 10 ns 6 A W E1, E2 PIE SIE POE SOE tAVKL tWHKH tEVKL tPIEHKH tSIEHKH tPOEVKH tSOEVKH 2.5 — 2.5 — 2.5 — ns A W E1, E2 PIE SIE POE SOE tKLAX tKHWX tKLEX tKHPIEX tKHSIEX tKHPOEX tKHSOEX 2 Output Enable High to Q High–Z tPOEHQZ tSOEHQZ 0 8 0 9 0 9 ns 6 Output Hold from Output Enable High tPOEHQX tSOEHQX 5 — 5 — 5 — ns 6 Output Enable Low to Q Active tPOELQX tSOELQX 0 — 0 — 0 — ns 6 Output Enable Low to Output Valid tPOELQV tSOELQV — 5 — 6 — 8 ns Clock High to Q High–Z (E1 or E2 = False) Setup TImes: Hold Times: 7 7 — 2 — 2 — ns 7 7 NOTES: 1. A read is defined by W high for the setup and hold times. 2. All read cycle timing is referenced from K, SOE, or POE. 3. Access time is controlled by tKLQV if the clock low pulse width is less than (tKLQV–tKHQV); otherwise it is controlled by KHQV. 4. K must be at a high level for outputs to transition. 5. DPE is valid exactly one clock cycle after the output data is valid. 6. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ is less than tKHQX, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less than tSOELQX for a given device. 7. These read cycle timings are used to guarantee proper parity operation only. MOTOROLA FAST SRAM MCM62110 5 READ CYCLE (See Notes) tKLKH tKHKH tKHKL K tKLAX tAVKL An A0 – A14 An + 1 An + 2 E1 tKLEX tEVKL E2 tKHPIEX tPIEHKH PIE tKHSIEX tSIEHKH SIE tKHWX tWHKH W tPOEVKH tKHPOEX POE tPOELQV tPOELQX tPOEHQZ tPOEHQX SOE tSOELQV Qn PDQ0 – PDQ7, PDQP tKHQZ tKHQV Qn SDQ0 – SDQ7, SDQP tKHQX2 tKHDPEV DPE tKHQX1 DPE – 2 DPEn – 1 DPEn NOTES: 1. DPE is valid exactly one clock cycle after the output data is valid. MCM62110 6 MOTOROLA FAST SRAM WRITE CYCLE (See Note 1) MCM62110–15 Parameter MCM62110–17 MCM62110–20 Symbol Min Max Min Max Min Max Unit Notes Write Cycle Times tKHKH 15 — 17 — 20 — ns 1, 2 Clock Low Pulse Width tKLKH 5 — 5 — 5 — ns Clock High Pulse Width tKHKL 7 — 7 — 7 — ns Clock High to Output High–Z (W = VIL and SIE = PIE = VIH) tKHQZ — 8 — 9 — 10 ns Setup Times: tAVKL tWLKH tEVKL tPIEVKH tSIEVKH tDVKH 2.5 — 2.5 — 2.5 — ns Hold Times: tKLAX tKHWX tKLEX tKHPIEX tKHSIEX tKHDX 2 — 2 — 2 — ns tKHQV — 7 — 7.5 — 8 ns 5 Output Enable High to Q High–Z tPOEHQZ tSOEHQZ 0 8 0 9 0 9 ns 6 Output Hold from Output Enable High tPOEHQX tSOEHQX 5 — 5 — 5 — ns Output Enable Low to Q Active tPOELQX tSOELQX 0 — 0 — 0 — ns Output Enable Low to Output Valid tPOELQV tSOELQV — 5 — 6 — 8 ns A W E1, E2 PIE SIE SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP A W E1, E2 PIE SIE SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP Write with Streaming (PIE = SOE = VIL or SIE = POE = VIL) Clock High to Output Valid 3, 4 6 NOTES: 1. A write is performed with W = VIL, E1 = VIL, E2 = VIH for the specified setup and hold times and either PIE = VIL or SIE = VIL. If both PIE = VIL and SIE = VIL or PIE = VIH and SIE = VIH, then this is treated like a NOP and no write is performed. 2. All write cycle timings are referenced from K. 3. K must be at a high level for the outputs to transition. 4. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ is less than tKHQX for a given device. 5. A write with streaming is defined as a write cycle which writes data from one data bus to the array and outputs the same data onto the other data bus. 6. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ is less than tKHQX, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less than tSOELQX for a given device. MOTOROLA FAST SRAM MCM62110 7 WRITE THROUGH — READ — WRITE (See Note) tKHKH tKLKH tKHKL K tKLAX tAVKL An A0 – A14 An + 1 An + 2 E1 tKLEX tEVKL E2 tKHPIEX tPIEVKH tPIEHKH tKHPIEX tSIEVKH tSIEHKH tKHSIEX tWLKH tWHKH tKHWX PIE tKHSIEX SIE tKHWX W POE tPOEHQZ SOE tPOEHQX tSOEHQZ tPOELQV tSOEHQX tDVKH tKHDX tSOELQV PDQ0 – PDQ7, PDQP Dn Qn – 1 Qn – 1 tPOEHQZ tDVKH Qn +1 Dn + 2 tPOELQX tKHQV SDQ0 – SDQ7, SDQP tKHDX Qn (STREAMED) tKHDPEV DPE DPEn – 2 DPEn – 1 NOTE: DPE is valid exactly one clock cycle after the output data is written. MCM62110 8 MOTOROLA FAST SRAM STREAM CYCLE (See Note 1) MCM62110–15 Parameter MCM62110–17 MCM62110–20 Symbol Min Max Min Max Min Max Unit Notes Stream Cycle Time tKHKH 15 — 17 — 20 — ns 1, 2 Clock Low Pulse Width tKLKH 5 — 5 — 5 — ns Clock High Pulse Width tKHKL 7 — 7 — 7 — ns Stream Access Time tKHQV — 7 — 7.5 — 8 ns Setup Times: tAVKL tWHKH tEVKL tPIEVKH tSIEVKH tDVKH 2.5 — 2.5 — 2.5 — ns Hold Times: tKLAX tKHWX tKLEX tKHPIEX tKHSIEX tKHDX 2 — 2 — 2 — ns Output Enable High to Q High–Z tPOEHQZ tSOEHQZ 0 8 0 9 0 9 ns 3 Output Enable Low to Q Active tPOELQX tSOELQX 0 — 0 — 0 — ns 3 Output Enable Low to Output Valid tPOELQV tSOELQV — 5 — 6 — 8 ns A W E1, E2 PIE SIE SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP A W E1, E2 PIE SIE SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP NOTES: 1. A stream cycle is defined as a cycle where data is passed from one data bus to the other data bus. 2. All stream cycle timing is referenced from K. 3. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tPOEHQZ is less than tPOELQX, tSOEHQZ is less than tSOELQX, and tKHQZ is less than tKHQX for a given device. MOTOROLA FAST SRAM MCM62110 9 STREAM CYCLE (See Note) tKHKH tKLKH tKHKL K tKLAX tAVKL An A0 – A14 An + 1 An + 2 E1 tKLEX tEVKL E2 tKHPIEX tPIEVKH PIE tKHSIEX tSIEVKH SIE tKHWX tWHKH W POE tPOEHQZ SOE tSOEHQZ tDVKH PDQ0 – PDQ7, PDQP tKHQV tKHDX Qn – 1 Dn Qn + 1 (STREAMED) tKHQV SDQ0 – SDQ7, SDQP Qn (STREAMED) Qn – 1 Dn + 1 tKHDPEV DPEn – 2 DPE DPEn – 1 NOTE: DPE is valid exactly one clock cycle after the output data is valid. ORDERING INFORMATION (Order by Full Part Number) MCM 62110 FN XX Motorola Memory Prefix Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns) Part Number Package (FN = PLCC) Full Part Numbers — MCM62110FN15 MCM62110 10 MCM62110FN17 MCM62110FN20 MOTOROLA FAST SRAM PACKAGE DIMENSIONS FN PACKAGE 52–LEAD PLCC CASE 778–02 B Y BRK -N- 0.007 (0.180) M T L –M 0.007 (0.180) U M S N T L –M S N S 0.010 (0.250) S S D -L- -M- 52 LEADS ACTUAL (NOTE 1) 52 Z W D 1 G1 X VIEW D-D V A 0.007 (0.180) M T L –M S N S R 0.007 (0.180) M T L –M S N S T L –M N S S Z C H 0.004 (0.100) G J -T- F S N S 0.007 (0.180) M T L –M S N S VIEW S G1 0.010 (0.250) T L –M K SEATING PLANE VIEW S S M K1 E (NOTE 1) 52 0.007 (0.180) T L –M S N S NOTES: 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS. 2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 8. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 — 0.020 — 0.025 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 0.020 — 10° 2° 0.710 0.730 0.040 — MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 19.05 19.20 19.05 19.20 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 18.04 18.54 1.02 — Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA FAST SRAM MCM62110 11 Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM62110 12 ◊ CODELINE TO BE PLACED HERE *MCM62110/D* MCM62110/D MOTOROLA FAST SRAM