MOTOROLA Order this document by MCM69Q618/D SEMICONDUCTOR TECHNICAL DATA MCM69Q618 Advance Information 64K x 18 Bit Synchronous Separate I/O Fast SRAM The Motorola MCM69Q618 is a 1 Megabit static random access memory, organized as 64K words of 18 bits. It features separate data input and data output buffers and incorporates input and output registers on board with high speed SRAM. The MCM69Q618 allows the user to perform transparent write and data pass through. Two data bus ports are provided – a data input (D) and a data output (Q) port. The synchronous design allows for precise cycle control with the use of an external single clock (K). Address port, data input (D0 – D17), data output (Q0 – Q17), write enable (W), chip enables (E1, E2), and pass–through enable (PT) are registered on the rising edge of clock (K). Any given cycle operates on only one address. However, for any cycle, reads and writes can be intermixed. Thus, one can perform a read, a write, or a combination read/ write during any one cycle. For a combination read/write, the contents of the array are read before the new data is written. By using the pass–through function, the output port Q can be made to reflect either the contents of the array or the data presented to the input port D. For read/write or a read cycle with G low, the Q port will output the contents of the array. However, if PT is asserted, the Q port will instead output the data presented at the D input port. • • • • • • • • • • • • • • TQ PACKAGE 100 PIN TQFP CASE 983A–01 Single 3.3 V ± 5% Power Supply Fast Access Times: 6/8/10 ns Max Sustained Throughput of 1.49 Gigabits/Second Single Clock Operation Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip 83 MHz Maximum Clock Cycle Time Self Timed Write Separate Data Input and Data Output Pins Pass–Through Feature Asynchronous Output Enable (G) LVTTL Compatible I/O No Dead Cycles Required for Reads after Writes or for Writes after Reads 100 Pin TQFP Package Simultaneous Reads and Writes Suggested Applications — ATM — Ethernet Switches — Cell/Frame Buffers — SNA Switches — Routers — Shared Memory Product Family Configurations Part Number Dual Address MCM69D536 MCM69D618 MCM69Q536 MCM69Q618 MCM67Q709 MCM67Q909 n n Single Address Note 1 Note 1 n n n n Dual I/O n n Separate I/O Note 2 Note 2 n n n n NOTES: 1. Tie AX and AY address ports together for the part to function as a single address part. 2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs. This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 5 11/24/97 Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM69Q618 1 BLOCK DIAGRAM K A0 – A15 16 ADDRESS REGISTER W WRITE REGISTER PT PT REGISTER 64K x 18 ARRAY WRITE DRIVER PASS–THROUGH DATA INPUT REGISTER E1 E2 G MCM69Q618 2 ENABLE REGISTER 1 SENSE AMP DATA OUTPUT REGISTER ENABLE REGISTER 2 D0 – D17 Q0 – Q17 MOTOROLA FAST SRAM A6 NC A7 NC K VDD VSS NC G E2 E1 NC W NC PT A8 NC A9 NC A15 PIN ASSIGNMENT 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC VSS VDD D8 Q8 D7 Q7 VSS VDD D6 Q6 D5 Q5 VSS VDD Q4 D4 Q3 D3 VSS VDD Q2 D2 Q1 D1 VSS VDD Q0 D0 NC NC A4 NC A3 NC A2 NC A1 NC A0 VDD A10 NC A11 NC A12 NC A13 NC A14 VDD VSS D9 Q9 D10 Q10 VDD VSS D11 Q11 D12 Q12 VDD VSS Q13 D13 Q14 D14 VDD VSS Q15 D15 Q16 D16 VDD VSS Q17 D17 NC A5 MOTOROLA FAST SRAM MCM69Q618 3 PIN DESCRIPTIONS Pin Locations Symbol Type 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 81, 83, 85, 98, 100 A0 – A15 Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Description 3, 5, 9, 11, 16, 18, 22, 24, 28, 52, 56, 58, 62, 64, 69, 71, 75, 77 D0 – D17 Input Synchronous Data Input. 90 E1 Input Synchronous Chip Enable: Active low for depth expansion. 91 E2 Input Synchronous Chip Enable: Active high for depth expansion. 92 G Input Asynchronous Output Enable Input: Low — enables output buffers (Qx pins). High — Qx pins are high impedance. 96 K Input Clock: This signal registers the address, data in, and all control signals except G. 86 PT Input Pass–through enable: Synchronous. 4, 6, 10, 12, 15, 17, 21, 23, 27, 53, 57, 59, 63, 65, 68, 70, 74, 76 Q0 – Q17 Output 88 W Input 1, 7, 13, 19, 25, 41, 54, 60, 66, 72, 78, 95 VDD Supply + 3.3 V Power Supply. 2, 8, 14, 20, 26, 55, 61, 67, 73, 79, 94 VSS Supply Ground. 29, 31, 33, 35, 37, 39, 43, 45, 47, 49, 51, 80, 82, 84, 87, 89, 93, 97, 99 NC — Synchronous Data Output. Synchronous Write. No Connection: There is no connection to the chip. TRUTH TABLE Input at tn Clock O Operation i E1 E2 W Write and Pass–Through L H Write/Read L H Pass–Through L Read Result from tn + 1 Clock Notes PT Data Input D Data Output Q L L D written to A D data appears 1 L H D written to A Q out from A 2 H H L D data D data appears 3 L H H H Don’t Care Q out from A 4 Deselected X L X X Don’t Care Q is high–Z 5 Deselected H X X X Don’t Care Q is high–Z 6 NOTES: 1. Write D to array and output D at Q. 2. Output contents of array to Q then write D to array. 3. Output D at Q. Do not write. 4. Output contents of array to Q. Do not write. 5. No operation. 6. No operation. tn tn + 1 K ADDRESS & CONTROL VALID PIPELINED READ ACCESS DATA INPUT D VALID PASS–THROUGH DATA OUTPUT Q MCM69Q618 4 VALID MOTOROLA FAST SRAM ABSOLUTE MAXIMUM RATINGS (See Note) Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VDD Output Current Power Dissipation Symbol Value Unit VDD – 0.5 to + 4.6 V Vin, Vout – 0.5 to VDD + 0.5 V Iout ± 20 mA PD TBD W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Tstg – 55 to + 125 °C Storage Temperature — Plastic This is a synchronous device. All synchronous inputs must meet specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. PACKAGE THERMAL CHARACTERISTICS (See Note 1) Symbol TQFP Unit Notes RθJA 40 25 °C/W 2 Junction to Board (Bottom) RθJB 17 °C/W 3 Junction to Case (Top) RθJC 9 °C/W 4 Rating Junction to Ambient (@ 200 lfm) Single Layer Board Four Layer Board NOTES: 1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38–87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MOTOROLA FAST SRAM MCM69Q618 5 DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VDD 3.135 3.465 V Input High Voltage VIH 2.0 VDD + 0.5** V Input Low Voltage VIL – 0.5* 0.8 V Input Leakage Current (All Inputs, Vin = 0 to VDD) Ilkg(I) — ± 1.0 µA Output Leakage Current (E = VIH, Vout = 0 to VDD) Ilkg(O) — ± 1.0 µA AC Supply Current (Iout = 0 mA) (VDD = max, f = fmax) MCM69Q618–6 ns MCM69Q618–8 ns MCM69Q618–10 ns IDDA — — — TBD TBD TBD mA CMOS Standby Supply Current (Deselected, Clock (K) Cycle Time ≥ tKHKH, All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) MCM69Q618–6 ns MCM69Q618–8 ns MCM69Q618–10 ns ISB1 — — — TBD TBD TBD mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 VDD V Symbol Max Unit Cin 6 pF Cin 6 pF Cout 8 pF * VIL ≥ –1.5 V for t ≤ tKHKH/2. ** VIH ≤ VDD + 1.0 V for t ≤ tKHKH/2. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Parameter Address and Data Input Capacitance Control Pin Input Capacitance Output Capacitance MCM69Q618 6 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted READ/WRITE CYCLE TIMING MCM69Q618–6 MCM69Q618–8 MCM69Q618–10 S b l Symbol Min Max Min Max Min Max U i Unit N Notes Cycle Time tKHKH 12 — 15 — 20 — ns 1 Clock Access Time tKHQV — 6 — 8 — 10 ns 2 Clock Low Pulse Width tKLKH 4 — 6 — 8 — ns Clock High Pulse Width tKHKL 4 — 6 — 8 — ns Clock High to Data Output Invalid tKHQX 0 — 0 — 0 — ns Clock High to Data Output High–Z tKHQZ — 5 — 6 — 7 ns Output Enable to Output Valid tGLQV — 6 — 8 — 10 ns Output Enable to Output Active tGLQX 0 — 0 — 0 — ns 3 Output Disable to Output High–Z tGHQZ — 5 — 6 — 7 ns 3 Setup Times: A0 – A15 W PT E1, E2 D0 – D17 tAVKH tWVKH tPTVKH tEVKH tDVKH 2.5 — 3 — 3 — ns 4 Hold Times: A0 – A15 W PT E1, E2 D0 – D17 tKHAX tKHWX tKHPTX tKHEX tKHDX 0.5 — 2 — 2 — ns 4 P Parameter 3 NOTES: 1. All read and write cycles are referenced from K. 2. Valid data from Clock High will be the data stored at the address or the last valid read cycle. 3. This parameter is sampled and not 100% tested. 4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected. RL = 50 Ω OUTPUT Z0 = 50 Ω VL = 1.5 V Figure 1. AC Test Load MOTOROLA FAST SRAM MCM69Q618 7 READ CYCLE TIMING tKHKH tKLKH tKHKL K tAVKH A0 – A15 A B C D E F G H tKHEX tEVKH E G tGLQV tKHQV tKHQZ tKHQX tGLQX Q Q(A) Q(B) Q(C) Q(E) tGHQZ Q(F) E low = E1 low, E2 high. E high = E1 high or E2 low. MCM69Q618 8 MOTOROLA FAST SRAM COMBINATION READ/WRITE CYCLE TIMING tKHKH tKLKH tKHKL K tKHAX A0 – A15 A B C D E Q[A] Q[B] Q[C] F G H Q(D) Q(E) D(F) E G Q tWVKH tKHWX W tPTVKH tKHAX PT tDVKH D D(B) tKHDX D(D) D(E) D(F) D(G) NOTES: 1. E low = E1 low and E2 high. E high = E1 high or E2 low. 2. Q[A] = Previous contents of array at address A. 3. Q(A) = Data presented at input port. MOTOROLA FAST SRAM MCM69Q618 9 E CONTROLLED WRITE K A0 – A15 A B D(A) D(B) C D E F G H D(C) D(D) D(E) D(F) D(G) D(H) W E D NOTES: 1. E low = E1 low, E2 high. E high = E1 high or E2 low. 2. Only D(B) and D(D) are written to the array. ORDERING INFORMATION (Order by Full Part Number) MCM 69Q618 XX Motorola Memory Prefix Part Number XX X Shipping Method (R = Tape and Reel, Blank = Rails) Speed (6 = 6 ns, 8 = 8 ns, 10 = 10 ns) Package (TQ = TQFP) Full Part Numbers — MCM69Q618TQ6 MCM69Q618TQ8 MCM69Q618TQ10 MCM69Q618TQ6R MCM69Q618TQ8R MCM69Q618TQ10R MCM69Q618 10 MOTOROLA FAST SRAM PACKAGE DIMENSIONS TQFP PACKAGE 100 PIN CASE 983A–01 4X e 0.20 (0.008) H A–B D 2X 30 TIPS e/2 0.20 (0.008) C A–B D –D– 80 51 50 81 B E/2 –A– –X– B X=A, B, OR D –B– VIEW Y E1 E E1/2 BASE METAL PLATING ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ b1 31 100 1 30 D1/2 c D/2 b D1 D 0.13 (0.005) 2X 20 TIPS A q 2 0.10 (0.004) C –H– –C– SEATING PLANE q 3 VIEW AB S S q 1 0.25 (0.010) R2 A2 A1 R1 L2 L L1 VIEW AB C A–B S D S GAGE PLANE q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2 q 1 2 q3 q q MOTOROLA FAST SRAM M SECTION B–B 0.20 (0.008) C A–B D 0.05 (0.002) c1 MILLIMETERS MIN MAX ––– 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 ––– 0.08 ––– 0.08 0.20 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ INCHES MIN MAX ––– 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 ––– 0.003 ––– 0.003 0.008 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ MCM69Q618 11 Motorola reserves the right to make changes without further notice to any products herein. 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