MITSUBISHI LSIs MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD 8-BIT / 524,288-WORD BY16-BIT) 8,388,608-BIT (1048,576-WORD BYBY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY DESCRIPTION The MITSUBISHI M5M29FB/T800FP, VP, RV are 3.3V-only high speed 8,388,608-bit CMOS boot block Flash Memories suitable for mobile and personal computing, and communication products. The M5M29FB/T800FP, VP, RV are fabricated by CMOS technology for the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 44pin SOP or 48pin TSOP(I). FEATURES ................................. 524,288 word x 16bit ................................. 1,048,576 word x 8 bit ............................. VCC = 3.3V±0.3V Supply voltage ................................ .............................. 80/100/120ns (Max) Access time Organization Boot Block ........................... Bottom Boot M5M29FB800 ........................... Top Boot M5M29FT800 Other Functions Software Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Sleep Package 48-Lead, 12mmx 20mm TSOP (type-I) 44-Lead SOP NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 /CE ADDRESS INPUTS CHIP ENABLE INPUT OUTPUT ENABLE INPUT DATA INPUTS/ OUTPUTS 44 /RP ENABLE /WE WRITE INPUT A8 A9 A10 A11 ADDRESS A12 INPUTS A13 A14 A15 A16 ENABLE /BYTE BYTE INPUT 2 43 3 42 4 41 5 40 6 39 7 8 9 10 11 12 GND /OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 RESET/ POWER DOWN INPUT 1 M5M29FB/T800FP Power Dissipation ....................... 108 mW (Max.) Read ....................... 144 mW (Max.) Program/Erase ....................... 0.72 mW (Max.) Standby Deep power down mode ....................... 3.3µW (typ.) Auto program ....................... 7.5ms (typ.) Program Time ................................. 128word Program Unit Auto Erase ................................. 50 ms (typ.) Erase time Erase Unit Boot Block ................................. 8Kword / 16Kbyte x 1 ........................ 4Kword / 8Kbyte x 2 Parameter Block ....................... 16Kword / 32Kbyte x 1 Main Block ........................... 32Kword / 64Kbyte x 15 Program/Erase cycles ....................................... 100Kcycles PIN CONFIGURATION (TOP VIEW) 38 37 36 35 34 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DATA INPUTS/ OUTPUTS Outline 600mil 44-pin SOP (FP: 44P2A-A) APPLICATION Code Storage PC BIOS Digital Cellular Phone/Telecommunication A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE /RP NC /WP RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 M5M29FB/T800VP 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 Outline 48pin TSOP type-I (12 X 20mm) VP(Normal bend): 48P3R-B A16 /BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 /OE GND /CE A0 A16 /BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 /OE GND /CE A0 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 12 38 M5M29FB/T800RV 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE /RP NC /WP RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 RV(Reverse bend): 48P3R-C NC : NO CONNECTION This product is compatible with HN29WB/T800 by Hitachi Ltd. 1 May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY BLOCK DIAGRAM ADDRESS INPUTS A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128 WORD PAGE BUFFER Boot Block 8KW Parameter Block1 4KW Parameter Block2 Main Block 4KW 16KW Main Block 32KW Main Block 32KW VCC (3.3V) GND (0V) X-DECODER Y-DECODER Y-GATE / SENSE AMP. STATUS / ID REGISTER CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT WRITE PROTECT INPUT RESET/POWER DOWN INPUT BYTE ENABLE INPUT READY/BUSY OUTPUT /CE /OE /WE /WP /RP /BYTE MULTIPLEXER CUI WSM INPUT/OUTPUT BUFFERS RY/BY D15/A-1D14D13 D12 D3 D2 D1 D0 DATA INPUTS/OUTPUTS FUNCTION The M5M29FB/T800FP,VP,RV includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the /RP pin is at GND, minimizing power consumption. Read The M5M29FB/T800FP,VP,RV has three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the M5M29FB/T800 automatically resets to read array mode. In the read array mode, low level input to /CE and /OE, high level input to /WE and /RP, and address signals to the address inputs (A0-A18) output the data of the addressed location to the data input/output(D0-15). Write Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing /WE to low level, while /CE is at low level and /OE is at high level. Address and data are latched on the earlier rising edge of /WE and /CE. Standard micro-processor write timings are used. 2 Output Disable When /OE is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. Standby When /CE is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance(High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. Deep Power-Down When /RP is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance(High-Z) state. After return from powerdown, the CUI is reset to Read Array , and the Status Register is cleared to value 80H. During block erase or program modes, /RP low will abort either operation. Memory array data of the block being altered become invalid. May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY SOFTWARE COMMAND DEFINITIONS The device operations are selected by writing specific software command into the Command User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device powerup and after exit from deep powerdown, or by writing FFH to the Command User Interface. The device remains in Read Array mode until the other commands are written. Read Device Identifier Command (90H) Though PROM programmers can normally read device identifier codes by raising A9 to V ID, multiplexing high voltage onto address lines is not desired for micro-processor system. It is an other means to read device identifier codes that Read Device Identifier Code Command(90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from address 0000H and 0001H, respectively. DATA PROTECTION The M5M29FB/T800 provides selectable block locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the M5M29FB/T800 has a master Write Protect pin (WP) which prevents any modifications to memory blocks whose lock-bits are set to "0", when /WP is low. When /WP is high or /RP is VHH, all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. Power Supply Voltage When the power supply voltage (Vcc) is less than 2.2V, the device is set to the Read-only mode. A delay time of 2 us is required before any device operation is initiated. The delay time is measured from the time Vcc reaches Vccmin (3.0V). During power up, /RP=GND is recommended. Falling in Busy status is not recommended for possibility of damaging the device. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. The contents of Status Register are latched on the later falling edge of /OE or /CE. So /CE or /OE must be toggled every status read. Clear Status Register Command (50H) The Erase Status and Program Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Page Program Commands(41H) Page Program allows fast programming of 128words of data. Writing of 41H initiates the page program operation. From 2nd cycle to 129th cycle write data must be serially inputted. Address A6-0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation. Basically re-program must not be done on a page which has already programmed. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes. 3 May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY x8 ( Bytemode) x16 ( Wordmode) x8 ( Bytemode) x16 ( Wordmode) 32Kword MAIN BLOCK FC000H-FFFFFH 7E000H-7FFFFH 8Kword BOOT BLOCK E0000H-EFFFFH 70000H-77FFFH 32Kword MAIN BLOCK FA000H-FBFFFH 7D000H-7DFFFH 4Kword PARAMETER BLOCK D0000H-DFFFFH 68000H-6FFFFH 32Kword MAIN BLOCK F8000H-F9FFFH 7C000H-7CFFFH 4Kword PARAMETER BLOCK 32Kword MAIN BLOCK F0000H-F7FFFH 78000H-7BFFFH 16Kword MAIN BLOCK E0000H-EFFFFH 70000H-77FFFH 32Kword MAIN BLOCK D0000H-DFFFFH 68000H-6FFFFH 32Kword MAIN BLOCK C0000H-CFFFFH 60000H-67FFFH 32Kword MAIN BLOCK B0000H-BFFFFH 58000H-5FFFFH 32Kword MAIN BLOCK A0000H-AFFFFH 50000H-57FFFH 32Kword MAIN BLOCK 90000H-9FFFFH 48000H-4FFFFH 32Kword MAIN BLOCK 80000H-8FFFFH 40000H-47FFFH 32Kword MAIN BLOCK 70000H-7FFFFH 38000H-3FFFFH 32Kword MAIN BLOCK 60000H-6FFFFH 30000H-37FFFH 32Kword MAIN BLOCK 50000H-5FFFFH 28000H-2FFFFH 32Kword MAIN BLOCK 40000H-4FFFFH 20000H-27FFFH 32Kword MAIN BLOCK 30000H-3FFFFH 18000H-1FFFFH 32Kword MAIN BLOCK 20000H-2FFFFH 10000H-17FFFH 32Kword MAIN BLOCK 10000H-1FFFFH 08000H-0FFFFH 32Kword MAIN BLOCK 00000H-0FFFFH 00000H-07FFFH 32Kword MAIN BLOCK F0000H-FFFFFH 78000H-7FFFFH C0000H-CFFFFH 60000H-67FFFH B0000H-BFFFFH 58000H-5FFFFH A0000H-AFFFFH 50000H-57FFFH 90000H-9FFFFH 48000H-4FFFFH 80000H-8FFFFH 40000H-47FFFH 70000H-7FFFFH 38000H-3FFFFH 60000H-6FFFFH 30000H-37FFFH 50000H-5FFFFH 28000H-2FFFFH 40000H-4FFFFH 20000H-27FFFH 30000H-3FFFFH 18000H-1FFFFH 20000H-2FFFFH 10000H-17FFFH 10000H-1FFFFH 08000H-0FFFFH 08000H-0FFFFH 04000H-07FFFH 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 32Kword MAIN BLOCK 16Kword MAIN BLOCK 04000H-05FFFH 02000H-02FFFH 4Kword PARAMETER BLOCK 4Kword PARAMETER BLOCK 00000H-03FFFH 00000H-01FFFH 8Kword BOOT BLOCK 06000H-07FFFH 03000H-03FFFH A-1-A18(Bytemode) A0-A18(Wordmode) M5M29FB800 Memory Map A-1-A18(Bytemode) A0-A18(Wordmode) M5M29FT800 Memory Map BUS OPERATIONS Bus Operations for Word-Wide Mode (/BYTE=VIH) Pins /CE /OE Array Status Register Lock Bit Status Identifier Code Output disable Stand by Program Write Erase Others Deep Power Down VIL VIL VIL VIL VIL VIH VIL VIL VIL X VIL VIL VIL VIL VIH X 2) VIH VIH VIH X Mode Read /WE /RP DQ0-15 RY/BY VIH VIH VIH VIH VIH X VIL VIL VIL X VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z VOH (Hi-Z) X 1) X VOH (Hi-Z) X X X X X VOH (Hi-Z) /WE /RP DQ0-7 RY/BY VIH VIH VIH VIH VIH X VIL VIL VIL X VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z VOH (Hi-Z) X 1) X VOH (Hi-Z) X X X X X VOH (Hi-Z) Bus Operations for Byte-Wide Mode (BYTE=VIL) Pins /CE /OE Array Read Status Register Lock Bit Status Identifier Code Output disable Stand by Program Write Erase Others Deep Power Down VIL VIL VIL VIL VIL VIH VIL VIL VIL X VIL VIL VIL VIL VIH X 2) VIH VIH VIH X Mode 1) X at RY/BY is VOL or VOH(Hi-Z). *The RY/BY is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY signal to transition high indicating a Ready WSM condition. 2) X can be VIH or VIL for control pins. 4 May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY SOFTWARE COMMAND DEFINITION Command List Command Mode Read Array Device Identifier Read Status Register Clear Status Register Page Program 4) Block Erase / Confirm Suspend Resume Read Lock Bit Status Lock Bit Program / Confirm Erase All Unlocked Blocks Sleep 7) 1st bus cycle Address Data (D7-0) Write Write Write Write Write Write Write Write Write Write Write Write X X X X X X X X X X X X Mode FFH 90H 70H 50H 41H 20H B0H D0H 71H 77H A7H F0H 2nd bus cycle Address Data (D7-0) Read Read IA 2) X ID 2) SRD 3) Write Write WA0 4) BA 5) WD0 4) D0H Read Write Write BA BA X Mode 3rd bus cycle Address Data (D7-0) Write WA1 WD1 DQ6 6) D0H D0H 1) In the word-wide mode, upper byte data (D8-D15) is ignored. 2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code, /BYTE =VIL : A-1, A1-A18 = VIL, /BYTE =VIH : A1-A18 = VIL 3) SRD = Status Register Data 4) WA=Write Address, WD=Write Data. /BYTE =VIL : Write Address and Write Data must be provided sequentially from 00H to FFH for A-1-A6. Page size is 256Byte (256byte x 8bit), /BYTE =VIH : Write Address and Write Data must be provided sequentially from 00H to 7FH for A0-A6. Page size is 128word (128word x 16bit). 5) BA = Block Address ( Addresses except Block Address mest be VIH.) 6) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked. 7) Sleep command (F0H) put the device into the sleep mode after completing the current operation. The active current is reduced to deep power -down levels. The Read Array command (FFH) must be written to get the device out of sleep mode. BLOCK LOCKING SOP Package TSOP Package /RP Lock Bit(Internally) /RP /WP VIL VHH VIH VIH X X 0 1 VIL VHH VIH VIH VIH X X VIL VIL VIH Write Protection Provided Lock Bit(Internally) X X 0 1 X All Blocks Locked (Deep Power Down Mode) All Blocks UnLocked Blocks Locked (Depend on Lock Bit Data) Blocks Unlocked (Depend on Lock Bit Data) All Blocks Unlocked D6 provides Lock Status of each block after writing the Read Lock Status command (71H). In case of TSOP package, /WP pin must not be switched during performing Read / Write operations or WSM Busy (WSMS = 0). STATUS REGISTER Symbol SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 (D7) (D6) (D5) (D4) (D3) (D2) (D1) (D0) Definition Status "1" Ready Suspended Error Error Error Device in Sleep Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Device Sleep Status "0" Busy Operation in Progress / Completed Successful Successful Successful Device Not in Sleep *The RY/BY is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY signal to transition high indicating a Ready WSM condition. *D3 indicates the block status after the page programming. When D3 is "1", the page has the over-programed cell . If over-program occures, the device is block fail. However if D3 is "1", please try the block erase to the block. The block may revive. DEVICE IDENTIFIER CODE Pins A0 D7 Manufacturer Code VIL 0 Device Code (-T) VIH 0 Device Code (-B) VIH 0 1 Code D6 D5 D4 D3 D2 0 0 1 1 1 0 1 1 0 1 1 Hex. Data D1 D0 1 0 0 1CH 1 0 1 5DH 1 1 0 5EH In the word-wide mode, the same data as D7-0 is read out from D15-8. A9 = VHH Mode : A9 = 11.5V~13.0V Set A9 to VHH min.200ns before falling edge of /CE in ready status. Min.200ns after return to VIH ,device can't be accessed. A1~A8, A10~A18, /CE,/OE = VIL, /WE = VIH D15/A-1 = VIL (/BYTE = L) 5 May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI1 VI2 Ta Tbs Tstg I OUT Conditions Parameter Vcc voltage All input or output voltage except Vcc,A9,/RP1) A9,RP supply voltage Ambient temperature Temperature under bias Storage temperature Output short circuit current With respect to Ground Min -0.2 -0.6 -0.6 0 -10 -65 Max 4.6 4.6 14.0 70 80 125 100 Unit V V V °C °C °C mA 1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns. CAPACITANCE Symbol CIN COUT Parameter Test conditions Input capacitance (Address, Control Pins) Output capacitance Min Limits Typ Ta = 25°C, f = 1MHz, Vin = Vout = 0V Max 8 12 Unit pF pF DC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc = 3.3V±0.3V, unless otherwise noted) Symbol ILI ILO ISB1 ISB2 Parameter Input leakage current Output leakage current VCC standby current ISB3 ISB4 VCC deep powerdown current ICC1 VCC read current for Word or Byte ICC2 VCC Write current for Word or Byte ICC3 ICC4 ICC5 I RP IID VIHH VID VIL VIH VOL VOH1 VOH2 VLKO VCC program current VCC erase current VCC suspend current /RP all block unlock current A9 intelligent identifier current /RP unlock voltage A9 intelligent identifier voltage Input low voltage Input high voltage Output low voltage Output high voltage Low VCC Lock-Out voltage 2) Test conditions Min 0V≤VIN≤VCC 0V≤VOUT≤VCC VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH VCC = 3.6V, VIN=GND or VCC, /CE = /RP = /WP= VCC±0.3V VCC = 3.6V, VIN=VIL/VIH, /RP = VIL VCC = 3.6V, VIN=GND or VCC, /RP =GND±0.3V VCC = 3.6V, VIN=VIL/VIH, /CE = VIL, /RP=OE=VIH, f = 10MHz, IOUT = 0mA VCC = 3.6V,VIN=VIL/VIH, /CE =/WE= VIL, /RP=/OE=VIH Limits Typ1) 50 1 5 µA 5 1 15 5 µA µA 7 25 mA 30 mA 40 40 200 100 100 12.6 12.6 0.8 mA mA µA µA µA V V V V V V V V VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH /RP = VHH max A9 = VID max 11.4 11.4 – 0.5 2.0 IOL = 5.8mA IOH = –2.5mA IOH = –100µA 12.0 12.0 Vcc+0.5 0.45 0.85Vcc Vcc–0.4 1.5 Unit Max ±1.0 ±10 200 2.5 µA µA µA All currents are in RMS unless otherwise noted. 1) Typical values at Vcc=3.3V, Ta=25°C 2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO. If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents may occur. 6 May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~70°C, Vcc = 3.3±0.3V) Read-Only Mode Symbol tRC ta (AD) ta (CE) ta (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ tAVAV tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ ta(BYTE) tFL/HQV tBHZ tOH tBCD tBAD tOEH tFLQZ tOH tELFL/H tAVFL/H tWHGL tPS tPHEL Parameter Read cycle time Address access time Chip enable access time Output enable access time Chip enable to output in low-Z Chip enable high to output in high Z Output enable to output in low-Z Output enable high to output in high Z /RP low to output high-Z M5M29FB/T800-80 Min Typ Max 80 80 80 40 0 25 0 25 150 Limits M5M29FB/T800-10 Min Typ Max 100 100 100 50 0 25 0 25 150 M5M29FB/T800-12 Min Typ Max 120 120 120 60 0 30 0 30 300 Unit ns ns ns ns ns ns ns ns ns /BYTE access time 80 100 120 ns /BYTE low to output high-Z Output hold from /CE, /OE, addresses /CE low to /BYTE high or low Address to /BYTE high or low /OE hold from /WE high 25 25 30 80 100 120 ns ns ns ns ns /RP recovery to /CE low 500 500 500 ns Limits M5M29FB/T800-10 Min Typ Max 100 50 10 50 10 0 0 60 20 50 100 M5M29FB/T800-12 Min Typ Max 120 50 10 50 10 0 0 60 20 50 120 80 100 120 ns 0 0 0 ns 0 0 0 5 5 5 5 5 5 Timing measurements are made under AC waveforms for read operations. AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc = 3.3V±0.3V) Write Mode (/WE control) Symbol tWC tAS tAH tDS tDH tCS tCH tWP tWPH tBS tBH tBLS tWPS tBLH tWPH tDAP tDAE tWHRL tPS Parameter tAVAV tAVWH tWHAX tDVWH tWHDX tELWL tWHEH tWLWH tWHWL tFL/HWH tWHFL/H Write cycle time Address set-up time Address hold time Data set-up time Data hold time Chip enable set-up time Chip enable hold time Write pulse width Write pulse width high Byte enable high or low set-up time Byte enable high or low hold time tPHHWH Block Lock set-up to write enable high tQVPH Block Lockhold from valid SRD tWHRH1 tWHRH2 tWHRL tPHWL Duration of auto-program operation Duration of auto-block erase operation Write enable high to RY/BY low /RP high recovery to write enable low M5M29FB/T800-80 Min Typ Max 80 50 10 50 10 0 0 60 20 50 80 7.5 50 500 120 600 80 7.5 50 120 600 100 500 7.5 50 500 120 600 120 Unit ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at Vcc=3.3V, Ta=25°C 7 May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc = 3.3V±0.3V) Write Mode (/CE control) Parameter Symbol tWC tAS tAH tDS tDH tWS tWH tCEP tCEPH tBS tBH tBLS tWPS Limits M5M29FB/T800-10 Min Typ Max 100 50 10 50 10 0 0 60 20 50 100 M5M29FB/T800-12 Min Typ Max 120 50 10 50 10 0 0 60 20 50 120 80 100 120 ns 0 0 0 ns M5M29FB/T800-80 Min Typ Max 80 50 10 50 10 0 0 60 20 50 80 tAVAV tAVEH tEHAX tDVEH tEHDX tWLEL tEHWH tELEH tEHEL tFL/HEH tEHFL/H Write cycle time Address set-up time Address hold time Data set-up time Data hold time Write enable set-up time Write enable hold time /CE pulse width /CE pulse width high Byte enable high or low set-up time Byte enable high or low hold time tPHHEH Block Lock set-up to write enable high tBLH tWPH tQVPH Block Lockhold from valid SRD tDAP tDAE tEHRL tPS tEHRH1 tEHRH2 tEHRL tPHEL Duration of auto-program operation Duration of auto-block erase operation /CE enable high to RY/BY low /RP high recovery to write enable low 7.5 50 500 120 600 80 7.5 50 120 600 100 500 7.5 50 500 120 600 120 Unit ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at Vcc=3.3V, Ta=25°C Erase and Program Performance Parameter Min Block Erase Time Main Block Write Time (Page Mode) Page Write Time Typ Max Unit 50 1.9 7.5 600 3.8 120 ms sec ms Typ Max Unit Vcc Power Up / Down Timing Symbol tVCS Parameter /RP =VIH set-up time from Vccmin Min 2 µs During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contens during power up/down. The delay time of min.2µsec is always required before read operation or write operation is initiated from the time Vcc reaches Vccmin during power up/down. By holding /RP VIL, the contens of memory is protected during Vcc power up/down. During power up, /RP must be held VIL for min.2µs from the time Vcc reaches Vccmin. During power down, /RP must be held VIL until Vcc reaches GND. /RP doesn't have latch mode ,so /RP must be held VIH during read operation or erase/program operation. 8 May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY Vcc POWER UP / DOWN TIMING Read /Write Inhibit Read /Write Inhibit VCC Read /Write Inhibit 3.3V GND tVCS /RP VIH VIL /CE VIH VIL /WE tPS tPS VIH VIL AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS TEST CONDITIONS FOR AC CHARACTERISTICS VIH ADDRESSES ADDRESS VALID VIL /CE tRC VIH VIL /OE tDF(CE) ta (CE) VIH VIL /WE Input voltage : VIL = 0V, VIH = 3.0V Input rise and fall times : ≤5ns (80ns) ≤10ns (100/120ns) Reference voltage at timing measurement : 1.5V ta (AD) tOEH tDF(OE) Output load : 1TTL gate + CL(100pF for 100/120ns) CL(30pF for 80ns) or VIH ta (OE) VIL tOH tOLZ DATA VOH VOL /RP tCLZ HIGH-Z tPS 1.3V HIGH-Z OUTPUT VALID 1N914 tPHZ VIH VIL 3.3kΩ DUT CL =30/100pF BYTE AC WAVEFORMS FOR READ OPERATION ADDRESSES VIH (A0 - A18) VIL ADDRESS VALID ADDRESS VALID ta(AD) /CE VIH VIL tDF(CE) ta(CE) /OE VIH ta(OE) VIL /BYTE ta(BYTE) tOLZ VIL VIH DATA (D0 - D7) VIL VIH DATA (D8 - D14) VIL D15 / A-1 VIH VIL tBAD tCLZ VIH tDF(OE) ta(BYTE) tBCD HIGH-Z tOH tBAD OUTPUT VALID VALID VALID tBHZ ta(AD) HIGH-Z VALID A-1 D15 A-1 When /BYTE=VIH, /CE=/OE=VIL , D15/A-1 is output status. At this time, input signal must not be applied. 9 May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR PAGE PROGRAM OPERATION (/WE control) READ STATUS WRITE READ REGISTER ARRAY COMMAND PROGRAM VIH A7~A18 ADDRESS VALID VIL /BYTE=VIL (A-1~A6) VIH 00H 00H /BYTE=VIH VIL (A0 ~A6) /CE tWC 01H 7FH ta(CE) tCH ta(OE) VIH tOEH tDAE,tDAP tWPH VIH VIL DATA FFH 02H~7EH tAH tAS VIL /WE 02H~FEH VIH VIL tCS /OE 01H tWP VIH tDH tDS 41H DIN DIN DIN SRD DIN VIL RY/BY VOH VOL /BYTE FFH tWHRL tBS tBH VIH VIL VHH /RP tBLH tWPS tWPH VIH VIL /WP tBLS tPS VIH VIL AC WAVEFORMS FOR ERASE OPERATIONS (/WE control) ERASE VIH ADDRESSES tWC tAH tAS ta(CE) VIH VIL tCS tCH ta(OE) VIH /OE VIL tOEH tDAP,tDAE tWPH VIH /WE VIL tWP RY/BY tDH tDS VIH DATA WRITE READ ARRAY COMMAND ADDRESS VALID VIL /CE READ STATUS REGISTER 20H SRD D0H VIL FFH tWHRL VOH VOL tBS tBH VIH /BYTE VIL tBLS VHH /RP tPS VIH VIL tBLH tWPS tWPH VIH /WP 10 VIL May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR PAGE PROGRAM OPERATION (/CE control) READ STATUS WRITE READ REGISTER ARRAY COMMAND PROGRAM VIH A7~A18 ADDRESS VALID VIL /BYTE=VIL (A-1~A6)VIH 00H 00H /BYTE=VIH VIL (A0 ~A6) /CE /OE tWC FFH 01H 02H~7EH 7FH tAH ta(CE) ta(OE) VIH tCEP tWS tOEH tDAE,tDAP tWH VIH VIL DATA 02H~FEH tCEPH VIL /WE tAS VIH VIL 01H tDH tDS VIH 41H DIN DIN DIN DIN SRD VIL RY/BY tEHRL VOH VOL /BYTE FFH tBS tBH VIH VIL VHH /RP /WP tBLS tBLH tWPS tWPH tPS VIH VIL VIH VIL AC WAVEFORMS FOR ERASE OPERATIONS (/CE control) ERASE ADDRESSES VIH tWC tAH tAS ta(CE) VIH VIL tCEPH tCEP ta(OE) VIH /OE tOEH tDAP,tDAE VIL tWS tWH VIH /WE VIL RY/BY tDH tDS VIH DATA WRITE READ ARRAY COMMAND ADDRESS VALID VIL /CE READ STATUS REGISTER 20H SRD D0H VIL FFH tEHRL VOH VOL tBS tBH VIH /BYTE VIL tBLS VHH /RP tPS VIH VIL tBLH tWPS tWPH VIH /WP 11 VIL May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY FULL STATUS CHECK PROCEDURE STATUS REGISTER READ SR.4 =1 and SR.5 =1 ? NO YES SR.5 = 0 ? COMMAND SEQUENCE ERROR BLOCK ERASE ERROR NO YES SR.4 = 0 ? NO PROGRAM ERROR (PAGE, LOCK BIT) YES SR.3 = 0 ? NO PROGRAM ERROR (BLOCK) YES SUCCESSFUL (BLOCK ERASE, PROGRAM) LOCK BIT PROGRAM FLOW CHART START PAGE PROGRAM FLOW CHART START WRITE 77H WRITE 41H WRITE D0H BLOCK ADDRESS n=0 n = n+1 WRITE ADDRESS n, DATA n SR.7 = 1 ? NO YES SR.4 = 0 ? NO YES LOCK BIT PROGRAM SUCCESSFUL LOCK BIT PROGRAM FAILED n = FFH ? or n = 7FH ? NO YES STATUS REGISTER READ SR.7 = 1 ? NO YES FULL STATUS CHECK IF DESIRED PAGE PROGRAM COMPLETED 12 WRITE B0H ? NO YES SUSPEND LOOP WRITE D0H YES May 1997 , Rev.6.1 MITSUBISHI LSIs M5M29FB/T800FP,VP,RV-80,-10,-12 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY BLOCK ERASE FLOW CHART SUSPEND / RESUME FLOW CHART START START WRITE 20H WRITE B0H WRITE D0H BLOCK ADDRESS STATUS REGISTER READ STATUS REGISTER READ SR.7 = 1? SUSPEND NO YES NO SR.7 = 1 ? WRITE B0H ? NO SR.6 =1? NO PROGRAM / ERASE COMPLETED YES YES FULL STATUS CHECK IF DESIRED BLOCK ERASE COMPLETED YES WRITE FFH SUSPEND LOOP WRITE D0H READ ARRAY DATA YES DONE READING ? NO YES WRITE D0H RESUME OPERATION RESUMED 13 May 1997 , Rev.6.1 14 70H 90H 71H Clear Status Register 71H Y IS REQUEST SLEEP? return request Sleep F0H Internal State Program & Verify D0H 77H 70H FFH 90H 90H 90H 70H Read Device Identifier 90H FFH B0H B0H FFH 90H FFH Read Array FFH 70H FFH 71H 71H 70H FFH A7H Erase & Verify D0H 71H Read Lock Status invalid data F0H return request Sleep OTHER D0H OTHER Erase All Unlocked Blocks Setup FFH Read Lock Status Block Erase Setup 20H FFH 71H 71H 71H 70H Read Status Register Read Array D0H 90H 70H Read Status Register Read Status Register D0H OTHER Suspend State Read Status Register READY N 41H ay] Lock Bit Program Setup F0H [Sleep] 90H Read Device Identifier ead Arr FFH [Wake Up / R WDi i=0-255 Page Program Setup Setup State 70H Read Lock Status Read Status Register 90H Read Device Identifier Sleep State 50H 50H Read/Standby State MITSUBISHI LSIs 8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT) M5M29FB/T800FP,VP,RV-80,-10,-12 CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY OPERATION STATUS and EFFECTIVE COMMAND May 1997 , Rev.6.1