ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters Check for Samples: ADS42JB49, ADS42JB69 FEATURES APPLICATIONS • • • • • • • • • • • • • 1 • • • • • • • • • Dual-Channel ADCs 14- and 16-Bit Resolution Maximum Clock Rate: 250 MSPS JESD204B Serial Interface – Subclass 0, 1, 2 Compliant – Up to 3.125 Gbps – Two and Four Lanes Support Analog Input Buffer with High-Impedance Input Flexible Input Clock Buffer: Divide-by-1, -2, and -4 Differential Full-Scale Input: 2 VPP and 2.5 VPP (Register Programmable) Package: 9-mm × 9-mm QFN-64 Power Dissipation: 850 mW/Ch Aperture Jitter: 85 fS rms Internal Dither Channel Isolation: 100 dB Performance: – fIN = 170 MHz at 2 VPP, –1 dBFS – SNR: 73.3 dBFS – SFDR: 93 dBc for HD2, HD3 – SFDR: 100 dBc for Non HD2, HD3 – fIN = 170 MHz at 2.5 VPP, –1 dBFS – SNR: 74.7 dBFS – SFDR: 89 dBc for HD2, HD3 and 95 dBc for Non HD2, HD3 Device 14-, 16-Bit ADC CLKINP, CLKINM SYSREFP, SYSREFM JESD204B Digital RELATED PRODUCTS INTERFACE OPTION 14-BIT, 160 MSPS 14-BIT, 250 MSPS 16-BIT, 250 MSPS DDR, QDR LVDS — ADS42LB49 ADS42LB69 JESD204B ADS42JB46 ADS42JB49 ADS42JB69 FFT for 170MHz Input Signal Gain Test Modes PLL x10, x20 DA0P, DA0M DA1P, DA1M SYNCP, SYNCM Delay 14-, 16-Bit ADC The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-todigital converters (ADCs). These devices support the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range. 0 Divide by 1, 2, 4 INBP, INBM DESCRIPTION OVRA Digital Block INAP, INAM Communication and Cable Infrastructure Multi-Carrier, Multimode Cellular Receivers Radar and Smart Antenna Arrays Broadband Wireless Test and Measurement Systems Software-Defined and Diversity Radios Microwave and Dual-Channel I/Q Receivers Repeaters Power Amplifier Linearization Digital Block JESD204B Digital Gain Test Modes DB0P, DB0M DB1P, DB1M Fs = 250Msps Fin = 170MHz Ain = -1dBFS HD2 = 90dBc HD3 = 89dBc Non HD2,3 = 100dBc -20 -40 Amplitude (dB) 2 -60 -80 OVRB Common Mode MODE CTRL1 CTRL2 STBY SDOUT PDN PDN_GBL SEN SCLK SDATA Device Configuration RESET VCM -100 -120 0 25 50 75 Frequency (MHz) 100 125 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) (2) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE ADS42JB49 (2) QFN-64 RGC –40°C to +85°C ADS42JB69 QFN-64 RGC –40°C to +85°C For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Product preview device. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range, unless otherwise noted. Supply voltage range VALUE UNIT AVDD3V –0.3 to 3.6 V AVDD –0.3 to 2.1 V DRVDD –0.3 to 2.1 V IOVDD –0.3 to 2.1 V –0.3 to 0.3 V Voltage between AGND and DGND INAP, INBP, INAM, INBM Voltage applied to input pins Temperature range –0.3 to 3 V CLKINP, CLKINM –0.3 to minimum (2.1, AVDD + 0.3) V SYNC~P, SYNC~M –0.3 to minimum (2.1, AVDD + 0.3) V SYSREFP, SYSREFM –0.3 to minimum (2.1, AVDD + 0.3) V SCLK, SEN, SDATA, RESET, PDN_GBL, CTRL1, CTRL2, STBY, MODE –0.3 to 3.9 V Operating free-air, TA –40 to +85 °C +125 °C Operating junction, TJ Storage, Tstg Electrostatic discharge (ESD) rating Human body model (HBM) –65 to +150 °C 2 kV THERMAL INFORMATION ADS42JB49, ADS42JB69 THERMAL METRIC (1) RGC (QFN) UNITS 64 PINS θJA Junction-to-ambient thermal resistance 22.9 θJCtop Junction-to-case (top) thermal resistance 7.1 θJB Junction-to-board thermal resistance 2.5 ψJT Junction-to-top characterization parameter 0.1 ψJB Junction-to-board characterization parameter 2.5 θJCbot Junction-to-case (bottom) thermal resistance 0.2 (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 RECOMMENDED OPERATING CONDITIONS (1) Over operating free-air temperature range, unless otherwise noted. PARAMETER MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage AVDD3V Analog buffer supply voltage 1.7 1.8 1.9 V 3.15 3.3 3.45 DRVDD V Digital supply voltage 1.7 1.8 1.9 V IOVDD Output buffer supply voltage 1.7 1.8 1.9 V ANALOG INPUTS VID Differential input voltage range VICR Input common-mode voltage Default after reset Register programmable (2) 2 VPP 2.5 VPP VCM ± 0.025 V Maximum analog input frequency with 2.5-VPP input amplitude 250 MHz Maximum analog input frequency with 2-VPP input amplitude 400 MHz CLOCK INPUT Input clock sample rate Input clock amplitude differential (VCLKP – VCLKM) 10x mode 60 250 MSPS 20x mode 40 156.25 MSPS Sine wave, ac-coupled (3) 1.5 VPP LVPECL, ac-coupled 0.3 1.6 VPP LVDS, ac-coupled 0.7 VPP LVCMOS, single-ended, ac-coupled Input clock duty cycle 1.5 35% 50% V 65% DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DRGND RLOAD Single-ended load resistance TA Operating free-air temperature (1) (2) (3) 3.3 pF Ω +50 –40 +85 °C After power-up, to reset the device for the first time, use the RESET pin only. Refer to the Register Initialization section. For details, refer to the Digital Gain section. Refer to the Performance vs Clock Amplitude curves, Figure 32 and Figure 33. Table 1. High-Frequency Modes Summary REGISTER ADDRESS VALUE Dh 90h High-frequency modes should be enabled for input frequencies greater than 250 MHz. Eh 90h High-frequency modes should be enabled for input frequencies greater than 250 MHz. DESCRIPTION Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 3 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS: ADS42JB69 (16-Bit) Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V. PARAMETER SNR Signal-to-noise ratio SINAD Signal-to-noise and distortion ratio TEST CONDITIONS 2-VPP FULL-SCALE MIN TYP THD HD2 HD3 Total harmonic distortion 2nd-order harmonic distortion 3rd-order harmonic distortion TYP MAX UNITS 74 75.9 dBFS fIN = 70 MHz 73.8 75.6 dBFS fIN = 170 MHz 73.3 74.7 dBFS fIN = 230 MHz 70.8 72.6 74 dBFS fIN = 10 MHz 73.9 75.7 dBFS 73.7 75.3 dBFS 73.2 74.5 dBFS 72.2 73.1 dBFS 95 90 dBc 91 88 dBc 93 89 dBc fIN = 230 MHz 84 82 dBc fIN = 10 MHz 92 88 dBc fIN = 70 MHz 89 86 dBc 91 86 dBc fIN = 230 MHz 82 80 dBc fIN = 10 MHz 95 95 dBc fIN = 70 MHz 91 88 dBc 93 94 dBc fIN = 230 MHz 84 82 dBc fIN = 10 MHz 95 90 dBc fIN = 70 MHz 96 93 dBc fIN = 70 MHz fIN = 170 MHz 69.6 fIN = 10 MHz SFDR MIN fIN = 10 MHz fIN = 230 MHz Spurious-free dynamic range (including second and third harmonic distortion) MAX 2.5-VPP FULL-SCALE fIN = 70 MHz fIN = 170 MHz fIN = 170 MHz fIN = 170 MHz 78 81 94 89 dBc fIN = 230 MHz 86 84 dBc fIN = 10 MHz 102 102 dBc 103 103 dBc 100 95 dBc fIN = 230 MHz 99 93 dBc f1 = 46 MHz, f2 = 50 MHz, each tone at –7 dBFS 97 95 dBFS f1 = 185 MHz, f2 = 190 MHz, each tone at –7 dBFS 90 89 dBFS Crosstalk 20-MHz, full-scale signal on channel under observation; 170-MHz, full-scale signal on other channel 100 100 dB Input overload recovery Recovery to within 1% (of fullscale) for 6-dB overload with sinewave input 1 1 PSRR AC power-supply rejection ratio For 50-mVPP signal on AVDD supply, up to 10 MHz > 40 > 40 dB ENOB Effective number of bits fIN = 170 MHz 11.9 12.1 LSBs DNL Differential nonlinearity fIN = 170 MHz ±0.6 ±0.6 LSBs INL Integrated nonlinearity fIN = 170 MHz ±3 ±3.5 LSBs Worst spur (other than second and third harmonics) IMD 4 Two-tone intermodulation distortion Submit Documentation Feedback fIN = 170 MHz 81 81 fIN = 70 MHz fIN = 170 MHz 87 ±8 Clock cycle Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS: ADS42JB49 (14-Bit) Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V. PARAMETER SNR Signal-to-noise ratio SINAD Signal-to-noise and distortion ratio TEST CONDITIONS 2-VPP FULL-SCALE MIN TYP THD HD2 HD3 Total harmonic distortion 2nd-order harmonic distortion 3rd-order harmonic distortion TYP MAX UNITS 73.4 75 dBFS fIN = 70 MHz 73.2 74.7 dBFS fIN = 170 MHz 72.7 74 dBFS fIN = 230 MHz 69.5 72.2 73.4 dBFS fIN = 10 MHz 73.3 74.8 dBFS 73.1 74.5 dBFS 72.7 73.8 dBFS 71.8 72.6 dBFS 95 90 dBc 91 88 dBc 93 89 dBc fIN = 230 MHz 84 82 dBc fIN = 10 MHz 92 88 dBc fIN = 70 MHz 89 86 dBc 90 86 dBc fIN = 230 MHz 82 80 dBc fIN = 10 MHz 95 95 dBc fIN = 70 MHz 91 88 dBc 93 94 dBc fIN = 230 MHz 84 82 dBc fIN = 10 MHz 95 90 dBc fIN = 70 MHz 96 93 dBc fIN = 70 MHz fIN = 170 MHz 68.5 fIN = 10 MHz SFDR MIN fIN = 10 MHz fIN = 230 MHz Spurious-free dynamic range (including second and third harmonic distortion) MAX 2.5-VPP FULL-SCALE fIN = 70 MHz fIN = 170 MHz fIN = 170 MHz fIN = 170 MHz 76 79 94 89 dBc fIN = 230 MHz 86 84 dBc fIN = 10 MHz 102 102 dBc 103 103 dBc 101 95 dBc fIN = 230 MHz 99 93 dBc f1 = 46 MHz, f2 = 50 MHz, each tone at –7 dBFS 97 95 dBFS f1 = 185 MHz, f2 = 190 MHz, each tone at –7 dBFS 90 89 dBFS Crosstalk 20-MHz, full-scale signal on channel under observation; 170-MHz, full-scale signal on other channel 100 100 dB Input overload recovery Recovery to within 1% (of fullscale) for 6-dB overload with sinewave input 1 1 PSRR AC power-supply rejection ratio For a 50-mVPP signal on AVDD supply, up to 10 MHz > 40 > 40 ENOB Effective number of bits fIN = 170 MHz 11.8 12 LSBs DNL Differential nonlinearity fIN = 170 MHz ±0.15 ±0.15 LSBs INL Integrated nonlinearity fIN = 170 MHz ±0.75 ±0.9 LSBs Worst spur (other than second and third harmonics) IMD Two-tone intermodulation distortion fIN = 170 MHz 79 79 fIN = 70 MHz fIN = 170 MHz 87 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ±2 Submit Documentation Feedback Clock cycle dB 5 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Differential input voltage range VID Default (after reset) 2 VPP Register programmed (1) 2.5 VPP Differential input resistance (at 170 MHz) 1.2 kΩ 4 pF Differential input capacitance (at 170 MHz) Analog input bandwidth VCM With 50-Ω source impedance, and 50-Ω termination 900 MHz Common-mode output voltage 1.9 V VCM output current capability 10 mA DC ACCURACY Offset error –20 20 mV EGREF Gain error as a result of internal reference inaccuracy alone ±2 %FS EGCHAN Gain error of channel alone –5 %FS Temperature coefficient of EGCHAN Δ%/°C 0.01 POWER SUPPLY IAVDD Analog supply current 128 160 mA IAVDD3V Analog buffer supply current 290 330 mA IDRVDD Digital supply current 228 252 mA 60 100 mA IOVDD Output buffer supply current 50-Ω external termination from pin to IOVDD, fIN = 2.5 MHz Analog power 231 mW Analog buffer power 957 mW Digital power 410 mW 109 mW Power consumption by output buffer 50-Ω external termination from pin to IOVDD, fIN = 2.5 MHz Total power 1.7 Global power-down (1) 6 1.96 W 160 mW Refer to the Serial Interface section. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TIMING CHARACTERISTICS Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V. See Figure 1. PARAMETER TEST CONDITIONS MIN TYP MAX 0.7 1.1 UNITS SAMPLE TIMING CHARACTERISTICS Aperture delay 0.4 Between two channels on the same device Aperture delay matching Between two devices at the same temperature and supply voltage Aperture jitter Wake-up time ps ±150 ps 85 Time to valid data after coming out of STANDBY mode Time to valid data after coming out of global power-down ns ±70 fS rms 50 200 µs 250 1000 µs tSU_SYNC~ Setup time for SYNC~ Referenced to input clock rising edge 400 ps tH_SYNC~ Hold time for SYNC~ Referenced to input clock rising edge 100 ps tSU_SYSREF Setup time for SYSREF Referenced to input clock rising edge 400 ps tH_SYSREF Hold time for SYSREF Referenced to input clock rising edge 100 ps CML OUTPUT TIMING CHARACTERISTICS Unit interval 320 Serial output data rate Total jitter Data rise time, data fall time tR, tF 2.5 Gbps (10x mode, fS = 250 MSPS) 1667 ps 3.125 Gbps 0.28 P-PUI 3.125 Gbps (20x mode, fS = 156.25 MSPS) 0.3 P-PUI Rise and fall times measured from 20% to 80%, differential output waveform, 600 Mbps ≤ bit rate ≤ 3.125 Gbps 105 ps Table 2. Latency in Different Modes (1) (2) MODE 10x PARAMETER LATENCY (N Cycles) TYPICAL DATA DELAY (tD, ns) ADC latency 23 0.65 × tS + 3 Normal OVR latency 14 6.7 Fast OVR latency 9 6.7 from SYNC~ falling edge to CGS phase 20x (1) (2) (3) (4) (3) 16 0.65 × tS + 3 from SYNC~ rising edge to ILA sequence (4) 25 0.65 × tS + 3 ADC latency 22 0.85 × tS + 3 Normal OVR latency 14 6.7 Fast OVR latency 9 6.7 from SYNC~ falling edge to CGS phase (3) 15 0.85 × tS + 3 from SYNC~ rising edge to ILA sequence (4) 16 0.85 × tS + 3 Overall latency = latency + tD. tS is the time period of the ADC conversion clock. Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15 clock cycles in 20x mode. Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and 11 clock cycles in 20x mode. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 7 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TIMING DIAGRAMS N+3 N+2 Sample N N+4 N + Latency + 1 N + Latency N+1 N + Latency + 2 tA CLKP Input Clock CLKM ADC Latency (1) tD (2) Dx0P, Dx0M N - Latency-1 N + Latency N - Latency+1 N - Latency+2 N - Latency+3 N-1 N N+1 N+1 N - Latency-1 N + Latency N - Latency+1 N - Latency+2 N - Latency+3 N-1 N N+1 N+1 (2) Dx1P, Dx1M (1) Overall latency = ADC latency + tD. (2) x = A for channel A and B for channel B. Figure 1. ADC Latency CLKINP Input Clock CLKINM tSU_SYNC~ tH_SYNC~ SYNC~ tD SYNC~ Asserted Latency Dx0P, Dx0M Dx1P, Dx1M CGS Phase (1) Data Data Data Data Data Data Data Data Data K28.5 Data Data Data Data Data Data Data Data Data K28.5 (1) (1) x = A for channel A and B for channel B. Figure 2. SYNC~ Latency in CGS Phase (Two-Lane Mode) 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TIMING DIAGRAMS (continued) CLKINP Input Clock CLKINM tSU_SYNC~ tH_SYNC~ SYNC~ tD SYNC~ Deasserted Latency ILA Sequence Dx0P, Dx0M Dx1P, Dx1M (1) K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.0 K28.0 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.5 K28.0 K28.0 (1) (1) x = A for channel A and B for channel B. Figure 3. SYNC~ Latency in ILAS Phase (Two-Lane Mode) Sample N tSU_SYSREF Sample N tSU_SYNC~ tH_SYSREF CLKIN tH_SYNC~ CLKIN SYSREF SYNC~ Figure 4. SYSREF Timing (Subclass 1) Figure 5. SYNC~ Timing (Subclass 2) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 9 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com DIGITAL CHARACTERISTICS The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level '0' or '1'. AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE) (1) High-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels Low-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels 1.2 V 0.4 SEN V 0 µA RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE 10 µA SEN 10 µA 0 µA High-level input voltage 1.3 V Low-level input voltage 0.5 V Input common-mode voltage 0.9 V DRVDD V High-level input current Low-level input current RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE DIGITAL INPUTS (SYNC~P, SYNC~M, SYSREFP, SYSREFM) VCM_DIG DIGITAL OUTPUTS (SDOUT, OVRA, OVRB) DRVDD – 0.1 High-level output voltage Low-level output voltage 0.1 DIGITAL OUTPUTS (JESD204B Interface: DA[0,1], DB[0,1]) High-level output voltage IOVDD V Low-level output voltage IOVDD – 0.4 V 0.4 V IOVDD – 0.2 V |VOD| Output differential voltage VOCM Output common-mode voltage Transmitter short-circuit current Transmitter terminals shorted to any voltage between –0.25 V and 1.45 V Single-ended output impedance Output capacitance (1) (2) 10 V (2) Output capacitance inside the device, from either output to ground –100 100 mA 50 Ω 2 pF RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2 and MODE pins have 150-kΩ (typical) internal pull-down resistor to ground, while SEN pin has 150-kΩ (typical) pull-up resistor to AVDD. 50-Ω, single-ended external termination to IOVDD. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 PINOUT INFORMATION 49 DRVDD 50 DGND 51 DA1M 52 DA1P 53 DA0M 54 DA0P 55 IOVDD 56 DB0P 57 DB0M 58 DB1P 59 DB1M 60 DRVDD 61 OVRA 62 OVRB 63 DGND 64 DRVDD RGC PACKAGE QFN-64 (Top View) DGND 1 48 DGND DRVDD 2 47 DRVDD DGND 3 46 DGND MODE 4 45 SDOUT STBY 5 44 RESET PDN_GBL 6 43 SCLK DRVDD 7 42 SDATA SYNC~M 8 41 SEN 9 40 AVDD CTRL2 10 39 CTRL1 AVDD 11 38 AVDD AGND 12 37 AGND INBP 13 36 INAP INBM 14 35 INAM AGND 15 34 AGND AVDD 16 33 AVDD Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 AVDD3V 32 AVDD 31 SYSREFM 30 SYSREFP 29 AGND 28 AVDD 27 AGND 26 CLKINP 25 CLKINM 24 AGND 23 AVDD 22 VCM 21 AGND 20 AGND 19 AVDD3V 17 SYNC~P AVDD 18 Thermal Pad Submit Documentation Feedback 11 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com PIN ASSIGNMENTS: JESD204B Output Interface NAME PIN NO. I/O FUNCTION DESCRIPTION AGND 12, 15, 19, 20, 23, 26, 28, 34, 37 I Supply Analog ground AVDD 11, 16, 18, 22, 27, 31, 33, 38, 40 I Supply 1.8-V analog power supply AVDD3V 17, 32 I Supply 3.3-V analog supply for analog buffer CLKINM 24 I Clock Differential ADC clock input CLKINP 25 I Clock Differential ADC clock input CTRL1 39 I Control Power-down control with an internal 150-kΩ pull-down resistor CTRL2 10 I Control Power-down control with an internal 150-kΩ pull-down resistor DA0P/M 54, 53 O Interface JESD204B serial data output for channel A, lane 0 DA1P/M 52,51 O Interface JESD204B serial data output for channel A, lane 1 DB0P/M 56,57 O Interface JESD204B serial data output for channel B, lane 0 DB1P/M 58,59 O Interface JESD204B serial data output for channel B, lane 1 DGND 1, 3, 46, 48, 50, 63 I Supply Digital ground DRVDD 2, 7, 47, 49, 60, 64 I Supply Digital 1.8-V power supply INAM 35 I Input Differential analog input for channel A INAP 36 I Input Differential analog input for channel A INBM 14 I Input Differential analog input for channel B INBP 13 I Input Differential analog input for channel B IOVDD 55 I Supply Digital 1.8-V power supply for the JESD204B transmitter Connect to GND MODE 4 I Control OVRA 61 O Interface Overrange indication channel A in CMOS output format. OVRB 62 O Interface Overrange indication channel B in CMOS output format. PDN_GBL 6 I Control Global power down. Active high with an internal 150-kΩ pull-down resistor. RESET 44 I Control Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor. SCLK 43 I Control Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor. SDATA 42 I Control Serial interface data input. This pin has an internal 150-kΩ pull-down resistor. SDOUT 45 O Control Serial interface data output SEN 41 I Control Serial interface enable. This pin has an internal 150-kΩ pull-up resistor. STBY 5 I Control Standby. Active high with an internal 150-kΩ pull-down resistor. SYNC~P 9 I Interface Synchronization input for JESD204B port SYNC~M 8 I Interface Synchronization input for JESD204B port SYSREFM 30 I Clock External SYSREF input (subclass 1) SYSREFP 29 I Clock External SYSREF input (subclass 1) VCM 21 O Output 1.9-V common-mode output voltage for analog inputs Thermal Pad 65 GND Ground Connect to ground plane 12 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: ADS42JB69 Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 0 0 fIN = 10 MHz SFDR = 96 dBc SNR = 74 dBFS SINAD = 73.9 dBFS THD = 94 dBc SFDR Non HD2, HD3 = 102 dBc −20 −20 −40 Amplitude (dBFS) Amplitude (dBFS) −40 −60 −60 −80 −80 −100 −100 −120 0 25 50 75 100 −120 125 Frequency (MHz) fIN = 170 MHz SFDR = 88 dBc SNR = 73.3 dBFS SINAD = 73 dBFS THD = 87 dBc SFDR Non HD2, HD3 = 101 dBc 0 75 100 125 G002 Figure 7. FFT FOR 170-MHz INPUT SIGNAL 0 0 fIN = 300 MHz SFDR = 74 dBc SNR = 72.4 dBFS SINAD = 69.9 dBFS THD = 73 dBc SFDR Non HD2,HD3 = 96 −20 −40 −60 −60 −80 −80 −100 −100 0 25 50 75 100 Frequency (MHz) fIN = 10 MHz SFDR = 90 dBc SNR = 75.8 dBFS SINAD = 75.7 dBFS THD = 89 dBc SFDR Non HD2, HD3 = 105 dBc −20 Amplitude (dBFS) −40 Amplitude (dBFS) 50 Frequency (MHz) G001 Figure 6. FFT FOR 10-MHz INPUT SIGNAL −120 25 125 −120 0 25 75 100 Frequency (MHz) G003 Figure 8. FFT FOR 300-MHz INPUT SIGNAL 50 125 G004 Figure 9. FFT FOR 10-MHz INPUT SIGNAL (2.5-VPP Full-Scale) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 13 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: ADS42JB69 (continued) Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 0 0 fIN = 170 MHz SFDR = 87 dBc SNR = 74.7 dBFS SINAD = 74.4 dBFS THD = 84 dBc SFDR Non HD2, HD3 = 94 dBc −20 −20 −40 Amplitude (dBFS) Amplitude (dBFS) −40 −60 −60 −80 −80 −100 −100 −120 0 25 50 fIN = 300 MHz SFDR = 71 dBc SNR = 73.4 dBFS SINAD = 69 dBFS THD = 70 dBc SFDR Non HD2, HD3 = 94 dBc 75 100 −120 125 Frequency (MHz) 0 G005 100 125 G006 0 Each Tone at −7 dBFS Amplitude fIN1 = 46 MHz fIN2 = 50 MHz 2−Tone IMD = 98 dBFS SFDR = 105 dBFS −20 Each Tone at −36 dBFS Amplitude fIN1 = 46 MHz fIN2 = 50 MHz 2−Tone IMD = 101 dBFS SFDR = 106 dBFS −20 −40 Amplitude (dBFS) −40 Amplitude (dBFS) 75 Figure 11. FFT FOR 300-MHz INPUT SIGNAL (2.5-VPP Full-Scale) 0 −60 −60 −80 −80 −100 −100 0 25 50 75 100 Frequency (MHz) Submit Documentation Feedback 125 −120 0 25 50 75 100 Frequency (MHz) G007 Figure 12. FFT FOR TWO-TONE INPUT SIGNAL (–7 dBFS at 46 MHz and 50 MHz) 14 50 Frequency (MHz) Figure 10. FFT FOR 170-MHz INPUT SIGNAL (2.5-VPP Full-Scale) −120 25 125 G007 Figure 13. FFT FOR TWO-TONE INPUT SIGNAL (–36 dBFS at 46 MHz and 50 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: ADS42JB69 (continued) Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 0 0 Each Tone at −7 dBFS Amplitude fIN1 = 185 MHz fIN2 = 190 MHz 2−Tone IMD = 90 dBFS SFDR = 102 dBFS −20 −20 −40 Amplitude (dBFS) Amplitude (dBFS) −40 −60 −60 −80 −80 −100 −100 −120 0 25 50 75 100 −120 125 Frequency (MHz) 0 25 50 75 100 125 Frequency (MHz) G009 Figure 14. FFT FOR TWO-TONE INPUT SIGNAL (–7 dBFS at 185 MHz and 190 MHz) G010 Figure 15. FFT FOR TWO-TONE INPUT SIGNAL (–36 dBFS at 185 MHz and 190 MHz) −98 −90 fIN1 = 46 MHz fIN2 = 50 MHz fIN1 = 185 MHz fIN2 = 190 MHz −92 −100 −94 Two − Tone IMD (dBFS) Two − Tone IMD (dBFS) Each Tone at −36 dBFS Amplitude fIN1 = 185 MHz fIN2 = 190 MHz 2−Tone IMD = 101 dBFS SFDR = 104 dBFS −102 −104 −106 −96 −98 −100 −102 −104 −106 −108 −108 −110 −36 −33 −30 −27 −24 −21 −18 −15 −12 −9 −7 Each Tone Amplitude (dBFS) Figure 16. INTERMODULATION DISTORTION vs INPUT AMPLITUDE (46 MHz and 50 MHz) −110 −36 −33 −30 −27 −24 −21 −18 −15 −12 −9 −7 Each Tone Amplitude (dBFS) G011 G001 Figure 17. INTERMODULATION DISTORTION vs INPUT AMPLITUDE (185 MHz and 190 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 15 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: ADS42JB69 (continued) Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 100 77 2−VPP Full−Scale 2.5−VPP Full−Scale 95 2−VPP Full−Scale 2.5−VPP Full−Scale 76 90 75 SNR (dBFS) SFDR (dBc) 85 80 75 74 73 70 72 65 71 60 55 0 50 100 150 200 250 300 350 70 400 Input Frequency (MHz) 50 100 150 200 250 300 350 400 Input Frequency (MHz) G013 Figure 18. SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY G014 Figure 19. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 120 110 0 80 10 MHz 70 MHz 100 MHz 130 MHz 170 MHz 230 MHz 270 MHz 350 MHz 400 MHz 491 MHz 10 MHz 70 MHz 100 MHz 130 MHz 78 170 MHz 230 MHz 270 MHz 350 MHz 400 MHz 491 MHz 76 SNR (dBFS) SFDR (dBc) 100 90 74 72 80 70 70 60 68 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Digital Gain (dB) Submit Documentation Feedback −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Digital Gain (dB) G015 Figure 20. SPURIOUS-FREE DYNAMIC RANGE vs DIGITAL GAIN 16 66 G016 Figure 21. SIGNAL-TO-NOISE RATIO vs DIGITAL GAIN Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: ADS42JB69 (continued) Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Input Frequency = 70 MHz SNR(dBFS) SFDR(dBc) SFDR(dBFS) SNR(dBFS) SFDR(dBc) SFDR(dBFS) 77 76 110 76.5 110 75.5 100 76 100 90 74.5 80 74 70 73.5 60 73 120 75.5 90 75 80 74.5 70 74 60 50 73.5 50 72.5 40 73 40 72 30 72.5 30 −60 −50 −40 −30 −20 −10 0 20 72 −70 −60 −50 −40 −30 −20 −10 0 20 Amplitude (dBFS) Amplitude (dBFS) G017 G018 Figure 22. PERFORMANCE vs INPUT AMPLITUDE (70 MHz) Figure 23. PERFORMANCE vs INPUT AMPLITUDE (170 MHz) 76 99 Input Frequency = 70 MHz 75.5 101 SFDR SNR Input Frequency = 170 MHz SFDR SNR 98 75 94 75 95 74.5 92 74.5 92 74 89 74 89 73.5 86 73.5 86 73 84 73 83 72.5 82 1.85 1.87 1.9 1.93 72.5 1.95 Input Common−Mode Voltage (V) Figure 24. PERFORMANCE vs INPUT COMMON-MODE VOLTAGE (70 MHz) SFDR (dBc) 75.5 SNR (dBFS) 96 80 1.85 G019 1.87 1.9 1.93 SNR (dBFS) 71.5 −70 SNR (dBFS) 75 SFDR (dBc,dBFS) SNR (dBFS) Input Frequency = 170 MHz 120 76.5 SFDR (dBc) 130 77.5 SFDR (dBc,dBFS) 130 77 72 1.95 Input Common−Mode Voltage (V) G020 Figure 25. PERFORMANCE vs INPUT COMMON-MODE VOLTAGE (170 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 17 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: ADS42JB69 (continued) Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 75 99 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 98 97 AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75V AVDD = 1.8 V 74.5 AVDD = 1.85 V AVDD = 1.9 V 96 74 SNR (dBFS) SFDR (dBc) 95 94 93 92 91 73.5 73 90 89 72.5 88 Input Frequency = 170 MHz 87 −40 −15 10 35 Temperature (°C) Input Frequency = 170 MHz 60 72 −40 85 −15 10 35 Temperature (°C) 60 85 G021 G022 Figure 26. SPURIOUS-FREE DYNAMIC RANGE vs AVDD SUPPLY AND TEMPERATURE (170 MHz) Figure 27. SIGNAL-TO-NOISE RATIO vs AVDD SUPPLY AND TEMPERATURE (170 MHz) 75 98 AVDD3V = 3.15 V AVDD3V = 3.2 V AVDD3V = 3.25 V AVDD3V = 3.3 V 97 96 AVDD3V = 3.35 V AVDD3V = 3.4 V AVDD3V = 3.45 V AVDD3V = 3.15 V AVDD3V = 3.2 V AVDD3V = 3.25 V AVDD3V = 3.3 V 74.5 AVDD3V = 3.35 V AVDD3V = 3.4 V AVDD3V = 3.45 V 95 74 SNR (dBFS) SFDR (dBc) 94 93 92 91 73.5 73 90 89 72.5 88 Input Frequency = 170 MHz 87 −40 −15 10 35 Temperature (°C) Input Frequency = 170 MHz 60 85 72 −40 −15 G023 Figure 28. SPURIOUS-FREE DYNAMIC RANGE vs AVDD_BUF SUPPLY AND TEMPERATURE (170 MHz) 18 Submit Documentation Feedback 10 35 Temperature (°C) 60 85 G024 Figure 29. SIGNAL-TO-NOISE RATIO vs AVDD_BUF SUPPLY AND TEMPERATURE (170 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: ADS42JB69 (continued) Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 75 97 DRVDD = 1.7 V DRVDD = 1.75 V DRVDD = 1.8 V 96 DRVDD = 1.85 V DRVDD = 1.9 V DRVDD = 1.7 V DRVDD = 1.75 V DRVDD = 1.8 V 74.5 DRVDD = 1.85 V DRVDD = 1.9 V 95 74 SNR (dBFS) SFDR (dBc) 94 93 92 73.5 91 73 90 72.5 89 Input Frequency = 170 MHz −15 Input Frequency = 170 MHz 10 35 Temperature (°C) 60 72 −40 85 −15 10 35 Temperature (°C) 60 85 G025 G026 Figure 30. SPURIOUS-FREE DYNAMIC RANGE vs DRVDD SUPPLY AND TEMPERATURE (170 MHz) 77 96 80 96 Input Frequency =170 MHz 94 76 92 75 74 90 SFDR (dBc) SFDR SNR SNR (dBFS) Input Frequency = 70 MHz SFDR (dBc) Figure 31. SIGNAL-TO-NOISE RATIO vs DRVDD SUPPLY AND TEMPERATURE (170 MHz) SFDR SNR 94 78 92 76 90 74 88 72 86 70 84 68 SNR (dBFS) 88 −40 73 88 72 86 84 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 71 2.1 Differential Clock Amplitudes (Vpp) Figure 32. PERFORMANCE vs CLOCK AMPLITUDE (70 MHz) 82 0.1 G027 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 66 2.1 Differential Clock Amplitudes (Vpp) G028 Figure 33. PERFORMANCE vs CLOCK AMPLITUDE (170 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 19 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: ADS42JB69 (continued) Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Input Frequency = 170 MHz 77 92 76 90 75 88 74 86 73 84 72 82 30 40 50 60 Input Clock Duty Cycle (%) 70 SFDR (dBc) 94 71 SNR SFDR 94 76 92 75 90 74 88 73 86 72 84 30 40 50 60 Input Clock Duty Cycle (%) 70 SNR (dBFS) SNR SFDR SNR (dBFS) SFDR (dBc) Input Frequency = 70 MHz 77 96 78 96 71 G029 Figure 34. PERFORMANCE vs CLOCK DUTY CYCLE (70 MHz) 20 Submit Documentation Feedback G030 Figure 35. PERFORMANCE vs CLOCK DUTY CYCLE (170 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: ADS42JB49 Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 0 0 fIN = 10 MHz SFDR = 97 dBc SNR = 73.4 dBFS SINAD = 73.3 dBFS THD = 95 dBc SFDR Non HD2, HD3 = 103 dBc −20 −20 −40 Amplitude (dBFS) Amplitude (dBFS) −40 −60 −60 −80 −80 −100 −100 −120 0 25 50 75 100 Frequency (MHz) fIN = 170 MHz SFDR = 89 dBc SNR = 72.8 dBFS SINAD = 72.5 dBFS THD = 88 dBc SFDR Non HD2, HD3 = 100 dBc −120 125 0 50 75 100 125 Frequency (MHz) G031 Figure 36. FFT FOR 10-MHz INPUT SIGNAL G032 Figure 37. FFT FOR 170-MHz INPUT SIGNAL 0 0 fIN = 300 MHz SFDR = 74 dBc SNR = 72.1 dBFS SINAD = 69.8 dBFS THD = 72 dBc SFDR Non HD2, HD3 = ±20 fIN = 10 MHz SFDR = 89 dBc SNR = 75 dBFS SINAD = 74.8 dBFS THD = 88 dBc SFDR Non HD2, HD3 = 103 dBc −20 −40 Amplitude (dBFS) ±40 Amplitude (dB) 25 ±60 −60 ±80 −80 ±100 −100 −120 ±120 0 25 50 75 100 125 0 25 50 75 100 Frequency (MHz) Frequency (Mhz) 125 G034 C033 Figure 38. FFT FOR 300-MHz INPUT SIGNAL Figure 39. FFT FOR 10-MHz INPUT SIGNAL (2.5-VPP Full-Scale) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 21 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: ADS42JB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 0 0 fIN = 170 MHz SFDR = 87 dBc SNR = 73.9 dBFS SINAD = 73.7 dBFS THD = 85 dBc SFDR Non HD2, HD3 = 94 dBc −20 −20 −40 Amplitude (dBFS) Amplitude (dBFS) −40 −60 −60 −80 −80 −100 −100 −120 0 25 50 fIN = 300 MHz SFDR = 71 dBc SNR = 73.1 dBFS SINAD = 68.4 dBFS THD = 69 dBc SFDR Non HD2, HD3 = 93 dBc 75 100 −120 125 Frequency (MHz) 0 100 125 G036 0 Each Tone at −7 dBFS Amplitude fIN1 = 46 MHz fIN2 = 50 MHz 2−Tone IMD = 98 dBFS SFDR = 105 dBFS −20 Each Tone at −36 dBFS Amplitude fIN1 = 46 MHz fIN2 = 50 MHz 2−Tone IMD = 101 dBFS SFDR = 106 dBFS −20 −40 Amplitude (dBFS) −40 Amplitude (dBFS) 75 Figure 41. FFT FOR 300-MHz INPUT SIGNAL (2.5-VPP Full-Scale) 0 −60 −60 −80 −80 −100 −100 0 25 50 75 100 Frequency (MHz) Submit Documentation Feedback 125 −120 0 25 50 75 100 Frequency (MHz) G037 Figure 42. FFT FOR TWO-TONE INPUT SIGNAL (–7 dBFS at 46 MHz and 50 MHz) 22 50 Frequency (MHz) G035 Figure 40. FFT FOR 170-MHz INPUT SIGNAL (2.5-VPP Full-Scale) −120 25 125 G038 Figure 43. FFT FOR TWO-TONE INPUT SIGNAL (–36 dBFS at 46 MHz and 50 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: ADS42JB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 0 0 Each Tone at −7 dBFS Amplitude fIN1 = 185 MHz fIN2 = 190 MHz 2−Tone IMD = 90 dBFS SFDR = 102 dBFS −20 −20 −40 Amplitude (dBFS) Amplitude (dBFS) −40 −60 −60 −80 −80 −100 −100 −120 0 25 50 75 100 −120 125 Frequency (MHz) 0 25 50 75 100 125 Frequency (MHz) G039 Figure 44. FFT FOR TWO-TONE INPUT SIGNAL (–7 dBFS at 185 MHz and 190 MHz) G040 Figure 45. FFT FOR TWO-TONE INPUT SIGNAL (–36 dBFS at 185 MHz and 190 MHz) −98 −90 fIN1 = 46 MHz fIN2 = 50 MHz fIN1 = 185 MHz fIN2 = 190 MHz −92 −100 −94 Two − Tone IMD (dBFS) Two − Tone IMD (dBFS) Each Tone at −36 dBFS Amplitude fIN1 = 185 MHz fIN2 = 190 MHz 2−Tone IMD = 101 dBFS SFDR = 104 dBFS −102 −104 −106 −96 −98 −100 −102 −104 −106 −108 −108 −110 −36 −33 −30 −27 −24 −21 −18 −15 −12 −9 −7 Each Tone Amplitude (dBFS) Figure 46. INTERMODULATION DISTORTION vs INPUT AMPLITUDE (46 MHz and 50 MHz) −110 −36 −33 −30 −27 −24 −21 −18 −15 −12 −9 −7 Each Tone Amplitude (dBFS) G041 G042 Figure 47. INTERMODULATION DISTORTION vs INPUT AMPLITUDE (185 MHz and 190 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 23 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: ADS42JB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 76 100 2−VPP Full−Scale 2.5−VPP Full−Scale 2−VPP Full−Scale 2.5−VPP Full−Scale 95 75 90 74 SNR (dBFS) SFDR (dBc) 85 80 73 72 75 71 70 70 65 60 0 50 100 150 200 250 300 350 69 400 Input Frequency (MHz) 50 100 150 200 250 300 350 400 Input Frequency (MHz) G043 Figure 48. SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY G044 Figure 49. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 120 110 0 77 10 MHz 70 MHz 100 MHz 130 MHz 170 MHz 230 MHz 270 MHz 350 MHz 400 MHz 491 MHz 10 MHz 70 MHz 100 MHz 130 MHz 76 75 170 MHz 230 MHz 270 MHz 350 MHz 400 MHz 491 MHz 74 73 SNR (dBFS) SFDR (dBc) 100 90 72 71 70 80 69 68 70 67 60 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Digital Gain (dB) Submit Documentation Feedback −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Digital Gain (dB) G045 Figure 50. SPURIOUS-FREE DYNAMIC RANGE vs DIGITAL GAIN 24 66 G046 Figure 51. SIGNAL-TO-NOISE RATIO vs DIGITAL GAIN Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: ADS42JB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. Input Frequency = 70 MHz SNR(dBFS) SFDR(dBc) SFDR(dBFS) SNR(dBFS) SFDR(dBc) SFDR(dBFS) 76 76 110 75.5 110 75.5 100 75 100 90 74.5 80 74 70 73.5 60 73 120 74.5 90 74 80 73.5 70 73 60 50 72.5 50 72.5 40 72 40 72 30 71.5 30 −60 −50 −40 −30 −20 −10 0 20 71 −70 −60 −50 −40 −30 −20 −10 0 20 Amplitude (dBFS) Amplitude (dBFS) G047 G048 Figure 52. PERFORMANCE vs INPUT AMPLITUDE (70 MHz) Figure 53. PERFORMANCE vs INPUT AMPLITUDE (170 MHz) 75.5 99 Input Frequency = 70 MHz 75 101 SFDR SNR Input Frequency = 170 MHz SFDR SNR 98 74.5 94 74.5 95 74 92 74 92 73.5 89 73.5 89 73 86 73 86 72.5 84 72.5 83 72 82 1.85 1.87 1.9 1.93 72 1.95 Input Common−Mode Voltage (V) Figure 54. PERFORMANCE vs INPUT COMMON-MODE VOLTAGE (70 MHz) SFDR (dBc) 75 SNR (dBFS) 96 80 1.85 G049 1.87 1.9 1.93 SNR (dBFS) 71.5 −70 SNR (dBFS) 75 SFDR (dBc,dBFS) SNR (dBFS) Input Frequency = 170 MHz 120 76.5 SFDR (dBc) 130 76.5 SFDR (dBc,dBFS) 130 77 71.5 1.95 Input Common−Mode Voltage (V) G050 Figure 55. PERFORMANCE vs INPUT COMMON-MODE VOLTAGE (170 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 25 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: ADS42JB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 99 74.5 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 98 97 AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75V AVDD = 1.8 V 74 AVDD = 1.85 V AVDD = 1.9 V 96 73.5 SNR (dBFS) SFDR (dBc) 95 94 93 92 73 72.5 91 72 90 89 71.5 88 Input Frequency = 170 MHz 87 −40 −15 10 35 Temperature (°C) Input Frequency = 170 MHz 60 71 −40 85 −15 10 35 Temperature (°C) 60 85 G051 G052 Figure 56. SPURIOUS-FREE DYNAMIC RANGE vs AVDD SUPPLY AND TEMPERATURE (170 MHz) Figure 57. SIGNAL-TO-NOISE RATIO vs AVDD SUPPLY AND TEMPERATURE (170 MHz) 74.5 98 AVDD3V = 3.15 V AVDD3V = 3.2 V AVDD3V = 3.25 V AVDD3V = 3.3 V 97 96 AVDD3V = 3.35 V AVDD3V = 3.4 V AVDD3V = 3.45 V AVDD3V = 3.15 V AVDD3V = 3.2 V AVDD3V = 3.25 V AVDD3V = 3.3 V 74 AVDD3V = 3.35 V AVDD3V = 3.4 V AVDD3V = 3.45 V 95 73.5 SNR (dBFS) SNR (dBFS) 94 93 92 91 73 72.5 90 89 72 88 Input Frequency = 170 MHz 87 −40 −15 10 35 Temperature (°C) Input Frequency = 170 MHz 60 85 71.5 −40 −15 10 35 Temperature (°C) 60 85 G053 Figure 58. SPURIOUS-FREE DYNAMIC RANGE vs AVDD_BUF SUPPLY AND TEMPERATURE (170 MHz) 26 Submit Documentation Feedback G054 Figure 59. SIGNAL-TO-NOISE RATIO vs AVDD_BUF SUPPLY AND TEMPERATURE (170 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: ADS42JB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 97 74.5 DRVDD = 1.7 V DRVDD = 1.75 V DRVDD = 1.8 V 96 DRVDD = 1.85 V DRVDD = 1.9 V DRVDD = 1.7 V DRVDD = 1.75 V DRVDD = 1.8 V 74 DRVDD = 1.85 V DRVDD = 1.9 V 95 73.5 SNR (dBFS) SFDR (dBc) 94 93 92 73 72.5 91 72 90 71.5 89 Input Frequency = 170 MHz 88 −40 −15 Input Frequency = 170 MHz 10 35 Temperature (°C) 60 71 −40 85 −15 10 35 Temperature (°C) 60 85 G055 G056 Figure 60. SPURIOUS-FREE DYNAMIC RANGE vs DRVDD SUPPLY AND TEMPERATURE (170 MHz) 77 96 Input Frequency = 70 MHz 82 98 SFDR SNR Input Frequency = 170 MHz SFDR SNR 96 80 94 78 92 76 90 74 88 72 86 70 84 68 76 94 88 73 SNR (dBFS) 74 SFDR (dBc) 90 SNR (dBFS) 75 92 SFDR (dBc) Figure 61. SIGNAL-TO-NOISE RATIO vs DRVDD SUPPLY AND TEMPERATURE (170 MHz) 72 86 84 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 71 2.1 Differential Clock Amplitudes (Vpp) Figure 62. PERFORMANCE vs CLOCK AMPLITUDE (70 MHz) 82 0.1 G057 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 66 2.1 Differential Clock Amplitudes (Vpp) G058 Figure 63. PERFORMANCE vs CLOCK AMPLITUDE (170 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 27 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: ADS42JB49 (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted. 74.5 96 SNR SFDR Input Frequency = 170 MHz SNR SFDR 94 74.5 94 74 92 74 92 73.5 90 73.5 90 73 88 73 88 72.5 86 72.5 86 72 84 72 84 71.5 71.5 82 82 30 40 50 60 Input Clock Duty Cycle (%) 70 SFDR (dBc) SNR (dBFS) SFDR (dBc) Input Frequency = 70 MHz 30 40 50 60 Input Clock Duty Cycle (%) 70 SNR (dBFS) 75 96 71 G059 Figure 64. PERFORMANCE vs CLOCK DUTY CYCLE (70 MHz) 28 Submit Documentation Feedback G060 Figure 65. PERFORMANCE vs CLOCK DUTY CYCLE (170 MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: COMMON Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted. 0 0 fIN = 100 MHz SFDR = 86 dBc fCM = 5 MHz, 50 mVPP Amplitude (fIN) = -1 dBFS Amplitude (fCM) = -105 dBFS Amplitude (fIN + fCM) = -90 dBFS Amplitude (fIN - fCM) = -87 dBFS ±20 −10 −15 −20 CMRR (dB) ±40 Amplitude (dB) Input Frequency = 10MHz 50−mVPP Signal Superimposed on VCM −5 ±60 −25 −30 −35 −40 ±80 −45 −50 −55 ±100 −60 −65 ±120 0 20 40 60 80 100 120 0 50 100 150 200 250 300 Common−Mode Test Signal Frequency (MHz) Frequency (Mhz) G062 C061 Figure 66. COMMON-MODE REJECTION RATIO FFT Figure 67. COMMON-MODE REJECTION RATIO vs TEST SIGNAL FREQUENCY −20 0 fIN = 20 MHz SFDR = 87 dBc fPSRR = 5 MHz, 50 mVPP Amplitude (fIN) = -1 dBFS Amplitude (fPSRR) = -88 dBFS Amplitude (fIN + fPSRR) = -97.8 dBFS ±20 50−mVPP Signal Superimposed on AVDD 100−mVPP Signal Superimposed on AVDD3V −30 −40 PSRR (dB) Amplitude (dB) ±40 ±60 −50 −60 ±80 −70 ±100 −80 ±120 −90 Input Frequency = 20MHz 0 20 40 60 80 100 120 0 50 100 150 200 250 300 Test Signal Frequency on Supply (MHz) Frequency (Mhz) G064 C063 Figure 68. POWER-SUPPLY REJECTION RATIO FFT FOR AVDD SUPPLY Figure 69. POWER-SUPPLY REJECTION RATIO vs TEST SIGNAL FREQUENCY Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 29 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: COMMON (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted. 0.18 2 AVDD Power DVDD Power IOVDD Power AVDD3V Power Total Power 1.8 1.6 20X Mode 10X Mode 0.15 IOVDD Power (W) Total Power (W) 1.4 1.2 1 0.8 0.12 0.09 0.06 0.6 0.4 0.03 0.2 0 0 50 100 150 200 Sampling Speed (MSPS) 250 Submit Documentation Feedback 0 50 100 150 Sampling Speed (MSPS) G065 Figure 70. TOTAL POWER vs SAMPLING FREQUENCY 30 0 200 250 G066 Figure 71. IOVDD POWER vs SAMPLING FREQUENCY Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: CONTOUR Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted. Spurious-Free Dynamic Range (SFDR): General 240 fS - Sampling Frequency - MSPS 220 75 80 85 95 70 90 200 180 160 80 85 68 75 70 65 90 95 140 90 120 95 90 100 80 85 80 150 100 50 200 250 75 70 300 61 400 350 fIN - Input Frequency - MHz 65 70 80 75 85 90 95 SFDR - dBc Figure 72. 0-dB GAIN (SFDR) 95 240 fS - Sampling Frequency - MSPS 220 95 90 85 75 80 70 95 200 95 180 95 90 160 140 85 75 80 70 95 120 95 100 95 80 200 100 90 85 75 70 80 300 400 500 600 85 90 95 fIN - Input Frequency - MHz 70 75 80 SFDR - dBc Figure 73. 6-dB GAIN (SFDR) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 31 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted. Signal-to-Noise Ratio (SNR): ADS42JB69 240 220 fS - Sampling Frequency - MSPS 73.2 73.6 72.8 72.4 72 71.5 74 200 180 73.2 73.6 160 72.8 72 72.4 71.5 71 140 74 120 100 73.6 73.2 72.4 72.8 72 71.5 80 50 70.5 71 74 150 100 250 200 300 350 400 73 73.5 74 fIN - Input Frequency - MHz 70.5 71 71.5 72 72.5 SNR - dBFS Figure 74. 0-dB GAIN (SNR, ADS42JB69) 240 68.1 220 fS - Sampling Frequency - MSPS 67.5 67.2 67.5 67.2 66.9 66.4 67.8 200 68.1 180 67.8 160 140 66.4 66.9 68.1 120 67.8 100 80 68.1 68.4 50 100 150 67.2 67.5 200 250 350 300 400 65.9 66.4 66.9 450 550 500 600 fIN - Input Frequency - MHz 65.5 66 66.5 67 67.5 68 SNR - dBFS Figure 75. 6-dB GAIN (SNR, ADS42JB69) 32 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 TYPICAL CHARACTERISTICS: CONTOUR (continued) Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted. Signal-to-Noise Ratio (SNR): ADS42JB49 240 72.6 73 fS - Sampling Frequency - MSPS 220 72.2 71.3 71.8 73.4 200 180 70.8 160 140 72.6 73 72.2 71.3 71.8 73.4 120 70.8 100 73 71.3 71.8 72.2 72.6 70.3 73.4 80 71 150 100 50 200 250 300 400 350 fIN - Input Frequency - MHz 70.5 70 71 71.5 72 72.5 73 SNR - dBFS Figure 76. 0-dB GAIN (SNR, ADS42JB49) 240 67.3 67.6 67.9 67 66.7 66.4 fS - Sampling Frequency - MSPS 220 200 67.9 180 67.3 67.6 160 67 66.7 66.4 67.9 140 120 67.9 100 67.6 68.2 80 200 100 67 67.3 300 66.7 65.9 66.4 400 500 600 fIN - Input Frequency - MHz 65.5 66 66.5 67 67.5 68 SNR - dBFS Figure 77. 6-dB GAIN (SNR, ADS42JB49) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 33 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com DEVICE CONFIGURATION The ADS42JB49 and ADS42JB69 can be configured using a serial programming interface, as described in the Serial Interface section. In addition, the device has four dedicated parallel pins (PDN_GBL, STBY, CTRL1, and CTRL2) for controlling the power-down modes. SERIAL INTERFACE The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial data are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 16th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The interface functions with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with non-50% SCLK duty cycle. Register Initialization After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of widths greater than 10 ns), as shown in Figure 78. Later during operation, if required serial interface registers can be cleared by: 1. Either through a hardware reset or 2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 08h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. Power Supply AVDD, DRVDD t1 RESET t3 t2 SEN NOTE: After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin. Figure 78. Reset Timing Diagram Table 3. Reset Timing PARAMETER (1) CONDITIONS MIN t1 Power-on delay Delay from AVDD and DRVDD power-up to active RESET pulse t2 Reset pulse width Active RESET signal pulse width t3 Register write delay Delay from RESET disable to SEN active (1) 34 TYP MAX 1 UNIT ms 10 ns 1 100 µs ns Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless otherwise noted. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 Serial Register Write The internal device register can be programmed following these steps: 1. Drive the SEN pin low. 2. Set the R/W bit to ‘0’ (bit A7 of the 8-bit address). 3. Set bit A6 in the address field to ‘0’. 4. Initiate a serial interface cycle specifying the address of the register (A5 to A0) whose content must be written (as shown in Figure 79 and Table 4). 5. Write the 8-bit data that is latched on the SCLK rising edge. Register Address <5:0> SDATA R/W 0 A5 A4 A3 A2 A1 Register Data <7:0> A0 D7 D6 D5 D4 D3 =0 D2 D1 D0 tDH tSCLK tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 79. Serial Register Write Timing Diagram Table 4. Serial Interface Timing (1) PARAMETER MIN MAX UNIT 20 MHz SCLK frequency (equal to 1 / tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDIO setup time 25 ns tDH SDIO hold time 25 ns (1) > dc TYP fSCLK Typical values are at +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD3V = 3.3 V, and AVDD = DRVDD = IOVDD = 1.8 V, unless otherwise noted. Serial Register Readout The device includes a mode where the contents of the internal registers can be read back. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. 1. Set bit A7 (MSB) of 8 bit address to '1'. 2. Write the address of register on bits A5 through A0 whose contents must be read. See Figure 80 3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 45). 4. The external controller can latch the contents at the SCLK rising edge. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 35 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com When serial registers are enabled for writing (bit A7 of 8-bit address bus is 0), the SDOUT pin is in a highimpedance mode. If serial readout is not used, the SDOUT pin must float. Figure 80 shows a timing diagram of this readout mode. SDOUT comes out at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 81. Register Address <5:0> SDATA R/W 0 A5 A4 A3 A2 A1 Register Data: don’t care A0 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 =1 Register Read Data <7:0> SDOUT D7 D6 D5 D4 D3 D2 SCLK SEN Figure 80. Serial Register Readout Timing Diagram SCLK tSD_DELAY SDOUT Figure 81. SDOUT Timing Diagram 36 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 PIN CONTROLS The device power-down functions can be controlled either through the parallel control pins (STBY, PDN_GBL, CTRL1, and CTRL2) or through an SPI register setting. STBY places the device in a standby power-down mode. PDN_GBL places the device in global power-down mode. Table 5. CTRL1, CTRL2 Pin Functions CTRL1 CTRL2 DESCRIPTION Low Low Normal operation High Low Channel A powered down Low High Channel B powered down High High Global power-down Table 6. PDN_GBL Pin Function PDN_GBL DESCRIPTION Low Normal operation High Global power-down. Wake-up from this mode is slow. Table 7. STBY Pin Function STBY DESCRIPTION Low Normal operation High ADCs are powered down while the input clock buffer and output CML buffers are alive. Wake-up from this mode is fast. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 37 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com SUMMARY OF SERIAL INTERFACE REGISTERS REGISTER ADDRESS REGISTER DATA A[7:0] (Hex) D7 D6 D5 D4 D3 D2 06 0 0 0 0 0 0 07 0 0 0 0 0 08 PDN CHA PDN CHB STDBY DATA FORMAT Always write 1 D0 CLK DIV SYSREF DELAY 0 0 RESET 0B CHA GAIN CHA GAIN EN 0 0 0C CHBGAIN CHB GAIN EN 0 0 0D HIGH FREQ 1 0 0 HIGH FREQ 1 0 0 0 FAST OVR EN 0E HIGH FREQ 2 0 0 HIGH FREQ 2 0 0 0 0 0F CHA TEST PATTERNS CHB TEST PATTERNS 10 CUSTOM PATTERN (15:8) 11 CUSTOM PATTERN (15:8) 12 CUSTOM PATTERN (15:8) 13 CUSTOM PATTERN (15:8) 1F Always write 0 26 FAST OVR THRESHOLD SERDES TEST PATTERN IDLE SYNC TESTMODE EN FLIP ADC DATA LAN ALIGN FRAME ALIGN TX LINK CONFIG DATA0 27 0 0 0 0 0 0 CTRLK CTRLF 2B SCRAMBLE EN 0 0 0 0 0 0 0 2C 0 0 0 0 0 0 0 OCTETS PER FRAME 2D 0 0 0 0 0 30 36 37 38 38 D1 SUBCLASS SYNC REQ LMFC RESET MASK 0 LINK LAYER TESTMODE FORCE LMFC COUNT Submit Documentation Feedback FRAMES PER MULTIFRAME 0 0 LINK LAYER RPAT 0 0 OUTPUT CURRENT SEL 0 PULSE DET MODES LMFC COUNT INIT RELEASE ILANE SEQ Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 DESCRIPTION OF SERIAL INTERFACE REGISTERS REGISTER ADDRESS A[7:0] (Hex) 6 REGISTER DATA D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 D0 D2 0 D1 D0 SYSREF DELAY CLK DIV Default: 00h D[1:0] CLK DIV 00 Divide-by-1 (clock divider bypassed) 01 Divide-by-2 10 Divide-by-1 11 Divide-by-4 REGISTER ADDRESS A[7:0] (Hex) 7 Internal clock divider for input sample clock REGISTER DATA D7 0 D6 0 D5 0 D4 0 D3 0 Default: 00h D[2:0] SYSREF DELAY 000 0-ps delay 001 60-ps delay 010 120-ps delay 011 180-ps delay 100 240-ps delay 101 300-ps delay 110 360-ps delay 111 420-ps delay Controls the delay of the SYSREF input with respect to the input clock. Typical values for the expected delay of different settings are: Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 39 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com REGISTER ADDRESS A[7:0] (Hex) D7 D6 D5 8 PDN CHA PDN CHB STDBY REGISTER DATA D4 DATA FORMAT D3 Always write 1 D2 D1 D0 0 0 RESET Default: 00h D7 PDN CHA 0 Normal operation Power-down channel A 1 Channel A power down D6 PDN CHB 0 Normal operation 1 Channel B power down D5 STBY 0 Normal operation 1 Both ADCs are powered down (input clock buffer and CML output buffers are alive) D4 DATA FORMAT 0 Twos complement 1 Offset binary D3 Always write 1 Power-down channel B Dual ADC is placed into standby mode Digital output data format Default value of this bit is 0. It must always be set to 1 D0 RESET Software reset applied This bit resets all internal registers to the default values and self-clears to ‘0’. 40 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com REGISTER ADDRESS A[7:0] (Hex) B Default: 00h D[7:3] CHA GAIN SLAS900C – OCTOBER 2012 – REVISED JULY 2013 REGISTER DATA D7 D6 D5 CHA GAIN D4 D3 D2 CHA GAIN EN D1 0 D0 0 Digital gain for channel A (must set the CHA GAIN EN bit first, bit D2) Table 8. Digital Gain for Channel A DIGITAL GAIN FULL-SCALE INPUT VOLTAGE REGISTER VALUE DIGITAL GAIN FULL-SCALE INPUT VOLTAGE 00000 0 dB 2.0 VPP 01010 1.5 dB 1.7 VPP 00001 Do not use — 01011 2 dB 1.6 VPP 00010 Do not use — 01100 2.5 dB 1.5 VPP 00011 –2.0 dB 2.5 VPP 01101 3 dB 1.4 VPP 00100 –1.5 dB 2.4 VPP 01110 3.5 dB 1.3 VPP 00101 –1.0 dB 2.2 VPP 01111 4 dB 1.25 VPP 00110 –0.5 dB 2.1 VPP 10000 4.5 dB 1.2 VPP 00111 0 dB 2.0 VPP 10001 5 dB 1.1 VPP 01000 0.5 dB 1.9 VPP 10010 5.5 dB 1.05 VPP 01001 1 dB 1.8 VPP 10011 6 dB 1.0 VPP REGISTER VALUE D2 0 1 CHA GAIN EN Digital gain enable bit for channel A Digital gain disabled Digital gain enabled REGISTER ADDRESS A[7:0] (Hex) REGISTER DATA D7 D6 D5 C D4 D3 CHB GAIN Default: 00h D[7:3] CHB GAIN D2 CHB GAIN EN D1 D0 0 0 Digital gain for channel B (must set the CHA GAIN EN bit first, bit D2) Table 9. Digital Gain for Channel B REGISTER VALUE DIGITAL GAIN FULL-SCALE INPUT VOLTAGE REGISTER VALUE DIGITAL GAIN FULL-SCALE INPUT VOLTAGE 00000 0 dB 2.0 VPP 01010 1.5 dB 1.7 VPP 00001 Do not use — 01011 2 dB 1.6 VPP 00010 Do not use — 01100 2.5 dB 1.5 VPP 00011 –2.0 dB 2.5 VPP 01101 3 dB 1.4 VPP 00100 –1.5 dB 2.4 VPP 01110 3.5 dB 1.3 VPP 00101 –1.0 dB 2.2 VPP 01111 4 dB 1.25 VPP 00110 –0.5 dB 2.1 VPP 10000 4.5 dB 1.2 VPP 00111 0 dB 2.0 VPP 10001 5 dB 1.1 VPP 01000 0.5 dB 1.9 VPP 10010 5.5 dB 1.05 VPP 01001 1 dB 1.8 VPP 10011 6 dB 1.0 VPP D2 0 1 CHB GAIN EN Digital gain disabled Digital gain enabled Digital gain enable bit for channel B Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 41 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 REGISTER ADDRESS A[7:0] (Hex) D D7, D4 00 11 D0 0 1 E D7 HIGH FREQ 1 D6 D5 0 0 D4 HIGH FREQ 1 D3 D2 D1 D0 0 0 0 FAST OVR EN REGISTER DATA D7 HIGH FREQ 2 D6 D5 0 0 D4 HIGH FREQ 2 D3 D2 D1 D0 0 0 0 0 HIGH FREQ 2 High frequency mode 2 Default Use for input frequencies > 250 MHz along with HIGH FREQ 1 REGISTER ADDRESS A[7:0] (Hex) F 42 REGISTER DATA HIGH FREQ 1 High frequency mode 1 Default Use for input frequencies > 250 MHz along with HIGH FREQ 2 FAST OVR EN Selects if normal or fast OVR signal is presented on OVRA, OVRB pins Normal OVR on OVRA, OVRB pins Fast OVR on OVRA, OVRB pins REGISTER ADDRESS A[7:0] (Hex) D7, D4 00 11 www.ti.com REGISTER DATA D7 D6 D5 CHA TEST PATTERNS Submit Documentation Feedback D4 D3 D2 D1 CHB TEST PATTERNS D0 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 Default: 00h D[7:4] CHA TEST PATTERNS Channel A test pattern programmability 16-bit test pattern data is selected as input to JESD block (in ADS42JB49, last two LSBs of 16-bit data are replaced by 00) 0000 Normal operation 0001 All '0's 0010 All '1's 0011 Toggle pattern: In ADS42JB69, data is an alternating sequence of 1010101010101010 and 0101010101010101. In ADS42JB49, data alternates between 10101010101010 and 01010101010101. 0100 Digital ramp: In ADS42JB69, data increments by 1 LSB every clock cycle from code 0 to 65535. In ADS42JB49 data increments by 1 LSB every 4th clock cycle from code 0 to 16383. 0101 Do not use 0110 Single pattern: In ADS42JB69, data is same as programmed by registers bits CUSTOM PATTERN 1 [15:0]. In ADS42JB49, data is same as programmed by register bits CUSTOM PATTERN 1 [15:2]. 0111 Double pattern: In ADS42JB69, data alternates between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN 2[15:0] .In ADS42JB49 data alternates between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2]. 1000 Deskew pattern: In ADS42JB69, data is AAAAh. In ADS42JB49, data is 3AAAh. 1001 Do not use 1010 PRBS pattern: Data is a sequence of pseudo random numbers. 1011 8-Point sine wave: In ADS42JB69, data is a repetitive sequence of following 8 numbers forming a sine-wave in 2s complement format: 1, 9598, 32768, 55938, 65535, 55938, 32768, 9598. In ADS42JB49, data is a repetitive sequence of following 8 numbers forming a sine-wave in 2s complement format: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399. D3-D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 CHB TEST PATTERNS Channel B test pattern programmability 16-bit test pattern data is selected as input to JESD block (in ADS42JB49, last two LSBs of 16-bit data are replaced by 00) Normal operation All '0's All '1's Toggle pattern: In ADS42JB69, data is an alternating sequence of 1010101010101010 and 0101010101010101. In ADS42JB49, data alternates between 10101010101010 and 01010101010101. Digital ramp: In ADS42JB69, data increments by 1 LSB every clock cycle from code 0 to 65535. In ADS42JB49 data increments by 1 LSB every 4th clock cycle from code 0 to 16383. Do not use Single pattern: In ADS42JB69, data is same as programmed by registers bits CUSTOM PATTERN 1 [15:0]. In ADS42JB49, data is same as programmed by register bits CUSTOM PATTERN 1 [15:2]. Double pattern: In ADS42JB69, data alternates between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN 2[15:0] .In ADS42JB49 data alternates between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2]. Deskew pattern: In ADS42JB69, data is AAAAh. In ADS42JB49, data is 3AAAh. Do not use PRBS pattern: Data is a sequence of pseudo random numbers. 8-Point sine wave: In ADS42JB69, data is a repetitive sequence of following 8 numbers forming a sine-wave in 2s complement format: 1, 9598, 32768, 55938, 65535, 55938, 32768, 9598. In ADS42JB49, data is a repetitive sequence of following 8 numbers forming a sine-wave in 2s complement format: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399. REGISTER ADDRESS A[7:0] (Hex) 10 REGISTER DATA D7 D6 D5 D4 D3 CUSTOM PATTERN 1 (15:8) D2 D1 D0 Default: 00h D[7:0] CUSTOM PATTERN 1 (15:8) Sets custom pattern 1 (15:8) using these bits for both channels Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 43 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 REGISTER ADDRESS A[7:0] (Hex) 11 REGISTER DATA D7 D6 Default: 00h D[7:0] CUSTOM PATTERN 1 (7:0) REGISTER ADDRESS A[7:0] (Hex) 12 www.ti.com D5 D4 D3 CUSTOM PATTERN 1 (7:0) D2 D1 D0 D1 D0 D1 D0 D1 D0 Sets custom pattern 1 (7:0) using these bits for both channels REGISTER DATA D7 D6 D5 D4 D3 CUSTOM PATTERN 2 (15:8) D2 Default: 00h D[7:0] CUSTOM PATTERN 2 (15:8) Sets custom pattern 2 (15:8) using these bits for both channels REGISTER ADDRESS A[7:0] (Hex) 13 REGISTER DATA D7 D6 Default: 00h D[7:0] CUSTOM PATTERN 2 (7:0) REGISTER ADDRESS A[7:0] (Hex) 1F D5 D4 D3 CUSTOM PATTERN 2 (7:0) D2 Sets custom pattern 2 (7:0) using these bits for both channels REGISTER DATA D7 Always write 0 D6 D5 D4 D3 D2 FAST OVR THRESHOLD Default: FFh D7 Always write 0 Default value of this bit is '1'. Always write this bit to '0' when fast OVR thresholds are programmed. D[6:0] FAST OVR THRESHOLD The device has a fast OVR mode that indicates an overload condition at the ADC input. The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the FAST OVR THRESHOLD bits. FAST OVR is triggered nine output clock cycles after the overload condition occurs. The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESHOLD bits] / 127). See section OVERRANGE INDICATION for details. 44 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com REGISTER ADDRESS A[7:0] (Hex) 26 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 REGISTER DATA D7 D6 SERDES TEST PATTERN D5 IDLE SYNC D4 TESTMODE EN D3 FLIP ADC DATA D2 LANE ALIGN D1 FRANE ALIGN D0 TX LINK CONFIG DATA Default: 00h D[7:6] SERDES TEST PATTERN Sets test patterns in the transport layer of the JESD204B interface 00 Normal operation 01 Outputs clock pattern: Output is 10101010 pattern 10 Encoded pattern: Output is 1111111100000000 11 PRBS sequence: Output is 215 – 1 D5 0 1 IDLE SYNC Sets output pattern when SYNC~ is asserted Sync code is k28.5 (0xBCBC) Sync code is 0xBC50 D4 TESTMODE EN 0 1 Test mode disabled Test mode enabled D3 0 1 FLIP ADC DATA Normal operation Output data order is reversed: D2 LANE ALIGN 0 1 Lane Alignment characters are not inserted. Inserts lane alignment characters D1 FRAME ALIGN 0 Frame Alignment characters are not inserted. Inserts frame alignment characters 1 D0 0 1 MSB – LSB Inserts lane alignment character (K28.3) for the receiver to align to lane boundary per section 5.3.3.5 of the JESD204B specification. TX LINK CONFIG DATA ILA Enabled ILA disabled REGISTER ADDRESS A[7:0] (Hex) 27 Generates long transport layer test pattern mode according to 5.1.63 clause of JESD204B specification Inserts frame alignment character (K28.7) for the receiver to align to frame boundary per section 5.3.3.4 of the JESD204B specification. Disables sending initial link alignment (ILA) sequence when SYNC~ is de-asserted, '0' REGISTER DATA D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 CTRL K D0 CTRL F Default: 00h D1 CTRL K Enables bit for number of frames per multiframe 0 Default 1 Frames per multiframe can be set in register 2Dh D0 0 1 CTRL F Enables bit for number of octets per frame Default Octets per frame can be specified in register 2Ch Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 45 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 REGISTER ADDRESS A[7:0] (Hex) 2B www.ti.com REGISTER DATA D7 SCRAMBLE EN D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Default: 00h D7 SCRAMBLE EN Scramble enable bit in the JESD204B interface 0 Scrambling disabled 1 Scrambling enabled REGISTER ADDRESS A[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 2C 0 0 0 0 0 0 0 REGISTER DATA D0 OCTETS PER FRAME Default: 00h D[7:0] OCTETS PER FRAME Sets number of octets per frame (F) 0 10x mode using two lanes per ADC 1 20x mode using one lane per ADC REGISTER ADDRESS A[7:0] (Hex) 2D REGISTER DATA D7 0 D6 0 D5 0 D4 D3 D2 D1 FRAMES PER MULTIFRAME D0 Default: 00h D[4:0] FRAMES PER MULTIFRAME Sets number of frames per multiframe After reset, the default settings for frames per multiframe are: 10x K = 16 20x K=8 For each mode, K should not be set to a lower value. REGISTER ADDRESS A[7:0] (Hex) 30 Default: 40h D[7:5] SUBCLASS 000 001 010 46 Subclass 0 Subclass 1 Subclass 2 REGISTER DATA D7 D6 SUBCLASS D5 D4 0 D3 0 D2 0 D1 0 D0 0 Sets JESD204B subclass. Note that the default value of these bits after reset is '010', which makes subclass 2 the default class. Backward compatibility with JESD204A Deterministic latency using SYSREF signal Deterministic latency using SYNC~ detection (default subclass after reset) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 REGISTER ADDRESS A[7:0] (Hex) 36 REGISTER DATA D7 SYNC REQ D6 LMFC RESET MASK Default: 00h D7 SYNC REQ 0 Normal operation 1 Generates sync request D6 0 1 D3-D0 0000 0001 0010 0011 0100 0101 0110 0111 D5 0 D4 0 D2 D1 OUTPUT CURRENT SEL D0 Generates synchronization request LMFC RESET MASK LMFC reset is not masked Ignores LMFC reset Mask LMFC reset coming to digital OUTPUT CURRENT SEL 16 mA 15 mA 14 mA 13 mA 20 mA 19 mA 18 mA 17 mA Changes JESD output buffer current REGISTER ADDRESS A[7:0] (Hex) 37 D3 1000 1001 1010 1011 1100 1101 1110 1111 8 mA 7 mA 6 mA 5 mA 12 mA 11 mA 10 mA 9 mA REGISTER DATA D7 D6 D5 LINK LAYER TESTMODE D4 LINK LAYER RPAT D3 0 D2 D1 D0 PULSE DET MODES Default: 00h D[7:5] LINK LAYER TESTMODE Generates pattern according to clause 5.3.3.8.2 of the JESD204B document 000 Normal ADC data 001 D21.5 (high-frequency jitter pattern) 010 K28.5 (mixed-frequency jitter pattern) 011 Repeats initial lane alignment (generates K28.5 character and repeats lane alignment sequences continuously) 100 12-octet RPAT jitter pattern D4 LINK LAYER RPAT 0 1 Normal operation Changes disparity D[2:0] PULSE DET MODES Changes the running disparity in modified RPAT pattern test mode (only when link layer test mode = 100) Selects different detection modes for SYSREF (subclass 1) and SYNC (subclass 2) D2 D1 D0 0 Don’t care 0 FUNCTIONALITY Allows all pulses to reset input clock dividers 1 Don’t care 0 Do not allow reset of analog clock dividers Don’t care 0 -> 1 transition 1 Allows one pulse immediately after the 0 -> 1 transition to reset the divider Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 47 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 REGISTER ADDRESS A[7:0] (Hex) 38 www.ti.com REGISTER DATA D7 FORCE LMFC COUNT D6 D5 D4 D3 LMFC COUNT INIT D2 D1 D0 RELEASE ILANE SEQ Default: 00h D7 FORCE LMFC COUNT Forces LMFC count 0 Normal operation 1 Enables using a different starting value for the LMFC counter D[6:2] LMFC COUNT INIT SYSREF receives the digital block and resets the LMFC count to '0'. K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, the Rx can be synchronized early because the Rx gets the LANE ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled. D[1:0] RELEASE ILANE SEQ Delays the generation of lane alignment sequence by 0, 1, 2, or 3 multiframes after the code group synchronization. 00 01 10 11 0 1 2 3 48 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 APPLICATION INFORMATION THEORY OF OPERATION The ADS42JB69 and ADS42JB49 is a family of high linearity, buffered analog input, dual-channel ADCs with maximum sampling rates up to 250 MSPS employing JESD204B interface. The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 23 clock cycles. The output is available in CML logic levels following JESD204B standard. ANALOG INPUT The analog input pins have analog buffers (running from the AVDD3V supply) that internally drive the differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external driving source (10-kΩ dc resistance and 4-pF input capacitance). The buffer helps isolate the external driving source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier than when compared to an ADC without the buffer. The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-V PP differential input swing. When programmed for 2.5-V PP full-scale, each input pin must swing symmetrically between VCM + 0.625 V and VCM – 0.625 V. The input sampling circuit has a high 3-dB bandwidth that extends up to 900 MHz (measured with a 50-Ω source driving a 50-Ω termination between INP and INM). The dynamic offset of the first-stage sub-ADC limits the maximum analog input frequency to approximately 250 MHz (with a 2.5-VPP full-scale amplitude) and to approximately 400 MHz (with a 2-VPP full-scale amplitude). This 3-dB bandwidth is different than the analog bandwidth of 900 MHz, which is only an indicator of signal amplitude versus frequency. Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics. Figure 82, Figure 83, and Figure 84 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz. INxP(1) ZIN(2) RIN CIN INxM (1) X = A or B. (2) ZIN = RIN || (1 / jωCIN). Figure 82. ADC Equivalent Input Impedance Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 49 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com 10 5 Differential Capacitance, Cin (pF) Differential Resistance, Rin (kΩ) 4 1 3 2 1 0.1 0.05 0 200 400 600 800 1000 Frequency (MHz) Submit Documentation Feedback 0 200 400 600 Frequency (MHz) G064 Figure 83. ADC Analog Input Resistance (RIN) Across Frequency 50 0 800 1000 G064 Figure 84. ADC Analog Input Capacitance (CIN) Across Frequency Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 Driving Circuit An example driving circuit configuration is shown in Figure 85. To optimize even-harmonic performance at high input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended, as shown in Figure 85. Note that the drive circuit is terminated by 50 Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage. An additional R-C-R (39 Ω - 6.8 pF - 39 Ω) circuit placed near device pins helps further improve HD3. 0.1µF 0.1µF 5Q INP RINT 39 25 0.1µF 6.8 pF 25 RINT 39 INM 1:1 5 0.1µF 1:1 Device Figure 85. Drive Circuit for Input Frequencies upto 250MHz The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 85. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω source impedance). For high input frequencies (>250MHz), the R-C-R circuit can be removed as indicated in Figure 86. 0.1µF 0.1µF 5Q INP RINT 0.1µF 25 25 RINT INM 1:1 1:1 0.1µF 5 Device Figure 86. Drive Circuit for Input Frequencies > 250MHz Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 51 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com CLOCK INPUT The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADS42JB69 and ADS42JB49 can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 87, Figure 88, and Figure 89. See Figure 90 for details regarding the internal clock buffer. 0.1 mF 0.1 mF Zo CLKP Differential Sine-Wave Clock Input CLKP RT Typical LVDS Clock Input 0.1 mF 100 W CLKM Device 0.1 mF Zo NOTE: RT = termination resistor, if necessary. CLKM Figure 87. Differential Sine-Wave Clock Driving Circuit Zo Device Figure 88. LVDS Clock Driving Circuit 0.1 mF CLKP 150 W Typical LVPECL Clock Input 100 W Zo 0.1 mF CLKM Device 150 W Figure 89. LVPECL Clock Driving Circuit Clock Buffer LPKG 2 nH 20 W CLKP CBOND 1 pF 5 kW RESR 100 W LPKG 2 nH CEQ CEQ 1.4 V 20 W 5 kW CLKM CBOND 1 pF RESR 100 W NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 90. Internal Clock Buffer 52 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 91. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. CMOS Clock Input 0.1 mF CLKP 0.1 mF CLKM Device Figure 91. Single-Ended Clock Driving Circuit DIGITAL GAIN The device includes gain settings that can be used to obtain improved SFDR performance (compared to no gain). Gain is programmable from –2 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally. Table 10 shows how full-scale input voltage changes when digital gain are programmed in 1-dB steps. Refer to Table 8 to set digital gain using a serial interface register. SFDR improvement is achieved at the expense of SNR; for 1 dB increase in digital gain, SNR degrades approximately between 0.5 dB and 1 dB. Therefore, gain can be used as a trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB with a 2.0-VPP full-scale voltage. Table 10. Full-Scale Range Across Gains (1) DIGITAL GAIN FULL-SCALE INPUT VOLTAGE –2 dB 2.5 VPP (1) –1 dB 2.2 VPP 0 dB (default) 2.0 VPP 1 dB 1.8 VPP 2 dB 1.6 VPP 3 dB 1.4 VPP 4 dB 1.25 VPP 5 dB 1.1 VPP 6 dB 1.0 VPP Shaded cells indicate performance settings used in the Electrical Characteristics and Typical Characteristics. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 53 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com OVERRANGE INDICATION The device provides two different overrange indications. Normal OVR (default) is triggered if the final 16-bit data output exceeds the maximum code value. Fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after only nine clock cycles, thus enabling a quicker reaction to an overrange event. By default, the normal overrange indication is output on the OVRA and OVRB pins. Using the register bit FAST OVR EN, the fast OVR indication can be presented on the overrange pins instead. The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the FAST OVR THRESHOLD bits. FAST OVR is triggered nine output clock cycles after the overload condition occurs. The threshold voltage amplitude at which fast OVR is triggered is: 1 × [the decimal value of the FAST OVR THRESH bits] / 127 When digital is programmed (for gain values > 0-dB ), 10-Gain/20 x [the decimal value of the FAST OVR THRESH bits] / 127 the threshold voltage amplitude is: SNR AND CLOCK JITTER The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 1. Quantization noise is typically not noticeable in pipeline converters and is 96 dBFS for a 16-bit ADC. Thermal noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies. SNRQuantization _ Noise æ SNR ADC [dBc] = -20 ´ log çç 10 20 è 2 2 2 ö æ SNRThermalNoise ö æ SNRJitter ö + 10 + 10 ÷÷ ç ÷ ç ÷ 20 20 ø è ø ø è SNR limitation is a result of sample clock jitter and can be calculated by Equation 2: SNRJitter [dBc] = -20 ´ log(2p ´ fIN ´ tJitter) (1) (2) The total clock jitter (TJitter) has three components: the internal aperture jitter (85 fS for the device) is set by the noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. TJitter can be calculated by Equation 3: TJitter = (TJitter,Ext.Clock_Input)2 + (TAperture_ADC)2 (3) External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input while a faster clock slew rate improves ADC aperture jitter. The device has a 74.1-dBFS thermal noise and an 85-fS internal aperture jitter. The SNR value depends on the amount of external jitter for different input frequencies, as shown in Figure 92. 76 SNR (dBFS) 74 72 35 fs 70 50 fs 68 100 fs 150 fs 66 200 fs 64 10 100 1000 Fin (MHz) Figure 92. SNR versus Input Frequency and External Clock Jitter 54 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 INPUT CLOCK DIVIDER The device is equipped with an internal divider on the clock input. This divider allows operation with a faster input clock, simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1) for operation with a 250-MHz clock. The divide-by-2 option supports a maximum 500-MHz input clock and the divide-by-4 option supports a maximum 1-GHz input clock frequency. JESD204B INTERFACE The JESD interface of ADS42JB49 and ADS42JB69, as shown in Figure 93 , supports device subclasses 0, 1, and 2 with a maximum output data rate (per lane) of 3.125 Gbps. An external SYSREF (subclass 1) or SYNC~ (subclass 2) signal is used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge. This alignment allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty. SYSREF SYNC~ INA JESD 204B JESD204B D0, D1 INB JESD 204B JESD204B D0, D1 Sample Clock Figure 93. JESD204B Interface Depending on the ADC sampling rate, the JESD204B output interface can be operated with either one or two lanes per ADC. The JESD204B interface can be configured using serial registers. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 55 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com The JESD204B transmitter block (Figure 94) consists of the transport layer, the data scrambler, and the link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format and manages if the ADC output data or test patterns are transmittied. The link layer performs the 8b and 10b data encoding as well as the synchronization and initial lane alignment using the SYNC~ input signal. Optionally, data from the transport layer can be scrambled. JESD204B Block Transport Layer Frame Data Mapping Test Patterns Link Layer Scrambler 1+x14+x15 8b,10b encoding Comma characters Initial lane alignment D0 D1 SYNC~ Figure 94. JESD204B Block JESD204B Initial Lane Alignment (ILA) When receiving device asserts the SYNC~ signal ( i.e a logic low signal is applied on SYNC~P - SYNC~M), the device begins transmitting comma (K28.5) characters to establish code group synchronization (CGS). When synchronization is complete, the receiving device de-asserts the SYNC~ signal and the ADS42JB49 and ADS42JB69 begin the initial lane alignment (ILA) sequence with the next local multiframe clock boundary. The device transmits four multiframes, each containing K frames (where K is SPI programmable). Each multiframe contains the frame start and end symbols; the second multiframe also contains the JESD204 link configuration data. JESD204B Test Patterns There are three different test patterns available in the transport layer of the JESD204B interface. The device supports a clock output, an encoded, and a PRBS (215 – 1) pattern. These patterns can be enabled by serial register write in address 26h, bits D[7:6]. 56 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 JESD204B Frame Assembly The JESD204B standard defines the following parameters: • L is the number of lanes per Lane. • M is the number of converters per device. • F is the number of octets per frame clock period. • S is the number of samples per frame. Table 11 lists the available JESD204B formats and valid device ranges. Ranges are limited by the maximum ADC sample frequency and the SERDES line rate. Table 11. JESD240B Ranges L M F S MAX ADC SAMPLING RATE (MSPS) MAX fSERDES (Gbps) 4 2 1 1 250 2.5 2 2 2 1 156.25 3.125 The detailed frame assembly in 10x and 20x modes for dual-channel operation is shown in Table 12. Note that unused lanes in 10x mode become 3-stated. Table 12. Frame Assembly for Dual-Channel Mode (1) LANE DA0 (1) LMF = 421 A0[15:8] A1[15:8] LMF = 222 A2[15:8] A0[15:8] A0[7:0] A1[15:8] A1[7:0] A2[15:8] A2[7:0] DA1 A0[7:0] A1[7:0] A2[7:0] — — — — — — DB0 B0[15:8] B1[15:8] B2[15:8] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B2[15:8] B2[7:0] DB1 B0[7:0] B1[7:0] B2[7:0] — — — — — — In ADS42JB49 two LSBs of 16-bit data are padded with 00. JESD LINK CONFIGURATION During the lane alignment sequence, the ADS42JB69 and ADS42JB49 transmit JESD204B configuration parameters in the second multi-frame of the ILA sequence. Configuration bits are mapped in octets, as per the JESD204B standard described in Figure 95 and Table 13. Figure 95. Initial Lane Alignment Sequence Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 57 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com Table 13. Mapping of Configuration Bits to Octets Octet No MSB D6 D5 D4 0 D3 D2 D1 LSB DID [7:0] 1 ADJCNT[3:0] ADJDI R[0] 2 X 3 SCR[0] BID[3:0] PHADJ[0] LID[4:0] L[4:0] 4 F[7:0] 5 K[4:0] 6 M[7:0] 7 CS[1:0] X N[4:0] 8 SUBCLASSV[2:0] N'[4:0] 9 JESDV[2:0] S[4:0] 10 HD[0] X X CF[4:0] 11 RES1[7:0] 12 RES2[7:0] 13 FCHK[7:0] Configuration for 2-Lane (20x) SERDES Mode Table 14 lists the values of the JESD204B configuration bits applicable for the 2-lane SERDES Mode. The default value of these bits after reset is also specified in the table. Table 14. Configuration for 2-Lane SERDES Mode 58 PARAMETER DESCRIPTION PARAMETER RANGE FIELD ENCODING DEFAULT VALUE AFTER RESET ADJCNT Number of adjustment resolution steps to adjust DAC LMFC. Applies to subclass 2 operation only. 0 ... 15 ADJCNT[3:0] Binary value 0 ADJDIR Direction to adjust DAC LMFC 0 – Advance 1 – Delay applies to subclass 2 operation only 0…1 ADJDIR[0] Binary value 0 BID Bank ID – extension to DID 0 ... 15 BID[3:0] Binary value 0 CF No. of control words per frame clock period per link 0 ... 32 CF[4:0] Binary value 0 CS No. of control bits per sample 0 ... 3 CS[1:0] Binary value 0 DID Device (= link) identification no. 0 ... 255 DID[7:0] Binary value 0 F No. of octets per frame 1 ... 256 F[7:0] Binary value minus 1 1 HD High-density format 0 ... 1 HD[0] Binary value 0 JESDV JESD204 version 000 – JESD204A 001 – JESD204B 0…7 JESDV[2:0] Binary value 1 K No. of frames per multi-frame 1 ... 32 K[4:0] Binary value minus 1 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 Table 14. Configuration for 2-Lane SERDES Mode (continued) PARAMETER DESCRIPTION PARAMETER RANGE FIELD ENCODING DEFAULT VALUE AFTER RESET L No. of lanes per converter device (link) 1 ... 32 L[4:0] Binary value minus 1 0 LID Lane identification no. (within link) 0 ... 31 LID[4:0] Binary value LID[0] = 0, LID[1] = 1 M No. of converters per device 1 ... 256 M[7:0] Binary value minus 1 1 N Converter resolution 1 ... 32 N[4:0] Binary value minus 1 15 N’ Total no. of bits per sample 1 ... 32 N'[4:0] Binary value minus 1 15 PHADJ Phase adjustment request to DAC subclass 2 only. 0 ... 1 PHADJ[0] Binary value 0 S No. of samples per converter per frame cycle 1 ... 32 S[4:0] Binary value minus 1 0 SCR Scrambling enabled 0 ... 1 SCR[0] Binary value 0 SUBCLASSV Device subclass version 000 – Subclass 0 001 – Subclass 1 010 – Subclass 2 0…7 SUBCLASSV[2:0] Binary value 2 RES1 Device subclass version 000 – Subclass 0 001 – Subclass 1 010 – Subclass 2 0 ... 255 RES1[7:0] Binary value 0 RES2 Reserved field 2 0 ... 255 RES2[7:0] Binary value 0 CHKSUM Checksum Σ (all above fields) mod 256 0 ... 255 FCHK[7:0] Binary value 44, 45 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 59 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com Configuration for 4-Lane (10x) SERDES Mode Table 15 lists the values of the JESD204 configuration bits applicable for the 4-lane SERDES Mode. The default value of these bits after reset is also specified in the table. Table 15. Configuration for 4-Lane SERDES Mode 60 PARAMETER DESCRIPTION PARAMETER RANGE FIELD ENCODING DEFAULT VALUE AFTER RESET ADJCNT Number of adjustment resolution steps to adjust DAC LMFC. Applies to subclass 2 operation only. 0 ... 15 ADJCNT[3:0] Binary value 0 ADJDIR Direction to adjust DAC LMFC 0 – Advance 1 – Delay applies to subclass 2 operation only 0…1 ADJDIR[0] Binary value 0 BID Bank ID – extension to DID 0 ... 15 BID[3:0] Binary value 0 CF No. of control words per frame clock period per link 0 ... 32 CF[4:0] Binary value 0 CS No. of control bits per sample 0 ... 3 CS[1:0] Binary value 0 DID Device (= link) identification no. 0 ... 255 DID[7:0] Binary value 0 F No. of octets per frame 1 ... 256 F[7:0] Binary value minus 1 0 HD High-density format 0 ... 1 HD[0] Binary value 1 JESDV JESD204 version 000 – JESD204A 001 – JESD204B 0…7 JESDV[2:0] Binary value 1 K No. of frames per multi-frame 1 ... 32 K[4:0] Binary value minus 1 16 L No. of lanes per converter device (link) 1 ... 32 L[4:0] Binary value minus 1 3 LID Lane identification no (within link) 0 ... 31 LID[4:0] Binary value LID[0] = 0, LID[1] = 1, LID[2] = 2, LID[3] = 3 M No. of converters per device 1 ... 256 M[7:0] Binary value minus 1 1 N Converter resolution 1 ... 32 N[4:0] Binary value minus 1 15 N’ Total no. of bits per sample 1 ... 32 N'[4:0] Binary value minus 1 15 PHADJ Phase adjustment request to DAC subclass 2 only. 0 ... 1 PHADJ[0] Binary value 0 S No. of samples per converter per frame cycle 1 ... 32 S[4:0] Binary value minus 1 0 SCR Scrambling enabled 0 ... 1 SCR[0] Binary value 0 SUBCLASSV Device subclass version 000 – Subclass 0 001 – Subclass 1 010 – Subclass 2 0…7 SUBCLASSV[2:0] Binary value 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 Table 15. Configuration for 4-Lane SERDES Mode (continued) PARAMETER DESCRIPTION PARAMETER RANGE FIELD ENCODING DEFAULT VALUE AFTER RESET RES1 Device subclass version 000 – Subclass 0 001 – Subclass 1 010 – Subclass 2 0 ... 255 RES1[7:0] Binary value 0 RES2 Reserved field 2 0 ... 255 RES2[7:0] Binary value 0 CHKSUM Checksum Σ(all above fields)mod 256 0 ... 255 FCHK[7:0] Binary value 54, 55, 56, 57 CML Outputs The device JESD204B transmitter uses differential CML output drivers. The CML output current is programmable from 5 mA to 20 mA using register settings. The output driver includes an internal 50-Ω termination to IOVDD supply. External 50-Ω termination resistors connected to receiver common-mode voltage should be placed close to receiver pins. AC coupling can be used to avoid the common-mode mismatch between transmitter and receiver, as shown in Figure 96. Vterm Rt= ZO Transmission Line Zo Rt= ZO 0.1uF DA/B[0,1]P Receiver DA/B[0,1]M 0.1uF Figure 96. CML Output Connections Figure 97 and Figure 98 show the data eye measurements of the device JESD204B transmitter against the JESD204B transmitter mask at 2.5 GBPS (10x mode) and 3.125 GBPS (20x mode), respectively. 300 300 150 Voltage (mV) Voltage (mV) 150 0 0 -150 -150 -300 -300 -200 -300 -200 -100 0 100 200 -150 300 -100 -50 0 50 100 150 200 Time (ps) Time (ps) Figure 97. Eye Diagram: 2.5 Gbps Figure 98. Eye Diagram: 3.125 Gbps Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 61 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel). Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay. Clock Pulse Width and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate: The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL): The INL is the deviation of the ADC transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error: Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of reference inaccuracy (EGREF) and error as a result of the channel (EGCHAN). Both errors are specified independently as EGREF and EGCHAN. To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) x FSideal to (1 + 0.5 / 100) x FSideal. Offset Error: The offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts. Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. Temperature drift is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN. Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. SNR = 10Log10 PS PN (4) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range. Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. SINAD = 10Log10 PS PN + PD (5) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range. 62 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 ADS42JB49 ADS42JB69 www.ti.com SLAS900C – OCTOBER 2012 – REVISED JULY 2013 Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (6) Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (7) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR): The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. DC Power-Supply Rejection Ratio (DC PSRR): DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The dc PSRR is typically given in units of mV/V. AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC output code (referred to the input), then: DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (8) Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and negative overload. The deviation of the first few samples after the overload (from the expected values) is noted. Common-Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is the resulting change of the ADC output code (referred to the input), then: DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (9) Crosstalk (only for multichannel ADCs): Crosstalk is a measure of the internal coupling of a signal from an adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). Crosstalk is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. Crosstalk is typically expressed in dBc. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 Submit Documentation Feedback 63 ADS42JB49 ADS42JB69 SLAS900C – OCTOBER 2012 – REVISED JULY 2013 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (July 2013) to Revision C Page • Added Internal Dither in Features Section ............................................................................................................................ 1 • Changed From "The devices provide excellent" to "The devices employ internal dither algorithms to provide" ................. 1 • Changed 2-VPP Full-Scale INL maximum specification in ADS42JB69 Electrical Characteristics table .............................. 4 • Deleted 2.5-VPP Full-Scale INL maximum specification in ADS42JB69 Electrical Characteristics table .............................. 4 • Changed 2-VPP Full-Scale INL maximum specification in ADS42JB49 Electrical Characteristics table .............................. 5 • Deleted 2.5-VPP Full-Scale INL maximum specification in ADS42JB49 Electrical Characteristics table .............................. 5 • Changed EGREF specifications in General Electrical Characteristics table ........................................................................... 6 Changes from Revision A (November 2012) to Revision B • 64 Page Moved document status to Mixed Status .............................................................................................................................. 1 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42JB49 ADS42JB69 PACKAGE OPTION ADDENDUM www.ti.com 12-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) ADS42JB49IRGCR PREVIEW VQFN RGC 64 2000 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 AZ42JB49 ADS42JB49IRGCT PREVIEW VQFN RGC 64 250 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 AZ42JB49 ADS42JB69IRGC25 PREVIEW VQFN RGC 64 25 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 AZ42JB69 ADS42JB69IRGCR PREVIEW VQFN RGC 64 2000 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 AZ42JB69 ADS42JB69IRGCT PREVIEW VQFN RGC 64 250 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 85 AZ42JB69 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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