Dual 3 A, 20 V Synchronous Step-Down Regulator with Integrated High-Side MOSFET ADP2323 Data Sheet FEATURES GENERAL DESCRIPTION The ADP2323 is a full featured, dual output, step-down dc-todc regulator based on current-mode architecture. The ADP2323 integrates two high-side power MOSFETs and two low-side drivers for the external N-channel MOSFETs. The two pulse-width modulation (PWM) channels can be configured to deliver dual 3 A outputs or a parallel-to-single 6 A output. The regulator operates from input voltages of 4.5 V to 20 V, and the output voltage can be as low as 0.6 V. The switching frequency can be programmed between 250 kHz and 1.2 MHz, or synchronized to an external clock to minimize interference in multirail applications. The dual PWM channels run 180° out of phase, thereby reducing input current ripple as well as reducing the size of the input capacitor. The bidirectional synchronization pin can be programmed at a 60°, 90°, or 120° phase shift, providing the possibility for a stackable multiphase power solution. The ADP2323 can be set to operate in pulse-frequency modulation (PFM) mode at a light load for higher efficiency or in forced PWM for noise sensitive applications. External compensation and soft start provide design flexibility. Independent enable CC1 VIN RBOT1 CSS1 INTVCC MODE SCFG TRK2 TRK1 VDRV BST1 EN1 PVIN1 CIN1 CBST1 L1 VOUT1 SW1 M1 COUT1 DL1 ADP2323 CDRV PGND GND PGOOD2 PGOOD1 SYNC DL2 RT SW2 RC2 RBOT2 CC2 BST2 PVIN2 EN2 SS2 COMP2 ROSC COUT2 M2 CBST2 L2 VOUT2 VIN CSS2 CIN2 RTOP2 09357-001 CINT SS1 COMP1 FB1 RC1 Figure 1. inputs and power good outputs provide reliable power sequencing. To enhance system reliability, the device also includes undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), and thermal shutdown (TSD). The ADP2323 operates over the −40°C to +125°C junction temperature range and is available in a 32-lead LFCSP_WQ package. 100 95 90 85 80 75 70 65 VOUT = 5V VOUT = 3.3V 60 55 50 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT CURRENT (A) 09357-002 Communications infrastructure Networking and servers Industrial and instrumentation Healthcare and medical Intermediate power rail conversion DC-to-dc point of load applications RTOP1 FB2 APPLICATIONS TYPICAL APPLICATION CIRCUIT EFFICIENCY (%) Input voltage: 4.5 V to 20 V ±1% output accuracy Integrated 90 mΩ typical high-side MOSFET Flexible output configuration Dual output: 3 A/3 A Parallel single output: 6 A Programmable switching frequency: 250 kHz to 1.2 MHz External synchronization input with programmable phase shift, or internal clock output Selectable PWM or PFM mode operation Adjustable current limit for small inductor External compensation and soft start Startup into precharged output Supported by ADIsimPower™ design tool Figure 2. Efficiency vs. Output Current at VIN = 12 V, fSW = 600 kHz Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. ADP2323 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overvoltage Protection .............................................................. 17 Applications ....................................................................................... 1 Undervoltage Lockout ............................................................... 18 Typical Application Circuit ............................................................. 1 Thermal Shutdown .................................................................... 18 General Description ......................................................................... 1 Applications Information .............................................................. 19 Revision History ............................................................................... 2 ADIsimPower Design Tool ....................................................... 19 Functional Block Diagram .............................................................. 3 Input Capacitor Selection .......................................................... 19 Specifications..................................................................................... 4 Output Voltage Setting .............................................................. 19 Absolute Maximum Ratings ............................................................ 6 Voltage Conversion Limitations ............................................... 19 Thermal Resistance ...................................................................... 6 Current-Limit Setting ................................................................ 19 ESD Caution .................................................................................. 6 Inductor Selection ...................................................................... 20 Pin Configuration and Function Descriptions ............................. 7 Output Capacitor Selection....................................................... 20 Typical Performance Characteristics ............................................. 9 Low-Side Power Device Selection ............................................ 21 Theory of Operation ...................................................................... 15 Programming UVLO Input ...................................................... 21 Control Scheme .......................................................................... 15 Compensation Components Design ....................................... 21 PWM Mode ................................................................................. 15 Design Example .............................................................................. 23 PFM Mode ................................................................................... 15 Output Voltage Setting .............................................................. 23 Precision Enable/Shutdown ...................................................... 15 Current-Limit Setting ................................................................ 23 Separate Input Voltages ............................................................. 15 Frequency Setting ....................................................................... 23 Internal Regulator (INTVCC) .................................................. 15 Inductor Selection ...................................................................... 23 Bootstrap Circuitry .................................................................... 16 Output Capacitor Selection....................................................... 23 Low-Side Driver.......................................................................... 16 Low-Side MOSFET Selection ................................................... 24 Oscillator ..................................................................................... 16 Compensation Components ..................................................... 24 Synchronization .......................................................................... 16 Soft Start Time Programming .................................................. 24 Soft Start ...................................................................................... 16 Input Capacitor Selection .......................................................... 24 Peak Current-Limit and Short-Circuit Protection................. 16 External Components Recommendation .................................... 25 Voltage Tracking ......................................................................... 17 Typical Application Circuits ......................................................... 26 Parallel Operation....................................................................... 17 Outline Dimensions ....................................................................... 31 Power Good ................................................................................. 17 Ordering Guide .......................................................................... 31 REVISION HISTORY 6/12—Rev. 0 to Rev. A Change to Features Section ............................................................. 1 Added ADIsimPower Design Tool Section ................................. 19 7/11—Revision 0: Initial Version Rev. A | Page 2 of 32 Data Sheet ADP2323 FUNCTIONAL BLOCK DIAGRAM ADP2323 1.2V UVLO EN1_BUF + ACS1 – EN1 1µA 4µA SLOPE RAMP1 Σ PVIN1 I1MAX + OCP – BOOST REGULATOR HICCUP MODE BST1 COMP1 ISS1 0.6V SS1 NFET1 DRIVER + + AMP1 + CMP1 – – – + TRK1 FB1 SKIP MODE THRESHOLD 0.7V – + OVP + SW1 SKIP CMP1 CONTROL LOGIC AND MOSFET DRIVER WITH MODE_BUF ANTICROSS PROTECTION DRIVER DL1 PGND CLK1 ZERO CURRENT – CMP – 0.54V VDRV + + PGOOD1 I1MAX CURRENTLIMIT SELECTION EN1_BUF CLK1 SCFG EN2_BUF INTVCC 5V REGULATOR SLOPE RAMP1 OSCILLATOR CLK2 SYNC RT GND SLOPE RAMP2 UVLO 1.2V EN2_BUF 1µA 4µA SLOPE RAMP2 Σ PVIN2 + ACS2 – EN2 I2MAX + OCP – BOOST REGULATOR HICCUP MODE BST2 COMP2 NFET2 0.6V SS2 DRIVER + + CMP2 – + + AMP2 TRK2 FB2 – 0.7V – + 0.54V OVP SKIP CMP2 CONTROL LOGIC AND MOSFET + DRIVER WITH ANTICROSS MODE_BUF PROTECTION – SKIP MODE THRESHOLD SW2 CLK2 VDRV DRIVER DL2 – ZERO CURRENT – CMP + + I2MAX CURRENTLIMIT SELECTION Figure 3. Functional Block Diagram Rev. A | Page 3 of 32 09357-042 ISS2 PGOOD2 VDRV PVIN1 MODE_BUF MODE ADP2323 Data Sheet SPECIFICATIONS PVIN1 = PVIN2 = 12 V at TJ = −40°C to +125°C, unless otherwise noted. Table 1. Parameters POWER INPUT (PVINx PINS) Power Input Voltage Range Quiescent Current (PVIN1 + PVIN2) Shutdown Current (PVIN1 + PVIN2) PVINx Undervoltage Lockout Threshold PVINx Rising PVINx Falling FEEDBACK (FBx PINS) FBx Regulation Voltage 1 FBx Bias Current ERROR AMPLIFIER (COMPx PINS) Transconductance EA Source Current EA Sink Current INTERNAL REGULATOR (INTVCC PIN) INTVCC Voltage Dropout Voltage Regulator Current Limit SWITCH NODE (SWx PINS) High-Side On Resistance 2 SWx Peak Current Limit SWx Minimum On Time 3 SWx Minimum Off Time3 LOW-SIDE DRIVER (DLx PINS ) Rising Time3 Falling Time3 Sourcing Resistor Sinking Resistor OSCILLATOR (RT PIN) PWM Switching Frequency PWM Frequency Range SYNCHRONIZATION (SYNC PIN) SYNC Input Synchronization Range Minimum On Pulse Width Minimum Off Pulse Width High Threshold Low Threshold SYNC Output Frequency on SYNC Pin Positive Pulse Time SOFT START (SSx PINS) SSx Pin Source Current Symbol Test Conditions/Comments VPVIN IQ ISHDN UVLO MODE = GND, no switching EN1 = EN2 = GND Min Typ Max Units 3 50 20 5 100 V mA µA 4.3 3.8 4.5 V V 0.594 0.6 0.01 0.606 0.1 V µA 230 25 25 300 45 45 370 65 65 µS µA µA 4.75 5 400 75 5.25 V mV mA 90 4.8 3 1.5 130 150 130 5.8 3.7 2.2 4.5 3.5 VFB IFB PVINx = 4.5 V to 20 V gm ISOURCE ISINK IINTVCC = 30 mA 40 VBST to VSW = 5 V RILIM = floating, VBST to VSW = 5 V RILIM = 47 kΩ, VBST to VSW = 5 V RILIM = 15 kΩ, VBST to VSW = 5 V 4 2.3 0.8 tMIN_ON tMIN_OFF CDL = 2.2 nF, see Figure 19 CDL = 2.2 nF, see Figure 22 fSW ROSC = 100 kΩ 20 10 4 2 530 250 600 120 mΩ A A A ns ns 6 4.5 ns ns Ω Ω 670 1200 kHz kHz 1200 kHz ns ns V V SYNC configured as input 300 100 100 1.3 0.4 SYNC configured as output fCLKOUT fSW kHz ns 100 ISS 2.5 Rev. A | Page 4 of 32 3.5 4.5 µA Data Sheet Parameters TRACKING INPUT (TRKx PINS) TRKx Input Voltage Range TRKx-to-FBx Offset Voltage TRKx Input Bias Current POWER GOOD (PGOODx PINS) Power Good Rising Threshold Power Good Hysteresis Power Good Deglitch Time PGOODx Leakage Current PGOODx Output Low Voltage ENABLE (ENx PINS) ENx Rising Threshold ENx Falling Threshold ENx Source Current ADP2323 Symbol Test Conditions/Comments Min TRKx = 0 mV to 500 mV 0 −10 87 From FBx to PGOODx VPGOOD = 5 V IPGOOD = 1 mA 1.02 EN voltage below falling threshold EN voltage above rising threshold MODE (MODE PIN) Input High Voltage Input Low Voltage THERMAL Thermal Shutdown Threshold Thermal Shutdown Hysteresis Typ Max Units 600 +10 100 mV mV nA 90 5 16 0.1 50 93 % % Clock cycle µA mV 1.2 1.1 5 1 1.28 1 100 1.3 0.4 150 15 1 Tested in a feedback loop that adjusts VFB to achieve a specified voltage on the COMPx pin. Pin-to-pin measurements. 3 Guaranteed by design. 2 Rev. A | Page 5 of 32 V V µA µA V V °C °C ADP2323 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter PVIN1, PVIN2, EN1, EN2 SW1, SW2 BST1, BST2 FB1, FB2, SS1, SS2,COMP1, COMP2, PGOOD1, PGOOD2, TRK1, TRK2, SCFG, SYNC, RT, MODE INTVCC, VDRV, DL1, DL2 PGND to GND Temperature Range Operating (Junction) Storage Soldering Conditions θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to +22 V −1 V to +22 V VSW + 6 V −0.3 V to +6 V Boundary Condition θJA is measured using natural convection on a JEDEC 4-layer board, and the exposed pad is soldered to the printed circuit board (PCB) with thermal vias. −0.3 V to +6 V −0.3 V to +0.3 V Table 3. Thermal Resistance Package Type 32-Lead LFCSP_WQ −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 32 θJA 32.7 Unit °C/W Data Sheet ADP2323 32 31 30 29 28 27 26 25 FB1 COMP1 SS1 TRK1 EN1 PVIN1 PVIN1 SW1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADP2323 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 SW1 BST1 DL1 PGND VDRV DL2 BST2 SW2 NOTES 1. THE EXPOSED PAD SHOULD BE SOLDERED TO AN EXTERNAL GND PLANE. 09357-003 FB2 COMP2 SS2 TRK2 EN2 PVIN2 PVIN2 SW2 9 10 11 12 13 14 15 16 PGOOD1 SCFG SYNC GND INTVCC RT MODE PGOOD2 Figure 4. Pin Configuration (Top View) Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic PGOOD1 SCFG 3 SYNC 4 5 GND INTVCC 6 7 RT MODE 8 9 PGOOD2 FB2 10 COMP2 11 SS2 12 TRK2 13 EN2 14, 15 PVIN2 16, 17 18 19 SW2 BST2 DL2 20 VDRV 21 22 PGND DL1 Description Power-Good Output (Open Drain) for Channel 1. A pull-up resistor of 10 kΩ to 100 kΩ is recommended. Synchronization Configuration Input. The SCFG pin configures the SYNC pin as an input or output. Connect SCFG to INTVCC to configure SYNC as an output. Using a resistor to pull down to GND configures SYNC as an input with various phase shift degrees. Synchronization. This pin can be configured as an input or an output. When configured as an output, it provides a clock at the switching frequency. When configured as an input, this pin accepts an external clock to which the regulators are synchronized and the phase shift is configured by SCFG. Note that when SYNC is configured as an input, the PFM mode is disabled and the device works only in continuous conduction mode (CCM). Analog Ground. Connect to the ground plane. Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 μF ceramic capacitor between INTVCC and GND. Connect a resistor between RT and GND to program the switching frequency between 250 kHz and 1.2 MHz. Mode Selection. When this pin is connected to INTVCC, the PFM mode is disabled and the regulator works only in CCM. When this pin is connected to ground, the PFM mode is enabled. If the low-side device is a diode, the MODE pin must be connected to ground. Power-Good Output (Open Drain) for Channel 2. A pull-up resistor of 10 kΩ to 100 kΩ is recommended. Feedback Voltage Sense Input for Channel 2. Connect to a resistor divider from the Channel 2 output voltage, VOUT2. Connect FB2 to INTVCC for parallel applications. Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to GND. Connect COMP1 and COMP2 together for parallel applications. Soft Start Control for Channel 2. Connect a capacitor from SS2 to GND to program the soft start time. For parallel applications, SS2 remains open. Tracking Input for Channel 2. To track a master voltage, drive this pin from a voltage divider from the master voltage. If the tracking function is not used, connect TRK2 to INTVCC. Enable Pin for Channel 2. An external resistor divider can be used to set the turn-on threshold. When not using the enable pin, connect EN2 to PVIN2. Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor between PVIN2 and ground. Switch Node for Channel 2. Supply Rail for the Gate Drive of Channel 2. Place a 0.1 μF capacitor between SW2 and BST2. Low-Side Gate Driver Output for Channel 2. Connect a resistor between DL2 and PGND to program the current-limit threshold of Channel 2. Low-Side Driver Supply Input. Connect VDRV to INTVCC. Place a 1 μF ceramic capacitor between the VDRV pin and PGND. Driver Power Ground. Connect to the source of the synchronous N-channel MOSFET. Low-Side Gate Driver Output for Channel 1. Connect a resistor between this pin and PGND to program the current-limit threshold of Channel 1. Rev. A | Page 7 of 32 ADP2323 Pin No. 23 24, 25 26, 27 Mnemonic BST1 SW1 PVIN1 28 EN1 29 TRK1 30 31 SS1 COMP1 32 FB1 Exposed Pad Data Sheet Description Supply Rail for the Gate Drive of Channel 1. Place a 0.1 µF capacitor between SW1 and BST1. Switch Node for Channel 1. Power Input for Channel 1. This pin is the power input for Channel 1 and provides power for the internal regulator. Connect to the input power source and connect a bypass capacitor between PVIN1 and ground. Enable Pin for Channel 1. An external resistor divider can be used to set the turn-on threshold. When not using the enable pin, connect the EN1 pin to PVIN1. Tracking Input for Channel 1. To track a master voltage, drive this pin from a voltage divider from the master voltage. If the tracking function is not used, connect TRK1 to INTVCC. Soft Start Control for Channel 1. To program the soft start time, connect a capacitor from SS1 to GND. Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to GND. Connect COMP1 and COMP2 together for a parallel application. Feedback Voltage Sense Input for Channel 1. Connect to a resistor divider from the Channel 1 output voltage, VOUT1. Solder the exposed pad to an external GND plane. Rev. A | Page 8 of 32 Data Sheet ADP2323 TYPICAL PERFORMANCE CHARACTERISTICS 100 95 95 90 90 85 85 80 75 70 VOUT = 5.0V VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 65 60 INDUCTOR: CDRH105RNP-3R3N MOSFET: FDS8880 55 50 0 0.5 1.0 1.5 2.0 2.5 80 75 70 60 3.0 50 0.5 1.0 1.5 2.0 2.5 3.0 Figure 8. Efficiency at VIN = 12 V, fSW = 300 kHz, FPWM 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 VOUT = 3.3V, FPWM VOUT = 3.3V, PFM VOUT = 5V, FPWM VOUT = 5V, PFM 60 50 VOUT = 3.3V, FPWM VOUT = 3.3V, PFM VOUT = 5V, FPWM VOUT = 5V, PFM 40 30 20 20 INDUCTOR: CDRH105RNP-3R3N MOSFET: FDS8880 0 0.01 INDUCTOR: CDRH105RNP-6R8N MOSFET: FDS8880 10 0.1 1 10 OUTPUT CURRENT (A) 0 0.01 09357-006 10 0.1 1 10 OUTPUT CURRENT (A) Figure 6. Efficiency at VIN = 12 V, fSW = 600 kHz, PFM 09357-009 EFFICIENCY (%) 0 OUTPUT CURRENT (A) Figure 5. Efficiency at VIN = 12 V, fSW = 600 kHz, FPWM 30 INDUCTOR: CDRH105RNP-6R8N MOSFET: FDS8880 55 OUTPUT CURRENT (A) 40 VOUT = 5.0V VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V 65 09357-008 EFFICIENCY (%) 100 09357-005 EFFICIENCY (%) Operating conditions: TA = 25°C, VIN = 12 V, VOUT = 3.3 V, L = 4.7 µH, COUT = 2 × 47 µF, fSW = 600 kHz, unless otherwise noted. Figure 9. Efficiency at VIN = 12 V, fSW = 300 kHz, PFM 3.20 40 3.15 25 20 TJ = –40°C TJ = +25°C TJ = +125°C 15 6 8 10 3.05 3.00 2.95 TJ = –40°C TJ = +25°C TJ = +125°C 2.90 2.85 10 4 3.10 12 14 16 VIN (V) 18 20 2.80 4 6 8 10 12 14 16 VIN (V) Figure 7. Shutdown Current vs. VIN Figure 10. Quiescent Current vs. VIN Rev. A | Page 9 of 32 18 20 09357-010 QUIESCENT CURRENT (mA) 30 09357-007 SHUTDOWN CURRENT (μA) 35 ADP2323 Data Sheet 4.5 1.30 4.4 RISING 1.25 ENABLE THRESHOLD (V) UVLO THRESHOLD (V) 4.3 4.2 4.1 4.0 3.9 FALLING 3.8 3.7 RISING 1.20 1.15 FALLING 1.10 1.05 0 20 40 60 80 100 120 TEMPERATURE (°C) 1.00 –40 5.05 1.06 5.00 EN SOURCE CURRENT (µA) 1.08 1.04 1.02 1.00 0.98 0.96 80 100 100 120 100 120 100 120 4.80 4.75 4.65 60 80 4.85 0.92 40 60 4.90 4.70 20 40 4.95 0.94 120 TEMPERATURE (°C) 4.60 –40 09357-012 EN SOURCE CURRENT (µA) 5.10 0 20 Figure 14. EN Threshold vs. Temperature 1.10 –20 0 TEMPERATURE (°C) Figure 11. UVLO Threshold vs. Temperature 0.90 –40 –20 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 12. EN Source Current at VEN = 1.5 V 09357-015 –20 09357-011 3.5 –40 09357-014 3.6 Figure 15. EN Source Current at VEN = 1 V 350 606 340 TRANSCONDUCTANCE (µS) 602 600 598 330 320 310 300 290 280 270 596 594 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 250 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 16. gm vs. Temperature Figure 13. FB Voltage vs. Temperature Rev. A | Page 10 of 32 09357-016 260 09357-013 FEEDBACK VOLTAGE (mV) 604 Data Sheet ADP2323 660 5.4 5.2 5.0 620 VOLTAGE (V) 600 4.8 4.6 580 4.4 ROSC = 100kΩ 560 0 20 40 60 80 100 120 TEMPERATURE (°C) 4.0 4 6 12 14 16 18 20 Figure 20. INTVCC Voltage vs. VIN 4.5 130 4.3 SSx PIN SOURCE CURRENT (µA) 120 110 100 90 80 70 4.1 3.9 3.7 3.5 3.3 3.1 2.9 60 2.7 0 20 40 60 80 100 120 TEMPERATURE (°C) 2.5 –40 09357-018 –20 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 18. MOSFET RDSON vs. Temperature Figure 21. SSx Pin Source Current vs. Temperature SW SW 1 1 DL DL 2 CH1 5.00V CH2 2.00V M20.0ns T 31.20% A CH1 1.10V 09357-022 2 09357-019 MOSFET RESISTOR (mΩ) 10 VIN (V) Figure 17. Frequency vs. Temperature 50 –40 8 09357-020 –20 09357-017 540 –40 4.2 CH1 5.00V Figure 19. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF CH2 2.00V M20.0ns T 60.20% A CH1 1.10V Figure 22. Low-Side Driver Falling Edge Waveform, CDL = 2.2 nF Rev. A | Page 11 of 32 09357-021 FREQUENCY (kHz) 640 ADP2323 Data Sheet 3.2 5.8 5.6 3.1 PEAK CURRENT LIMIT (A) 5.2 5.0 4.8 4.6 4.4 3.0 2.9 2.8 2.7 2.6 4.2 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 2.5 –40 09357-023 4.0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 23. Current-Limit Threshold vs. Temperature, RILIM = Floating Figure 26. Current-Limit Threshold vs. Temperature, RILIM = 47 kΩ 2.0 VOUT (AC) 1 1.8 PEAK CURRENT LIMIT (A) IL 1.6 4 1.4 1.2 2 SW –20 0 20 40 60 80 100 120 TEMPERATURE (°C) B CH1 10.0mV 09357-024 0.8 –40 09357-027 1.0 Figure 24. Current-Limit Threshold vs. Temperature, RILIM = 15 kΩ W CH2 10.0V CH4 2.00A Ω M2.00µs A CH2 T 50.00% 5.80V Figure 27. Continuous Conduction Mode (CCM) VOUT (AC) 1 1 VOUT (AC) IL IL 4 4 2 SW SW CH1 10.0mV B W CH2 10.0V M2.00µs A CH2 CH4 500mA Ω T 50.20% 9.40V 09357-028 09357-025 2 CH1 100mV Figure 25. Discontinuous Conduction Mode (DCM) B W CH2 10.0V M400µs A CH1 CH4 1.00A Ω T 60.40% Figure 28. Power Saving Mode Rev. A | Page 12 of 32 –12.0mV 09357-026 PEAK CURRENT LIMIT (A) 5.4 Data Sheet ADP2323 EN EN 3 3 VOUT VOUT 1 1 PGOOD PGOOD 2 2 IL IOUT CH1 2.00V BW CH3 10.0V CH2 5.00V CH4 2.00A Ω M1.00ms T A CH2 09357-032 4 09357-029 4 CH1 2.00V BW CH3 10.0V 1.80V CH2 5.00V CH4 1.00A Ω 50.40% Figure 29. Soft Start With Full Load M1.00ms T A CH2 1.80V 50.40% Figure 32. Precharged Output VOUT (AC) 1 VOUT (AC) 1 VIN 3 SW IOUT IOUT CH1 100mV B M200µs W CH4 1.00A Ω T A CH4 09357-033 2 09357-030 4 B CH1 20.0mV CH3 5.00V 1.00A W CH2 5.00V M1.00ms A CH1 –8.00mV B W T 70.20% 72.00% Figure 33. Line Transient Response, VIN from 8 V to 14 V, IOUT = 3 A Figure 30. Load Transient Response, 0.5 A to 2.5 A VOUT VOUT 1 1 SW SW 2 2 IL IL CH1 2.00V BW CH2 10.0V CH4 2.00A Ω M10.0ms T A CH1 09357-034 4 09357-031 4 CH1 2.00V BW 960mV 20.60% Figure 31. Output Short CH2 10.0V CH4 2.00A Ω M10.0ms T A CH1 60.40% Figure 34. Output Short Recovery Rev. A | Page 13 of 32 1.28V ADP2323 Data Sheet SYNC SYNC 3 3 SW1 SW1 1 1 SW2 SW2 CH1 10.0V CH3 5.00V CH2 10.0V M1.00µs T A CH3 2.90V 09357-038 2 09357-035 2 CH1 10.0V CH3 5.00V CH2 10.0V M1.00µs T 50.20% Figure 35. External Synchronization with 60° Phase Shift A CH3 2.90V 50.20% Figure 38. External Synchronization with 90° Phase Shift SYNC SW1 3 1 SW2 SW1 2 1 SW2 IL2 IL1 CH1 10.0V CH3 5.00V CH2 10.0V M1.00µs T A CH3 09357-039 3 09357-036 2 CH1 10.0V CH3 2.00A Ω 2.90V CH2 10.0V CH4 2.00A Ω 50.20% M1.00µs T A CH2 5.80V 50.00% Figure 39. Dual Phase, Single Output, VOUT = 3.3 V, IOUT = 6 A Figure 36. External Synchronization with 120° Phase Shift VMASTER VMASTER VSLAVE VSLAVE CH2 1.00V BW CH3 1.00V BW M2.00ms T A CH2 09357-040 3 09357-037 3 CH2 1.00V BW 660mV CH3 1.00V BW 43.00% Figure 37. Coincident Tracking M2.00ms T A CH2 43.00% Figure 40. Ratiometric Tracking Rev. A | Page 14 of 32 660mV Data Sheet ADP2323 THEORY OF OPERATION The ADP2323 is a full featured, dual output, step-down dc-todc regulator based on current-mode architecture. It integrates two high-side power MOSFETs and two low-side drivers for external MOSFETs. The ADP2323 targets high performance applications that require high efficiency and design flexibility. The ADP2323 can operate with an input voltage from 4.5 V to 20 V, and can regulate the output voltage down to 0.6 V. Additional features for flexible design include programmable switching frequency, programmable soft start, external compensation, independent enable inputs, and power good outputs. CONTROL SCHEME The ADP2323 uses a fixed frequency, current-mode PWM control architecture during medium to full loads, but shifts to a power save mode (PFM) at light loads when the PFM mode is enabled. The power save mode reduces switching losses and boosts efficiency under light loads. When operating in the fixed frequency PWM mode, the duty cycle of the integrated Nchannel MOSFET (referred to interchangeably as NFET or MOSFET) is adjusted, which, in turn, regulates the output voltage. When operating in power save mode, the switching frequency is adjusted to regulate the output voltage. PWM MODE In PWM mode, the ADP2323 operates at a fixed frequency that is set by an external resistor. At the start of each oscillator cycle, the high-side NFET turns on, placing a positive voltage across the inductor. The inductor current increases until the current sense signal crosses the peak inductor current threshold that turns off the high-side NFET and turns on the low-side NFET (diode). This places a negative voltage across the inductor causing the inductor current to reduce. The low-side NFET (diode) stays on for the remainder of the cycle or until the inductor current reaches zero. PRECISION ENABLE/SHUTDOWN The ADP2323 has two independent enable pins (EN1 and EN2) for each channel. The ENx pin has an internal pull-down current source (5 µA) that provides default turn off when an ENx pin is open. When the voltage on the EN1 or EN2 pin exceeds 1.2 V (typical), Channel 1 or Channel 2 is enabled and the internal pull-down current source at the EN1 or EN2 pin is reduced to 1 µA, which allows the user to program the input voltage undervoltage lockout (UVLO). When the voltage on the EN1 or EN2 pin drops below 1.1 V (typical), Channel 1 or Channel 2 turns off. When EN1 and EN2 are both below 1.1 V, all of the internal circuits turn off and the device enters the shutdown mode. SEPARATE INPUT VOLTAGES The ADP2323 supports two separate input voltages. This means that the PVIN1 and PVIN2 voltages can be connected to two different supply voltages. In these types of applications, the PVIN1 voltage needs to be above the UVLO voltage before the PVIN2 voltage begins to rise because the PVIN1voltage provides the power supply for the internal regulator and control circuitry. This feature makes it possible for a cascading supply operation as shown in Figure 41, where PVIN2 is sourced from the Channel 1 output. In this configuration, the Channel 1 output voltage needs to be high enough to maintain Channel 2 in regulation, and the Channel 1 output voltage needs to be higher than the input voltage UVLO threshold. VIN ADP2323 VOUT1 Pull the MODE pin to ground to enable the PFM mode. When the COMPx voltage is below the PFM threshold voltage, the device enters the PFM mode. When the device enters the PFM mode, it monitors the FBx voltage to regulate the output voltage. Because the high-side and low-side NFETs are turned off, the output voltage drops due to the load current discharging the output capacitor. When the FBx voltage drops below 0.605 V, the device starts switching and the output voltage increases as the output capacitor is charged by the inductor current. When the FBx voltage exceeds 0.62 V, the device turns off both the high-side and low-side NFETs until the FBx voltage drops to 0.605 V. In the PFM mode, the output voltage ripple is larger than the ripple in the PWM mode. COUT1 L2 L1 M1 SW1 SW2 DL1 DL2 M2 VOUT2 COUT2 PGND 09357-043 PFM MODE PVIN2 PVIN1 Figure 41. Cascading Supply Operation INTERNAL REGULATOR (INTVCC) The internal regulator provides a stable voltage supply for the internal control circuits and bias voltage for the low-side gate drivers. A 1 µF ceramic capacitor is recommended to be placed between INTVCC and GND. The internal regulator also includes a current-limit circuit for protection. The internal regulator is active when either one of the channels is enabled. The PVIN1 pin provides power for the internal regulator that is used by both channels. Rev. A | Page 15 of 32 ADP2323 Data Sheet BOOTSTRAP CIRCUITRY The ADP2323 integrates the boot regulators to provide the gate drive voltage for the high-side NFETs. The regulators generate 5 V bootstrap voltages between the BSTx pin and the SWx pin. It is recommended that an X7R or an X5R, 0.1 µF ceramic capacitor be placed between the BSTx and the SWx pins. LOW-SIDE DRIVER The DLx pin provides the gate drive for the low-side N-channel MOSFET. Internal circuitry monitors the gate driver signal to ensure break-before-make switching to prevent cross conduction. The VDRV pin provides the power supply to the low-side drivers. It is limited to a 5.5 V maximum input, and placing a 1 µF ceramic capacitor close to this pin is recommended. OSCILLATOR When the SYNC pin is configured as an output, it generates a clock with a frequency that is equal to the internal switching frequency. When the SYNC pin is configured as an input, the ADP2323 synchronizes to the external clock that is applied to the SYNC pin, and the internal clock must be programmed lower than the external clock. The phase shift can be programmed by the SCFG pin. When working in synchronization mode, the ADP2323 disables the PFM mode and works only in the CCM mode. SOFT START The SSx pins are used to program the soft start time. Place a capacitor between SSx and GND; an internal current charges this capacitor to establish the soft start ramp. The soft start time can be calculated using the following equation: TSS = A resistor from RT to GND programs the switching frequency according to the following equation: fSW [kHz] = 60,000 ROSC [kΩ] A 200 kΩ resistor sets the frequency to 300 kHz, and a 100 kΩ resistor sets the frequency to 600 kHz. Figure 42 shows the typical relationship between fSW and ROSC. 1200 I SS where: CSS is the soft start capacitance. ISS is the soft start pull-up current (3.5 µA). If the output voltage is precharged prior to power up, the ADP2323 prevents the low-side MOSFET from turning on until the soft start voltage exceeds the voltage on the FBx pin. During soft start, the ADP2323 uses frequency foldback to prevent output current runaway. The switching frequency is reduced according to the voltage present at the FBx pin, which allows more time for the inductor to discharge. The correlation between the switching frequency and the FBx pin voltage is listed in Table 6. 1100 1000 FREQUENCY (kHz) 0.6 V × CSS 900 800 700 600 Table 6. FBx Pin Voltage and Switching Frequency 500 FBx Pin Voltage VFB ≥ 0.4 V 0.4 V > VFB ≥ 0.2 V VFB < 0.2 V 400 300 50 70 90 110 130 150 170 190 210 230 ROSC (kΩ) 250 09357-044 200 Figure 42. fSW vs. ROSC SYNCHRONIZATION The SYNC pin can be configured as an input or an output by setting the SCFG pin as shown in Table 5. Table 5. SCFG Configuration SCFG High GND 180 kΩ to GND 100 kΩ to GND SYNC Output Input Input Input Phase Shift 0° 90° 120° 60° Switching Frequency fSW 1/2 fSW 1/4 fSW PEAK CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION The ADP2323 uses a peak current-limit protection circuit to prevent current runaway. Place a resistor between DLx and PGND to program the current-limit value listed in Table 7. The programmable current-limit threshold feature allows for the use of a small size inductor for low current applications. Table 7. Peak Current-Limit Threshold Setting RILIM Floating 47 kΩ 15 kΩ Rev. A | Page 16 of 32 Peak Current-Limit Threshold 4.8 A 3A 1.5 A Data Sheet ADP2323 The ADP2323 uses hiccup mode for overcurrent protection. When the peak inductor current reaches the current-limit threshold, the high-side MOSFET turns off and the low-side driver turns on until the next cycle while the overcurrent counter increments. Ratiometric tracking is shown in Figure 45. The slave output is limited to a fraction of the master voltage. In this application, the slave and master voltages reach the final value at the same time. In some cases, the input voltage (PVIN) ramp rate is too slow or the output capacitor is too large to support the setting regulation voltage during the soft start causing the device to enter the hiccup mode. To avoid such cases, use a resistor divider at the ENx pin to program the input voltage UVLO or use a longer soft start time. VOLTAGE TRACKING The ADP2323 has a tracking input, TRKx, that allows the output voltage to track an external (master) voltage. It allows power sequencing applicable to FPGAs, DSPs, and ASICs, which may require a power sequence between the core and the I/O voltages. The internal error amplifier includes three positive inputs: the internal reference voltage, the soft start voltage, and the tracking input voltage. The error amplifier regulates the feedback voltage to the lowest of the three voltages. To track a master voltage, tie the TRKx pin to a resistor divider from the master voltage as shown in Figure 43. VMASTER RTRK_TOP RTRK_BOT SWx ADP2323 RTOP 09357-045 Figure 43. Voltage Tracking A common application is coincident tracking, which is shown in Figure 44. Coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. For coincident tracking, set RTRK_TOP = RTOP and RTRK_BOT = RBOT. VOLTAGE VMASTER TIME VSLAVE = V MASTER 1+ 1+ RTOP R BOT RTRK _ TOP RTRK _ BOT The final TRKx pin voltage must be higher than 0.54 V. If the TRK function is not used, connect the TRKx pin to INTVCC. PARALLEL OPERATION ADP2323 supports a two phase parallel operation to provide a single output of 6 A. To configure the ADP2323 as a two phase single output 1. 2. 3. Connect the FB2 pin to INTVCC, thereby disabling the Channel 2 error amplifier. Connect COMP1 to COMP2 and connect EN1 to EN2. Use SS1 to set the soft start time and keep SS2 open. During parallel operation, the voltages of PVIN1 and PVIN2 should be the same. OVERVOLTAGE PROTECTION The ADP2323 provides an overvoltage protection (OVP) feature to protect the system against the output shorting to a higher voltage supply or when a strong load transient occurs. If the feedback voltage increases to 0.7 V, the internal high-side MOSFET and low-side driver turn off until the voltage at the FBx pin reduces to 0.63 V, at which time the ADP2323 resumes normal operation. 09357-046 VSLAVE The ratio of the slave output voltage to the master voltage is a function of the two dividers, as follows: The power good (PGOODx) pin is an active high, open drain output that indicates if the regulator output voltage is within regulation. High indicates that the voltage at an FBx pin (and, hence, the output voltage) is above 90% of the reference voltage. Low indicates that the voltage at an FBx pin (and, hence, the output voltage) is below 85% of the reference voltage. There is a 16-cycle deglitch time between FBx and PGOODx. FBx RBOT TIME Figure 45. Ratiometric Tracking POWER GOOD VSLAVE TRKx VSLAVE 09357-047 If the overcurrent counter reaches 10, or the FBx pin voltage falls to 0.51 V after the soft start, the device enters hiccup mode. During this mode, the high-side MOSFET and low-side driver are both turned off. The device remains in this mode for seven soft start times and then attempts to restart from soft start. If the currentlimit fault is cleared, the device resumes normal operation; otherwise, it reenters hiccup mode. VOLTAGE VMASTER Figure 44. Coincident Tracking Rev. A | Page 17 of 32 ADP2323 Data Sheet UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN The undervoltage lockout (UVLO) threshold is 4.2 V with 0.5 V hysteresis to prevent the device from power-on glitches. When the PVIN1 or PVIN2 voltage rises above 4.2 V, Channel 1 or Channel 2 is enabled and the soft start period initiates. When either PVIN1 or PVIN2 drops below 3.7 V, it turns off Channel 1 or Channel 2, respectively. In the event that the ADP2323 junction temperature exceeds 150°C, the thermal shutdown circuit turns off the regulator. A 15°C hysteresis is included so that the ADP2323 does not recover from thermal shutdown until the on-chip temperature drops below 135°C. Upon recovery, soft start is initiated prior to normal operation. Rev. A | Page 18 of 32 Data Sheet ADP2323 APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL VOLTAGE CONVERSION LIMITATIONS The ADP2323 is supported by the ADIsimPower design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic and bill of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and parts count while taking into consideration the operating conditions and limitations of the IC and all real external components. For more information about ADIsimPower design tools, refer to www.analog.com/ADIsimPower. The tool set is available from this website, and users can request an unpopulated board through the tool. The minimum output voltage for a given input voltage and switching frequency is constrained by the minimum on time. The minimum on time of the ADP2323 is typically 130 ns. The minimum output voltage in CCM mode at a given input voltage and frequency can be calculated by using the following equation: INPUT CAPACITOR SELECTION The input decoupling capacitor attenuates high frequency noise on the input and acts as an energy reservoir. This capacitor should be a ceramic capacitor in the range of 10 µF to 47 µF and must be placed close to the PVINx pin. The loop composed of this input capacitor, high-side NFET, and low-side NFET must be kept as small as possible. The voltage rating of the input capacitor must be greater than the maximum input voltage. The rms current rating of the input capacitor should be larger than the following equation: I C IN _ rms = I OUT × D × (1 − D ) VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) × IOUT_MIN × tMIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN where: VOUT_MIN is the minimum output voltage. tMIN_ON is the minimum on time. IOUT_MIN is the minimum output current. fSW is the switching frequency. RDSON1 is the high-side MOSFET on resistance. RDSON2 is the low-side MOSFET on resistance. RL is the series resistance of output inductor. The maximum output voltage for a given input voltage and switching frequency is constrained by the minimum off time and the maximum duty cycle. The minimum off time is typically 150 ns and the maximum duty is typically 90% in the ADP2323. The maximum output voltage that is limited by the minimum off time at a given input voltage and frequency can be calculated using the following equation: VOUT_MAX = VIN × (1 – tMIN_OFF × fSW) – (RDSON1 – RDSON2) × IOUT_MAX × (1 – tMIN_OFF × fSW) – (RDSON2 + RL) × IOUT_MAX OUTPUT VOLTAGE SETTING The output voltage of the ADP2323 can be set by an external resistive divider using the following equation: R VOUT = 0.6 × 1 + TOP RBOT The maximum output voltage limited by the maximum duty cycle at a given input voltage can be calculated by using the following equation: To limit output voltage accuracy degradation due to FBx pin bias current (0.1 µA maximum) to less than 0.5% (maximum), ensure that RBOT is less than 30 kΩ. VOUT_MAX = DMAX × VIN Table 8 provides the recommended resistive divider for various output voltage options. Table 8. Resistive Divider for Various Output Voltages VOUT (V) 1.0 1.2 1.5 1.8 2.5 3.3 5.0 RTOP, ±1% (kΩ) 10 10 15 20 47.5 10 22 RBOT, ±1% (kΩ) 15 10 10 10 15 2.21 3 where: VOUT_MAX is the maximum output voltage. tMIN_OFF is the minimum off time. IOUT_MAX is the maximum output current. where DMAX is the maximum duty. As the previous equations show, reducing the switching frequency alleviates the minimum on time and minimum off time limitation. CURRENT-LIMIT SETTING The ADP2323 has three selectable current-limit thresholds. Make sure that the selected current-limit value is larger than the peak current of the inductor, IPEAK. Rev. A | Page 19 of 32 ADP2323 Data Sheet INDUCTOR SELECTION Table 9. Recommended Inductors The inductor value is determined by the operating frequency, input voltage, output voltage, and inductor ripple current. Using a small inductor leads to a faster transient response but degrades efficiency due to larger inductor ripple current, whereas a large inductor value leads to smaller ripple current and better efficiency but results in a slower transient response. Thus, there is a trade-off between the transient response and efficiency. As a guideline, the inductor ripple current, ΔIL, is typically set to 1/3 of the maximum load current. The inductor value can be calculated using the following equation: L= Vendor Sumida Coilcraft (VIN − VOUT ) × D ∆I L × f SW Wurth Elektronik where: VIN is the input voltage. VOUT is the output voltage. ΔIL is the inductor ripple current. fSW is the switching frequency. D is the duty cycle. D= V IN The ADP2323 uses adaptive slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is larger than 50%. The internal slope compensation limits the minimum inductor value. ISAT [A] 10.5 9.25 7.8 6.4 5.4 10.5 8.4 7.38 6.46 5.94 13.3 10.5 8.0 7.5 IRMS [A] 8.3 7.5 6.5 6.1 5.4 10.8 9.78 7.22 6.9 6.01 7.3 7.0 5.8 5.5 DCR [mΩ] 5.8 7.2 10.4 12.3 18 5.8 7.2 10.4 12.3 18 16 18 27 30 The output capacitor selection affects both the output voltage ripple and the loop dynamics of the regulator. For example, during load step transient on the output, when the load is suddenly increased, the output capacitor supplies the load until the control loop has a chance to ramp up the inductor current, which causes an undershoot of the output voltage. Use the following equation to calculate the output capacitance that is required to meet the voltage droop requirement: For a duty cycle that is larger than 50%, the minimum inductor value is determined by the following equation: VOUT × (1 − D ) 2 × f SW COUT _ UV = K UV × ∆I STE P 2 × L 2 × (VIN − VOUT )× ∆VOUT _ UV where: ΔISTEP is the load step. ΔVOUT_UV is the allowable undershoot on the output voltage. KUV is a factor, typically setting KUV = 2. The inductor peak current is calculated using the following equation: ∆I L 2 The saturation current of the inductor must be larger than the peak inductor current. For the ferrite core inductors with a quick saturation characteristic, the saturation current rating of the inductor should be higher than the current-limit threshold of the switch to prevent the inductor from getting into saturation. The rms current of the inductor can be calculated by the following equation: I RMS = I OUT 2 + Value [µH] 1.5 2.2 3.3 4.7 6.8 1.5 2.2 3.3 4.7 6.8 1.8 3.0 4.7 6.2 OUTPUT CAPACITOR SELECTION VOUT I PEAK = IOUT + Part No. CDRH105RNP-1R5N CDRH105RNP-2R2N CDRH105RNP-3R3N CDRH105RNP-4R7N CDRH105RNP-6R8N MSS1048-152NL MSS1048-222NL MSS1048-332NL MSS1048-472NL MSS1048-682NL 7447797180 7447797300 7447797470 7447797620 Another case is when a load is suddenly removed from the output and the energy stored in the inductor rushes into the output capacitor, which causes the output to overshoot. The output capacitance required to meet the overshoot requirement can be calculated using the following equation: COUT _ OV = K OV × ∆I STEP 2 × L (VOUT + ∆VOUT _ OV ) 2 − VOUT 2 where: ΔVOUT_OV is the allowable overshoot on the output voltage. KOV is a factor, typically setting KOV = 2. ∆I L 2 12 Shielded ferrite core materials are recommended for low core loss and low EMI. The output ripple is determined by the ESR of the output capacitor and its capacitance value. Use the following equation to select a capacitor that can meet the output ripple requirements: COUT _ RIPPLE = R ESR = Rev. A | Page 20 of 32 ∆I L 8 × f SW × ∆VOUT _ RIPPLE ∆VOUT _ RIPPLE ∆I L Data Sheet ADP2323 where: ΔVOUT_RIPPLE is the allowable output voltage ripple. RESR is the equivalent series resistance of the output capacitor. Select the largest output capacitance given by COUT_UV, COUT_OV, and COUT_RIPPLE to meet both load transient and output ripple performance. The selected output capacitor voltage rating must be greater than the output voltage. The minimum rms current rating of the output capacitor is determined by the following equation: I COUT _ rms = ∆I L 12 Table 10. Recommended MOSFETs Vendor Fairchild Fairchild Fairchild Vishay Vishay AOS AOS Part No. FDS8880 FDMS7578 FDS6898A Si4804CDY SiA430DJ AON7402 AO4884L ID 10.7 A 14 A 9.4 A 7.9 A 10.8 A 39 A 10 A RDSON 12 mΩ 8 mΩ 14 mΩ 27 mΩ 18.5 mΩ 15 mΩ 16 mΩ Qg 12 nC 8 nC 16 nC 7 nC 5.3 nC 7.1 nC 13.6 nC PROGRAMMING UVLO INPUT The precision enable input can be used to program the UVLO threshold and hysteresis of the input voltage as shown in Figure 46. LOW-SIDE POWER DEVICE SELECTION PVINx The ADP2323 has integrated low-side MOSFET drivers, which can drive the low-side N-channel MOSFETs (NFETs). The selection of the low-side N-channel MOSFET affects the dc-todc regulator performance. RTOP_EN EN CMP ENx 1.2V RBOT_EN The selected MOSFET must meet the following requirements: 1µA Drain source voltage (VDS) must be higher than 1.2 × VIN. Drain current (ID) must be greater than the 1.2 × ILIMIT_MAX, where ILIMIT_MAX is the selected maximum current-limit threshold. Figure 46. Programming UVLO Input Use the following equation to calculate RTOP_EN and RBOT_EN: The ADP2323 low-side gate drive voltage is 5 V. Make sure that the selected MOSFET can be fully turned on at 5 V. RTOP _ EN = Total gate charge (Qg at 5 V) must be less than 30 nC. Lower Qg characteristics constitute higher efficiency. RBOT _ EN = When the high-side MOSFET is turned off, the low-side MOSFET carries the inductor current. For low duty cycle applications, the low-side MOSFET carries the current for most of the period. To achieve higher efficiency, it is important to select a low on-resistance MOSFET. The power conduction loss for the low-side MOSFET can be calculated using the following equation: PFET_LOW = IOUT2 × RDSON × (1 − D) where RDSON is the on resistance of the low-side MOSFET. Make sure that the MOSFET can handle the thermal dissipation due to the power loss. In some cases, efficiency is not critical for the system; therefore, the diode can be selected as the low-side power device. The average current of the diode can be calculated using the following equation: 1.1 V × 5 μA − 1.2 V × 1 μA 1.2 V × RTOP _ EN VIN _ RISING − RTOP _ EN × 5 μΑ − 1.2 V COMPENSATION COMPONENTS DESIGN For peak current-mode control, the power stage can be simplified as a voltage controlled current source supplying current to the output capacitor and load resistor. It is composed of one domain pole and a zero contributed by the output capacitor ESR. The control-to-output transfer function is shown in the following equations: s 1 + 2 × π × f z VOUT (s) Gvd (s) = = AVI × R × VCOMP (s) s 1 + 2× π× f p fz = fp = If a diode is used for the low-side device, the ADP2323 must enable the PFM mode by connecting the MODE pin to ground. 1.1 V × VIN _ RISING − 1.2 V × VIN _ FALLING where: VIN_RISING is the VIN rising threshold. VIN_FALLING is the VIN falling threshold. IDIODE (AVG) = (1 − D) × IOUT The reverse breakdown voltage rating of the diode must be greater than the input voltage with an appropriate margin to allow for ringing, which may be present at the SWx node. A Schottky diode is recommended because it has low forward voltage drop and fast switching speed. 4µA 09357-048 • • VDS 30 V 25 V 20 V 30 V 20 V 30 V 40 V 1 2 × π × RESR × COUT 1 2 × π × (R + R ESR ) × COUT where: AVI = 5 A/V R is the load resistance. COUT is the output capacitance. Rev. A | Page 21 of 32 ADP2323 Data Sheet RESR is the equivalent series resistance of the output capacitor. The ADP2323 uses a transconductance amplifier for the error amplifier to compensate the system. Figure 47 shows the simplified peak current-mode control small signal circuit. VOUT 1. VOUT 2. RTOP RBOT The following design guideline shows how to select the compensation components, RC, CC, and CCP, for ceramic output capacitor applications. VCOMP – gm + + AVI COUT RC = R RC CCP – 3. RESR 09357-049 CC The compensation components, RC and CC, contribute a zero, and the optional CCP and RC contribute an optional pole. 4. The closed-loop transfer equation is as follows: RBOT −gm × × RBOT + RTOP CC + CCP 1 + RC × CC × s R ×C ×C s × 1 + C C CP × s CC + CCP 2 × π × VOUT × COUT × f C 0.6 V × g m × AVI Place the compensation zero at the domain pole (fP). CC can be determined by CC = Figure 47. Simplified Peak Current-Mode Control Small Signal Circuit TV (s) = Determine the cross frequency (fC). Generally, the fC is between fSW/12 and fSW/6. RC can be calculated using the following equation: (R + RESR )× COUT CCP is optional. It can be used to cancel the zero caused by the ESR of the output capacitor. CCP = × Gvd (s) Rev. A | Page 22 of 32 RC RESR × COUT RC The ADP2323 has a 10 pF capacitor internally at the COMPx pin; therefore, if CCP is smaller than 10 pF, no external capacitor is needed. Data Sheet ADP2323 DESIGN EXAMPLE This section explains design procedure and component selection as shown in Figure 50; Table 11 provides a list of the required settings. Table 11. Dual Step-Down DC-to-DC Regulator Requirements Parameter Channel 1 Input Voltage Output Voltage Output Current Output Voltage Ripple Load Transient Channel 2 Input Voltage Output Voltage Output Current Output Voltage Ripple Load Transient Switching Frequency Specification Calculate the peak-to-peak inductor ripple current as follows: ∆I L = VIN1 = 12.0 V ± 10% VOUT1 = 1.2 V IOUT1 = 3 A ΔVOUT1_RIPPLE = 12 mV ±5%, 0.5 A to 3A, 1 A/µs For VOUT1 = 1.2 V, ΔIL1 = 0.98 A. For VOUT2 = 3.3 V, ΔIL2 = 1.02 A. I PEAK = I OUT + ∆I L 2 For the 1.2 V rail, the peak inductor current is 3.49 A, and for the 3.3 V rail, the peak inductor current is 3.51 A. The rms current through the inductor can be estimated by VIN2 = 12.0 V ± 10% VOUT2 = 3.3 V IOUT2 = 3 A ΔVOUT2_RIPPLE = 33 mV ±5%, 0.5 A to 3 A, 1 A/µs fSW = 500 kHz I RMS = I OUT 2 + ∆I L 2 12 The rms current of the inductor for both 1.2 V and 3.3 V is approximately 3.01 A. Choose a 10 kΩ top feedback resistor (RTOP); calculate the bottom feedback resistor by using the following equation: 0. 6 RBOT = RTOP × − 0 . 6 V OUT To set the output voltage to 1.2 V, the resistor values are RTOP1 = 10 kΩ and RBOT1 = 10 kΩ. To set the output voltage to 3.3 V, the resistors values are RTOP2 = 10 kΩ and RBOT2 = 2.21 kΩ. CURRENT-LIMIT SETTING For 3 A output current operation, the typical peak current limit is 4.8 A. In this case, no RILIM is required. For the 1.2 V rail, select an inductor with a minimum rms current rating of 3.01 A and a minimum saturation current rating of 3.49 A. For the 3.3 V rail, select an inductor with a minimum rms current rating of 3.01 A and a minimum saturation current rating of 3.51 A. Based on these requirements, for the 1.2 V rail, select a 2.2 µH inductor, such as the Sumida CDRH105RNP-2R2N, with a DCR = 7.2 mΩ; for the 3.3 V rail, select a 4.7 µH inductor, such as the Sumida CDRH105RNP-4R7N, with a DCR = 12.3 mΩ. OUTPUT CAPACITOR SELECTION The output capacitor is required to meet the output voltage ripple and load transient requirement. To meet the output voltage ripple requirement, use the following equation to calculate the ESR and capacitance: FREQUENCY SETTING COUT _ RIPPLE = To set the switching frequency to 500 kHz, use the following equation to calculate the resistor value, ROSC: RESR = 60,000 f SW (kHz ) ∆I L 8 × f SW × ∆VOUT _ RIPPLE ∆VOUT _ RIPPLE IL For VOUT1 = 1.2 V, COUT_RIPPLE1 = 20 µF and RESR1 = 12 mΩ. For VOUT2 = 3.3 V, COUT_RIPPLE2 = 7.7 µF and RESR2 = 32 mΩ. Therefore, ROSC =100 kΩ. INDUCTOR SELECTION The peak-to-peak inductor ripple current, ΔIL, is set to 30% of the maximum output current. Use the following equation to estimate the value of the inductor: L= L × f SW Find the peak inductor current by using the following equation: OUTPUT VOLTAGE SETTING ROSC (kΩ ) = (VIN − VOUT ) × D To meet the ±5% overshoot and undershoot requirement, use the following equation to calculate the capacitance: (VIN − VOUT )× D ∆I L × f SW For VOUT1 = 1.2 V, Inductor L1 = 2.4 µH, and for VOUT2 = 3.3 V, Inductor L2 = 5.3 µH. Select the standard inductor value of 2.2 µH and 4.7 µH for the 1.2 V and 3.3 V rails. COUT _ OV = K OV × ∆I STEP 2 × L (VOUT + ∆VOUT _ OV )2 − VOUT 2 COUT _UV = K UV × ∆I STEP 2 × L 2 × (VIN − VOUT ) × ∆VOUT _UV For estimation purposes, use KOV = KUV = 2. For VOUT1 = 1.2 V, use COUT_OV1 = 191 µF and COUT_UV1 = 21 µF. For VOUT2 = 3.3 V, use COUT_OV2 = 54 µF and COUT_UV2 = 20 µF. Rev. A | Page 23 of 32 ADP2323 Data Sheet For the 3.3 V rail, the 47µF ceramic output capacitor has a derated value of 32 µF. RC2 = For the 3.3 V rail, the ESR of the output capacitor must be smaller than 32 mΩ and the output capacitance must be larger than 54 µF. It is recommended that two pieces of 47 µF/X5R/6.3 V ceramic capacitor be used, such as the Murata GRM32ER60J476ME20, with an ESR = 2 mΩ. It is recommended that a 30 V, N-channel MOSFET be used, such as the FDS8880 from Fairchild. The RDSON of the FDS8880 at a 4.5 V driver voltage is 12 mΩ, and the total gate charge is 12 nC. COMPENSATION COMPONENTS For better load transient and stability performance, set the cross frequency, fC, to fSW/10. In this case, fSW is running at 500 kHz; therefore, the fC is set to 50 kHz. For the 1.2 V rail, the 100 µF ceramic output capacitor has a derated value of 64 µF. RC1 = CC 1 2 × π × 1.2 V × 3 × 64 μF × 50 kHz 0.6 V × 300 μs × 5 A/V CCP1 = = 1 pF Figure 49 shows the 3.3 V rail bode plot at 3 A. The cross frequency is 59 kHz and phase margin is 61°. 60 180 48 144 36 108 24 72 12 36 0 0 –12 –36 –24 –72 –36 –108 –48 –144 = 2.4 pF 180 48 144 36 108 24 72 12 36 0 0 –12 –36 –24 –72 –36 –108 –48 –144 –180 100k FREQUENCY (Hz) 1M 100k FREQUENCY (Hz) 1M The soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during soft start and limiting inrush current. The soft start time is set to 3 ms. CSS = I SS × TSS 3.5 μA × 3 ms = = 17.5 nF 0. 6 V 0. 6 V Choose a standard component value of CSS1 = CSS2 = 22 nF. INPUT CAPACITOR SELECTION A minimum 10 µF ceramic capacitor is required, placed near the PVINx pin. In this application, one piece of 10 µF, X5R, 25 V ceramic capacitor is recommended. PHASE (Degrees) 60 –60 –180 10k SOFT START TIME PROGRAMMING 09357-148 MAGNITUDE (dB) 73.7 kΩ Figure 49. Bode Plot for 3.3 V Rail Figure 48 shows the 1.2 V rail bode plot at 3 A. The cross frequency is 49 kHz and the phase margin is 59°. 10k 0.001 Ω × 2 × 32 μF Choose standard component values of RC2 = 75 kΩ and CC2 = 1000 pF. No CCP2 is needed. 1k Choose standard components, RC1 = 82 kΩ and CC1 = 1000 pF. No CCP1 is needed. 1k 73.7 kΩ CCP2 = = 80.4 kΩ 80.4 kΩ 80.4 kΩ (1.1 Ω + 0.001 Ω)× 2 × 32 μF = 956 pF –60 (0.4 Ω + 0.001 Ω)× 3 × 64μF = 957 pF = 0.001 Ω × 3 × 64 μF = 73.7 kΩ PHASE (Degrees) A low RDSON N-channel MOSFET is selected for high efficiency solutions. The MOSFET breakdown voltage needs to be greater than 1.2 V × VIN, and the drain current needs to be greater than 1.2 V × ILIMIT. 0.6 V × 300 μs × 5A/V CC 2 = MAGNITUDE (dB) LOW-SIDE MOSFET SELECTION 2 × π × 3.3 V × 2 × 32 μF × 50 kHz 09357-149 For the 1.2 V rail, the output capacitor ESR needs to be smaller than 12 mΩ, and the output capacitance needs to be larger than 191 µF. It is recommend that three pieces of 100 µF/X5R/6.3 V ceramic capacitor be used, such as the GRM32ER60J107ME20 from Murata, with an ESR = 2 mΩ. Figure 48. Bode Plot for 1.2 V Rail Rev. A | Page 24 of 32 Data Sheet ADP2323 EXTERNAL COMPONENTS RECOMMENDATION Table 12. Recommended External Components for Typical Applications with 3 A Output Current fSW (kHz) 300 600 1000 1 VIN (V) 12 12 12 12 12 12 12 5 5 5 5 5 5 12 12 12 12 12 5 5 5 5 5 5 12 12 12 12 5 5 5 5 5 5 VOUT (V) 1 1.2 1.5 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 1.5 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 L (µH) 3.3 4.7 4.7 4.7 6.8 10 10 3.3 3.3 3.3 4.7 4.7 4.7 2.2 3.3 3.3 4.7 4.7 1.5 1.5 2.2 2.2 2.2 2.2 1.5 2.2 2.2 3.3 1 1 1 1 1 1 COUT (µF) 1 330 330 330 2 × 100 100 + 47 100 + 47 100 330 330 330 2 × 100 100 + 47 100 2 × 100 100 + 47 2 × 47 2 × 47 47 2 × 100 2 × 100 100 + 47 2 × 47 2 × 47 2 × 47 100 47 47 47 2 × 100 100 + 47 2 × 47 2 × 47 47 47 RTOP (kΩ) 10 10 15 20 47.5 10 22 10 10 15 20 47.5 10 15 20 47.5 10 22 10 10 15 20 47.5 10 20 47.5 10 22 10 10 15 20 47.5 10 RBOT (kΩ) 15 10 10 10 15 2.21 3 15 10 10 10 15 2.21 10 10 15 2.21 3 15 10 10 10 15 2.21 10 15 2.21 3 15 10 10 10 15 2.21 RC (kΩ) 62 82 100 47 47 62 62 62 82 100 47 47 47 82 75 62 82 62 56 62 62 47 62 82 82 56 68 100 82 82 68 82 56 62 330 µF: 6.3 V, Sanyo 6TPD330M; 100 µF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 µF: 6.3 V, X5R, Murata GRM32ER60J476ME20. Rev. A | Page 25 of 32 CC (pF) 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 820 820 820 820 820 820 820 820 820 820 820 470 470 470 470 470 470 470 470 470 470 CCP (pF) 33 22 22 4.7 4.7 3.3 2.2 33 22 22 4.7 4.7 3.3 2.2 3.3 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 ADP2323 Data Sheet TYPICAL APPLICATION CIRCUITS RTOP1 10kΩ CDRV 1µF CIN1 10µF, 25V DL1 ADP2323 VOUT1 1.2V, 3A L1 2.2µH M1 FDS8880 COUT1 100µF COUT2 100µF COUT4 47µF COUT5 47µF COUT3 100µF PGND SW2 RTOP2 10kΩ CSS2 22nF M2 FDS8880 CBST2 0.1µF VOUT2 3.3V, 3A L2 4.7µH VIN 12V CIN2 10µF, 25V 09357-050 CC2 1000pF BST2 SS2 RC2 75kΩ PVIN2 RT EN2 DL2 COMP2 PGOOD2 PGOOD1 SYNC FB2 RBOT2 2.21kΩ CBST1 0.1µF SW1 GND ROSC 120kΩ BST1 EN1 PVIN1 CSS1 22nF SS1 COMP1 FB1 RC1 82kΩ INTVCC MODE SCFG TRK2 TRK1 VDRV CINT 1µF VIN 12V CC1 1000pF RBOT1 10kΩ Figure 50. Using External MOSFET Application, VIN1 = VIN2 = 12 V, VOUT1 = 1.2 V, IOUT1 = 3 A, VOUT2 = 3.3 V, IOUT2 = 3 A, fSW = 500 kHz RTOP1 22kΩ CIN1 10µF, 25V CC2 1.5nF RILIM2 47kΩ D2 B220A SW2 BST2 PVIN2 EN2 SS2 COMP2 FB2 DL2 RC2 47kΩ RTOP2 10kΩ COUT1 22µF COUT2 22µF COUT3 22µF COUT4 22µF CSS2 22nF CIN2 10µF, 25V CBST2 0.1µF L2 8.2µH VOUT2 3.3V, 1.5A VIN 12V 09357-051 RBOT2 2.21kΩ D1 B220A PGND GND MODE RT VOUT1 5V, 2A L1 8.2µH DL1 ADP2323 ROSC 100kΩ CBST1 0.1µF SW1 CDRV 1µF PGOOD2 PGOOD1 SYNC BST1 EN1 PVIN1 CSS1 22nF SS1 COMP1 FB1 RC1 75kΩ INTVCC SCFG TRK2 TRK1 VDRV CINT 1µF VIN 12V CC1 1.2nF RBOT1 3kΩ Figure 51. Using External Diode Application, VIN1 = VIN2 = 12 V, VOUT1 = 5 V, IOUT1 = 2 A, VOUT2 = 3.3 V, IOUT2 = 1.5 A, fSW = 600 kHz Rev. A | Page 26 of 32 Data Sheet ADP2323 RTOP1 20kΩ CC1 470pF RBOT1 10kΩ RC1 150kΩ VIN 12V CSS1 22nF CINT 1µF CDRV 1µF ADP2323 DL2 COUT1 100µF COUT2 100µF COUT3 100µF M2 FDS8880 SW2 SW2 BST2 PVIN2 PVIN2 SS2 EN2 TRK2 FB2 M1 FDS8880 PGND PGOOD2 GND VOUT1 1.8V, 6A L1 1µH DL1 MODE VDRV BST1 PVIN1 EN1 PVIN1 SS1 PGOOD1 SCFG SYNC INTVCC RT ROK2 100kΩ CBST1 0.1µF SW1 SW1 COMP2 ROSC 100kΩ TRK1 L2 1µH CBST2 0.1µF VIN 12V CIN2 10µF, 25V 09357-052 ROK1 100kΩ COMP1 FB1 CIN1 10µF, 25V Figure 52. Parallel Single Output Application, VIN = 12 V, VOUT = 1.8 V, IOUT = 6 A, fSW = 600 kHz RTOP1 22kΩ L1 3.3µH M1 DL1 ADP2323 VOUT1 5V, 2A COUT1 22µF M1 FDS6898A PGND SS2 RC2 82kΩ RTOP2 10kΩ CC2 390pF CSS2 22nF PVIN2 SW2 EN2 RT COMP2 DL2 FB2 PGOOD2 PGOOD1 SYNC CIN2 10µF, 25V COUT2 100µF CBST2 0.1µF L2 1µH COUT3 100µF VOUT2 1.0V, 3A 09357-053 RBOT2 15kΩ BST1 SS1 SW1 GND ROSC 50kΩ CBST1 0.1µF BST2 CDRV 1µF CIN1 10µF, 25V CSS1 22nF PVIN1 INTVCC MODE SCFG TRK2 TRK1 VDRV COMP1 FB1 RC1 62kΩ EN1 RBOT1 3kΩ CINT 1µF VIN 12V CC1 390pF Figure 53. Cascading Supply Application, VIN1 = 12 V, VOUT1 = 5 V, IOUT1 = 2 A, VOUT2 = 1 V, IOUT2 = 3 A, fSW = 1.2 MHz Rev. A | Page 27 of 32 ADP2323 Data Sheet RTOP1 20kΩ BST1 EN1 PVIN1 CBST1 0.1µF SW1 SCFG INTVCC MODE TRK2 TRK1 VDRV CDRV1 1µF CIN1 10µF, 25V CSS1 22nF SS1 COMP1 FB1 RC1 75kΩ SYNC CINT1 1µF VIN 12V CC1 820pF RBOT1 10kΩ DL1 ADP2323 VOUT1 1.8V, 3A L1 3.3µH M1 FDS8880 COUT1 100µF COUT2 47µF COUT3 47µF COUT4 47µF PGND GND DL2 RC2 82kΩ RTOP2 10kΩ CC2 820pF RTOP3 20kΩ BST2 PVIN2 EN2 CBST2 0.1µF BST1 PVIN1 EN1 SS1 COMP1 FB1 CIN1 10µF, 25V CSS3 22nF SW1 INTVCC MODE TRK2 TRK1 VDRV DL1 ADP2323 VOUT3 1.8V, 3A L3 3.3µH M3 FDS8880 COUT5 100µF COUT6 47µF CSS4 22nF COUT7 47µF COUT8 47µF SW2 BST2 PVIN2 M4 FDS8880 CIN4 10µF, 25V CBST4 0.1µF L4 4.7µH VOUT4 3.3V, 3A VIN 12V 09357-054 CC4 820pF EN2 DL2 RC4 82kΩ RTOP4 10kΩ CBST3 0.1µF PGND COMP2 FB2 RT VOUT2 3.3V, 3A L2 4.7µH VIN 12V CIN2 10µF, 25V SCFG GND PGOOD2 PGOOD1 SYNC RBOT4 2.21kΩ SW2 VIN 12V RC3 75kΩ SYNC ROSC2 120kΩ M2 FDS8880 CC3 820pF RBOT3 10kΩ CDRV2 1µF CSS2 22nF SS2 RBOT2 2.21kΩ CINT2 1µF SS2 COMP2 RT ROSC1 100kΩ FB2 PGOOD2 PGOOD1 Figure 54. Synchronization with 90° Phase Shift Between Each Channel Rev. A | Page 28 of 32 Data Sheet ADP2323 RTOP1 15kΩ RC2 75kΩ RBOT2 15kΩ BST1 EN1 PVIN1 SS1 RTOP2 47.5kΩ COUT1 47µF COUT2 47µF COUT4 47µF COUT5 47µF COUT3 47µF CSS2 22nF BST2 CBST2 0.1µF VOUT2 2.5V, 3A L2 3.3µH VIN 9V CIN2 10µF, 25V 09357-055 CC2 820pF M2 FDS8880 SW2 PVIN2 EN2 SS2 FB2 DL2 COMP2 RT M1 FDS8880 PGND GND MODE ROSC 100kΩ VOUT1 1.5V, 3A L1 2.2µH DL1 ADP2323 PGOOD2 PGOOD1 SYNC CBST1 0.1µF SW1 TRK1 VDRV CDRV 1µF CIN1 10µF, 25V CSS1 22nF COMP1 FB1 RC1 68kΩ INTVCC SCFG TRK2 CINT 1µF VIN 9V CC1 820pF RBOT1 10kΩ Figure 55. Enable PFM Mode with MODE Pin Pulled to GND, VIN1 = VIN2 = 9 V, VOUT1 = 1.5 V, IOUT1 = 3 A, VOUT2 = 2.5 V, IOUT2 = 3 A, fSW = 600 kHz REN_BOT REN_TOP 330kΩ 68kΩ RTOP1 10kΩ CDRV 1µF EN1 SS1 CSS1 22nF PVIN1 BST1 SYNC PGOOD2 PGOOD1 COMP1 RC1 100kΩ FB1 CINT 1µF CIN1 10µF, 25V CC1 1500pF RBOT1 2.21kΩ RPGOOD1 100kΩ VIN 12V SW1 INTVCC MODE SCFG TRK2 TRK1 VDRV DL1 ADP2323 DL2 CC2 1500pF CSS2 22nF M1 FDS8880 M2 FDS8880 SW2 BST2 PVIN2 EN2 SS2 COMP2 FB2 RC2 51kΩ RTOP2 20kΩ L1 8.2µH COUT1 100µF COUT2 100µF COUT3 100µF COUT4 100µF CIN2 10µF, 25V CBST2 0.1µF L2 5.6µH VOUT2 1.8V, 3A VIN 12V 09357-056 RBOT2 10kΩ RT VOUT1 3.3V, 3A PGND GND ROSC 200kΩ CBST1 0.1µF Figure 56. Programmable VIN_RISING = 8.7 V, VIN_FALLING = 6.7 V, 3.3 V Start Up Before 1.8 V, VIN1 = VIN2 = 12 V, VOUT1 = 3.3 V, IOUT1 = 3 A, VOUT2 = 1.8 V, IOUT2 = 3 A, fSW = 300 kHz Rev. A | Page 29 of 32 ADP2323 Data Sheet RTOP1 47.5kΩ RC1 68kΩ CIN1 10µF, 25V PGOOD2 BST1 EN1 SS1 CSS1 22nF PVIN1 TRK2 COMP1 FB1 RTRK_TOP 47.5kΩ RTRK_BOT 15kΩ VIN 12V CC1 1000pF RBOT1 15kΩ CBST1 0.1µF SW1 L1 4.7µH PGOOD1 SYNC INTVCC CINT 1µF DL1 ADP2323 TRK2 VOUT1 2.5V, 3A M1 FDS8880 COUT1 47µF COUT2 47µF COUT3 100µF COUT4 100µF PGND MODE SCFG DL2 VDRV CDRV 1µF M2 FDS8880 RTOP2 13kΩ CC2 1000pF BST2 PVIN2 SW2 CSS2 10nF CIN2 10µF, 25V CBST2 0.1µF L2 2.2µH VIN 12V Figure 57. Channel 2 Tracking with Channel 1 VIN1 = VIN2 = 12 V, VOUT1 = 2.5 V, IOUT1 = 3 A, VOUT2 = 1.25 V, IOUT2 = 3 A, fSW = 500 kHz Rev. A | Page 30 of 32 VOUT2 1.25V, 3A 09357-057 RC2 58kΩ EN2 FB2 RBOT2 12kΩ SS2 RT ROSC 120kΩ COMP2 GND Data Sheet ADP2323 OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 58. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP2323ACPZ-R7 ADP2323-EVALZ 1 Temperature Range −40°C to +125°C Output Voltage Adjustable Z = RoHS Compliant Part. Rev. A | Page 31 of 32 Package Description 32-Lead LFCSP_WQ Evaluation Board Package Option CP-32-7 ADP2323 Data Sheet NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09357-0-6/12(A) Rev. A | Page 32 of 32