Low Cost Instrumentation Amplifier AD622 Easy to use Low cost solution Higher performance than two or three op amp design Unity gain with no external resistor Optional gains with one external resistor (Gain range: 2 to 1000) Wide power supply range: ±2.6 V to ±15 V Available in 8-lead PDIP and 8-lead SOIC_N packages Low power, 1.5 mA maximum supply current DC performance 0.15% gain accuracy: G = 1 125 μV maximum input offset voltage 1.0 μV/°C maximum input offset drift 5 nA maximum input bias current 66 dB minimum common-mode rejection ratio: G = 1 Noise 12 nV/√Hz @ 1 kHz input voltage noise 0.60 μV p-p noise: 0.1 Hz to 10 Hz, G = 10 AC characteristics 800 kHz bandwidth: G = 10 10 μs settling time to 0.1% @ G = 1 to 100 1.2 V/μs slew rate APPLICATIONS PIN CONFIGURATION RG 1 8 RG –IN 2 7 +VS +IN 3 6 OUTPUT –VS 4 5 REF AD622 00777-001 FEATURES Figure 1. 8-Lead PDIP and 8-Lead SOIC_N (N and R Suffixes) GENERAL DESCRIPTION The AD622 is a low cost, moderately accurate instrumentation amplifier that requires only one external resistor to set any gain between 2 and 1000. For a gain of 1, no external resistor is required. The AD622 is a complete difference or subtracter amplifier system that also provides superior linearity and common-mode rejection by incorporating precision lasertrimmed resistors. The AD622 replaces low cost, discrete, two or three op amp instrumentation amplifier designs and offers good commonmode rejection, superior linearity, temperature stability, reliability, and board area consumption. The low cost of the AD622 eliminates the need to design discrete instrumentation amplifiers to meet stringent cost targets. While providing a lower cost solution, it also provides performance and space improvements. Transducer interface Low cost thermocouple amplifier Industrial process controls Difference amplifier Low cost data acquisition Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1996–2007 Analog Devices, Inc. All rights reserved. AD622 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation .........................................................................9 Applications....................................................................................... 1 Make vs. Buy: A Typical Application Error Budget..................9 Pin Configuration............................................................................. 1 Gain Selection ................................................................................. 11 General Description ......................................................................... 1 Input and Output Offset Voltage.............................................. 11 Revision History ............................................................................... 2 Reference Terminal .................................................................... 11 Specifications..................................................................................... 3 Input Protection ......................................................................... 11 Absolute Maximum Ratings............................................................ 5 RF Interference ........................................................................... 11 Thermal Resistance ...................................................................... 5 Ground Returns for Input Bias Currents ................................ 12 ESD Caution.................................................................................. 5 Outline Dimensions ....................................................................... 13 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 14 REVISION HISTORY 8/07—Rev. C to Rev. D Updated Format..................................................................Universal Added Thermal Resistance Section ............................................... 5 Added Figure 16................................................................................ 9 Added Large Input Voltages at Large Gains Section.................. 11 Replaced RF Interference Section ................................................ 11 Deleted Grounding Section........................................................... 10 Deleted Figure 16............................................................................ 10 Changes to Ground Returns for Input Bias Currents Section.. 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 4/99—Rev. B to Rev. C 8/98—Rev. A to Rev. B 2/97—Rev. 0 to Rev. A 1/96—Revision 0: Initial Version Rev. D | Page 2 of 16 AD622 SPECIFICATIONS TA = 25°C, VS = ±15 V, and RL = 2 kΩ typical, unless otherwise noted. Table 1. Parameter GAIN Gain Range Gain Error 1 G=1 G = 10 G = 100 G = 1000 Nonlinearity G = 1 to 1000 G = 1 to 100 Gain vs. Temperature VOLTAGE OFFSET Input Offset, VOSI Average Temperature Coefficient Output Offset, VOSO Average Temperature Coefficient Offset Referred to Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Average Temperature Coefficient Input Offset Current Average Temperature Coefficient INPUT Input Impedance Differential Common Mode Input Voltage Range 2 Over Temperature Conditions G = 1 + (50.5 k/RG) Typ 1 Max Unit 1000 VOUT = ±10 V 0.05 0.2 0.2 0.2 VOUT = ±10 V RL = 10 kΩ RL = 2 kΩ Gain = 1 Gain > 11 Total RTI Error = VOSI + VOSO/G VS = ±5 V to ±15 V VS = ±5 V to ±15 V VS = ±5 V to ±15 V VS = ±5 V to ±15 V VS = ±5 V to ±15 V 0.15 0.50 0.50 0.50 % % % % 10 −50 ppm ppm ppm/°C ppm/°C 125 1.0 1500 15 μV μV/°C μV μV/°C 10 10 60 600 80 95 110 110 100 120 140 140 2.0 3.0 0.7 2.0 dB dB dB dB 5.0 2.5 10||2 10||2 VS = ±2.6 V to ±5 V VS = ±5 V to ±18 V Over Temperature Common-Mode Rejection Ratio DC to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT Output Swing Min −VS + 1.9 −VS + 2.1 −VS + 1.9 −VS + 2.1 +VS – 1.2 +VS – 1.3 +VS – 1.4 +VS – 1.4 nA pA/°C nA pA/°C G Ω||pF GΩ||pF V V V V VCM = 0 V to ±10 V 66 86 103 103 RL = 10 kΩ VS = ±2.6 V to ±5 V Over Temperature VS = ±5 V to ±18 V Over Temperature Short Current Circuit 78 98 118 118 −VS + 1.1 −VS + 1.4 −VS + 1.2 −VS + 1.6 +VS – 1.2 +VS – 1.3 +VS – 1.4 +VS – 1.5 ±18 Rev. D | Page 3 of 16 dB dB dB dB V V V V mA AD622 Parameter DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.1% G = 1 to 100 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 10 G = 100 Current Noise 0.1 Hz to 10 Hz REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range 3 Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance Conditions Min Typ Max Unit 1000 800 120 12 1.2 kHz kHz kHz kHz V/μs 10 μs 12 72 nV/√Hz nV/√Hz 4.0 0.6 0.3 100 10 μV p-p μV p-p μV p-p fA/√Hz pA p-p 10 V step Total RTI Noise = √(e2ni) + (eno⁄G)2 f = 1 kHz 20 50 VIN+, VREF = 0 −VS + 1.6 60 +VS – 1.6 kΩ μA V ±18 1.3 1.5 V mA mA 1 ± 0.0015 ±2.6 VS = ±2.6 V to ±18 V 0.9 1.1 −40 to +85 1 Does not include effects of External Resistor RG. One input grounded, G = 1. 3 Defined as the same supply range that is used to specify PSR. 2 Rev. D | Page 4 of 16 °C AD622 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Supply Voltage Internal Power Dissipation1 Input Voltage (Common Mode) Differential Input Voltage2 Output Short Circuit Duration Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) 1 2 θJA is specified for the device in free air. Rating ±18 V 650 mW ±VS ±25 V Indefinite −65°C to +125°C −40°C to +85°C 300°C Table 3. Thermal Resistance Package Type 8-Lead PDIP (N-8) 8-Lead SOIC_N (R-8) ESD CAUTION Specification is for device in free air; see Table 3. May be further restricted for gains greater than 14. See the Input Protection section for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. D | Page 5 of 16 θJA 95 155 Unit °C/W °C/W AD622 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted. 50 1000 SAMPLE SIZE = 191 VOLTAGE NOISE (nV/ Hz) PERCENTAGE OF UNITS 40 30 20 GAIN = 1 100 GAIN = 10 10 GAIN = 100, 1000 10 –0.8 –0.4 0 0.4 0.8 1.2 OUTPUT OFFSET VOLTAGE (mV) 1 00777-002 0 –1.2 Figure 2. Typical Distribution of Output Offset Voltage 1 10 100 1k 10k 100k FREQUENCY (Hz) 00777-005 GAIN = 1000 BW LIMIT Figure 5. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000) 50 1000 SAMPLE SIZE = 383 CURRENT NOISE (fA/ Hz) PERCENTAGE OF UNITS 40 30 20 100 60 80 100 120 10 00777-003 0 140 COMMON-MODE REJECTION RATIO (dB) 1 100 1000 FREQUENCY (Hz) Figure 3. Typical Distribution of Common-Mode Rejection Figure 6. Current Noise Spectral Density vs. Frequency 2.0 140 120 1.5 100 G = 1000 G = 100 CMR (dB) G = 10 1.0 80 G=1 60 40 0.5 0 0 1 2 3 4 WARM-UP TIME (Minutes) 5 Figure 4. Change in Input Offset Voltage vs. Warm-Up Time 0 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 7. CMR vs. Frequency, RTI, 0 kΩ to 1 kΩ Source Imbalance Rev. D | Page 6 of 16 00777-007 20 00777-004 INPUT OFFSET VOLTAGE (µV) 10 00777-006 10 AD622 30 180 VS = ±15V G = 10 OUTPUT VOLTAGE SWING (V p-p) 160 120 G = 1000 100 G = 100 80 60 G = 10 40 20 10 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 0 10 100 1k 10k LOAD RESISTANCE (Ω) Figure 8. Positive PSR vs. Frequency, RTI (G = 1 to 1000) 00777-011 G=1 20 0.1 00777-008 POSITIVE PSR (dB) 140 Figure 11. Output Voltage Swing vs. Load Resistance 20 180 160 15 SETTLING TIME (µs) 120 100 G = 1000 80 G = 100 60 10 G=1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 0 0 5 10 15 20 OUTPUT STEP SIZE (V) Figure 9. Negative PSR vs. Frequency, RTI (G = 1 to 1000) 00777-012 G = 10 40 20 0.1 TO 0.1% 5 00777-009 NEGATIVE PSR (dB) 140 Figure 12. Settling Time vs. Step Size (G = 1) 1000 1000 SETTLING TIME (µs) 10 100 10 0.1 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 10. Gain vs. Frequency 1 1 10 100 GAIN Figure 13. Settling Time to 0.1% vs. Gain, for a 10 V Step Rev. D | Page 7 of 16 1000 00777-013 1 00777-010 GAIN (V/V) 100 AD622 10kΩ 0.01% INPUT 20V p-p 1kΩ POT 10kΩ 0.1% VOUT 100kΩ 0.1% 100 90 +VS 1kΩ 0.1% 2 100Ω 0.1% G = 1000 2V 5.62kΩ 8 3 Figure 14. Gain Nonlinearity, G = 1, RL = 10 kΩ (20 μV = 2 ppm) 4 Figure 15. Settling Time Test Circuit Rev. D | Page 8 of 16 6 5 –VS 00777-014 10µV 511Ω 51.1Ω 0% AD622 G=1 G = 100 G = 10 10 7 1 00777-015 11kΩ 0.1% Ø AD622 THEORY OF OPERATION The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has the following three important advantages: The AD622 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.5% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus insuring AD622 performance. • • Input Transistor Q1 and Input Transistor Q2 provide a single differential-pair bipolar input for high precision (see Figure 16). Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the Q1 and Q2 input devices, thereby impressing the input voltage across External Gain-Setting Resistor RG. This creates a differential gain from the inputs to the A1 and A2 outputs given by G = (R1 + R2)/RG + 1. Unity-Gain Subtracter A3 removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. 20µA VB MAKE vs. BUY: A TYPICAL APPLICATION ERROR BUDGET I2 20µA A1 The internal gain resistors, R1 and R2, are trimmed to an absolute value of 25.25 kΩ, allowing the gain to be programmed accurately with a single external resistor. A2 The AD622 offers cost and performance advantages over discrete two op amp instrumentation amplifier designs along with smaller size and fewer components. In a typical application shown in Figure 17, a gain of 10 is required to receive and amplify a 0 to 20 mA signal from the AD694 current transmitter. The current is converted to a voltage in a 50 Ω shunt. In applications where transmission is over long distances, line impedance can be significant so that differential voltage measurement is essential. Where there is no connection between the ground returns of transmitter and receiver, there must be a dc path from each input to ground, implemented in this case using two 1 kΩ resistors. The error budget detailed in Table 4 shows how to calculate the effect of various error sources on circuit accuracy. 10kΩ C2 C1 10kΩ A3 R3 400Ω R1 R2 Q1 Q2 R4 400Ω RG GAIN SENSE OUTPUT 10kΩ REF +IN GAIN SENSE 00777-021 –IN 10kΩ –VS Figure 16. Simplified Schematic of the AD622 + RL2 10Ω AD694 0 TO 20mA TRANSMITTER 0 TO 20mA 1kΩ 1/2 LT1013 VIN 50Ω RL2 10Ω 1kΩ 1kΩ RG 5.62kΩ AD622 REF 1/2 LT1013 – 1kΩ 9kΩ* 1kΩ* 1kΩ* 9kΩ* *0.1% RESISTOR MATCH, 50ppm/°C TRACKING 0 TO 20mA CURRENT LOOP WITH 50Ω SHUNT IMPEDANCE AD622 MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 9.986 Figure 17. Make vs. Buy Rev. D | Page 9 of 16 HOMEBREW IN-AMP, G = 10 00777-016 I1 • Open-loop gain is boosted for increasing programmed gain, thus reducing gain-related errors. The gain-bandwidth product (determined by C1, C2, and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. The input voltage noise is reduced to a value of 12 nV/√Hz, determined mainly by the collector current and base resistance of the input devices. AD622 The AD622 provides greater accuracy at lower cost. The higher cost of the homebrew circuit is dominated in this case by the matched resistor network. One could also realize a homebrew design using cheaper discrete resistors that are either trimmed or hand selected to give high common-mode rejection. This level of common-mode rejection, however, degrades significantly over temperature due to the drift mismatch of the discrete resistors. Note that for the homebrew circuit, the LT1013 specification for noise has been multiplied by √2. This is because a two op amp type instrumentation amplifier has two op amps at its inputs, both contributing to the overall noise. Table 4. Make vs. Buy Error Budget Error Source ABSOLUTE ACCURACY at TA = 25°C Total RTI Offset Voltage, μV Input Offset Current, nA CMR, dB AD622 Circuit Calculation Homebrew Circuit Calculation Total Error in ppm Relative to 1 V FS AD622 Homebrew 250 μV + 1500 μV/10 2.5 nA × 1 kΩ 86 dB→50 ppm × 0.5 V 800 μV × 2 15 nA × 1 kΩ (0.1% Match × 0.5 V)/10 V Total Absolute Error 400 2.5 25 427.5 1600 15 50 1665 DRIFT TO 85°C Gain Drift, ppm/°C Total RTI Offset Voltage, μV/°C Input Offset Current, pA/°C (50 ppm + 5 ppm) × 60°C (2 μV/°C + 15 μV/°C /10) × 60°C 2 pA/°C × 1 kΩ × 60°C (50 ppm)/°C × 60°C 9 μV/°C × 2 × 60°C 155 pA/°C × 1 kΩ × 60°C Total Drift Error 3300 210 0.12 3510.12 3000 1080 9.3 4089.3 RESOLUTION Gain Nonlinearity, ppm of Full Scale Typ 0.1 Hz to 10 Hz Voltage Noise, μV p-p 10 ppm 0.6 μV p-p 20 ppm 0.55 μV p-p × √2 Total Resolution Error Grand Total Error 10 0.6 10.6 3948 20 0.778 20.778 5775 Rev. D | Page 10 of 16 AD622 GAIN SELECTION The AD622 gain is resistor programmed by RG or, more precisely, by whatever impedance appears between Pin 1 and Pin 8. The AD622 is designed to offer gains as close as possible to popular integer values using standard 1% resistors. Table 5 shows required values of RG for various gains. Note that for G = 1, the RG pins are unconnected (RG = ∞). For any arbitrary gain, RG can be calculated by using the formula 50.5 k Ω G −1 To minimize gain error, avoid high parasitic resistance in series with RG. To minimize gain drift, RG should have a low temperature coefficient less than 10 ppm/°C for the best performance. Table 5. Required Values of Gain Resistors Desired Gain 2 5 10 20 33 40 50 65 100 200 500 1000 1% Std Table Value of RG, Ω 51.1 k 12.7 k 5.62 k 2.67 k 1.58 k 1.3 k 1.02 k 787 511 255 102 51.1 Calculated Gain 1.988 4.976 9.986 19.91 32.96 39.85 50.50 65.17 99.83 199.0 496.1 989.3 Large Input Voltages at Large Gains When operating at high gain, large differential input voltages may cause more than 6 mA of current to flow into the inputs. This condition occurs when the maximum differential voltage exceeds the following critical voltage: VCRITICAL = (400 + RG) × (6 mA) This is true for differential voltages of either polarity. The maximum allowed differential voltage can be increased by adding an input protection resistor in series with each input. The value of each protection resistor should be as follows: RPROTECT = (VDIFF_MAX − VCRITICAL)/6 mA RF INTERFERENCE RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance may appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass, RC network placed at the input of the instrumentation amplifier, as shown in Figure 18. In addition, this RC input network also provides additional input overload protection (see the Input Protection section). +VS 0.1µF INPUT AND OUTPUT OFFSET VOLTAGE The low errors of the AD622 are attributable to two sources: input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains and the output errors dominate at low gains. The total VOS for a given gain is calculated as follows: R 4.02kΩ CC 1nF R 4.02kΩ CD 47nF CC 1nF 10µF + +IN RG AD622 REF –IN 0.1µF 10µF –VS Total Error RTI = input error + (output error/G) VOUT + 00777-017 RG = separately. For longer time periods, the input current should not exceed 6 mA. For input overloads beyond the supplies, clamping the inputs to the supplies (using a diode such as a BAV199) reduces the required resistance, yielding lower noise. Figure 18. RFI Suppression Circuit for AD622 Series In-Amps Total Error RTO = (input error × G) + output error REFERENCE TERMINAL The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. The reference terminal provides a direct means of injecting a precise offset to the output, with an allowable range of 2 V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR. INPUT PROTECTION The filter limits the input signal bandwidth to the following cutoff frequencies: FilterFreq DIFF = FilterFreqCM = where CD ≥ 10CC. The AD622 features 400 Ω of series thin film resistance at its inputs and safely withstands input overloads of up to ±15 V or ±60 mA for up to an hour at room temperature. This is true for all gains and power on and off, which is particularly important because the signal source and amplifier can be powered Rev. D | Page 11 of 16 1 2π R(2C D + CC ) 1 2π RCC AD622 +VS Figure 18 shows an example where the differential filter frequency is approximately 400 Hz, and the common-mode filter frequency is approximately 40 kHz. With this differential filter in place and operating at gain of 1000, the typical dc offset shift over a frequency range of 1 Hz to 20 MHz is less than 1.5 μV RTI, and the RF signal rejection of the circuit is better than 71 dB. At a gain of 100, the dc offset shift is well below 1 mV RTI, and RF rejection is greater than 70 dB. 7 1 RG AD622 8 VOUT 6 5 3 LOAD 4 REF –VS TO POWER SUPPLY GROUND 00777-018 +IN Figure 19. Ground Returns for Bias Currents with Transformer Coupled Inputs +VS –IN 2 7 1 RG AD622 8 VOUT 6 5 3 LOAD 4 REF –VS TO POWER SUPPLY GROUND 00777-019 +IN GROUND RETURNS FOR INPUT BIAS CURRENTS Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents; therefore, when amplifying floating input sources such as transformers or ac-coupled sources, there must be a dc path from each input to ground as shown in Figure 19, Figure 20, and Figure 21. Refer to the Designer’s Guide to Instrumentation Amplifiers (free from Analog Devices, Inc.) for more information regarding in-amp applications. 2 Figure 20. Ground Returns for Bias Currents with Thermocouple Inputs +VS –IN 2 7 1 RG AD622 8 +IN 100kΩ 100kΩ 3 VOUT 6 5 LOAD 4 REF –VS TO POWER SUPPLY GROUND 00777-020 The input resistors should be selected to be high enough to isolate the sensor from the CC and C D capacitors but low enough not to influence system noise. Mismatch between R × CC at the positive input and R × CC at the negative input degrades the CMRR of the AD622. Therefore, the CC capacitors should be high precision types such as NPO/COG ceramics. The tolerance of the CD capacitor is less critical. –IN Figure 21. Ground Returns for Bias Currents with AC-Coupled Inputs Rev. D | Page 12 of 16 AD622 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 22. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 8 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 23. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. D | Page 13 of 16 012407-A 4.00 (0.1574) 3.80 (0.1497) AD622 ORDERING GUIDE Model AD622AN AD622ANZ 1 AD622AR AD622AR-REEL AD622AR-REEL7 AD622ARZ1 AD622ARZ-RL1 AD622ARZ-RL71 1 Temperature Range −40°C to +85°C −40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Z = RoHS Compliant Part. Rev. D | Page 14 of 16 Package Option N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 AD622 NOTES Rev. D | Page 15 of 16 AD622 NOTES ©1996–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00777-0-8/07(D) Rev. D | Page 16 of 16