a FEATURES 80 MHz Pipelined Operation 10-Bit D/A Converters RS-343A/RS-170 Compatible Outputs TTL Compatible Inputs +5 V CMOS Monolithic Construction 28-Pin SOIC Package APPLICATIONS High Definition Television (HDTV) High Resolution Color Graphics Digital Radio Modulation CAE/CAD/CAM Applications Image Processing Instrumentation Video Signal Reconstruction Direct Digital Synthesis (DDS) & I/O Modulation Wireless LAN Wireless Local Loop CMOS 80 MHz, 10-Bit Video DAC ADV7128 FUNCTIONAL BLOCK DIAGRAM FS ADJUST VREF VAA REFERENCE AMPLIFIER ADV7128 COMP CLOCK D0 D9 10 DATA REGISTER 10 DAC IOUT GND SPEED GRADES 80 MHz 50 MHz 30 MHz GENERAL DESCRIPTION The ADV7128 (ADV) is a video speed, digital-to-analog converter on a single monolithic chip. It consists of a high speed, 10-bit, video D/A converters; a standard TTL input interface; and a high impedance, analog output, current source. PRODUCT HIGHLIGHTS 1. Fast video refresh rate, 80 MHz. 2. Guaranteed monotonic to 10 bits. Ten bits of resolution allows for implementation of linearization functions such as gamma correction and contrast enhancement. The ADV7128 has a 10-bit pixel input port. A single +5 V power supply, an external 1.23 V reference and pixel clock input are and all that are required to make the part operational. 3. Compatible with a wide variety of high resolution color graphics systems including RS-343A/RS-170 and the proposed SMPTE 240M standard for HDTV. The ADV7128 is capable of generating video output signals which are compatible with RS-343A, RS-170 and most proposed production system HDTV video standards, including SMPTE 240M. 4. Combined with a numerically controlled oscillator (AD9955), it forms a complete frequency synthesizer (DDS). The ADV7128 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low power dissipation. The ADV7128 is available in a 28lead small outline IC (SOIC). 5. Using the parts reduced power output DAC modes, it is ideal for power and cost sensitive communications type applications. ADV is a registered trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 = +5 V 6 5%; V = +1.235 V; R = 37.5 V, C = 10 pF; R ADV7128–SPECIFICATIONS (VAll specifications T to T unless otherwise noted.) AA REF MIN Parameter STATIC PERFORMANCE Resolution Accuracy Integral Nonlinearity, INL Differential Nonlinearity, DNL Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 ANALOG OUTPUT Gray Scale Current Range Output Current White Level Black Level LSB Size Output Compliance, VOC Output Impedance, ROUT2 Output Capacitance, COUT2 VOLTAGE REFERENCE Voltage Reference Range, V REF Input Current, IVREF POWER REQUIREMENTS VAA IAA Power Supply Rejection Ratio 2 Power Dissipation DYNAMIC PERFORMANCE Glitch Impulse2, 3 DAC Noise2, 3, 4 K Version Units 10 Bits ±1 ±1 ±5 LSB max LSB max % Gray Scale max Binary 2 0.8 ±1 10 V min V max µA max pF max 15 22 mA min mA max 16.74 18.50 0 50 17.28 0 +1.4 100 30 mA min mA max µA min µA max µA typ V min V max kΩ typ pF max 1.14/1.26 –5 V min/V max mA typ 5 125 100 0.5 625 500 V nom mA max mA max %/% max mW max mW max 50 200 pV secs typ pV secs typ L L 1 MAX SET = 560 V. Test Conditions/Comments Guaranteed Monotonic Max Gray Scale Current = (VREF* 7,969/RSET) mA VIN = 0.4 V or 2.4 V Typically 17.62 mA Typically 5 µA IOUT = 0 mA VREF = 1.235 V for Specified Performance Typically 80 mA: 80 MHz Parts Typically 70 mA: 50 MHz & 35 MHz Parts Typically 0.12%/%: f = 1 kHz, COMP = 0.1 µF Typically 400 mW: 80 MHz Parts Typically 350 mW: 50 MHz & 30 MHz Parts NOTES 1 Temperature range (T MIN to TMAX); 0°C to +70°C. 2 Sample tested at +25°C to ensure compliance. 3 TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 4 This includes effects due to clock and data feedthrough. Specifications subject to change without notice. –2– REV. 0 ADV7128 TIMING CHARACTERISTICS1 (VAA = +5 V 6 5%; VREF = +1.235 V; RL = 37.5 V, CL = 10 pF; RSET = 560 V. All specifications TMIN to TMAX2 unless otherwise noted.) Parameter 80 MHz Version 50 MHz Version 30 MHz Version Units Conditions/Comments fMAX t1 t2 t3 t4 t5 t6 80 3 2 12.5 4 4 30 20 3 12 50 6 2 20 7 7 30 20 3 15 30 8 2 33.3 9 9 30 20 3 15 MHz max ns min ns min ns min ns min ns min ns max ns typ ns max ns typ Clock Rate Data & Control Setup Time Data & Control Hold Time Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time Analog Output Delay t7 t 83 Analog Output Rise/Fall Time Analog Output Transition Time NOTES 1 TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 2 Temperature range (T MIN to TMAX): 0°C to +70°C 3 Sample tested at +25°C to ensure compliance. Specifications subject to change without notice. t4 t5 CLOCK t3 t2 t1 DIGITAL INPUTS DATA D0–D9 t6 ANALOG OUTPUTS (I OUT ) t8 t7 NOTES 1. OUTPUT DELAY ( t6 ) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF THE CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. TRANSITION TIME ( t8 ) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. 3. OUTPUT RISE/FALL TIME ( t7 ) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. Figure 1. Video Input/Output Timing RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage REV. 0 Symbol Min VAA 4.75 TA RL VREF 0 1.14 Typ 5.00 37.5 1.235 Max ORDERING GUIDE Units 5.25 Volts +70 °C Ω Volts 1.26 Model Speed Accuracy Temperature DNL INL Range ADV7128KR80 80 MHz ± 1 ADV7128KR50 50 MHz ± 1 ADV7128KR30 30 MHz ± 1 *R = SOIC. –3– ±1 ±1 ±1 0°C to +70°C 0°C to +70°C 0°C to +70°C Package Option* R-28 R-28 R-28 ADV7128 ABSOLUTE MAXIMUM RATINGS * PIN CONFIGURATION VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V Voltage on Any Digital Pin . . . . . . GND –0.5 V to VAA +0.5 V Ambient Operating Temperature (TA) . . . . . . . . 0°C to +70°C Storage Temperature (TS) . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Vapor Phase Soldering (2 minutes) . . . . . . . . . . . . . . . +220°C IOUT to GND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA NOTES * Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. VAA 1 28 VAA D0 2 27 D1 3 26 VAA D2 4 25 RSET D3 5 24 D4 6 D5 7 ADV7128 22 VAA D6 8 TOP VIEW (Not to Scale) 21 IOUT VAA V REF 23 COMP D7 9 D8 10 20 19 GND 18 VAA D9 11 VAA 12 17 CLOCK VAA 13 16 VAA 14 15 VAA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7128 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. GND VAA WARNING! ESD SENSITIVE DEVICE PIN FUNCTION DESCRIPTION Pin Mnemonic CLOCK D0–D9 IOUT RSET COMP VREF VAA GND Function Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9, SYNC and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. Data inputs (TTL compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit. Unused data inputs should be connected to either the regular PCB power or ground plane. Current output. This high impedance current source is capable of directly driving a doubly terminated 75 Ω coaxial cable. Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOUT is given by: IOUT (mA) = 7,969 3 VREF(V)/RSET(Ω) Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor must be connected between COMP and VAA. Voltage reference input. An external 1.23 V voltage reference must be connected to this pin. The use of an external resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA. Analog power supply (5 V ± 5%). All VAA pins on the ADV7128 must be connected. Ground. All GND pins must be connected. –4– REV. 0 ADV7128 TERMINOLOGY Color Video (RGB) Reference Black Level This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. Reference White Level The maximum negative polarity amplitude of the video signal. Gray Scale The discrete levels of video signal between reference black and reference white levels. A 10-bit DAC contains 1024 different levels, while an 8-bit DAC contains 256. The maximum positive polarity amplitude of the video signal. Video Signal That portion of the composite video signal which varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion which may be visually observed. Raster Scan The most basic method of sweeping a CRT one line at a time to generate and display images. CIRCUIT DESCRIPTION AND OPERATION The ADV7128 contains one 10-bit D/A converter, with one input channel containing a 10-bit register. Also integrated on board the part is a reference amplifier. If we, therefore, have a graphics system with a 1024 × 1024 resolution, a noninterlaced 60 Hz refresh rate and a retrace factor of 0.8, then: Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz Digital Inputs Ten bits of data (color information) D0–D9 are latched into the device on the rising edge of each clock cycle. This data is presented to the 10-bit DAC and is then converted to an analog output waveform. See Figure 2. CLOCK The required CLOCK frequency is thus 78.6 MHz. All video data and control inputs are latched into the ADV7128 on the rising edge of CLOCK, as previously described in the “Digital Inputs” section. It is recommended that the CLOCK input to the ADV7128 be driven by a TTL buffer (e.g., 74F244). IOUT DIGITAL INPUTS D0–D9 DATA mA V 17.61 0.66 WHITE LEVEL ANALOG OUTPUTS IOUT 100 IRE 0 Figure 2. Video Data Input/Output 0 BLACK LEVEL NOTES All these digital inputs are specified to accept TTL logic levels. 1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD. Clock Input 2. V REF = 1.235V, R SET = 560Ω. The CLOCK input of the ADV7128 is typically the pixel clock rate of the system. It is also known as the dot rate. The dot rate, and hence the required CLOCK frequency, will be determined by the on-screen resolution, according to the following equation: Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/ (Retrace Factor) Horiz Res = Number of Pixels/Line. Vert Res = Number of Lines/Frame. Refresh Rate = Horizontal Scan Rate. This is the rate at which the screen must be refreshed, typically 60 Hz for a noninterlaced system or 30 Hz for an interlaced system. Retrace Factor = REV. 0 3. RS–343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS. Figure 3. IOUT Video Output Waveform Table I. Video Output Truth Table for the ADV7128 Description IOUT1 DAC Input Data WHITE LEVEL VIDEO VIDEO to BLACK BLACK LEVEL 17.62 video video 0 3FF data data 00H NOTE 1 Typical with full scale = 17.62 mA. V REF = 1.235 V, R SET = 560 Ω. Total Blank Time Factor. This takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8). –5– ADV7128 Reference Input An external 1.23 V voltage reference is required to drive the ADV7128. The AD589 from Analog Devices is an ideal choice of reference. It is a two-terminal, low cost, temperature compensated bandgap voltage reference which provides a fixed 1.23 V output voltage for input currents between 50 µA and 5 mA. Figure 4 shows a typical reference circuit connection diagram. The voltage reference gets its current drive from the ADV7128’s VAA through an on-board 1 kΩ resistor to the VREF pin. A 0.1 µF ceramic capacitor is required between the COMP pin and VAA. This is necessary so as to provide compensation for the internal reference amplifier. A resistance RSET connected between RSET and GND determines the amplitude of the output video level according to the following equation: IOUT (mA) = 7,969 × VREF(V)/RSET(Ω) (1) will develop RS-343A video output voltage levels across a 75 Ω monitor. IOUT ZO = 75Ω DAC (CABLE) ZL = 75Ω ZS = 75Ω (MONITOR) (SOURCE TERMINATION) Figure 5a. Analog Output Termination for RS-343A A suggested method of driving RS-170 video levels into a 75 Ω monitor is shown in Figure 5b. The output current level of the DAC remains unchanged, but the source termination resistance, ZS, on the DAC is increased from 75 Ω to 150 Ω. Using a variable value of RSET, as shown in Figure 4, allows for accurate adjustment of the analog output video levels. Use of a fixed 560 Ω RSET resistor yields the analog output levels as quoted in the specification page. These values typically correspond to the RS-343A video waveform values as shown in Figure 3. IOUT (CABLE) DAC ZS = 150Ω (SOURCE TERMINATION) ANALOG POWER PLANE ZO = 75Ω ZL = 75Ω (MONITOR) +5V 0.01µF COMP Figure 5b. Analog Output Termination for RS-170 VAA More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is available in an Application Note entitled “Video Formats & Required Load Terminations” available from Analog Devices, publication no. E1228-15-1/89. I REF ~ 5mA 1kΩ VREF TO DAC RSET 500Ω R SET 560Ω Figure 3 shows the video waveforms associated with the current output driving the doubly terminated 75 Ω load of Figure 5a. AD589 (1.235V VOLTAGE REFERENCE) Gray Scale Operation The ADV7128 can be used for stand-alone, gray scale (monochrome) or composite video applications (i.e., only one channel used for video information). 100Ω GND ADV7128 Video Output Buffer The ADV7128 is specified to drive transmission line loads, which is what most monitors are rated as. The analog output configurations to drive such loads are described in the Analog Interface section and illustrated in Figure 5. However, in some applications it may be required to drive long “transmission line” cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of output buffers will compensate for some cable distortion. Buffers with large full power bandwidths and gains between 2 and 4 will be required. These buffers will also need to be able to supply sufficient current over the complete output voltage swing. Analog Devices produces a range of suitable op amps for such applications. These include the AD84x series of monolithic op amps. In very high frequency applications (80 MHz), the AD9617 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets. *ADDITIONAL CIRCUITRY, INCLUDING DECOUPLING COMPONENTS, EXCLUDED FOR CLARITY Figure 4. Reference Circuit D/A Converter The ADV7128 contains a 10-bit D/A converter. The DAC is designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either the analog output (bit = “1”) or GND (bit = “0”) by a sophisticated decoding scheme. The use of identical current sources in a monolithic design guarantees monotonicity and low glitch. The on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations. Analog Output The analog output of the ADV7128 is a high impedance current source. The current output is capable of directly driving a 37.5 Ω load, such as a doubly terminated 75 Ω coaxial cable. Figure 5a shows the required configuration for the output connected into a doubly terminated 75 Ω load. This arrangement Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170. Altering the gain components of the buffer circuit will result in any desired video level. –6– REV. 0 ADV7128 Z2 The analog ground plane should encompass all ADV7128 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces and any output amplifiers. Z1 +VS 2 IOUT 7 The regular PCB ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the ADV7128. Z O = 75Ω 75Ω AD848 3 DAC 0.1µF (CABLE) 6 Power Planes 4 0.1µF ZL= 75Ω The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the ADV7128 (VAA) and all associated analog circuitry. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 7. This bead should be located within three inches of the ADV7128. (MONITOR) –V S ZS = 75Ω (SOURCE TERMINATION) GAIN (G) = 1+ Z1 Z2 Figure 6. AD848 As an Output Buffer PC Board Layout Considerations The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7128 power pins, voltage reference circuitry and any output amplifiers. The ADV7128 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7128 it is imperative that great care be given to the PC board layout. Figure 7 shows a recommended connection diagram for the ADV7128. The PCB power and ground planes should not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. The layout should be optimized for lowest noise on the ADV7128 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should be minimized so as to minimize inductive ringing. Supply Decoupling Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors. (See Figure 7.) Ground Planes Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of VAA should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. The ADV7128 and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 7. This bead should be located as close as possible (within 3 inches) to the ADV7128. COMP C6 0.1µF VIDEO DATA INPUTS ANALOG POWER PLANE VAA D0 L1 (FERRITE BEAD) D9 C3 0.1µF C4 0.1µF C5 0.1µF +5V (VCC ) VREF C2 10µF Z1 (AD589) ANALOG GROUND PLANE ADV7128 C1 33µF GND GROUND R SET 560Ω R1 75Ω L2 (FERRITE BEAD) COMPONENT RSET C1 C2 CLOCK IOUT VIDEO OUTPUT C3, C4, C5,C6 L1, L2 R1 R SET Z1 DESCRIPTION 0.1µF CERAMIC CAPACITOR FERRITE BEAD FAIR-RITE 274300111 OR 75Ω 1% METAL FILM RESISTOR MURATA BL01/02/03 DALE CMF-55C 560Ω 1% METAL FILM RESISTOR DALE CMF-55C 1.235V VOLTAGE REFERENCE ANALOG DEVICES AD589JH Figure 7. ADV7128 Typical Connection Diagram and Component List REV. 0 –7– VENDOR PART NUMBER 33µF TANTALUM CAPACITOR 10µF TANTALUM ADV7128 It is important to note that while the ADV7128 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three terminal voltage regulator. Analog Signal Interconnect The video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high frequency power supply rejection. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV7128 so as to minimize reflections. Digital Signal Interconnect The digital signal lines to the ADV7128 should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. C1760–24–1/93 The ADV7128 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. Additional information on PCB design is available in an application note entitled “Design and Layout of a Video Graphics System for Reduced EMI.” This application note is available from Analog Devices, publication number E1309-15-10/89. Due to the high clock rates used, long clock lines to the ADV7128 should be avoided so as to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). SOIC (R-28) 15 28 0.299 (7.60) 0.291 (7.40) 0.419 (10.65) 0.394 (10.00) PIN 1 1 14 0.712 (18.10) 0.697 (17.70) 0.104 (2.65) 0.093 (2.35) 0.050 (1.27) BSC 0.019 (0.49) 0.014 (0.35) 0.05 (1.27) 0.016 (0.40) PRINTED IN U.S.A. 0.011 (0.30) 0.004 (0.10) 0.012 (0.32) 0.009 (0.23) –8– REV. 0