ISM Band FSK Receiver IC ADF7902 FEATURES GENERAL DESCRIPTION Single-chip, low power UHF receiver Companion receiver to ADF7901 transmitter Frequency range: 369.5 MHz to 395.9 MHz Eight RF channels selectable with three digital inputs Modulation parameters supported FSK demodulation 2 kbps data rate 34.8 kHz frequency deviation 5.0 V supply voltage Low power consumption 18.5 mA with receiver enabled 1 μA standby current 24-lead TSSOP The ADF7902 is a low power UHF receiver. The device demodulates frequency shift keyed (FSK) signals with 34.8 kHz frequency deviation and at data rates of up to 2 kbps. There are eight specific RF channels ranging from 369.5 MHz to 395.9 MHz on which the receiver can operate. Each channel is selectable by configuring three digital control lines. The ADF7902 is designed for low power applications, consuming 18.5 mA (typical) during normal operation and 1 μA (maximum) in standby mode. FUNCTIONAL BLOCK DIAGRAM GND CE ADF7902 LNA_1 FSK DEMODULATOR IF FILTER LNA LNA_2 VBAT2 CREG2 LDO1 CH1_SEL N DIVIDER SELECT CH3_SEL VCO LNA_RSET CH2_SEL LDO2 CP PFD OSC BIAS RSET CLKOUT CLKOUT_ENB CVCO VCOIN CPOUT OSC1 OSC2 06456-001 VBAT1 CREG1 Rx_DATA Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADF7902 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Applications Information .................................................................7 Functional Block Diagram .............................................................. 1 Applications Circuits ....................................................................7 Revision History ............................................................................... 2 Test Modes..........................................................................................9 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 10 Absolute Maximum Ratings............................................................ 4 Ordering Guide .......................................................................... 10 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 REVISION HISTORY 1/07—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADF7902 SPECIFICATIONS VDD =5.0 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Typical specifications TA = 25°C. Table 1. Parameter CHANNEL FREQUENCIES Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 RECEIVER PARAMETERS Data Rate Frequency Deviation Min Input Sensitivity LNA Input Impedance CHANNEL FILTERING IF Filter Bandwidth Adjacent Channel Rejection PHASE-LOCKED LOOP CE High to Receive Data REFERENCE INPUT Crystal Reference INPUT LOGIC LEVELS Input High Voltage, VIH Input Low Voltage, VIL OUTPUT LOGIC LEVELS Output High Voltage, VOH Output Low Voltage, VOL Output Drive Level POWER SUPPLY Voltage Supply VDD Current Consumption Receiver Enabled Low Power Sleep Mode Typ Max Unit 369.5 371.1 375.3 376.9 388.3 391.5 394.3 395.9 MHz MHz MHz MHz MHz MHz MHz MHz 2 −34.8 +34.8 −110 128 − j125 kbps kHz kHz dBm Ω 200 60 kHz dB 4 ms 9.8304 MHz 0.7 × VDD 0.2 × VDD V V 0.4 2 V V mA 4.5 5 Test Conditions Data = 0 Data = 1 fRF = 388.3 MHz −3 dB bandwidth 1 MHz offset Desired signal 3 dB above input sensitivity level, with interferer power increased until BER = 10−3 ±25 ppm frequency accuracy V 18.5 1 mA μA Rev. 0 | Page 3 of 12 CE = 1 CE = 0 ADF7902 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VBAT to GND 1 Digital I/O Voltage to GND LNA_1, LNA_2 Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to +6.0 V −0.3 V to VBAT + 0.3 V 0 dBm −40°C to +85°C −40°C to +125°C 125°C 150.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 235°C 240°C GND = GND1 = GND1B = GND2 = 0 V. Rev. 0 | Page 4 of 12 ADF7902 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CREG2 1 24 VCOIN TEST 2 23 GND2 VBAT2 3 22 CVCO CE 4 21 RSET GND1 6 ADF7902 20 LNA_RSET CH1_SEL 19 LNA_1 TOP VIEW 7 (Not to Scale) 18 LNA_2 CH2_SEL 8 17 CREG1 CLKOUT 9 16 VBAT1 CH3_SEL 10 15 OSC1 CLKOUT_ENB 11 14 OSC2 CPOUT 12 13 GND1B 06456-002 Rx_DATA 5 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic CREG2 2 3 TEST VBAT2 4 5 6 7 8 9 CE Rx_DATA GND1 CH1_SEL CH2_SEL CLKOUT 10 11 CH3_SEL CLKOUT_ENB 12 CPOUT 13 14 GND1B OSC2 15 OSC1 16 VBAT1 17 CREG1 18 LNA_2 19 20 21 22 LNA_1 LNA_RSET RSET CVCO 23 24 GND2 VCOIN Description A 0.1 μF capacitor should be added at CREG2 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but may cause higher spurs. Test Output Pin. Leave as no connect. 5 V Power Supply for RF Circuitry. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. Chip Enable Input. Driving CE low puts the part into power-down mode, drawing <1 μA. Receiver Output. Demodulated data appears on this pin. Ground for Digital Circuitry. Channel Select Pin. This represents the LSB of the channel select pins. Channel Select Pin. Square Wave Clock Output at the Crystal Frequency. This can be used to drive the OSC2 pin of a partnering ADF7902. The output has a 50:50 mark-space ratio and switches between 0 V and 2.2 V. If CLKOUT is disabled by setting Pin 11 high, then CLKOUT must be tied low. Channel Select Pin. CLKOUT Enable Input. This should be driven low to enable the reference clock signal to appear on the CLKOUT pin. Driving the pin high removes the clock signal on CLKOUT. It should be driven high when an external reference is used. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Ground for Digital Circuitry. The reference crystal should be connected between this pin and OSC1. The necessary crystal load capacitor should be tied between this pin and ground. A square wave signal can be applied to this pin as an external reference source. The reference crystal should be connected between this pin and OSC2. The necessary crystal load capacitor should be tied between this pin and ground. This pin should be connected to ground when OSC2 is driven by an external reference. 5 V Power Supply for Digital Circuitry. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. A 0.1 μF capacitor should be added at CREG1 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but may cause higher spurs. LNA Input. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. Complementary LNA Input. External Bias Resistor for LNA. A value of 1.1 kΩ is recommended. External Resistor to Set Charge Pump Current and Some Internal Bias Currents. A value of 3.6 kΩ is recommended. Voltage Controlled Oscillator (VCO) Capacitor. A 22 nF capacitor should be placed between this pin and CREG2 to reduce VCO noise. Ground for RF Circuitry. The tuning voltage on this pin determines the output frequency of the VCO. The higher the tuning voltage, the higher the output frequency. The output of the loop filter is connected here. Rev. 0 | Page 5 of 12 ADF7902 TYPICAL PERFORMANCE CHARACTERISTICS 0 70 CARRIER ONLY INTERFERER SIGNAL –2 40 –3 FSK INTERFERER SIGNAL 20 –5 10 –6 0 –7 –10 375.5 376.0 376.50 377.0 377.5 378.0 –8 –125 378.5 Figure 3. Narrow-Band Interference Rejection Plot CARRIER ONLY INTERFERER SIGNAL 80 60 FSK INTERFERER SIGNAL 40 06456-004 20 365 375 –115 –110 Figure 5. Sensitivity Plot 100 0 355 –120 RF INPUT LEVEL (dBm) FREQUENCY (MHz) REJECTION (dB) –4 06456-005 LOG (BER) 50 30 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 –1 06456-003 REJECTION (dB) 60 385 395 FREQUENCY (MHz) Figure 4. Wideband Interference Rejection Plot Rev. 0 | Page 6 of 12 –105 –100 ADF7902 APPLICATIONS INFORMATION Table 4. Channel Frequency Truth Table CH1_SEL 0 1 0 1 0 1 0 1 CH2_SEL 0 0 0 1 1 0 1 1 CH3_SEL 0 0 1 0 0 1 1 1 Channel Frequency (MHz) 369.5 371.1 375.3 376.9 388.3 391.5 394.3 395.9 APPLICATIONS CIRCUITS 22nF VCOIN CREG2 TEST 5V GND2 ADF7902 VBAT2 MICROCONTROLLER 0.1µF RSET CE 62pF Rx_DATA GND1 5V LNA_RSET LNA_2 CH2_SEL CREG1 CLKOUT VBAT1 CH3_SEL OSC1 CLKOUT_ENB OSC2 CPOUT GND2 15nF 3.6kΩ 1.1kΩ MATCHING 10pF LNA_1 CH1_SEL 3.3kΩ 680pF 820Ω ANTENNA CVCO 68nH 5V 3.9pF 0.1µF 62pF 9.8304MHz 33pF 33pF 0.1µF CRYSTAL LOOP FILTER 150pF Figure 6. Single Receiver Applications Circuit Rev. 0 | Page 7 of 12 06456-006 0.1µF ADF7902 22nF VCOIN CREG2 0.1µF 5V MICROCONTROLLER 0.1µF ADF7902 TEST 62pF GND2 (Rx1) VBAT2 CVCO CE RSET Rx_DATA LNA_RSET GND1 3.6kΩ 1.1kΩ MATCHING 6.8pF LNA_1 CH1_SEL LNA_2 CH2_SEL CREG1 CLKOUT VBAT1 CH3_SEL OSC1 CLKOUT_ENB OSC2 CPOUT GND2 62nH 5V 3.9pF 0.1µF 62pF Y1 33pF 0.1µF 33pF ANTENNA CRYSTAL 3.3kΩ 680pF 820Ω LOOP FILTER 15nF 150pF 22nF VCOIN CREG2 0.1µF TEST 5V (Rx2) CVCO RSET CE 62pF Rx_DATA GND1 5V LNA_RSET LNA_2 CH2_SEL CREG1 CLKOUT VBAT1 CH3_SEL OSC1 CLKOUT_ENB OSC2 CPOUT GND2 15nF MATCHING 1.1kΩ 10pF LNA_1 CH1_SEL 3.3kΩ 680pF 820Ω 3.6kΩ 68nH 5V 0.1µF 3.9pF 62pF 0.1µF LOOP FILTER 150pF 06456-007 0.1µF GND2 ADF7902 VBAT2 Figure 7. Dual Receiver Applications Circuit Rev. 0 | Page 8 of 12 ADF7902 TEST MODES If CLKOUT_ENB is tied high, CLKOUT is disabled. The CLKOUT pin is reconfigured as a test enable input. If the CLKOUT pin is then tied low, the part operates as is normal with CLKOUT off. If it is tied high (2.2 V), the part is in test mode. Test mode is described in Table 5. When CLKOUT_ENB = 0, RSSI appears on the test output pin (Pin 2), and CLKOUT is configured as an output with a 9.8 MHz clock coming out. When test mode is enabled, the channel frequency is set to 369.5 MHz (Channel 1). Table 5. Test Modes CH1_SEL 0 0 0 0 1 1 1 1 CH2_SEL 0 0 1 1 0 0 1 1 CH3_SEL 0 1 0 1 0 1 0 1 Test Mode agc gain is set to maximum (filti is also set to maximum on test output pin) filti on test output pin filtq on test output pin Charge pump output is set to maximum (test pin is also tri-state) Charge pump output is set to minimum (also n-divider output ÷ 2 on test output pin) Charge pump is tri-state (test pin is also tri-state) n-divider output ÷ 2 on test output pin Recovered data clock on test output pin Rev. 0 | Page 9 of 12 ADF7902 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 6.40 BSC 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 8. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model ADF7902BRUZ 1 ADF7902BRUZ-RL1 ADF7902BRUZ-RL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP], 13’’ REEL 24-Lead Thin Shrink Small Outline Package [TSSOP], 7’’ REEL Z = Pb-free part. Rev. 0 | Page 10 of 12 Package Option RU-24 RU-24 RU-24 ADF7902 NOTES Rev. 0 | Page 11 of 12 ADF7902 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06456-0-4/07(0) Rev. 0 | Page 12 of 12