INTEGRATED CIRCUITS DATA SHEET UAA1570HL Global Positioning System (GPS) front-end receiver circuit Product specification File under Integrated Circuits, IC18 1999 May 10 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING INFORMATION 7 FUNCTIONAL DESCRIPTION 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.2 Low noise amplifiers LNA1 and LNA2 LNA1IN LNA1OUT LNA2IN LNA2OUT MX1IN General remarks and results Correlation of the UAA1570HL data sheet, application and test boards RF mixer with preamplifier VCO First IF filter Second IF mixer Second IF filter Time and amplitude quantization Clock inputs CMOS to ECL sample clock squaring circuit Time quantization (sampler) TTL output stage 1-bit delays Programmable synthesizer VCO prescaler Main synthesizer dividers (N-path) Second local oscillator dividers (L-path) Reference dividers (R-path) Serial interface p0 and p1 r5 r0, r1, r2, r3 and r4 n7 n0, n1, n2, n3, n4, n5 and n6 l0, l1, l2 and l3 The serial interface word The default frequency plan Phase detector, charge pump and loop filter 7.3 7.4 7.5 7.6 7.7 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.10 7.10.1 7.10.2 7.10.3 7.10.4 7.10.5 7.10.6 7.11 7.12 7.13 1999 May 10 8 OPERATING MODE SELECTION TABLES 8.1 Manual selection operating modes 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 DC CHARACTERISTICS 12 AC CHARACTERISTICS 13 CHARACTERIZATION TEST CIRCUIT 14 DEFAULT APPLICATION AND DEMONSTRATION BOARD 15 INTERNAL CIRCUITRY 16 PACKAGE OUTLINE 17 SOLDERING 17.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 17.2 17.3 17.4 17.5 2 UAA1570HL 18 DEFINITIONS 19 LIFE SUPPORT APPLICATIONS Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 1 2 FEATURES • Complete single-chip programmable double-superheterodyne C/A-code GPS receiver UAA1570HL GENERAL DESCRIPTION The UAA1570HL is a complete single-chip double-superheterodyne receiver front-end intended for GPS and GLONASS navigation systems. The IC includes a programmable on-chip DPLL synthesizer, VCO with external varactor and resonator, a 1-bit amplitude quantizer and a time sampled TTL/CMOS compatible SIGN output bit driver. It can be used with either an active or passive antenna system by disabling or enabling the on-chip LNAs and is ideally suited for low power GPS receiver applications because of its 3 V supply and the power management features through control pins. • Programmable high IF frequencies supporting wideband/P-code GPS and Global Navigation Satellite System (GLONASS) applications • Supports frequency plans with a 2nd IF of 4 × f0(1.023 MHz) = 4.092 MHz • 48-pin LQFP package • −40 to +85 °C operating temperature range • 2.7 V minimum supply voltage • Low DC power consumption [57 mA typical with both Low-Noise Amplifiers (LNAs) active] Programmable prescaler controls provide the flexibility of using different frequency schemes. • Power-down mode (<900 µA) The UAA1570HL is optimized to provide SIGN bit data to the companion Philips part, the SAA1575HL baseband digital signal processor. The SAA1575HL can provide the sample clock input to the UAA1570HL by dividing a TTL/CMOS level reference clock signal down to a programmable sampling clock output frequency. Both ICs can also be used independently. • Typical receiver noise figure at 1.57542 GHz: 4.5 dB • Typical phase noise −72 dBc/Hz at 10 kHz offset • Simple microstrip LNA1/2 and first mixer matching • Single pin VCO with external varactor and resonator • Digital Phase Locked Loop (DPLL) synthesizer with programmable VCO, 2nd Local Oscillator (LO) and reference dividers The UAA1570HL is supplied in a low profile, 48-pin LQFP package for excellent Radio Frequency (RF) performance and small size. • 3-bit synthesizer and power-down control input • Reference and independent sample clock input with internal squaring • 1-bit amplitude quantized and time sampled TTL/CMOS compatible output driver • High active gain supporting SAW filter applications • Configurable for external first LNA applications. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UAA1570HL LQFP48 1999 May 10 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm 3 VERSION SOT313-2 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL 4 QUICK REFERENCE DATA VCCA = VDDD = 3 V; Tamb = 25 ±2 °C; unless otherwise specified. SYMBOL PARAMETER VCCA analog supply voltage VDDD digital supply voltage CONDITIONS MIN. 2.7 TYP. 3 MAX. 5 UNIT V 2.7 3 5 V IVCCA + IVDDD analog supply current plus digital supply current VCCA and VDDD = 2.7 V − 55.1 62.3 mA VCCA and VDDD = 5 V − 61 69.3 mA GRF available RF power gain LNAs at 1.57542 GHz − 31 − dB GIF1 available 1st mixer power gain MX1 at 1.57542 GHz − 17.7 − dB GIF2 available 2nd mixer power gain MX2 at 41.8 MHz − 21.4 − dB Gv(lim) limiter voltage gain to 1st latch limiter at 3.48 MHz − 78 − dBV ∆Vlim(M) differential limiter sensitivity (peak value) f = 3.48 MHz − 100 − µV FRX receiver noise figure f = 1.57542 GHz − 4.5 5.2 dB Tamb operating ambient temperature 1999 May 10 VCCA and VDDD = 3.3 to 5 V −40 +25 +85 °C VCCA and VDDD = 3 to 5 V −30 +25 +85 °C VCCA and VDDD = 2.7 to 5 V 0 +25 +85 °C 4 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 48 47 46 45 44 43 42 41 LNA2GND1 LNA2IN BIASGND2 LNA2GND2 LNA2OUT CLOCK REFIN VCCA(VCO) TANK VCOGND P12GND 1 UAA1570HL SCLK 37 SQUARING CIRCUIT 35 33 LNA2 5 31 DIVIDE-BY-2 6 8 38 DIVIDE-BY-1 or 2 3 7 PLLGND P39GND 39 36 2 4 40 PHASE FREQUENCY DETECTOR LNA1 VCCA(LNA2) COMP P41GND P42GND LNA1GND1 LNA1IN LNA1OUT LNA1GND2 handbook, full pagewidth VCCA(LNA1) BLOCK DIAGRAM BIASGND1 5 UAA1570HL to data register DIVIDE-BY-1 or 2 SQUARING CIRCUIT DIVIDE-BY-R(1) (4 to 31) DATA REGISTER FOR PROGRAMMING DIVIDE-BY-N(1) (64 to 127) 34 DIVIDE-BY-3 30 29 9 10 32 QUANTIZER DIVIDE-BY-2 VCO 28 27 11 DIVIDE-BY-L(1) (4 to 15) 12 to data register MIXER 1 13 14 15 16 17 18 23 26 DIVIDE-BY-2 25 MIXER 2 19 20 21 22 24 Shaded blocks are NOT active during synthesizer state. (1) The default values are: L = 10, N = 71 and R = 4. Fig.1 Block diagram. 1999 May 10 5 IF2P IF2INP IF2INN MX2GND VCCA(MX2) STROBE IF1N IF1P VCCA(MX1P) MX1GND MX1IN MXPGND MHB269 VCCA(PLL) DGND VDDD VCCA(LIM) DATA SIGN BFCP LIMINP LIMINN BFCN LIMGND IF2N Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 6 UAA1570HL PINNING INFORMATION SYMBOL PIN VOLTAGE TYPICAL VALUES (V) PIN VCC = 2.7 V DESCRIPTION VCC = 5 V VCCA(LNA2) 1 2.7 5 LNA2 power supply: DC operation range 2.7 to 5 V; use close proximity RF decoupling to pins 2, 4 and 5 LNA2GND1 2 0 0 LNA2 ground 1: minimize RF ground inductance LNA2IN 3 0.815 0.807 LNA2 input: use external RF AC coupling BIASGND2 4 0 0 LNA2 bias circuit ground: minimize RF ground inductance LNA2GND2 5 0 0 LNA2 ground 2: minimize RF ground inductance LNA2OUT 6 1.48 3.629 LNA2 output: use external RF AC coupling. The DC voltage is approximately 1.3 V below the VCCA(LNA2) supply on pin 1. CLOCK 7 CMOS level CMOS level Serial interface clock input: this DC coupled CMOS CLOCK input moves 20-bit programming words into the synthesizer DATA input register while the STROBE is LOW. A DC short-circuit to ground is recommended with the default frequency plan. REFIN 8 1.69 3.99 Reference input: use external AC coupling. The DC voltage is approximately 1 V below the VCCA(PLL) supply on pin 36. VCCA(VCO) 9 2.7 5 VCO power supply: DC operation range 2.7 to 5 V; use critical close proximity RF decoupling to pin 11 TANK 10 1.92 1.92 VCO negative impedance resonator port: use the absolute minimum trace lengths and widths and keep the loop to the VCO ground pin 11 as short as possible, while centring the COMP output voltage at pin 40 within the charge pump output voltage range given in Chapter 11 by adjusting the resonator inductance and/or required AC coupling component. VCOGND 11 0 0 VCO ground: minimize RF ground inductance; use critical close proximity RF decoupling to VCO supply pin 9 P12GND 12 0 0 this pin provides additional RF shielding and has to be connected to ground MXPGND 13 0 0 RF mixer preamplifier ground: minimize RF ground inductance MX1IN 14 0.82 0.81 RF mixer preamplifier input: use external AC coupling and RF matching MX1GND 15 0 0 RF mixer ground: minimize RF ground inductance; use critical close proximity RF decoupling to VCCA(MX1P) supply pin 16 VCCA(MX1P) 16 2.7 5 RF preamplifier/mixer power supply: DC operation range 2.7 to 5 V; use critical close proximity RF decoupling to pin 15 IF1P 17 2.7 5 RF mixer IF positive output: DC couple this output pin to the VCCA(MX1P) supply through first IF filter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced first mixer IF1 outputs are recommended. Prevent externally squared reference harmonics from entering the first IF signal path or components. 1999 May 10 6 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL PIN VOLTAGE TYPICAL VALUES (V) PIN VCC = 2.7 V UAA1570HL DESCRIPTION VCC = 5 V IF1N 18 2.7 5 RF mixer IF negative output: DC couple this output pin to the VCCA(MX1P) supply through first IF filter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced first mixer IF1 outputs are recommended. Prevent externally squared reference harmonics from entering the first IF signal path or components. VCCA(MX2) 19 2.7 5 IF mixer power supply: if present, decouple the common VCC line sourcing the first and second mixer by placing a large decoupling capacitor between the two MX2GND 20 0 0 IF mixer ground: minimize IF ground inductance; use close proximity IF decoupling to the VCCA(MX2) supply pin 19 IF2INN 21 0.983 0.98 IF mixer negative input: use external AC coupling. Balanced IF1 second mixer inputs are recommended. Prevent externally squared reference harmonics from entering the first IF signal path or components. IF2INP 22 0.983 0.98 IF mixer positive input: use external AC coupling. Balanced IF1 second mixer inputs are recommended. Prevent externally squared reference harmonics from entering the first IF signal path or components. STROBE 23 CMOS level CMOS level Serial interface strobe input: a LOW level on this DC-coupled CMOS STROBE input enables the CLOCK input to load the 20-bit programming word into the synthesizer input DATA register. A mandatory DC short-circuit to ground is required to ensure that the default frequency plan is invoked on power-up. IF2P 24 2.7 5 IF mixer second IF positive output: DC couple this output pin to the VCCA(MX2) supply through second IF filter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced second mixer IF2 outputs are optional for many applications. Short the unused IF2P or IF2N output directly to the supply in single-ended applications. IF2N 25 2.7 5 IF mixer second IF negative output: DC couple this output pin to the VCCA(MX2) supply through second IF filter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced second mixer IF2 outputs are optional for many applications. Short the unused IF2P or IF2N output directly to the supply in single-ended applications. LIMGND 26 0 0 Limiter ground: minimize ground inductance BFCN 27 1.696 3.999 Negative limiter input DC feedback loop decoupling: AC couple this pin to ground in close proximity to the pin. The DC voltage is approximately 1 V below the VCCA(LIM) supply on pin 31. No DC coupling. LIMINN 28 1.696 3.999 Negative limiter input: AC couple this pin to the second IF filter output or to ground if unused with single-ended filter applications. The DC voltage is approximately 1 V below the VCCA(LIM) supply on pin 31. No DC coupling. 1999 May 10 7 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL PIN VOLTAGE TYPICAL VALUES (V) PIN VCC = 2.7 V UAA1570HL DESCRIPTION VCC = 5 V LIMINP 29 1.696 3.999 Positive limiter input: AC couple this pin to the second IF filter output or to ground if unused with single-ended filter applications. The DC voltage is approximately 1 V below the VCCA(LIM) supply on pin 31. No DC coupling. BFCP 30 1.696 3.999 Positive limiter input DC feedback loop decoupling: AC couple this pin to ground in close proximity to the pin. The DC voltage is approximately 1 V below the VCCA(LIM) supply on pin 31. No DC coupling. VCCA(LIM) 31 2.7 5 Limiter, sample clock squaring and sampler Emitter Coupled Logic (ECL) circuits power supply: decouple in close proximity to pins 26 and 31. If present, isolate from the common VCC line sourcing the first and second mixer by placing a large decoupling capacitor between this block and the mixers. DATA 32 CMOS level CMOS level Serial interface data input: this DC-coupled CMOS DATA input accepts 20-bit programming words into the synthesizer data input register, while the STROBE is LOW, on the rising edge of the CLOCK input. A DC short-circuit to ground is recommended with the default frequency plan. VDDD 33 2.7 5 SIGN bit TTL output driver power supply: critically isolate and (independent (independent separately decouple this digital VDDD supply from all other of VCC level) of VCC level) analog (VCCA) supplies. Maintain minimum trace lengths to decoupling components. Particular attention should be applied to prevent coupling into VCCA(LIM) pin 31. If SAA1575HL is used, use the digital supply from the back-end. SIGN 34 TTL output TTL output Amplitude and time quantized second IF output signal: extreme care should be taken to isolate this sampled TTL output signal from all analog traces and components, particularly the second IF filter components at the limiter input. Avoid coupling into the reference oscillator signal trace. DGND 35 0 0 SIGN bit TTL output driver sink ground: critically isolate this digital supply ground from all other analog supplies and grounds. Maintain minimum trace lengths to decoupling components. VCCA(PLL) 36 2.7 5 Synthesizer power supply: decouple in close proximity to pin 38 SCLK 37 1.34 2.5 Sample clock squaring input: accepts LOW-level AC coupled sample clock inputs directly from the PLL reference oscillator or DC-coupled externally squared digital clocks derived from the PLL reference oscillator after external frequency division. The maximum DC-coupled input level at pin 37 should not exceed 75% of the VCCA(LIM) supply value. The threshold level is set at half the supply value on VCCA(LIM) pin 31. PLLGND 38 0 0 PLL ground: minimize ground inductance; use close proximity decoupling to the VCCA(PLL) supply pin 36 P39GND 39 0 0 this pin provides additional RF/IF shielding and has to be connected to ground 1999 May 10 8 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL PIN VOLTAGE TYPICAL VALUES (V) PIN VCC = 2.7 V UAA1570HL DESCRIPTION VCC = 5 V COMP 40 depends on VCO application depends on VCO application Charge pump phase frequency detector output: the PLL loop filter is connected in shunt and close proximity to this pin. The PLL loop filter tuning control voltage should be routed to the external VCO varactor circuit using minimal trace lengths in complete isolation from all potential coupling sources. P41GND 41 0 0 this pin provides additional RF/IF shielding and has to be connected to ground P42GND 42 0 0 this pin provides additional RF/IF shielding and has to be connected to ground VCCA(LNA1) 43 2.7 5 LNA1 power supply: DC operation range 2.7 to 5 V; use close proximity RF decoupling to pins 44, 46 and 47. LNA1GND1 44 0 0 LNA1 ground 1: minimize RF ground inductance LNA1IN 45 0.815 0.807 LNA1 input: use external RF AC coupling BIASGND1 46 0 0 LNA1 bias circuit ground: minimize RF ground inductance LNA1GND2 47 0 0 LNA1 ground 2: minimize RF ground inductance LNA1OUT 48 1.48 3.629 LNA1 output: use external RF AC coupling. The DC voltage is approximately 1.3 V below the VCCA(LNA1) supply on pin 43. 1999 May 10 9 Philips Semiconductors Product specification VCCA(LNA2) 37 SCLK 38 PLLGND 39 P39GND UAA1570HL 40 COMP 41 P41GND 42 P42GND 43 VCCA(LNA1) 44 LNA1GND1 45 LNA1IN 46 BIASGND1 48 LNA1OUT handbook, full pagewidth 47 LNA1GND2 Global Positioning System (GPS) front-end receiver circuit 36 VCCA(PLL) 1 LNA2GND1 2 35 DGND 34 SIGN LNA2IN 3 BIASGND2 4 33 VDDD LNA2GND2 5 32 DATA LNA2OUT 6 31 VCCA(LIM) UAA1570HL 30 BFCP CLOCK 7 REFIN 8 29 LIMINP VCCA(VCO) 9 28 LIMINN 27 BFCN TANK 10 26 LIMGND VCOGND 11 25 IF2N Fig.2 Pin configuration. 1999 May 10 10 IF2P 24 IF2INP 22 STROBE 23 IF2INN 21 MX2GND 20 VCCA(MX2) 19 IF1P 17 IF1N 18 VCCA(MX1P) 16 MX1GND 15 MX1IN 14 MXPGND 13 P12GND 12 MHB270 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7 LNA1 can be powered down in the UAA1570HL to accommodate applications built around external LNAs, typically where long antenna cable runs are required. FUNCTIONAL DESCRIPTION The programmability of the UAA1570HL and flexible interface definitions allow the device to be configured for a wide range of applications. To restrict the content of this document the functional description of the device will generally concentrate on the C/A-code application circuit based on the default frequency plan. The first LNA is assumed to be matched with a 2nd-order band-pass structure to provide some input selectivity, since no dielectric or SAW filter has been used in the demonstration board. It should be noted that low loss RF SAW filters now make it possible to significantly improve the jam immunity of this amplifier, by placing a SAW filter at the output of the antenna. The application circuit does not allow easy measurement, calibration and documentation of the many sub-block characteristics which ensure good system performance. Therefore, test boards have been developed which allow direct measurement of the sub-block characteristics. On the demonstration board the first LNA is followed by a low loss RF SAW filter (<2.4 dB). On the demonstration board the second LNA has been matched to 50 Ω using a simple transmission line structure. The tables and graphs reflect the UAA1570HL specification as derived from simulation and measured results in these characterization board environments. The tables and graphs do not directly specify application board expectations. The functional description however, focuses on the default application. Finally, another identical RF SAW filter follows the second LNA into the first mixer. The RF system diagram (see Fig.3) illustrates the default application of the UAA1570HL in the Philips GPS demonstration board. In this application the UAA1570HL is intended to be operated directly from a passive GPS antenna through a very short antenna cable. Any cable loss in this demonstrator adds directly to the system noise figure and should therefore be minimized. 1999 May 10 UAA1570HL 11 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL handbook, full pagewidth C327 C328 R307 VRF L = 1020 mils W = 8.8 mils L = 900 mils W = 8.8 mils L = 376 mils W = 33 mils 50 Ω line stretcher C326 VRF C346 J301 OPTIMUM PERFORMANCE REQUIRES THAT THE GPS DIGITAL BASEBAND, SUPPLY REGULATORS, AND OTHER SOURCES OF DIGITAL NOISE BE PLACED IN THIS RELATIVE ORIENTATION TO THE UAA1570HL. VRF ISOLATE THE REFERENCE INPUT AND ITS HARMONICS FROM THE FIRST IF AND ITS FILTERING COMPONENTS C325 R315 C341 LK L = 315 mils W = 6 mils 100 Ω 48 SAW C307 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 SI L = 286 mils W = 6 mils 100 Ω BPF301 47 R319 N VRF C334 C340 G C335 C321 SC L = 355 mils W = 6 mils 100 Ω REFIN S, AL N M G RO . SI F NS S AL D IO IT N T IG U C D RO UN E G F ES ND RF TH , A OG TE IES AL LA L N O P A IS UP LL S A Vtune C324 C329 C323 C306 VDDD DATA C320 31 6 L = 412 mils W = 6 mils CLOCK 100 Ω UAA1570HL C337 7 30 8 29 9 28 C303 C311 REFIN C312 C331 VRF C338 R314 C310 C336 L305 10 27 11 26 R305 L302 C309 C304 C302 D301 25 12 13 Vtune L = 217 mils W = 33 mils 50 Ω line stretcher L301 R301/C301 R316 C339 C347 14 15 16 17 18 19 20 21 22 23 24 L309 C301 R323 L308 C330 C313 C319 C332 BPF302 R306 SAW C322 L = 386 mils W = 6 mils 100 Ω R311 R310 C305 C345 STROBE L304 C318 C317 L303 R322 C316 analog ground C315 C314 digital ground L306 C308 L307 MHB271 Fig.3 UAA1570HL RF system diagram (default application). 1999 May 10 12 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.1 These RF port impedances are marked on the following Smith charts (see Figs 4 to 8; normalized to 50 Ω) and suggested matching structure netlists are provided. They contain transmission lines defined by their characteristic impedance Z (in ohms), their electrical length E (in degrees) and the operating frequency f (in GHz). Capacitors C are given in pF. TLIN is a series transmission line and TLOC is an open-circuit stub transmission line. Node 1 is the UAA1570HL RF port being matched and Node 0 is ground. These matching networks are structurally identical to those illustrated on the GPS application block diagram, however, the component values in the application diagram are somewhat different to account for stray capacitances and other real world influences. The netlists are derived from EEZMATCH software (Besser Associates, Los Altos, CA, USA). Low noise amplifiers LNA1 and LNA2 Two identical LNAs are provided on the IC although LNA1 need not be biased, if sufficient external gain is provided by an external LNA. The input stage of each amplifier consists of an unbalanced common emitter and a cascode stage. The AC-coupled output stage is a compound feedback bootstrap amplifier. Each stage is independently biased and regulated. LNA1 can be disabled by connecting the respective supply (pin 43) to ground. LNA2 has to be powered-up even if not used. Each LNA can supply a power matched gain of approximately 15.5 dB with an associated noise figure of 3.7 dB. Both LNAs have −1 dB input compression points of approximately −22 dBm from a 3 V supply. The 2nd and 3rd-order input intercepts are approximately −7.9 and −13 dBm, respectively, in a power matched environment. Generally, we assume a minimum shunt capacitance, due to the IC pin pad and adjacent pin strays, of approximately 0.25 pF as an initial stray element in the netlist below, that will always be present in the matching structure design. This value should be re-estimated and matched if the layout introduces significant additional strays at the pin pads. The RF match impedances at L1 (1.57542 GHz) are provided in Table 1 for all RF inputs and outputs. Table 1 RF matching impedances PIN REAL PART (Ω) IMAGINARY PART (Ω) 45 31 −j32 LNA1 input 48 77.5 +j6 LNA1 output FUNCTION 3 24 −j25 LNA2 input 6 74.5 −j0.5 LNA2 output 14 33.5 −j25.5 1st mixer input 1999 May 10 UAA1570HL 13 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.1.1 UAA1570HL LNA1IN CAP 1 0 C = 0.25 ! C1 C = PF TLIN 1 2 Z = 97.0 E = 34.5 F = 1.57542 ! TL1 Z = OH, E = DEG, F = GHZ CAP 2 0 C = 2.0 ! C3 C = PF Alternatively the 2 pF shunt capacitance at the input of the 97 Ω matching line above might be replaced with a 25 Ω microstrip open stub if space permits. TLOC 2 0 Z = 25.0 E = 26.1 F = 1.57542 1 handbook, full pagewidth 0.5 2 0.2 5 10 +j 0.2 0 0.5 1 2 5 ∞ 10 −j 10 5 0.2 2 0.5 1 MHB318 Fig.4 LNA1 input impedance and matching network. 1999 May 10 14 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.1.2 UAA1570HL LNA1OUT To facilitate matching of both LNA outputs, a small shunt capacitance should be placed as close as possible to the output pin pad increasing the assumed 0.25 pF lumped pin capacitance by approximately 0.5 pF to 0.75 pF. This ensures that a simple, short, high impedance transmission line will provide a good 50 Ω match at high gain. A via to the opposite side of the board right at this output pin allows a stub or chip capacitance to be added without comprising the characteristics of the 97 Ω matching line. CAP 1 0 C = 0.25 ! C22 C = PF IND 1 28 L = 0.7 ! L7 = NH CAP 28 0 C = 7.1658792e−1 ! C23 C = PF TLIN 28 29 Z = 97.0 E = 26.239010 F = 1.57542 ! TL15 If an open line stub is used, the latter components have to be replaced by: TLOC 28 0 Z = 20.0 E = 8.0 F = 1.57542 ! OTL7 Z = OH, E = DEG, F = GHZ TLIN 28 30 Z = 97.0 E = 26.2 F = 1.57542 ! TL16 Z = OH, E = DEG, F = GHZ 1 handbook, full pagewidth 0.5 2 0.2 5 10 +j 0 0.2 0.5 1 2 5 ∞ 10 −j 10 5 0.2 2 0.5 1 MHB319 Fig.5 LNA1 output impedance and matching network. 1999 May 10 15 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.1.3 UAA1570HL LNA2IN CAP 1 0 C = 0.25 ! C13 C = PF TLIN 1 14 Z = 97.0 E = 30.0 F = 1.57542 ! TL9 Z = OH, E = DEG, F = GHZ CAP 14 0 C = 2.3309277 ! C14 C = PF 1 handbook, full pagewidth 0.5 2 0.2 5 10 +j 0.2 0 0.5 1 2 5 ∞ 10 −j 10 5 0.2 2 0.5 1 MHB320 Fig.6 LNA2 input impedance and matching network. 1999 May 10 16 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.1.4 UAA1570HL LNA2OUT CAP 1 0 C = 0.25 ! C22 C = PF IND 1 31 L = 0.1 ! L8 L = NH CAP 31 0 C = 0.5 ! C24 C = PF TLIN 31 32 Z = 97.0 E = 25.077020 F = 1.57542 ! TL17 Z = OH, E = DEG, F = GHZ In the event that the second capacitor is replaced by an open line stub, the last two components have to be changed: TLOC 31 0 Z = 20.0 E = 5.5 F = 1.57542 ! OTL8 Z = OH, E = DEG, F = GHZ TLIN 31 33 Z = 97.0 E = 24.460094 F = 1.57542 ! TL = 18 Z = OH, E = DEG, F = GHZ 1 handbook, full pagewidth 0.5 2 0.2 5 10 +j 0 0.2 0.5 1 2 5 ∞ 10 −j 10 5 0.2 2 0.5 1 MHB321 Fig.7 LNA2 output impedance and matching network. 1999 May 10 17 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.1.5 UAA1570HL MX1IN CAP 1 0 C = 0.25 ! C5 C = PF TLIN 1 13 Z = 100.0 E = 31.083933 F = 1.57542 ! TL9 Z = OH, E = DEG, F = GHZ CAP 13 0 C = 1.673902 ! C6 C = PF Again an alternative open stub line is suggested which could be used to replace the 1.67 pF capacitance at this end of the previous netlist. TLOC 13 0 Z = 25.0 E = 23.0 F = 1.57542 ! OTL5 Z = OH, E = DEG, F = GHZ 1 handbook, full pagewidth 0.5 2 0.2 5 10 +j 0.2 0 0.5 1 2 5 ∞ 10 −j 10 5 0.2 2 0.5 1 MHB322 Fig.8 MX1 input impedance and matching network. 1999 May 10 18 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.1.6 UAA1570HL GENERAL REMARKS AND RESULTS The RF match has an important effect on the gains, noise figure, and dynamic characteristics of the RF system blocks. Reflection coefficients better than −15 dB are easily attainable and can be improved to better than −25 dB with attention to details. MHB272 20 output (dBm) 0 handbook, halfpage −20 (1) (2) (3) −40 −60 −80 (1) Fundamental output. (2) 3rd-order product output. (3) 2nd-order product output. −100 −90 −70 −50 −30 −10 input (dBm) Fig.9 Typical LNA fundamental, 2nd and 3rd-order product output levels as a function of input level. In the following graph (see Fig.10) the solid trace GLNA (dB) represents the measured frequency response of the UAA1570HL LNAs as measured on a spectrum analyzer, while the dotted and dashed results were obtained using a noise figure meter over a more restricted frequency range. MHB273 30 handbook, halfpage 1575.42 GLNA (dB) (2) 20 15.3 (1) 10 3.68 (3) 0 (1) LNA gain (dB). (2) Power gain. (3) Noise figure. −10 0 1000 2000 f (MHz) 3000 Fig.10 Typical LNA gain and noise figure as a function of frequency (50 Ω power matched on the input and output). 1999 May 10 19 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.2 In addition to the direct effects of power losses introduced by the transformer (approximately −1.3 dB at 41.82 MHz), which are reflected in the measured S21 results, the test board results may also be impacted by deficiencies in the transformer 1 : 4 voltage step-up ratio at 41.8 MHz; however, this has not been quantified. Correlation of the UAA1570HL data sheet, application and test boards The application circuit does not allow easy measurement, calibration and documentation of the many sub-block characteristics which ensure good system performance. Therefore, test boards have been developed which allow direct measurement of the sub-block characteristics. An additional correction must be made to the current test results to compensate for internal 4 pF shunt capacitors on each collector output of the first mixer, which have not been resonated out in the testing. These boards use a 1 : 16 Ω ratio RF transformer to transform 50 Ω to the more appropriate value of 800 Ω at IF frequencies. The high-impedance side of these transformers is terminated with a physical resistor to adjust the UAA1570HL impedance at the port being measured, to approximately 800 Ω. This ensures that a calibrated signal is applied or received in the 50 Ω test environment. The transformer provides marginal performance at 41.8 MHz, so calibration results for this transformer are also included in this document. The first mixer measurements also include a 3 dB loss due to the 800 Ω transformer termination. This loss is also removed from the specification result. The second mixer has similar 2.1 dB input and 3 dB output transformer termination losses removed from the specification. For measurements made at 3.48 MHz in the second IF, 0.4 dB must be added to the measured results to reflect transformer losses at IF2, also. The 800 Ω impedance environment is somewhat less than that used in the application board. The UAA1570HL Characteristic tables provided in this document are calibrated to this 800 Ω environment as quantified in the notes at the end of the table. The effects of the transformer and associated termination losses have also been removed to some extent, so that specifications reflect the performance of the IC. The measured graph results were all derived from the test boards and corrected to again reflect part performance as much as possible. In summary the measured gain of the first mixer has been increased by 1.3 dB (transformer IL) + 1.4 dB (capacitive roll-off effects) + 0.2 dB (gain match) + 3 dB (output transformer termination loss) or 5.9 dB to calibrate out these losses in the specification. The measured gain of the second mixer has been increased by 1.3 dB (input transformer IL) + 1.7 dB (input term loss) + 0.4 dB (output transformer IL) and + 3 dB (output term loss) or 6.4 dB to calibrate out these losses in the specification. However, this was not always possible, so some discussion concerning the measurement limitations is provided where appropriate. Where possible, fundamental design relationships and limitations are indicated. The following two graphs (Figs 11 and 12) reflect the measured performance of the 1 : 16 Ω ratio RF transformer used to test the IF functions. Two transformers were placed back-to-back to make these measurements. Figure 11 represents the transmission function of just one of these transformers over frequency. Figure 12 represents the associated return loss at one input with the second transformer terminated into 50 Ω. In the actual UAA1570HL test board a single transformer is terminated in 800 Ω. 1999 May 10 UAA1570HL 20 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL MHB274 0 S21 handbook, halfpage (dB) −1 (1) (2) −2 (3) −3 −4 −5 0 20 40 60 80 100 f (MHz) (1) S21; Tamb = −40 °C. (2) S21; Tamb = +25 °C. (3) S21; Tamb = +85 °C. Fig.11 S21 for the test measurement transformer. MHB275 20 S11 handbook, halfpage (dB) 10 0 −10 (1) (2) (3) −20 −30 0 20 40 60 80 100 f (MHz) (1) S11; Tamb = −40 °C. (2) S11; Tamb = +25 °C. (3) S11; Tamb = +85 °C. Fig.12 S11 for the test measurement transformer. 1999 May 10 21 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.3 Therefore, the test circuit voltage conversion gain is estimated at 0.0531 A/V times the effective differential loading of approximately 440 Ω. This results in a voltage conversion gain of approximately 27.4 dBV. Subtracting 9.4 dB to convert from power in a 50 Ω environment to power into 440 Ω, we see that the first mixer delivers a total power conversion gain of approximately 18.0 dB in the test circuit. It is important to note that approximately 3 dB of this available power gain is lost in the test circuit output transformer termination and that much of this power can be recovered in application circuits. RF mixer with preamplifier The 1st mixer (the RF mixer) consists of an RF preamplifier followed by a Gilbert cell mixer. The RF preamplifier consists of the same unbalanced common emitter and cascode stage as used in the LNAs, but without the compound feedback bootstrap output stage. The cascode output is AC-coupled into one side of the lower tree of the Gilbert cell mixer. The other side is internally AC-coupled to mixer ground via a 20 pF decoupling capacitor. The Gilbert mixer RF input is degenerated with low loss inductive emitter feedback to increase the effective −1 dB compression point and intercept points. Referenced to the preamplifier input, the −1 dB compression point and 3rd-order intercept point are −25.4 dBm and −16.3 dBm, respectively. Another important first mixer parameter is its 2nd-order input intercept point, which will extrapolate to approximately 1.38 V (peak value) differential or +12.8 dBm in the 50 Ω mixer input environment. The peak differential output voltage swing of the mixer should be limited to less than approximately 1 V (peak value) or 2 V (p-p) differential or 0.5 V (peak value) single-ended to prevent clipping by the internal output ESD protection diodes and to prevent mixer output saturation. This implies that effective differential output loads of approximately 2.5 kΩ could result in clipping at the output of the mixer. The first mixer output structure also supports single-ended first IF filter applications. By taking one of the mixer outputs to the supply rail, the other can drive a single-ended first IF filter, thereby reducing external component cost in some applications. Maintaining the same single-ended loading impedance, as in the differential case (i.e. double the effective single-ended load) results in the same peak voltage across the same load, even with only half the transconductance 1⁄2(0.0531 A/V) available. Therefore the same power is delivered to the same filter load and the conversion gain remains the same. However, an effective load of 1.25 kΩ would also bring this single-ended mixer output to the same clipping point as the full differential equivalent load of 2.5 kΩ. The maximum recommended first mixer single-sided voltage conversion gain (input to one output) is therefore approximately 32 for both single-ended and differential output applications. The differential output of the Gilbert cell mixer is open-collector to allow optimization of conversion gain and matching to the first IF filter over a wide range of frequencies and filter options. The total conversion gain is therefore determined by the real part of the effective output load, which is given by the IF filter input impedance and loss and/or fixed filter input matching networks, if present. The voltage conversion gain can be estimated by multiplying the effective single-ended to differential transconductance value for the first mixer (0.0531 A/V) by the total effective differential output resistance. The total power conversion gain to a differential load can be estimated from the voltage conversion gain by subtracting diff_load 10 log ---------------------- . The total power delivered by the mixer to 50 Ω the output resistance is distributed between the fixed output termination, the IF filter input impedance, as well as equivalent loss impedances associated with the finite Q of filter components. The assumption has also been made that the output impedance which the mixer sees is real, at least in the IF band. The power matched Double-Side Band (DSB) noise figure of the RF mixer with preamplifier is approximately 12 dB at 1.57542 GHz from a 3 V supply. Note: The open-collector outputs of the first mixer each include internal 4 pF capacitors to ground. These capacitors should be included in the design of the first IF filter by removing 2 pF from the differential input capacitance for balanced filters and 4 pF from single-ended designs. 1999 May 10 UAA1570HL 22 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL MHB276 20 output (dBm) 0 handbook, halfpage −20 (1) (2) (3) −40 −60 −80 −100 −90 −70 −50 −30 −10 input (dBm) (1) Fundamental output. (2) 3rd-order product output. (3) 2nd-order product output. Fig.13 Typical first mixer fundamental, 2nd and 3rd-order product output levels as a function of input level. MHB277 20 handbook, halfpage FDSB (dB) (3) 16 12 (2) 8 (1) 4 0 2 3 4 VCC (V) 5 (1) FDSB; Tamb = −40 °C. (2) FDSB; Tamb = +25 °C. (3) FDSB; Tamb = +85 °C. Fig.14 Typical RF mixer noise figure as a function of temperature and supply voltage (test board). 1999 May 10 23 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.4 UAA1570HL Series or parallel resonators can be used, while tuning is achieved by an external varactor diode. VCO The VCO consists of a single transistor in common collector configuration with internal positive feedback realized by capacitors connected from emitter to ground and emitter to base. Together with the external resonator/inductor, this is a typical Colpitts circuit. With the transistor’s base connected to pin 10 (TANK), the internal circuit arrangement produces a large negative input impedance at this pin. VCO gain as well as the out-of-loop bandwidth phase noise are dependent on the choice of external elements used here. Consequently, they should be selected with great care; their quality factor is especially important and should be as high as possible. Finally, the VCO is followed by a differential buffer stage with emitter follower inputs splitting the signal to the divider and LO driver stage path to increase isolation between mixer and synthesizer and their wanted or unwanted signals. At VCCA = 3 V and Tamb = 27 °C the oscillator transistor is initially biased with approximately 1.5 mA of start-up current. This value is relatively constant varying from approximately 1.56 mA at Tamb = +120 °C to 1.4 mA at Tamb = −55 °C. During operation, the average currents are higher due to the large amplitudes involved leading to rectification and bias point shifting. This first buffer stage is followed by two other specialized buffer amplifier stages in the individual signal paths bringing the signal to the required levels for driving a mixer or a divider. The VCO operates as a negative impedance oscillator with a suitable external inductive resonator. MHB278 100 handbook, full pagewidth R (Ω) (1) (2) (3) 0 −100 4 (1) C (pF) (3) (2) 2 0 0 0.5 1 1.5 2 2.5 f (GHz) 3 (1) Tamb = −55 °C. (2) Tamb = +27 °C. (3) Tamb = +120 °C. Fig.15 Simulated VCO small signal negative resistance (top diagram) and capacitance (below), without strays. 1999 May 10 24 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL MHB279 2.4 handbook, halfpage 2.0 (1) 1.6 (2) 1.2 0.8 0.4 0.4 0.6 0.8 1 2 3 f (GHz) (1) Corrected for strays. (2) Raw data 3 V supply voltage. Fig.16 Magnitude of the reflection coefficient of VCO negative resistance tank pin (measured). MHB280 0 handbook, halfpage Φ (deg) −40 (2) −80 (1) −120 −160 −200 0.4 0.6 0.8 1 2 3 f (GHz) (1) Corrected for strays. (2) Raw data 3 V supply voltage. Fig.17 Phase of the reflection coefficient of VCO negative resistance tank pin (measured). 1999 May 10 25 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.5 UAA1570HL Rs = 331 Ω First IF filter The first IF filter provides four functions: Tank 1 = 165 nH in parallel with 81.6 pF 1. It provides selectivity to protect the 2nd mixer (the IF mixer) from high level spurious RF signals which pass through the wide band-pass envelope of the RF filters, typically 40 to 60 MHz. Coupling capacitor 1 = 6.2 pF Tank 2 = 165 nH in parallel with 74.9 pF Coupling capacitor 2 = 6.7 pF Tank 3 = 165 nH in parallel with 81.1 pF 2. The filter attenuates thermal noise and spurious signals in the 2nd mixer image band. RL = 690 Ω. To convert this filter to a balanced design it can be mirrored in the ground plane which would result in the following balanced structure. It should be noted that the tank design inductances have doubled while the tank capacitances have halved, which can be seen by removing the virtual ground plane. The series elements remain unchanged in the balanced design, while the differential source and load have of course doubled. 3. It can provide impedance matching/transformation from the RF mixer output to the IF mixer input. 4. It can reject spurious common mode and/or differential signals generated by high level local sources such as harmonics of the reference clock or sample clock. The first IF can be structured to support a wide range of single-ended or balanced filters including LC or SAW realizations. High RF gain provides first IF signal levels high enough to accommodate first IF filter losses of 15 dB with optimum RF matching and conversion gain in the first mixer. Rs = 663 Ω Tank 1 = 330 nH in parallel with 40.8 pF Coupling capacitor 1 = 6.2 pF Tank 2 = 330 nH in parallel with 37.5 pF The Philips application board uses a 6th-order coupled resonator filter based on the butterworth response. The design method is described in the “Handbook of FILTER SYNTHESIS” by Anatol Zverev. The handbook tables formulate single-ended filter designs which we later convert to a balanced form. Coupling capacitor 2 = 6.7 pF Tank 3 = 330 nH in parallel with 40.6 pF RL = 1380 Ω. To optimize the power developed by the first mixer its load was maximized by driving the 1380 Ω side of this filter. It was also decided to bias the output of the first mixer through Tank 3 components by breaking the former differential 330 nH inductor back into two 165 nH inductors connected to the supply which also acts as a virtual ground. The initial centre frequency and bandwidth were 41.82 and 4.5 MHz, respectively. The following list illustrates the tabular design 3 dB down k and q parameters from Zverev that were developed for the initial single-ended structure. Rs = 331.4 Ω RL = 689.6 Ω The filter was then resimulated in ‘SPICE’ to optimize against available discrete surface mount component values with finite quality factors. All filters must be driven by their design impedances to produce their prescribed response. Since the finite quality factors of the filter inductors emulate an equivalent shunting load of approximately 2 × π × f × L × Q, the source and load terminating impedances can be increased to compensate for this parasitic element while maintaining ideal filter response and minimizing losses. In the default application, R322/306 in conjunction with the equivalent parallel resistance at the respective filter input and output give the desired terminating impedance. q0 = 5.0; insertion loss = 4.742; q1 = 0.8226; qn = 1.7115; k12 = 0.6567; k23 = 0.7060. This tabular listing was chosen based on the desired selectivity and minimal insertion loss, which could be realized with available surface mount inductors operating with quality factors (Q) in the range of 40 to 50. The impedance level is determined by the choice of design inductance (165 nH), with foresight given to eventual balancing of the design. Maximizing the load presented to the first mixer was also a consideration. With some frequency plans stability in both the first and second IF will also need to be considered when choosing the impedance level of the design. The handbook calculations result in a preliminary single-ended three shunt tank structure with a coupling capacitor between each tank as follows: 1999 May 10 26 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit The limitation imposed by image noise is illustrated in Fig.18 where the ideal calculated filter response is compared against the measured noise density at the output of the first IF filter. The single sided FET probe measured result was corrected by +6 dB to account for 50 Ω balanced processing and 10 log ---------------663 Ω or −11.2 dB to accommodate power conversion losses. The IF noise density selectivity is seen to be limited by the available RF gain and noise figure of the first mixer. At the image frequency, 34.86 MHz, the measured noise floor is approximately 13 dB below the desired IF level at 41.82 MHz. This will result in an image contribution to the noise figure of the system of approximately 0.2 dB. UAA1570HL The in-band noise density can be estimated based on the single-ended voltage gain to the output of the IF filter. With the antenna thermal input level at approximately −174 dBm/Hz, noise figure of approximately 4 dB and voltage gain from the antenna to the IF filter output of approximately 47 dBV (at 5 V supply voltage), we can expect the differential noise power density to be approximately −174 dBm + 4 dB + 47 dBV + 6 dB 663 Ω (conversion to balanced) − 10 log ---------------50 Ω or −129 dBm/Hz. The final term converts the measured power using a high impedance FET probe, calibrated to a 50 Ω environment, to the actual 663 Ω differential filter output environment. MHB281 −120 handbook, halfpage 34.86 × 106/sec 41.82 × 106/sec Nd (dBm/Hz) −130 (2) −140 (1) −150 −160 30 34 38 42 46 50 f (MHz) (1) Ideal calculated filter response. (2) Measured filter noise density. Fig.18 First IF filter output noise power density (application board). 1999 May 10 27 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.6 The demonstration board was converted from a balanced second IF filter in this manner. Second IF mixer The second mixer is a standard Gilbert cell mixer operating with a total tail current of 4.3 mA, which is Proportional To Absolute Temperature (PTAT). The RF input, or lower tree of the mixer, is not internally terminated other than by 5 kΩ biasing resistors to each input. With no significant emitter degeneration, the real part of the RF port input impedance is dominated by the two differential junction Rπs in parallel with the bias elements. The differential output of the Gilbert cell mixer is open-collector to allow the conversion gain and matching to the second IF filter to be optimized over a wide range of frequencies and to many types of IF filters. To optimize the noise figure of the second mixer the input termination admittance should be reduced. However, this will be at the expense of the mixers input compression and 3rd-order intercept characteristics. Since the RF input of the IF mixer is a simple differential stage, the input −1 dB compression point and 3rd-order intercept points are relatively fixed at approximately 67 and 215 mV (peak value), respectively, in the second mixer. This results from noting that an undegenerated differential input can be expected to have an input −1 dB compression point of approximately 36.6 mV (peak value) differential. With a small additional extrinsic emitter degeneration the −1 dB compression point is raised to approximately 67 mV (peak value) differential. This is approximately −24.7 dBm in the 663 Ω second mixer GPS application input environment with the 3rd-order intercept point being approximately 10 dB higher at −14.6 dBm. Another important second mixer parameter is its 2nd-order input intercept point, which will extrapolate to approximately 79.8 V (peak value) differential or 36.8 dBm in the 663 Ω mixer input environment. The conversion voltage gain is determined by the tuned real part of the effective output load. This load may consist of the IF filter input impedance as well as fixed filter input matching compensation terminations and losses. The voltage conversion gain can be estimated by multiplying the effective differential conversion transconductance value (0.0294 A/V) by the total effective differential load at the output of the mixer. The conversion power gain is best described relative to specified mixer input and output impedance environments. The peak output voltage swing of the IF mixer should be limited to a peak differential swing of less than approximately 1 V (peak value) or 2 V (p-p) differential to prevent clipping by the internal output ESD protection diodes and to prevent mixer output saturation. This implies that an effective differential output load of approximately 3.2 kΩ could result in clipping at the output of the mixer. The power conversion gain is calculated by subtracting output resistance environment 10 log -------------------------------------------------------------------------------- from the dBV value input resistance environment of the voltage conversion gain of the mixer. It should be noted that differential second mixer input terminations may be DC-coupled. We can simplify and estimate the second mixer conversion gain in the default application by noting that the input impedance environment is approximately 663 Ω, while the output environment is approximately 1394 Ω. With effective output loading of 854 Ω (2.2 kΩ in parallel with 0.7 × 2 × 996 Ω) the voltage conversion gain can therefore be expected to be approximately 25.1 V/V or 28 dBV. The power correction from 663 Ω at the input to 1394 Ω (0.7 × 2 × 996 Ω) at the output is −3.2 dB, so the resulting power conversion gain is approximately 24.8 dB. The factor of 0.7 in the calculation of the impedance level is explained in Section 7.7. The IF mixer supports single-ended first and second IF filter applications. A single-ended input is implemented by AC bypassing one side of the IF mixer input to ground and accepting an associated drop in mixer conversion voltage gain. It should be noted that single-ended input terminations can still be DC-coupled to the mixer input pins by using the above mentioned bypass capacitor. The IF mixer output can be made single-ended by connecting the unused mixer output to the supply rail. Extra care should be taken to characterize single-ended first IF applications. Using a single-ended second IF filter in combination with a balanced first IF filter may help reject common mode signals not rejected by the first IF filter. However, it should be noted that the differential tank capacitors of the fully differential IF filters can be replaced by common mode capacitors by doubling the differential value and connecting two of these capacitors to ground. Any distribution between these two extremes is also acceptable. It should be noted that a balanced coupled k filter can be converted to a single-ended equivalent with a single-ended input impedance exactly equal to that of the full differential filter by keeping the same tank resonator components, but placing the series coupling capacitors in single-ended series (i.e. halving the differential value) and AC grounding one side of the tanks. 1999 May 10 UAA1570HL 28 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL With tuned inputs, the IF mixer RF input bandwidth can be extended quite high, but practical consideration warrant that the RF filter terminating the input should provide band limiting, thereby restricting the RF high frequency roll-off to less than 200 MHz without special characterization efforts. This is also, generally, the upper limit that the programmable synthesizer supports. The noise figure of the IF mixer as well as the limiter can be expected to degrade as the operating frequencies are increased. For example, at 200 MHz in a terminated 100 Ω system the DSB noise figure of the IF mixer will increase by at least 10 dB to approximately 18 dB. If stability permits low impedance first IF filters can be matched into the IF mixer using step-up matching circuits such as baluns or transformer like tuned networks, to minimize the degradations. As with the RF mixer maintaining the same single-ended load as an effective differential load would result in the same voltage applied to the equivalent resistance. However, a single-ended effective load of 1.6 kΩ could also bring this mixer output to its clipping point. The maximum recommended second mixer single-sided voltage conversion gain (one input to one output) is therefore approximately 16 for both single-ended and differential output applications. The estimated Single-Side Band (SSB) noise figure of the IF mixer is approximately 7.5 dB at Tamb = 27 °C from a 3 V supply with an input termination matching resistor of 2 kΩ. Removing the termination results in an expected noise figure of 4.9 dB from a 1 kΩ source. This degradation is distributed between the input termination input loss and approximately a 1.6 dB increase in the actual mixer noise figure. The input compression point and noise figure of the IF mixer, as measured in the characterization test board, are plotted against temperature and supply voltage in Figs 19 and 20. The characterization test board employs the 1 : 16 Ω ratio transformers to provide a 50 Ω match to the 800 Ω test environment. The losses of the input and output transformers, as well as transformer insertion losses at 41.82 and 3.48 MHz, have been removed before plotting. Therefore, this graph correlates to specification and expected performance of the second mixer in the referenced 800 Ω environment. The conversion gain is expected to be relatively supply independent, increasing by only approximately 0.5 dB from a supply value of 2.7 to 5.5 V. The IF mixer RF bandwidth is also expected to only increase by approximately 4%, while the mixer noise figure is expected to decrease by less than 0.1 dB as the supply is increased over the same supply range. The IF mixer RF bandwidth, if not resonated, is dominated by the mixer differential input capacitance of approximately 1 pF. MHB282 −24 handbook, halfpage CP−1dB (3) (dBm) −26 (2) −28 (1) (1) Tamb = −40 °C. (2) Tamb = +25 °C. (3) Tamb = +85 °C. −30 2 3 4 VCC (V) 5 Fig.19 IF mixer −1 dB input compression point (800 Ω test circuit). 1999 May 10 29 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL MHB283 6 handbook, halfpage FDSB (3) (dB) 5 (2) (1) 4 3 2 3 4 VCC (V) 5 (1) Tamb = −40 °C. (2) Tamb = +25 °C. (3) Tamb = +85 °C. Fig.20 IF mixer DSB noise figure (800 Ω test circuit). MHB284 20 output (dBm) 0 handbook, halfpage −20 (1) −40 (2) (3) −60 −80 −100 −90 −70 −50 −30 −10 input (dBm) (1) Fundamental output. (2) 3rd-order product output. (3) 2nd-order product output. Fig.21 Typical second mixer fundamental, 2nd and 3rd-order product output levels as a function of input level (800 Ω environment). 1999 May 10 30 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.7 The filter was then resimulated in ‘PSPICE’ to optimize against available discrete surface mount component values. Finally the filters input and output direction were reversed to ensure that the highest impedance side was placed at the mixer output to maximize the available power developed. A 909 Ω termination was used at the output of the filter to terminate the 4.87 kΩ limiter input. This effective 766 Ω termination is somewhat lower than the initial design value of 2 × 548 Ω or 1096 Ω and therefore develops approximately −1.56 dB less power with respect to second mixer loading. The reduction of the impedance level by 30% (or a factor of 0.7) was done in order to have a large safety margin against instability of the limiter/quantizer path. Instability can be caused here by the large small-signal gain associated with this signal path in conjunction with the high signal levels present at the SIGN output. Furthermore, due to the strong non-linearities present in this signal path, LO2 leakage in conjunction with the IF2 itself can produce signals at the IF1 frequency and thus enter the IF1 filter together with the wanted signal. This impedance level reduction is passed through the second IF filter and consequently lowers the mixer 2 conversion gain by approximately 30%, too. The filter design was determined to be sufficiently tolerant to this adjustment by observing the effect on the filter’s output noise response with respect to unstable peaking and maintaining the desired selectivity response. Care must be taken not to induce instability while observing the IF2 filter noise response by using a 10 : 1 divider in conjunction with a very low capacitance RF FET probe (<0.5 pF). Second IF filter The second IF filter provides five functions: 1. It provides selectivity to protect the limiter input from spurious signals which pass through the first IF band-pass filter envelope, typically 5 MHz wide. 2. The filter attenuates undesired second mixer output products, such as the LO leak, to levels which will not block/capture the following limiter stage. 3. The filter defines and shapes the noise bandwidth to be amplitude quantized. 4. It can provide impedance matching/transformation from the IF mixer output to the limiter input while maintaining stability. 5. It can reject spurious common mode and/or differential signals generated by high level local sources such as harmonics of the reference clock or sample clock and digital processing noise from associated devices such as the SAA1575HL. The second IF can be structured to support a wide range of single-ended or balanced filters including LC or ceramic realizations. The available system gain can provide second IF signal levels sufficient to accommodate high second IF filter losses. The Philips application board again uses a 6th-order coupled resonator filter based on the butterworth response. The design method is described in the “Handbook of FILTER SYNTHESIS” by Anatol Zverev. Initially a skewed centre frequency and bandwidth were input at 3.1 and 1.75 MHz, respectively, to help overcome the asymmetry which is intrinsic in geometric low frequency band-pass filter designs as they approach DC. The following table design 3 dB down k and q parameters were used: In the default application, R323/305 in conjunction with the equivalent parallel resistance at the respective filter input and output give the desired terminating impedance. The frequency of the mixed down third harmonic of the reference oscillator is usually the most significant spurious product which is generated in the default frequency plan and must be kept at least 13 dB below the integrated noise response of the filter. For example, typical true power noise densities (Dn) for a nominal GPS demonstration board operating at 3 V are expected to be approximately −100 dBm/Hz differential at the input of the limiter and reflect the importance of designing a well matched RF system. Assuming that a somewhat lower gain variation has been realized with a noise density of approximately −105 dBm/Hz over an estimated 2 MHz noise equivalent bandwidth, it is possible to evaluate and measure the associated spurious product level that would result in a −13 dB jammer-to-noise (J/N) and 0.2 dB system noise figure degradations as follows: Rs = 548 Ω RL = 996 Ω q0 = 20.0; insertion loss = 0.958; q1 = 0.8041; qn = 1.4156; k12 = 0.7687; k23 = 0.6582. This filter was originally mirrored by a virtual ground to convert it to a balanced form, but later the balanced components were converted back to a single-ended form (to reduce component count) simply by placing the balanced series capacitors in series on one side of the filter (effectively halving the capacitance value) and grounding the opposite side of the tanks where these series capacitors were removed. This effectively maintains the differential power gain while only using a single-sided output. 1999 May 10 UAA1570HL 31 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit The true power of a product at the output of the second IF filter in a 1 kΩ environment should be no more than −105 dBm/Hz + 63 dB − 13 dB or approximately −55 dBm. The equivalent single-sided measurement with 548 a 50 Ω calibrated probe would be – 55 dBm + 10 log ---------50 or −44.6 dBm. Figure 22 illustrates the true noise power density as measured points for this lower gain case. The filter response of the first IF filter is translated to the second IF and superimposed at the second IF to show that the 3rd harmonic reference spur at 43.2 MHz, is not filtered by this response. UAA1570HL Also shown is the second IF filter response and the combined first and second IF filter selectivities, which account for total observed selectivity noise response. For difficult applications which require higher losses in the IF filters, self jamming can be minimized by choosing a reference and frequency plan which places the harmonics of the reference exactly at the second LO frequency, where they are benign. MHB285 −90 handbook, halfpage 3.48 x 106/sec 4.86 x 106/sec Nd (dBm/Hz) −110 (1) (2) −130 (3) (4) −150 0 4 8 12 f (MHz) 16 (1) IF1 filter response superimposed on IF2 filter response. (2) IF2 filter response (calculated). (3) IF2 filter noise density (measured). (4) IF1 filter response translated to IF2 frequency. Fig.22 Second IF filter output noise density frequency response on the application board. 1999 May 10 32 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.8 The first is LO leakage from the first mixer output which will couple into the package die pad through internal 4 pF common mode capacitors at the output of the 1st mixer. This leakage signal is effectively filtered at the 2nd IF filter output, but reappears internally on all down-bonded grounds. It appears at a level of approximately 0.5 mV (peak value differential) across the limiter input transistor bases with an assumed 1st mixer input RF offset of approximately 1 mV. Time and amplitude quantization After frequency conversion in the double-superheterodyne portion of the UAA1570HL and filtering to approximately a 2 MHz bandwidth in the second and final IF filter, the frequency translated thermal noise from the GPS pass-band around the L1 carrier is ready to be converted to a digital signal for processing by the companion GPS chip-set part (SAA1575HL). First the thermal noise’s sign is determined by amplitude quantization in a 1-bit hard limiter. This asynchronous information is then time quantized by latching in a master/slave D-flip-flop to complete the analog-to-digital conversion process. Finally, this ECL digital SIGN bit data is translated to TTL levels and sent to the SAA1575HL. The second is LO leakage from the second mixer. Assuming 1.5 mV RF input offset, the leakage at the output of the second IF filter is expected to be approximately 500 µV (peak value differential) (−69 dBm into 1 kΩ) and sets the worst case nominal process blocking level. With a nominal −50 dBm IF thermal level at this point there is a 19 dB margin to blocking. To prevent blocking, IF filter losses should be minimized and the selectivity of the single-ended or differential second IF filter has to be designed and characterized to maintain this leakage product at least 11 dB below the integrated second IF filter thermal noise signal. Four differential stages are used to hard limit the thermal noise in the final IF. The total gain is approximately 63.9 dBV with a bandwidth of roughly 66 MHz and a noise figure of approximately 11.3 dB in a 1 kΩ environment. The parallel equivalent differential input impedance of the limiter is 4.87 kΩ in parallel with 0.3 pF. Offset control is provided through 42.5 kΩ feedback resistors from each balanced output back to the inputs. External decoupling capacitors cut the feedback loop for AC signals. The third form of blocking can occur if LO1 leakage is sufficiently high (greater than 15 mV (peak value) on the die pad) to be injected into the 2nd mixer regulators and all down-bonded IF grounds. This results in burst of LO1 leakage at the 2nd mixer LO2 zero transition points which increase LO2 leakage peaks by factors of 10. Limiter inputs as low as 25 µV (peak value differential) are resolved at the output master flip-flop DFF1 in its transparent mode. As the master flip-flop is latched positive feedback resolves metastable states. While the master flip-flop is in its transparent state the positive feedback in the slave flip-flop will resolve the remaining metastable states as it is latched. The gain response of the limiter from a low impedance source with no input strays is illustrated from the input to the output of each stage in Fig.23. Three forms of LO leakage can block the limiter if they capture the device. 1999 May 10 UAA1570HL 33 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL MHB286 80 handbook, full pagewidth (4) (3) G (dB) (2) (1) 0 −80 −160 10−2 (1) (2) (3) (4) 10−1 1 10 102 103 f (MHz) Limiter input. 1st stage gain response. 2nd stage gain response. 3rd stage gain response. Fig.23 Limiter input, 1st, 2nd and 3rd stage gain response as a function of frequency (simulated). 1999 May 10 34 104 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL MHB287 8 handbook, full pagewidth R i(diff) (kΩ) 6 (3) (2) (1) 4 2 0 10−2 10−1 1 10 102 103 f (MHz) 104 (1) Tamb = −55 °C. (2) Tamb = +27 °C. (3) Tamb = +120 °C. Fig.24 Limiter differential input resistance as a function of frequency (simulated). 7.8.1 being applied. Direct sinusoidal inputs should be as large as possible within the prescribed range to optimize phase noise performance. CLOCK INPUTS Both the reference and the sample clock input can be driven by a Temperature Compensated Crystal Oscillator (TCXO). Typical TCXOs produce 0.5 to 1.0 V (p-p) clipped sine wave outputs. The drive capability is typically 20 kΩ in parallel with 5 pF or 10 kΩ in parallel with 10 pF. Some TCXOs are even capable of driving loads as low as 1 kΩ without buffering. The sample clock input also features a high impedance of 23.3 kΩ. The sample clock input can be AC-coupled directly to the reference if the system sampling objectives are met. Alternatively, the TCXO/XO reference can be externally squared to CMOS input levels and applied to the SAA1575HL RCLK input (pin 98) and divided under firmware control to produce a signal commensurate with the sampling objective. Alternatively, cost can be reduced by designing a simple discrete crystal oscillator reference, paying careful attention to temperature tolerance (±6 ppm) as well as shock and vibration characteristics. Due to the wide range of programmable frequency plans and sampling rates supported by the UAA1570HL, it is not possible to predict the frequencies and levels of the associated spurious products that will be generated. One significant source of potential spurs are the harmonics of the reference and sampling signals. The availability of on-chip squaring circuits provide some freedom to minimize large digital signal effects in sensitive RF circuit areas. In most cases digital sampling signal levels are acceptable as long as careful attention is paid to avoid injecting these signals or their harmonics into the pass bands of the IF filters. Both UAA1570HL clock inputs, the synthesizer reference input REFIN (pin 8), and the sample clock input SCLK (pin 37), accept low level inputs and provide internal gain/squaring circuits. The reference clock input has a high impedance with 20 kΩ in parallel with 0.07 pF. A high stability, low phase noise crystal reference source should be AC-coupled to this port. Reference inputs up to 35 MHz and levels between 50 to 500 mV (peak value) are acceptable. This source can be externally squared and attenuated before 1999 May 10 35 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit Since the TTL/CMOS output stage is transparent the SIGN bit output is updated on the rising edge of the CLK with the master latched and the slave transparent. This implies the DSP can expect SIGN bit data to be latched on the LOW CLK state. The SCLK input of the UAA1570HL is self-biased at 50% of the analog supply voltage (VCCA) near the internal threshold level. It is therefore possible to operate this input with levels as low as 10 mV (peak value) in order to avoid large digital signal flow on the Printed-Circuit Board (PCB) runners. This is done in the default application with a 6.8 and 3.9 kΩ resistive divider followed by a 10 pF AC coupling series capacitor in between the SAA1575HL and the UAA1570HL. 7.8.4 Operating from a 2.7 V supply, VOL and VOH are nominally 132 mV and 1.95 V, respectively. Operating from a 5.5 V supply, VOL and VOH are nominally 195 mV and 4.6 V, respectively. CMOS TO ECL SAMPLE CLOCK SQUARING CIRCUIT Typical rise times of 8 ns and fall times of 10 ns can be expected from this output driving CMOS loads. The UAA1570HL internal sample clock squaring circuit allows single-ended sinusoidal clock inputs as low as 10 mV (peak value) over a frequency range from 5 to 35 MHz. The rise time of the clock output should be in the order of 25% of the maximum sampling frequency to ensure that aperture losses are less than approximately 1 dB (0.91 dB). The period of a 35 MHz clock is 28.57 ns. To keep the sampling aperture on the order of one fourth 28.57 ns this period implies a rise time of 5.7 ns ----------------------- is 4 × 1.25 required and should also be kept with lower sampling clock rates. 7.8.5 Typical propagation delay times through the time quantization circuitry while switching amplitude quantization states from a 5.5 V supply are: SCLK input to TTL SIGN output 16 ns (rising edge) SCLK input to TTL SIGN output 17.6 ns (falling edge). 7.9 Programmable synthesizer The UAA1570HL includes a programmable synthesizer allowing the main, second LO and reference dividers to be programmed under external control via a three-wire serial control bus. Alternatively, a LOW on the STROBE input on power-up will load a 20-bit default frequency plan word and power-on options into the synthesizer registers. Frequency plans with a 2nd IF of 4 × f0(1.023 MHz) = 4.092 MHz can be implemented. TIME QUANTIZATION (SAMPLER) Two clocked D flip-flops are connected in a master/slave configuration to implement the sampling function of the 1-bit sampler. With the internal DFF clock (CLK) LOW the master flip-flop DFF1 is in its transparent mode and continuously follows the amplitude quantized limiter output. As the clock (CLK) goes HIGH the data is latched in the master flip-flop and the slave DFF2 becomes transparent to the latched output from the master flip-flop. The falling edge of the CLK signal latches the slave and again loads the limiter output into the master flip-flop. These stages also provide additional limiting gain for marginal input signals from the limiter. 1999 May 10 1-BIT DELAYS The rise and fall times of the TTL output with a 15 pF load are approximately 8 ns and are relatively independent of supply and temperature. A small decrease (1 to 2 ns) in rise and fall times is seen at Tamb = −55 °C and a small increase at Tamb = 120 °C (2 to 4 ns). Using a 14.4 MHz sampling rate test signal into the SCLK input results in good TTL eye pattern characteristics over a measured input range down to at least −25 dBm. At −35 dBm the effects of slew rate limiting begin to appear with the eye pattern closing beyond −40 dBm. 7.8.3 TTL OUTPUT STAGE The TTL output stage is a variation of a totem pole modified to operate from an independent isolated supply voltage from 2.7 to 5.5 V. This supply voltage is also independent of other supply voltages used in the UAA1570HL. Circuits to minimize cross-conductance and short-circuit currents are provided. However, when it is nevertheless intended to use full CMOS or TTL levels, some attenuation is required so that the peak sample clock input does not exceed 75% of the UAA1570HL analog supply voltage. This is especially important while the UAA1570HL is operating from a lower supply (3 V) than the SAA1575HL (5 V). A resistive divider can help in these cases, but the AC coupling method described above should be preferred. 7.8.2 UAA1570HL 7.9.1 VCO PRESCALER After the VCO signal leaves its single-ended-to-balanced cascode buffer it is again amplified on its way to a high speed fixed divide-by-2 prescaler using a super buffer such as that described for the first mixer (see Section 7.3). 36 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 7.9.2 7.10.2 MAIN SYNTHESIZER DIVIDERS (N-PATH) SECOND LOCAL OSCILLATOR DIVIDERS (L-PATH) The second LO signal is divided down from the VCO prescaler output, first by a programmable L-divider and then by a fixed divide-by-2 before being buffered and applied to the second mixer. 7.9.4 7.10.3 REFERENCE DIVIDERS (R-PATH) Serial interface The three-wire serial bus consists of DC-coupled DATA, CLOCK and STROBE CMOS level inputs. The DATA input loads serial 20-bit programming words into the synthesizer data input register on each rising edge of the CLOCK input, while the strobe line is held LOW. 7.10.4 Each DATA bit should be set-up for at least 30 ns before being clocked into the register and then held for at least 30 ns. The CLOCK rate should not exceed 10 MHz and the CLOCK pulse width should be at least 30 ns. The 20-bit DATA word definition follows in the order in which they are to be read (clocked) into the DATA register. 7.10.5 n0, n1, n2, n3, n4, n5 AND n6 The next seven bits clocked into the DATA register are the binary equivalent value of the variable main synthesizer divider ratio. The programmable range of this divider is 64 to 127, continuous. The default value is set to 71 (n0, n1, n2, n3, n4, n5, n6 = 1, 1, 1, 0, 0, 0, 1) with the MSB clocked into the DATA register first. The output of the main programmable divider includes a fixed divide-by-2 which modifies the previous range to all even values from 128 to 254, inclusive. The programmable portion of the main synthesizer division ratio is set by these seven bits if n7 is set to the HIGH state as described above for the default case. p0 AND p1 The first bit read into the synthesizer should be the power-down bit, p1, which enables one of two power-down states if set HIGH. The second bit read into the register, p0, defines the type of power-down. A complete power-down of the UAA1570HL is performed if this bit is set HIGH and a partial power-down with the synthesizer remaining on if this bit is set LOW. For normal operation of the UAA1570HL both of these bits are set LOW, which are also the default values for p0,p1 = 0,0. The final p0,p1 = 1,0 state is undefined. 1999 May 10 n7 As in the reference divider case the main synthesizer divider includes an optional post scaler divider following the main programmable divider. This divide-by-1 or divide-by-2 is controlled by program word bit n7. With this bit set LOW the divide-by-2 post scaler is enabled and the phase frequency detector receives equal mark/space ratio signals at its main synthesizer port. The default state for this bit is (n7 = 1) which does NOT double the total main synthesizer divide ratio as described below. The CLOCK signal should be set-up HIGH for at least 30 ns before the STROBE state is changed. 7.10.1 r0, r1, r2, r3 AND r4 The next five bits clocked into the DATA register are the binary equivalent value of the variable reference divider ratio. The programmable range of this divider is 4 to 31, continuous. The default value is set to 4 (r0, r1, r2, r3, r4 = 0, 0, 1, 0, 0) with the Most Significant Bit (MSB) clocked into the DATA register first. The total reference division ratio is set by these five bits if r5 is set to the HIGH state. The range can be optionally doubled to even values from 8 to 62 if r5 is set LOW. This option is set in the default case, resulting in equal mark/space ratios as described above. The total default reference division ratio is therefore 8 with (r0, r1, r2, r3, r4, r5 = 0, 0, 1, 0, 0, 0). After squaring (limiting), the reference signal is divided down first by a variable R-divider. The divide ratio ranges from 4 to 31. The variable divider is followed by an optional divide-by-1 or divide-by-2 before being applied to the phase/frequency detector. 7.10 r5 Next a post reference scaler bit, r5, is set to program a divide-by-1 or divide-by-2 following the variable reference divider. With this bit set LOW the divide-by-2 post scaler is enabled and the phase frequency detector receives equal mark/space ratio reference port signals. This is the default state for this bit (r5 = 0). In the HIGH state the mark/space ratio is a function of the variable reference divider value, and the range of the reference divider is extended to lower division ratios. The main synthesizer divider path includes an additional fixed divide-by-3 prescaler preceding a programmable variable N-divider which can be programmed over a range from 64 to 127. The output of the programmable divider passes through a fixed divide-by-2 and finally an optional divide-by-1 or divide-by-2 before being applied to the phase frequency detector. 7.9.3 UAA1570HL 37 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit This ratio can again be optionally doubled by setting n7 LOW. The range is then extended to values from 256 to 508, inclusive, in increments of 4. Equal mark/space-ratio signals are always fed to the main synthesizer port of the phase frequency detector since the fixed divide-by-2 post scaler is always present. The main synthesizer path divisions ratio range, including the fixed divide-by-2 and divide-by-3 prescalers, is increased by a factor of 6 from 768 to 1524 in increments of 12 when n7 is set HIGH or from 1536 to 3048 in increments of 24 if n7 is set LOW. The total default main synthesizer path division ratio from the VCO is 12 × 71 or 852 with (n0, n1, n2, n3, n4, n5, n6, n7 = 1, 1, 1, 0, 0, 0, 1, 1). 7.10.6 7.12 Table 2 Frequency plan PARAMETER l0, l1, l2 AND l3 The default values are set to 10 (l0, l1, l2, l3 = 0, 1, 0, 1). Again a post scaler is provided with a fixed divide-by-2 value to ensure that the LO signal exhibits equal mark/space ratios driving the second mixer. The programmable divider and fixed post scaler provide division between 8 and 30 in even increments. Since the 2nd local oscillator path from the VCO includes the divide-by-2 prescaler common to both the L-divider and N-divider paths, the total programmable 2nd local oscillator division range, relative to the VCO, is 16 to 60 in increments of 4. VALUE RF input frequency 1.57542 GHz VCO frequency 1.5336 GHz RF image frequency 1.49178 GHz First IF frequency 41.82 MHz Second LO division ratio 2 × 10 × 2 = 40 Second LO frequency 38.34 MHz Second image frequency 34.86 Hz Second IF frequency 3.48 MHz Reference frequency 14.4 MHz Total main synthesizer division ratio 2 × 3 × 71 × 2 = 852 Total reference division ratio 2×4=8 Phase comparison frequency 1.8 MHz 7.13 Phase detector, charge pump and loop filter The phase detector is of a phase and frequency sensitive digital type. In conjunction with the charge pump, it operates without a ‘dead zone’. The charge pump itself has a single-ended output delivering or sinking current pulses with a maximum amplitude of 240 µA into the external loop filter. With the 20-bit programming word completely clocked into the DATA register the STROBE signal is returned to a HIGH state after a minimum delay of 30 ns to latch and effect the parallel loading of the programmed word states. The layout for the connection between the loop filter and the VCO input should be made with utmost care in order to avoid other signals entering this path. The loop filter as chosen on the demonstration board yields a loop bandwidth of approximately 100 kHz, with a damping constant of 1. It consists of a 3.9 nF capacitor and a series resistor of 20 kΩ, both in parallel with a 150 pF capacitor. The serial interface word The complete default program word once serially loaded or loaded by default on power-up with the STROBE held LOW realizes the following frequency plan in the UAA1570HL. It should be noted that the MSB for the complete 20-bit program word is l0 and the Least Significant Bit (LSB) is p1 with the latter the first loaded into the DATA register. This is in contrast to the sequence in which the different bits determining the individual divider ratios are structured. The resulting default 20-bit word is: l0, l1, l2, l3, n0, n1, n2, n3, n4, n5, n6, n7, r0, r1, r2, r3, r4, r5, p0, p1 = 0, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0. 1999 May 10 The default frequency plan The default synthesizer programming produces the following frequency plan: The last four bits clocked into the DATA register set the programmable division ratio for the 2nd local oscillator. Again the MSB is read in first with the binary word set to a number between 4 and 15. 7.11 UAA1570HL 38 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 8 UAA1570HL OPERATING MODE SELECTION TABLES Table 3 Programmable operating modes p0 p1 LNA1 LNA2 VCO MX1, MX2, 1-BIT 2nd LO DPLL Normal 0 0 yes yes yes yes yes yes Partial power-down 0 1 no no yes no no yes Undefined 1 0 − − − − − − Complete power-down 1 1 no no no no no no MODE 8.1 Manual selection operating modes Some applications of the UAA1570HL may require the use of an external LNA. Since LNA1 is self contained and includes independent bias circuitry, it can be powered down simply by not connecting the respective supply pin or tying it to ground. Some considerations apply to optimize performance when using an external LNA. Generally the UAA1570HL has been optimized with approximately 15 dB of gain in the first LNA. To prevent degradation of the system noise figure or dynamic range in subsequent system functions, such as the first mixer or synthesizer, some limitations on the nominal effective gain and noise figure of external devices should be taken into account. The following values are not specified, since exceeding the recommended ranges may still result in adequate dynamic performance in some 1-bit GPS system applications. Note: LNA2 has to be powered-up under all circumstances, i.e. its supply pin has to be connected to VCC under all circumstances due to biasing constraints. Table 4 Operation with external LNAs MODE VCC(LNA1) VCC(LNA2) MAXIMUM RECOMMENDED EXTERNAL GAIN INCLUDING CABLE AND FILTER LOSSES MINIMUM RECOMMENDED EXTERNAL GAIN INCLUDING CABLE AND FILTER LOSSES MAXIMUM RECOMMENDED EXTERNAL NOISE FIGURE INCLUDING CABLE AND FILTER LOSSES INTERNAL CURRENT REDUCTION Normal yes yes 10 dB −3.5 dB 3.5 dB − LNA1 replacement; note 1 no yes 25 dB 8 dB 4 dB 6.5 mA LNA1/LNA2 replacement; notes 1 and 2 no yes 41 dB 21 dB 4 dB 6.5 mA Notes 1. The maximum external noise figure listed is that which will produce approximately a 1 dB degradation in system noise figure using the minimum recommended external gain. The maximum recommended external gain listed results in approximately 1 dB compression in the second mixer input with an in-band continuous wave jammer present (J/S = 35 dB) for nominal processed parts. 2. If a high gain external LNA is used, both LNA1 and LNA2 should be removed from the signal path. However, the LNA2 supply pin has to be connected to VCC to retain power to the first mixer. 1999 May 10 39 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All ground pins are tied together. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Vmax maximum voltage at any pin with respect to ground −0.5 VCC + 0.5 V VCCA analog supply voltage −0.5 +5.5 V VDDD digital supply voltage −0.5 +5.5 V Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb operating ambient temperature VCCA = VDDD = 5 V −40 +85 °C Ves electrostatic handling note 1 −2000 +2000 V Note 1. Human body model: Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 74 K/W 11 DC CHARACTERISTICS Tamb = 25 ±2 °C; test circuit see Fig.25; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies ICCA(LNA1) ICCA(LNA2) ICCA(VCO) Ibias(MX1) IO(MX1) Ibias(MX2) 1999 May 10 LNA1 analog supply current LNA2 analog supply current VCO analog supply current MX1 bias current MX1 output current (pins 17 and 18) MX2 bias current VCCA = 2.7 V 4.27 6.4 8.23 mA VCCA = 3 V 4.79 6.54 8.04 mA VCCA = 5 V 5.3 7.15 8.73 mA VCCA = 2.7 V 5 7.1 8.9 mA VCCA = 3 V 5.22 7.26 9.01 mA VCCA = 5 V 5.68 7.92 9.83 mA VCCA = 2.7 V 2.85 3.74 4.64 mA VCCA = 3 V 2.86 3.77 4.69 mA VCCA = 5 V 2.89 3.82 4.76 mA VCCA = 2.7 V 5.18 7.49 9.03 mA VCCA = 3 V 5.36 7.63 9.13 mA VCCA = 5 V 5.61 8.02 9.63 mA VCCA = 2.7 V 3.84 4.97 5.77 mA VCCA = 3 V 3.89 5.06 5.9 mA VCCA = 5 V 4.06 5.39 6.33 mA VCCA = 2.7 V 1.67 2.36 2.88 mA VCCA = 3 V 1.69 2.39 2.92 mA VCCA = 5 V 1.71 2.44 2.98 mA 40 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL IO(MX2) ICCA(LIM) ICCA(PLL) IDDDL IDDDH Itot(wake) Itot(sleep) Itot(synth) PARAMETER MX2 output current (pins 24 and 25) LIM analog supply current PLL analog supply current LOW TTL digital current HIGH TTL digital current total current (wake state) total current (sleep state) total current (synthesizer state) UAA1570HL CONDITIONS MIN. TYP. MAX. UNIT VCCA = 2.7 V 2.41 3.73 4.56 mA VCCA = 3 V 2.46 3.79 4.62 mA VCCA = 5 V 2.53 3.93 4.81 mA VCCA = 2.7 V 0.9 1.31 1.53 mA VCCA = 3 V 0.97 1.41 1.65 mA VCCA = 5 V 1.39 2 2.34 mA VCCA = 2.7 V 11.45 14.3 16.07 mA VCCA = 3 V 11.67 14.98 17.06 mA VCCA = 5 V 12.2 15.85 18.13 mA 5 kΩ DC load; VDDD = 2.7 V 2.9 3.75 4.6 mA 5 kΩ DC load; VDDD = 3 V 3.02 3.9 4.77 mA 5 kΩ DC load; VDDD = 5 V 3.49 4.58 5.94 mA 5 kΩ DC load; VDDD = 2.7 V 0.13 0.44 0.65 mA 5 kΩ DC load; VDDD = 3 V 0.2 0.5 0.7 mA 5 kΩ DC load; VDDD = 5 V 0.47 0.88 1.15 mA VCCA = VDDD = 2.7 V 46.36 55.1 62.3 mA VCCA = VDDD = 3 V 47.54 56.66 64.26 mA VCCA = VDDD = 5 V 51.04 61.02 69.33 mA VCCA = VDDD = 2.7 V − 116.2 223.5 µA VCCA = VDDD = 3 V − 182.7 323.2 µA VCCA = VDDD = 5 V − 648.4 900.9 µA VCCA = VDDD = 2.7 V 14.36 18.08 20.4 mA VCCA = VDDD = 3 V 14.98 19.02 21.54 mA VCCA = VDDD = 5 V 15.72 20.37 23.27 mA VCCA = VDDD = 2.7 V 781 815 856 mV VCCA = VDDD = 3 V 784 811 843 mV VCCA = VDDD = 5 V 780 807 839 mV VCCA = VDDD = 2.7 V 1.02 1.48 1.71 V VCCA = VDDD = 3 V 1.284 1.75 1.983 V VCCA = VDDD = 5 V 3.115 3.629 3.886 V VCCA = 2.7 V 1.56 1.69 1.87 V VCCA = 3 V 1.87 1.99 2.15 V VCCA = 5 V 3.84 3.99 4.19 V LNA1 and LNA2 VLNAIN VLNAOUT DC operating point LNA1IN and LNA2IN (pins 45 and 3) DC operating point LNA1OUT and LNA2OUT (pins 48 and 6) Reference input; pin 8 VREFIN 1999 May 10 DC operating point REFIN 41 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL PARAMETER UAA1570HL CONDITIONS MIN. TYP. MAX. UNIT VCO; pin 10 VTANK DC operating point TANK VCCA = 2.7 V 1.825 1.918 2.01 V VCCA = 3 V 1.822 1.916 2.011 V VCCA = 5 V 1.818 1.918 2.018 V VCCA = 2.7 V 800 818 846 mV VCCA = 3 V 797 814 839 mV VCCA = 5 V 792 810 837 mV VCCA = 2.7 V 939 983 1011 mV VCCA = 3 V 937 981 1009 mV VCCA = 5 V 936 980 1008 mV Mixer 1; pin 14 VMX1IN DC operating point MX1IN Mixer 2; pins 21 and 22 VIF2IN DC operating point IF2INN and IF2INP Limiter VBFC VLIMIN DC operating point BFCN and BFCP (pins 27 and 30) VCCA = 2.7 V 1.276 1.696 1.831 V VCCA = 3 V 1.578 1.998 2.133 V VCCA = 5 V 3.579 3.999 4.134 V VCCA = 2.7 V 1.276 1.696 1.831 V VCCA = 3 V 1.578 1.998 2.133 V VCCA = 5 V 3.579 3.999 4.134 V 5 kΩ DC load; VCCA = 2.7 V 45 130.6 160.8 mV 5 kΩ DC load; VCCA = 3 V 42 127 157 mV 5 kΩ DC load; VCCA = 5 V − 71.8 − mV 5 kΩ DC load; VCCA = 2.7 V 1.589 1.876 1.956 V 5 kΩ DC load; VCCA = 3 V 1.794 2.168 2.273 V 5 kΩ DC load; VCCA = 5 V 3.566 4.1 4.251 V DC operating point SCLK threshold [0.5 × VCCA(LIM) (pin 31)] VCCA = VDDD = 2.7 V 1.329 1.341 1.353 V VCCA = VDDD = 3 V 1.479 1.491 1.503 V VCCA = VDDD = 5 V 2.478 2.499 2.519 V charge pump output voltage swing VCCA = 2.7 V 0.2 − 2.1 V VCCA = 3 V 0.2 − 2.4 V VCCA = 5 V 0.2 − 4.4 V VCCA = 2.7 V − 240 − µA VCCA = 3 V − 240 − µA VCCA = 5 V − 240 − µA DC operating point LIMINN and LIMINP (pins 28 and 29) SIGN bit output (TTL); pin 34 VOL(SIGN) VOH(SIGN) LOW-level DC operating point output SIGN HIGH-level DC operating point output SIGN SCLK input (CMOS to ECL); pin 37 Vth(SCLK) COMP; pin 40 VO(COMP) Icp(max) 1999 May 10 maximum current sinked or sourced by the charge pump 42 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL 12 AC CHARACTERISTICS Tamb = 25 ±2 °C; default frequency plan; test circuit see Fig.25; unless otherwise specified. S-parameters given below (S11, S22 and S12) are design goals which should be achieved in order to reach the other given values. They are depending on application. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System performance FRX receiver noise figure (LNA1 input to SIGN bit output) f = 1.57542 GHz; VCCA = 3 V; note 1 3.8 4.5 5.2 dB S sensitivity −3 dB; note 2 −103 −106 −109 dBm power gain 50 Ω matched input and output VCCA = 2.7 V 12.3 15.4 18.1 dB VCCA = 3 V 12.4 15.7 18.5 dB VCCA = 5 V 12.9 16.6 19.7 dB VCCA = 2.7 V − −18 −16.3 dB VCCA = 3 V − −18 −16.2 dB VCCA = 5 V − −18 −16.2 dB LNA 1; note 3 S21LNA1 S11LNA1 S12LNA1 S22LNA1 IP3LNA1 IP2LNA1 1999 May 10 input reflection coefficient reverse isolation output reflection coefficient 3rd-order input intercept point 2nd-order input intercept point 50 Ω matched input and output 50 Ω matched input and output VCCA = 2.7 V − −38.9 −29.9 dB VCCA = 3 V − −38 −29 dB VCCA = 5 V − −35.6 −26.6 dB VCCA = 2.7 V − −21.2 −12.7 dB VCCA = 3 V − −18 −13.4 dB VCCA = 5 V − −10.8 −8.7 dB VCCA = 2.7 V −17 −13.4 − dBm VCCA = 3 V −16.8 −13.2 − dBm VCCA = 5 V −16.6 −12.6 − dBm 50 Ω matched input and output 50 Ω matched input and output 50 Ω matched input and output VCCA = 2.7 V − 7.7 − dBm VCCA = 3 V − 7.9 − dBm VCCA = 5 V − 8.6 − dBm 43 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL CP−1dB(LNA1) FLNA1 PARAMETER −1 dB input compression point noise figure LNA1 UAA1570HL CONDITIONS MIN. TYP. MAX. UNIT 50 Ω matched input and output VCCA = 2.7 V −26.6 −22.2 − dBm VCCA = 3 V −26.6 −22.2 − dBm VCCA = 5 V −28.2 −22 − dBm VCCA = 2.7 V − 3.6 4.7 dB VCCA = 3 V − 3.6 4.3 dB VCCA = 5 V − 3.6 4.2 dB 50 Ω matched input and output LNA 2; note 3 S21LNA2 S11LNA2 S12LNA2 S22LNA2 IP3LNA2 IP2LNA2 1999 May 10 power gain input reflection coefficient reverse isolation output reflection coefficient 3rd-order input intercept point 2nd-order input intercept point 50 Ω matched input and output VCCA = 2.7 V 11.4 14.8 18.2 dB VCCA = 3 V 12.1 15.3 18.5 dB VCCA = 5 V 11.6 15.9 20.3 dB VCCA = 2.7 V − −18.5 −14.2 dB VCCA = 3 V − −18 −13.5 dB VCCA = 5 V − −17.1 −12.6 dB VCCA = 2.7 V − −35.8 −26.8 dB VCCA = 3 V − −34.9 −25.9 dB VCCA = 5 V − −32.5 −23.5 dB VCCA = 2.7 V − −18.4 −14.9 dB VCCA = 3 V − −18 −15 dB VCCA = 5 V − −15.7 −14.1 dB 50 Ω matched input and output 50 Ω matched input and output 50 Ω matched input and output 50 Ω matched input and output VCCA = 2.7 V −28.6 −13.5 − dBm VCCA = 3 V −16.9 −12.8 − dBm VCCA = 5 V −16.3 −12 − dBm VCCA = 2.7 V − 7.7 − dBm VCCA = 3 V − 7.9 − dBm VCCA = 5 V − 8.6 − dBm 50 Ω matched input and output 44 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL CP−1dB(LNA2) FLNA2 PARAMETER −1 dB input compression point noise figure LNA2 UAA1570HL CONDITIONS MIN. TYP. MAX. UNIT 50 Ω matched input and output VCCA = 2.7 V −28.1 −22.4 − dBm VCCA = 3 V −27.1 −22.6 − dBm VCCA = 5 V −26.6 −22.2 − dBm VCCA = 2.7 V − 3.7 4.4 dB VCCA = 3 V − 3.7 4.3 dB VCCA = 5 V − 3.8 6.3 dB VCCA = 2.7 V 0.032 0.0513 0.0813 A/V VCCA = 3 V 0.0334 0.0531 0.0837 A/V VCCA = 5 V 0.0403 0.0593 0.0889 A/V VCCA = 2.7 V 23.9 27.1 32.1 dBV VCCA = 3 V 24.3 27.5 32.4 dBV VCCA = 5 V 25.7 28.4 32.7 dBV VCCA = 2.7 V 14.5 17.7 22.6 dB VCCA = 3 V 14.8 18 22.9 dB VCCA = 5 V 16.2 18.9 23.2 dB VCCA = 2.7 V − −17.8 −15.9 dB VCCA = 3 V − −18 −16.2 dB VCCA = 5 V − −18.9 −16.6 dB 50 Ω matched input and output Mixer 1 Y21MX1 Gconv(v) Gconv(p) S11MX1 CP−1dB(MX1) 1999 May 10 conversion transconductance voltage conversion gain power conversion gain input reflection coefficient −1 dB input compression point 50 Ω matched input and 800 Ω matched output; note 4 50 Ω matched input and output; note 5 50 Ω matched input and 800 Ω matched output; note 6 50 Ω matched input and 800 Ω matched output 50 Ω matched input and 800 Ω matched output; note 6 VCCA = 2.7 V −29.7 −25.4 − dBm VCCA = 3 V −31.2 −25.4 − dBm VCCA = 5 V −31 −25.4 − dBm 45 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL FDSB(MX1) PARAMETER double-side band noise figure MX1 UAA1570HL CONDITIONS MIN. TYP. MAX. UNIT 50 Ω matched input and 800 Ω matched output; note 6 VCCA = 2.7 V − 12.8 16.8 dB VCCA = 3 V − 12 15.8 dB VCCA = 5 V − 10 12.7 dB VCCA = 2.7 V 0.0252 0.0293 0.0344 A/V VCCA = 3 V 0.0171 0.0294 0.0438 A/V VCCA = 5 V 0.0258 0.03 0.0352 A/V VCCA = 2.7 V 17.8 21.4 25.5 dBV VCCA = 3 V 17.8 21.4 25.6 dBV VCCA = 5 V 18 21.6 25.8 dBV VCCA = 2.7 V 17.8 21.4 25.6 dB VCCA = 3 V 17.8 21.4 25.6 dB VCCA = 5 V 18 21.6 25.8 dB Mixer 2 Y21MX2 Gconv(v) Gconv(p) Ri(dif) Ci(dif) conversion transconductance voltage conversion gain power conversion gain differential input resistance differential input capacitance CP−1dB(MX2)(M) −1 dB differential input compression point FDSB(MX2) 1999 May 10 double-side band noise figure MX2 800 Ω matched input and output; note 7 800 Ω matched input and output; note 8 800 Ω matched input and output; note 9 note 10 VCCA = 2.7 V 1.6 2.05 2.45 kΩ VCCA = 3 V 1.6 2.05 2.45 kΩ VCCA = 5 V 1.6 2.05 2.45 kΩ VCCA = 2.7 V 0.9 1 1.1 pF VCCA = 3 V 0.9 1 1.1 pF VCCA = 5 V 0.9 1 1.1 pF VCCA = 2.7 V 50 67.2 84.3 mV VCCA = 3 V 44 67.2 90.3 mV VCCA = 5 V 44.6 67.2 89.8 mV note 10 800 Ω matched input and output (peak value); note 9 800 Ω matched input and output; note 9 VCCA = 2.7 V − 4.8 6.1 dB VCCA = 3 V − 4.8 5.5 dB VCCA = 5 V − 4.8 7 dB 46 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL PARAMETER UAA1570HL CONDITIONS MIN. TYP. MAX. UNIT Limiter Gv(lim) Ri(dif) small signal limiting voltage gain differential input resistance 800 Ω matched limiter input to internal limiter output VCCA = 2.7 V − 64.5 − dB VCCA = 3 V 61.8 65.7 69.5 dB VCCA = 5 V − 66.0 − dB VCCA = 2.7 V 4.10 4.85 6.67 kΩ VCCA = 3 V 4.11 4.87 6.69 kΩ VCCA = 5 V 4.15 4.92 6.76 kΩ 0.25 0.28 0.31 pF VCCA = 2.7 V − 16.5 − dB VCCA = 3 V 12.0 15.0 17.0 dB VCCA = 5 V − 11.0 − dB VCCA = 2.7 V 46 100 154 µV VCCA = 3 V 68.8 100 131.2 µV VCCA = 5 V 46 100 154 µV VCCA = 2.7 V − 38.9 − dB VCCA = 3 V − 39.0 − dB VCCA = 5 V − 39.6 − dB VCCA = 2.7 V − 23.2 − kΩ VCCA = 3 V − 23.4 − kΩ VCCA = 5 V − 23.7 − kΩ VCCA = 2.7 V − 0.86 − pF VCCA = 3 V − 0.84 − pF VCCA = 5 V − 0.74 − pF 50 Ω terminated source − 42.5 − MHz note 10 Ci(dif) differential input capacitance Flim limiter noise figure referred to 800 Ω 800 Ω matched source; note 11 Slim(M) differential limiter sensitivity note 10 800 Ω matched source (peak value); note 11 SCLK (sample clock conditioning) Gv(SCLK) Ri(SCLK) Ci(SCLK) BSCLK 1999 May 10 small signal voltage gain input resistance input capacitance small signal bandwidth 50 Ω terminated SCLK input to internal DFF clock input note 10 note 10 47 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit SYMBOL SSCLK(M) PARAMETER SCLK sensitivity UAA1570HL CONDITIONS MIN. TYP. MAX. UNIT 50 Ω terminated source (peak value) VCCA = 2.7 V 10 − − mV VCCA = 3 V 10 − − mV VCCA = 5 V 10 − − mV VCCA = 2.7 V − −14.5 − Ω VCCA = 3 V − −14.7 − Ω VCCA = 5 V − −15.0 − Ω VCCA = 2.7 V − 2.61 − pF VCCA = 3 V − 2.56 − pF VCCA = 5 V − 2.47 − pF VCO Ri(1.4GHz)(seqn) Ci(1.4GHz)(seq) Ri(1.5GHz)(seqn) Ci(1.5GHz)(seq) Ri(1.6GHz)(seqn) Ci(1.6GHz)(seq) VVCO(M) KVCO(av) series equivalent negative resistance at 1.4 GHz (only for reference) series equivalent capacitance at 1.4 GHz (only for reference) series equivalent negative resistance at 1.5 GHz (only for reference) series equivalent capacitance at 1.5 GHz (only for reference) series equivalent negative resistance at 1.6 GHz (only for reference) series equivalent capacitance at 1.6 GHz (only for reference) first LO signal level (peak value) average VCO gain in typical application VCCA = 2.7 V − −12.1 − Ω VCCA = 3 V − −12.3 − Ω VCCA = 5 V − −12.6 − Ω VCCA = 2.7 V − 3.06 − pF VCCA = 3 V − 3.00 − pF VCCA = 5 V − 2.90 − pF VCCA = 2.7 V − −10.4 − Ω VCCA = 3 V − −10.7 − Ω VCCA = 5 V − −11.0 − Ω VCCA = 2.7 V − 2.94 − pF VCCA = 3 V − 2.89 − pF VCCA = 5 V − 2.78 − pF VCCA = 2.7 V − − 0.9 V VCCA = 3 V − − 0.9 V VCCA = 5 V − − 0.9 V note 12 VCCA = 2.7 V − 84.84 − MHz/V VCCA = 3 V 61.7 96.62 101 MHz/V VCCA = 5 V − 67.15 − MHz/V 1 14.4 35 MHz relative to 50 Ω −32.27 +5 +9.75 dBm − 20 − kΩ VCCA = 2.7 V − 72 − dBc/Hz VCCA = 3 V − 72 − dBc/Hz VCCA = 5 V − 72 − dBc/Hz Synthesizer fi(ref) reference input frequency Pi(ref) reference input level Zi(ref) reference input impedance PN10kHz PLL phase noise 10 kHz offset 1999 May 10 note 12 48 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL Notes 1. The noise figure of the GPS application board is estimated from the −3 dB sensitivity testing by substitution using a 10 dB external LNA with a noise figure of less than 2 dB. 2. The sensitivity of the GPS application board is measured by recording the RF level required to observe a 3 dB drop in the sampled L1 signal, after sampling to 1.32 MHz product [3.48 MHz(IF2) − 4.8 MHz (fsample)] in the SIGN bit output. 3. At L1 (1.57542 GHz) with a −35 dBm input with matching components tuned at 3 V at Tamb = 25 °C. 4. From the matched single-ended RF mixer preamplifier input to the differential IF output of MX1. 5. From the matched single-ended RF mixer preamplifier input to the differential IF output of MX1 across an equivalent 400 Ω loading of an 800 Ω termination and transformer differential load (4 : 1 ratio to a 50 Ω measurement termination). 6. From the matched single-ended RF input to the differential IF output of MX1 into an equivalent 400 Ω differential load. Half of the delivered conversion gain power is delivered to an 800 Ω termination, with the remaining power transformed (z-ratio 16 : 1) down and delivered to a 50 Ω termination. The available tabulated power is 3 dB higher than the power delivered to the 50 Ω termination. 7. From the differential transformer matched RF input to the differential IF output of MX2. 8. From the differential transformer matched RF input to the differential IF output of MX2 across an equivalent 400 Ω loading of an 800 Ω termination and transformer differential load (4 : 1 ratio to a 50 Ω measurement termination). 9. From the differential transformer matched RF input to the differential IF output of MX2 into an equivalent 400 Ω differential load. Half of the delivered conversion gain power is delivered to an 800 Ω termination, with the remaining power transformed (z-ratio 16 : 1) down and delivered to a 50 Ω termination. The available tabulated power is 3 dB higher than the power delivered to the 50 Ω termination. The back-to-back 50 Ω : 800 Ω : 800 Ω : 50 Ω response characteristics of mini circuits RF transformer T16-6T are provided in Fig.11. 10. Simulated values without external pin strays. 11. Due to test time constraints the sensitivity of the limiter is measured indirectly in the current ATE test definition. Bench characterization using a 1 : 16 Ω ratio transformer established −3 dB limiting sensitivity at 100 µV (peak value) across the 800 Ω terminated transformer output at the limiter input. This sensitivity is not due to gain limitations, but rather intrinsic complex broadband noise characteristics over an estimated 800 MHz equivalent sampled spectral bandwidth. However, the measured −82 dBm sensitivity of the device in an 800 Ω operating environment defines the minimum level which can be detected in the sampling quantizer. The ATE test method results perform about 8.2 dBV better than bench characterization using conventional −3 dB limiting. The specification results represent the ATE results degraded by 8.2 dB. The limiter noise figure test is being degraded by 800 Ω transformer termination loss. Only a weak and remote correlation exist between highly non-linear noise figure measurements made on a time sampled quantizer output and linear simulation results. 12. The peak VCO tank swing and phase noise are measured in the default application board. With high Q resonators the peak voltage swing at the resonator pin should be limited to <0.8 V (peak value). A de-biasing resistor can be added from the TANK pin to ground. 1999 May 10 49 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... TRACE L17 4.7 nH C53 1.2 pF X TRACE TRACE Y Z C51 1.2 pF TRACE TRACE Y Z L15 33 nH R18 Vtune C49 0.01 µF C46 C45 5.1 kΩ 0.047 µF C47 0.1 µF C44 C42 100 pF C48 100 pF C43 48 47 46 45 44 43 42 41 40 39 38 LNA2IN J1 SMA LNA2OUT J2 SMA L2 X 4.7 nH C3 C4 1.5 pF C6 1.2 pF TRACE C5 Y 2 35 3 34 C39 100 pF TRACE Y Z 5.1 kΩ 4 33 5 32 6 31 C36 29 0.01 µF C32 28 50 11 10 Ω G L5 5.6 nH C11 100 nF TXS1134M R4 2.4 kΩ J5 3WB 14 Z C12 4.7 pF Y VR1 R19 100 Ω R20 100 Ω C54 10 pF R21 100 Ω C55 10 pF 15 SMV1204-133 R3 10 kΩ C14 1.0 pF L6 3.9 nH C56 10 pF 18 C16 20 C17 C19 R6 100 pF C20 820 Ω 0.01 µF 19 21 22 23 T4 T16-6T R9 STROBE R8 1.2 kΩ 0.01 µF C30 C24 R11 LENGTH (MILS) (VIA) Z (62 Ω) 894 125 75 LNA1OUT 1261 568 125 45 220 nH LNA2IN 586 932 125 89 C23 100 pF LNA2OUT 345 1005 125 C22 0.01 µF 85 MIX1IN 1565 311 125 69 C25 1 nF R7 C18 C26 0.01 µF C27 100 pF T3 T16-6T R10 IF1P J7 SMA C29 IF2P J8 SMA 4 LAYER FR4 BOARD 125 MILS THICK 50 Ω COPLANAR MICROSTRIP H = 12 MILS W = 20 MILS G = 10 MILS 62 Ω COPLANAR MICROSTRIP H = 12 MILS W = 12 MILS G = 11.5 MILS MHB288 Fig.25 Characterization test circuit. Product specification TRACE C21 1 nF T1 T16-6T Y (50 Ω) 1500 C28 L8 X LNA1IN L10 220 nH 220 nH MIX2IN J9 SMA T2 T16-6T L9 0 nH L7 33 nH 820 Ω UAA1570HL MIXIN J6 SMA LIMINP J10 SMA 24 L11 X C57 2.2 µF 17 C15 C13 SELECT VCC 16 100 pF C100 STROBE DATA CLOCK R12 C34 R15 25 13 R5 2.4 kΩ C10 15 pF 0.1 µF C33 26 12 Vtune TRACE Out R13 820 Ω C31 0.01 µF Johnstech International jti-TS048QFP07-0.50 Giga 3 socket TRACE VCC R14 27 10 TCXO 0.1 µF C8 100 pF 220 nH C38 0.01 µF 0.01 µF C35 R2 C37 100 pF 30 8 C9 0.01 µF VDDD POST C41 2.2 µF DATA UAA1570HL 7 9 G 33 nH L12 CLOCK L4 33 nH SIGN J11 SMA R16 Z C7 R1 51 Ω C40 0.01 µF L13 J4 JUMPER EXT REFIN J3 SMA L14 220 nH TRACE TRACE L3 0 nH X AGND 36 C2 100 pF TRACE TRACE 100 pF 37 1 C1 0.01 µF AGND 0.01 µF C50 L1 33 nH SCLK J12 SMA R17 51 Ω Philips Semiconductors 5.6 nH C52 Global Positioning System (GPS) front-end receiver circuit L16 X 13 CHARACTERIZATION TEST CIRCUIT LNA1OUT J14 SMA TRACE book, full pagewidth 1999 May 10 LNA1IN J13 SMA Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit Table 5 UAA1570HL Component list for Fig.25 COMPONENT CHARACTERISTICS COMPONENT C1, C7, C9, C16, C20, C22, C26, C31, C36, C38, C40, C42 and C49 C2, C8, C15, C19, C23, C27, C37, C39, C43, C47 and C48 VALUE TOLERANCE PACKAGE 0.01 µF 10% 603 100 pF 5% 603 not loaded − − C4 1.5 pF ±0.25 pF 805 C6, C51 and C53 1.2 pF ±0.25 pF 805 C10 15 pF 5% 603 not loaded − − C12 4.7 pF ±0.25 pF 603 C13 short − − C14 1.0 pF ±0.25 pF 805 C3, C5, C50 and C100 C11(1) not loaded − − 1000 pF 5% 603 C32, C35 and C45 0.1 µF 10% 603 C33, C34 and C44 not loaded − − C17, C18, C24, C28, C29 and C30 C21 and C25 C41 and C57(2) C46 C52 C54 to C56(3) R1 and R17 R2(4) 2.2 µF 10% − 0.047 µF 10% 603 not loaded − − 10 pF 5% 603 51 Ω 1% 603 not loaded − − R3 10 kΩ 1% 603 R4 and R5 2.4 kΩ 1% 603 R6, R9 and R13 820 Ω 1% 603 R7, R10 and R11 not loaded − − R8 1.2 kΩ 1% 603 R12 not loaded − − R14 not loaded − − R15 not loaded − − R16(5) 5.1 kΩ 1% 603 R18 5.1 kΩ 1% 603 R19, R20 and R21 100 Ω 5% 603 L1, L4, L7, L13 and L15 33 nH 10% 805 (Coilcraft) L2 and L17 4.7 nH ±0.3 nH 805 (Toko) L3 short − − L5 5.6 nH ±0.3 nH 603 (Toko) L6 3.9 nH ±0.3 nH 805 (Toko) L8, L10, L11, L12 and L14 220 nH 10% 805 (Coilcraft) short − − L9 1999 May 10 51 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL COMPONENT CHARACTERISTICS COMPONENT L16 VR1 VALUE TOLERANCE PACKAGE 5.6 nH ±0.3 nH 805 (Toko) SMV1204-133 low capacitance varactor (Alpha) T1 to T4 transformer Mini circuits T16-6T-KK81/W38, 16 : 1 impedance ratio TCXO(6) not loaded − Notes 1. 0.1 µF, 10%, 603 if used. 2. 16 V voltage rating. 3. For default frequency plan: short. 4. 10 Ω, 5%, 603 if used. 5. For AC characterization, terminate with 50 Ω to ground and use a 50 Ω input test instrument. 6. TXS1134MTEW if used. 1999 May 10 52 − Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL 14 DEFAULT APPLICATION AND DEMONSTRATION BOARD handbook, full pagewidth VRTC VRTC RCLK RCLK VBB SCLK SCLK BATT_ON BATT_ON SIGN SIGN BATT_OFF BATT_OFF VBB RFDATA RFCLK RFLE POWER SUPPLY DIGITAL PROCESSOR RFDATA RFCLK RFLE RF FRONT-END MHB492 Fig.26 Overall schematic. 1999 May 10 53 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit handbook, full pagewidth UAA1570HL VCC R207 470 Ω D201 BAS16 U206 ZM33064 VCC VCC 2 U207 ZM33164 VCC OUT 3 2 OUT 3 1 1 C209 10 µF (6.3 V) GND VCC VCC GND R206 10 kΩ GND R205 10 kΩ U204 GND PWRFAIL TP217 TP216 PWRDN C207 TP215 XTAL1 TP214 Y201 30 MHz TP229 C208 R204 1 MΩ GND XTAL2 TP213 R203 XTAL3 TP212 XTAL4 180 Ω 10 pF C205 27 pF Y202 32.678 kHz R202 10 MΩ C206 R201 27 pF 0Ω GND TxD0 RxD0 TxD1 RxD1 TP211 TP210 TP209 TP208 GND TP4 VCC VCC TP230 n.c. n.c. n.c. TP207 TEST1 TEST2 JP201 JMP3 JP202 TP2 VCC 1 2 3 4 5 6 7 8 9 10 GND HEADER 10 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO7 GPIO6 GPIO5 TP203 RCLK SCLK TP204 SIGN BATT_ON BATT_OFF BATT_ON BATT_OFF IF1 IF2 TP3 SIGN VCC RCLK SCLK SIGN 73 14 47 15 46 45 76 40 39 36 35 34 33 32 29 28 27 24 23 22 21 20 19 18 11 10 75 83 84 81 82 4 8 9 97 99 100 42 96 95 94 88 87 5 6 7 SAA1575HL GND TP201 TP202 RCLK SCLK 44 52 41 GND 10 pF 74 TP205 TP206 VCC T1S_OUT T1S BATT_ON PWRB BATT_OFF 98 1 93 92 3 70 69 68 67 64 63 62 59 58 57 56 55 54 53 49 48 89 90 91 2 16 25 77 PWRM 78 RSTIME 43 VSS 13 VSS 17 VSS 26 VSS 31 VSS 38 VSS 50 VSS 60 VSS 65 VSS 71 VSS 79 VSS 85 37 51 61 86 12 30 66 72 80 TP1 PMCS DMCS RD WRL WRH GND TP218 TP225 TP219 TP220 TP221 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RFDAT RFCLK RFLE VCC(P) VCC(P) VCC(P) VCC(P) VCC(P) VCC(P) TP222 TP223 TP224 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC(core) VDD1 VCC(core) VDD2 VCC(core) VDD3 VCC(R) VCC(B) VRTC1 VBB1 GND VDD1 VDD2 C210 33 nF VDD3 C211 33 nF VBB1 C212 33 nF VRTC1 C213 33 nF VCC1 C214 33 nF VCC2 C215 33 nF VCC3 C216 33 nF VCC4 C217 33 nF VCC5 C218 33 nF VCC6 C219 33 nF C220 33 nF VCC C221 33 nF C222 33 nF C223 33 nF C224 33 nF MHB290 GND Fig.27 Baseband circuitry (continued in Fig.28). 1999 May 10 54 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit handbook, full pagewidth J201 C201 C202 100 nF (50 V) 100 nF (50 V) U201 5 9 4 8 3 7 2 6 1 T1OUT 2 T2OUT 3 T3OUT 1 T4OUT 28 DB9 /R1IN /R2IN /R3IN /R4IN /R5IN J202 5 9 4 8 3 7 2 6 1 DB9 C1+ 12 C1− 14 C2+ 15 C2− 16 VCC 9 4 27 23 18 UAA1570HL C203 13 17 7 6 20 21 8 5 26 22 19 24 25 VCC 100 nF (50 V) V+ V− C204 /T1IN /T2IN /T3IN /T4IN TXD0 TXD1 R1OUT R2OUT R3OUT R4OUT R5OUT RXD0 RXD1 EN /SHDN 100 nF (50 V) GND VCC U202 VCC MAX213EAI GND RFD R224 RFDATA 220 Ω RFC R223 R222 TP226 28 14 D8 D9 D10 D11 D12 D13 D14 D15 VBB GND U203 RFLE R208 open VCC3 TP228 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 /DMCS /RD /WRL /CE /OE /WE C225 47 µF (6.3 V) VCC4 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 11 12 13 15 16 17 18 19 20 22 27 28 14 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 VBB GND M5M5256BVP GND U205 R216 VCC 1Ω VDD1 C226 47 µF (6.3 V) VDD2 GND VBB1 20 22 27 D0 D1 D2 D3 D4 D5 D6 D7 M5M5256BVP VCC2 VRTC1 11 12 13 15 16 17 18 19 TP227 VCC1 VDD3 /CE /OE /WE 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 RFCLK R209 open GND VCC6 /DMCS /RD /WRH RFDATA R210 open RFLE 220 Ω VCC5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 RFCLK 220 Ω RFL A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 R213 1Ω R212 1Ω R211 1Ω VDD VRTC VBB A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 /PMCS /CE /OE VCC 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 41 42 44 3 22 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 12 34 2 43 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D11 D12 D13 D14 D15 D16 GND VPP /PGM VCC 27C202 GND Fig.28 Baseband circuitry (continued from Fig.27). 1999 May 10 55 MHB291 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit handbook, full pagewidthVRF UAA1570HL VRF L306 180 nH L307 180 nH C345 1 µF (16 V) R324 open C308 open R322 L309 open L308 27 µH R304 0Ω R323 AGND 12 kΩ AGND C343 2.21 kΩ 4700 pF M1BIASP M1BIASN M2BIASP VRF M2BIASN VRF VCCA R317 10 kΩ VRF R320 X301 TCO-987Q R326 10 kΩ 7 5 R327 10 kΩ 1 4 2.21 kΩ R321 C344 10 nF (50 V) 8 3 2.21 kΩ R318 10 kΩ AGND 6 2 + − U302 MAX903ESA 1 8 4 5 AGND DGND AGND AGND C341 3.9 nF AGND C342 C340 150 pF R314 R319 20 kΩ P39GND AGND R315 2.7 kΩ 2.7 kΩ COMP P12GND 3 AGND REFIN 4700 pF C338 L305 15 pF 6.8 nH TANK DATA RFDATA CLOCK RFCLK D301 SMV1233-004 1 2 STROBE RFLE SIGN SIGN AGND C348 R313 SCLK 6.8 kΩ R316 10 kΩ AGND C339 4.7 pF AGND R312 3.9 kΩ 10 pF SCLK C337 33 nF BFCP LIMINP LIMINN AGND C336 VCC C333 33 nF VRF C346 33 nF BFCN C335 33 nF VCCA(LNA1) 33 nF C334 VCCA(LNA2) 33 nF VCCA(PLL) C347 8 39 40 12 10 32 7 23 34 37 30 29 28 27 43 1 36 VCCA(LIM) open AGND 31 C332 VCCA(MX2) C330 33 nF VCCA(MX1P) 19 33 nF P41GND C331 VCCA(VCO) 33 nF C329 VDDD 33 nF DGND AGND R310 18 Ω R311 18 Ω VRF R309 VDDD open R325 VCCD MHB292 1Ω Fig.29 RF front-end circuit (continued in Fig.30). 1999 May 10 56 7 6 16 41 9 33 UAA1570HL RCLK Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL handbook, full pagewidth L = 900 mils W = 8.8 mils VRF R303 R307 9Ω 9Ω L = 1020 mils W = 8.8 mils C328 33 nF (50 V) C327 10 pF (50 V) AGND AGND J301 SMA-F C325 L = 315 mils (8.1 mm) W = 6 mils 100 Ω C324 1.5 pF 27 pF L = 367 mils (9.3 mm) W = 33 mils 50 Ω C326 0.56 pF BPF301 MF1012S-1 L = 355 mils (9 mm) W = 6 mils 100 Ω I/O C321 0.27 pF 45 48 3 6 14 17 18 21 22 24 25 AGND AGND AGND 2 5 1 C307 open 3 4 I/O 6 C323 2.2 pF LNA1IN AGND LNA1OUT AGND L = 286 mils (7.3 mm) AGND AGND W = 6 mils 100 Ω LNA2IN LNA2OUT MX1IN L = 412 mils (10.5 mm) W = 6 mils 100 Ω IF1P L = 217 mils (5.5 mm) W = 33 mils 50 Ω I/O IF1N C320 1.2 pF IF2INN IF2INP AGND AGND 2 5 1 C306 0.47 pF IF2P BPF302 MF1012S-1 L = 386 mils (10 mm) 3 4 I/O 6 C322 2.2 pF AGND AGND W = 6 mils 100 Ω IF2N C315 C317 6.8 pF 8.2 pF UAA1570HL 44 46 47 5 4 2 42 38 26 20 13 15 11 35 LNA1GND1 M1BIASP BIASGND1 L303 330 nH C313 36 pF LNA1GND2 L304 330 nH C314 36 pF C316 C318 6.8 pF 8.2 pF C319 39 pF R306 909 Ω LNA2GND2 M1BIASN BIASGND2 LNA2GND1 P42GND C305 open AGND PLLGND LIMGND MX2GND MXPGND C302 C311 C303 LIMINP MX1GND 47 pF M2BIASP C301 82 pF VCOGND DGND M2BIASN 47 pF C309 18 pF L301 22 µH L302 22 µH C304 R301 open 0Ω C310 68 pF 1000 pF R305 820 Ω C312 LIMINN 1000 pF R302 0Ω DGND AGND AGND Fig.30 RF front-end circuit (continued from Fig.29). 1999 May 10 57 MHB293 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL D101 handbook, full pagewidth TP101 VCC LL4007 PL101 JMP3 U101 IN ADJ 3 2 R101 OUT 1 R118 270 Ω LM317T(3) C102 1 nF GND GND C109 10 µF (10 V) C107 1 µF (20 V) C101 1 nF GND C108 22 µF (5 V) R119 820 Ω GND GND VCC 1Ω D102 LL4007 GND GND D103 TP102 VRF LL4007 U102 IN ADJ 3 2 R102 OUT 1 LM317T(3) C103 1 nF C104 1 nF JP101 C116 10 µF (10 V) C115 1 µF (20 V) R121 390 Ω VRF 1Ω D104 LL4007 R120 240 Ω VBAT R117 1 kΩ C110 22 µF (5 V) B101 3V 170 mAh 1 2 GND R122 3 V/5 V 330 Ω VBAT VCC VCC R111 1 MΩ R113 47 kΩ R109 R112 V102 BC848 470 Ω R110 V103 BC858 1 MΩ 1 MΩ BATT_ON VBB GND VDD C112 470 nF R114 GND GND GND R115 10 MΩ C114 22 µF (6.3 V) V101 BC848 BATT_OFF V105 BC858 47 kΩ VBAT V104 BC858 V106 BC858 R116 10 MΩ VRTC TP103 VDD(IN) U103 LP2951CM IN VCC SD FB 1 8 5 3 2 7 6 4 C105 100 nF C113 22 µF (6.3 V) OUT R103 ERR 1Ω SNSE VTAP R106 18 kΩ GND VDD C106 100 nF C111 10 µF (6.3 V) GND R108 12 kΩ GND GND GND GND GND GND MHB294 Fig.31 Power supply circuitry. 1999 May 10 58 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL The GPS system application demonstration board consists of 6 layers with a total final thickness of 1.5 mm. The PCB material is FR4. handbook, full pagewidth 3 V/170 mAh U101 C109 + R118 R119 C102 R101 R103 C223 C101 VCC IN U102 C116 RS232 #1 C107 1 GPS DEMO BOARD Version 1.3 U205 C115 X301 + JP101 SIGN DAC RCLK SCLK T1S_OUT R326 C327 R303 C328 R327 BATT_ON RXD0 C212 C214 R122 U204 C210 R307 C215 BPF302 C312 C301 R306 D301 R311 C322 C318 C305 L303 C319 C302 R310 L304 L301 C309 C213 C211 C217 PMCS R302 L302 L305 * C219 R325 1 R309 C209 WRH WRL RD PWRDN C306 C338 R316 C216 C329 C311 * R314 C334 C320 RS232 #0 R205 R319 R305 R301 C310 C303 C325 C341 U301 C324 C326 BATT_OFF U201 RXD1 TXD1 TXD0 U207 VRF IN DMCS PWRFAIL RFDATA RFCLK RFLE R213 R212 R120 R121 R102 R216 C220 R211 C213 C103 R208 R222 R209 R223 R210 R224 PL101 VDD IN PTEST R206 U206 GND/VCC 1 JP202 C317 C314 MHB295 Fig.32 Demonstration board top layer plus components (real size 88.9 mm × 88.9 mm). 1999 May 10 59 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL handbook, full pagewidth MHB296 Fig.33 Demonstration board 2nd layer. 1999 May 10 60 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL handbook, full pagewidth MHB297 Fig.34 Demonstration board 3rd layer. 1999 May 10 61 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL handbook, full pagewidth MHB298 Fig.35 Demonstration board 4th layer. 1999 May 10 62 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL handbook, full pagewidth MHB299 Fig.36 Demonstration board 5th layer. 1999 May 10 63 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit handbook, full pagewidth 3 V/170 mAh U101 C109 + R118 R119 C102 R101 RS232 #1 R103 C223 C101 VCC IN U102 C116 VDD IN C107 1 GPS DEMO BOARD Version 1.3 U205 C115 X301 + JP101 SIGN DAC RCLK SCLK T1S_OUT R326 C327 R303 C328 R327 BATT_ON RXD0 C212 C214 R122 U204 C210 R307 C215 BPF302 C312 C301 R306 D301 R311 C322 C318 C305 L303 C319 C302 R310 L304 L301 C309 C213 C211 C217 PMCS R302 L302 L305 * C219 R325 1 R309 C209 WRH WRL RD PWRDN C306 C338 R316 C216 C329 C311 * R314 C334 C320 RS232 #0 R205 R319 R305 R301 C310 C303 C325 C341 U301 C324 C326 BATT_OFF U201 RXD1 TXD1 TXD0 U207 VRF IN DMCS PWRFAIL RFDATA RFCLK RFLE R213 R212 R120 R121 R102 R216 C220 R211 C213 C103 R208 R222 R209 R223 R210 R224 PL101 UAA1570HL PTEST R206 U206 GND/VCC 1 JP202 C317 C314 MHB300 Fig.37 Demonstration board bottom layer plus components. 1999 May 10 64 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit Table 6 UAA1570HL Component list for GPS demonstration board COMPONENT CHARACTERISTICS COMPONENT B101 TYPE Lithium battery VALUE TOLERANCE PACKAGE 3 V/170 mAh − CR1/3 C101 to C104, C311 and C312 ceramic capacitor 1 nF/50 V 10% 603 C105, C106, C201 to C204 ceramic capacitor 100 nF/50 V 20% 603 C107 and C115 ceramic capacitor 1 µF/63 V 20% 1210 C108 and C110 tantalum capacitor 22 µF/16 V 20% − C109 and C116 tantalum capacitor 10 µF/16 V 20% − C111 and C209 tantalum capacitor 10 µF/6.3 V 20% − C112 ceramic capacitor 470 nF/63 V 20% 1206 C113 and C114 tantalum capacitor 22 µF/6.3 V 20% − C205, C206 and C325 ceramic capacitor 27 pF/50 V 5% 603 C207, C208, C327 and C348 ceramic capacitor 10 pF/50 V 5% 603 C210 to C224, C328 to C337 and C346 ceramic capacitor 33 nF/63 V 10% 603 C225 and C226 tantalum capacitor 47 µF/6.3 V 20% − C301 ceramic capacitor 82 pF/50 V 5% 603 C302 and C303 ceramic capacitor 47 pF/50 V 5% 603 − not loaded − − C306 ceramic capacitor 0.47 pF/50 V ±0.1 pF 603 C309 ceramic capacitor 18 pF/50 V 5% 603 C310 ceramic capacitor 68 pF/50 V 5% 603 C313 and C314 ceramic capacitor 36 pF/50 V 5% 603 C315 and C316 ceramic capacitor 6.8 pF/50 V ±0.25 pF 603 C317 and C318 ceramic capacitor 8.2 pF/50 V ±0.25 pF 603 C319 ceramic capacitor 39 pF/50 V 5% 603 C320 ceramic capacitor 1.2 pF/50 V ±0.25 pF 603 C321 ceramic capacitor 0.27 pF/50 V ±0.1 pF 603 C322 and C323 ceramic capacitor 2.2 pF/50 V ±0.25 pF 603 C324 ceramic capacitor 1.5 pF/50 V ±0.25 pF 603 C326 ceramic capacitor 0.56 pF/50 V ±0.1 pF 603 C338 ceramic capacitor 15 pF/50 V 5% 603 C339 ceramic capacitor 4.7 pF/50 V ±0.25 pF 603 C340 ceramic capacitor 150 pF/50 V 5% 603 C341 ceramic capacitor 3.9 nF/50 V 10% 603 C342 and C343 ceramic capacitor 4.7 nF/50 V 5% 603 C344 ceramic capacitor 10 nF/50 V 10% 603 C345 tantalum capacitor 1 µF/16 V 20% − LL4007 diode, equivalent to 1N4007 − − − SMD diode BAS 16 − − SOT23 C304, C305, C307, C308 and C347 D101 to D104 D201 1999 May 10 65 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL COMPONENT CHARACTERISTICS COMPONENT TYPE VALUE TOLERANCE PACKAGE Alpha SMV1204-133 varactor − − SOT23 L301 and L302 SMD inductor 22 µH 5% 1008 L303 and L304 SMD inductor 330 nH 5% 1008 D301 L305 SMD inductor 6.8 nH ±5% 603 L306 and L307 SMD inductor 180 nH ±5% 1008 L308 SMD inductor 27 µH 5% 1008 − not loaded − − R101, R102, R103, R211, R212, R213, R216 and R325 SMD resistor 1Ω 5% 603 R106 SMD resistor 18 kΩ 5% 603 L309 R108 and R322 SMD resistor 12 kΩ 1% 603 R109 and R207 SMD resistor 470 Ω 1% 603 R110, R111, R112 and R204 SMD resistor 1 MΩ 1% 603 R113 and R114 SMD resistor 47 kΩ 1% 603 R115, R116 and R202 SMD resistor 10 MΩ 1% 603 R117 SMD resistor 1 kΩ 1% 603 R118 SMD resistor 270 Ω 1% 603 R119 and R305 SMD resistor 820 Ω 1% 603 R120 SMD resistor 240 Ω 1% 603 R121 SMD resistor 390 Ω 1% 603 R122 SMD resistor 330 Ω 1% 603 R201, R301, R302 and R304 SMD resistor 0Ω − 603 R203 SMD resistor 180 Ω 5% 603 R205, R206, R316, R317, R318, R326 and R327 SMD resistor 10 kΩ 1% 603 − not loaded − − SMD resistor 220 Ω 5% 603 R208, R209, R210, R309 and R324 R222 to R224 R303 and R307 SMD resistor 9.1 Ω 5% 603 R306 SMD resistor 910 Ω 1% 603 R310 and R311 SMD resistor 18 Ω 1% 603 R312 SMD resistor 3.9 kΩ 1% 603 R313 SMD resistor 6.8 kΩ 1% 603 R314 and R315 SMD resistor 2.7 kΩ 1% 603 R319 SMD resistor 20 kΩ 5% 603 R320, R321 and R323 SMD resistor 2.2 kΩ 1% 603 LM317T voltage regulator − − TO220 LP2951CM voltage regulator (National) − − SO8 U101 and U102(1) U103 1999 May 10 66 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL COMPONENT CHARACTERISTICS COMPONENT TYPE VALUE TOLERANCE PACKAGE U201 MAX213EAIRS2312 transceiver (Maxim) − − SSOP28 U202 and U203 SRAM M5M5256BFP-70LL 32k × 8 (Mitsubishi) − − SO28 U205 27C202 EPROM − − PLCC44 U206 ZM33064 power monitor − − − U207 ZM33164 power monitor − − − U302 MAX903ESA comparator (Maxim) − − SO8 BC848 or BC847C NPN transistor − − SOT23 BC858 PNP transistor − − SOT23 X301 TCXO TCO-987Q − − − Y201 30 MHz crystal, 16 pF load capacitance − − − Y202 SMD crystal 32.768 kHz ±30 ppm − MF1012S-1 saw filter − − − V101 and V102 V103 to V106 BPF301 and BPF302 Note 1. With heat sink depending on input voltage. 1999 May 10 67 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL 15 INTERNAL CIRCUITRY PIN PIN VOLTAGE TYPICAL VALUES (V) SYMBOL VCC = 2.7 V EQUIVALENT CIRCUIT WITHOUT ESD PROTECTION CIRCUITS VCC = 5 V 1 VCCA(LNA2) 2.7 5 2 LNA2GND1 0 0 3 LNA2IN 0.815 0.807 3 2 4 BIASGND2 0 0 5 LNA2GND2 0 0 6 LNA2OUT 1.48 3.629 MHB301 6 5 7 CLOCK CMOS level MHB302 CMOS level 7 MHB303 8 REFIN 1.69 3.99 8 MHB304 9 VCCA(VCO) 2.7 5 10 TANK 1.92 1.92 10 11 1999 May 10 68 MHB305 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit PIN PIN VOLTAGE TYPICAL VALUES (V) SYMBOL VCC = 2.7 V UAA1570HL EQUIVALENT CIRCUIT WITHOUT ESD PROTECTION CIRCUITS VCC = 5 V 11 VCOGND 0 0 12 P12GND 0 0 13 MXPGND 0 0 14 MX1IN 0.82 0.81 14 13 15 MX1GND 0 0 16 VCCA(MX1P) 2.7 5 17 IF1P 2.7 5 18 IF1N 2.7 5 17 MHB306 18 MHB307 19 VCCA(MX2) 2.7 5 20 MX2GND 0 0 21 IF2INN 0.983 0.98 22 IF2INP 0.983 0.98 22 21 MHB308 23 STROBE CMOS level CMOS level 23 MHB309 24 IF2P 2.7 5 25 IF2N 2.7 5 24 25 MHB310 26 LIMGND 1999 May 10 0 0 69 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit PIN PIN VOLTAGE TYPICAL VALUES (V) SYMBOL VCC = 2.7 V UAA1570HL EQUIVALENT CIRCUIT WITHOUT ESD PROTECTION CIRCUITS VCC = 5 V 27 BFCN 1.696 3.999 28 LIMINN 1.696 3.999 29 LIMINP 1.696 3.999 30 BFCP 1.696 3.999 31 VCCA(LIM) 2.7 5 32 DATA CMOS level CMOS level 27 28 29 MHB311 32 MHB312 33 VDDD 2.7 (independent of VCC level) 5 (independent of VCC level) 34 SIGN TTL output TTL output 34 MHB313 35 DGND 0 0 36 VCCA(PLL) 2.7 5 37 SCLK 1.34 2.5 37 MHB314 38 PLLGND 0 0 39 P39GND 0 0 1999 May 10 30 70 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit PIN PIN VOLTAGE TYPICAL VALUES (V) SYMBOL VCC = 2.7 V 40 COMP depends on VCO application UAA1570HL EQUIVALENT CIRCUIT WITHOUT ESD PROTECTION CIRCUITS VCC = 5 V depends on VCO application 40 MHB315 41 P41GND 0 0 42 P42GND 0 0 43 VCCA(LNA1) 2.7 5 44 LNA1GND1 0 0 45 LNA1IN 0.815 0.807 45 44 46 BIASGND1 0 0 47 LNA1GND2 0 0 48 LNA1OUT 1.48 3.629 MHB316 48 47 1999 May 10 71 MHB317 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit UAA1570HL 16 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M pin 1 index θ bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 94-12-19 97-08-01 SOT313-2 1999 May 10 EUROPEAN PROJECTION 72 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit If wave soldering is used the following conditions must be observed for optimal results: 17 SOLDERING 17.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 17.2 UAA1570HL – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. 17.3 17.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 1999 May 10 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 73 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit 17.5 UAA1570HL Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE HLQFP, HSQFP, HSOP, SMS not suitable(2) suitable PLCC(3), suitable suitable SO recommended(3)(4) LQFP, QFP, TQFP not SQFP not suitable SSOP, TSSOP, VSO not suitable suitable recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 18 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 19 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 May 10 74 Philips Semiconductors Product specification Global Positioning System (GPS) front-end receiver circuit NOTES 1999 May 10 75 UAA1570HL Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1999 SCA 64 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 285002/00/01/pp76 Date of release: 1999 May 10 Document order number: 9397 750 04463