PHILIPS UDA1334ATS

INTEGRATED CIRCUITS
DATA SHEET
UDA1334ATS
Low power audio DAC with PLL
Product specification
Supersedes data of 2000 Feb 09
File under Integrated Circuits, IC01
2000 Jul 31
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
CONTENTS
9
LIMITING VALUES
10
HANDLING
11
THERMAL CHARACTERISTICS
12
QUALITY SPECIFICATION
13
DC CHARACTERISTICS
14
AC CHARACTERISTICS
1
FEATURES
1.1
1.2
1.3
1.4
1.5
General
Multiple format data interface
DAC digital features
Advanced audio configuration
PLL system clock generation
2
APPLICATIONS
14.1
14.2
Analog
Timing
3
GENERAL DESCRIPTION
15
APPLICATION INFORMATION
4
ORDERING INFORMATION
16
PACKAGE OUTLINE
5
QUICK REFERENCE DATA
17
SOLDERING
6
BLOCK DIAGRAM
17.1
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
8.1.1
8.1.2
8.2
8.3
8.4
8.5
8.6
8.6.1
8.6.2
8.6.3
System clock
Audio mode
Video mode
Interpolation filter
Noise shaper
Filter stream DAC
Power-on reset
Feature settings
Digital interface format select
De-emphasis control
Mute control
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
2000 Jul 31
17.2
17.3
17.4
17.5
2
18
DATA SHEET STATUS
19
DEFINITIONS
20
DISCLAIMERS
Philips Semiconductors
Product specification
Low power audio DAC with PLL
1
UDA1334ATS
FEATURES
1.1
General
• 2.4 to 3.6 V power supply voltage
• On-board PLL to generate the internal system clock:
– Operates as an asynchronous DAC, regenerating the
internal clock from the WS signal (called audio mode)
– Generates audio related system clock (output) based
on 32, 48 or 96 kHz sampling frequency (called video
mode).
2
• Integrated digital filter plus DAC
APPLICATIONS
This audio DAC is excellently suitable for digital audio
portable application, specially in applications in which an
audio related system clock is not present.
• Supports sample frequencies from 16 to 100 kHz in
asynchronous DAC mode
• No analog post filtering required for DAC
• Easy application
3
• SSOP16 package.
1.2
•
The UDA1334ATS is a single chip 2 channel
digital-to-analog converter employing bitstream
conversion techniques, including an on-board PLL.
The extremely low power consumption and low voltage
requirements make the device eminently suitable for use
in low-voltage low-power portable digital audio equipment
which incorporates a playback function.
Multiple format data interface
I2S-bus
and LSB-justified format compatible
• 1fs input data rate.
1.3
DAC digital features
The UDA1334ATS supports the I2S-bus data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 20 and 24 bits.
• Digital de-emphasis for 44.1 kHz sampling frequency
• Mute function.
1.4
The UDA1334ATS has basic features such as
de-emphasis (44.1 kHz sampling frequency, only
supported in audio mode) and mute.
Advanced audio configuration
• High linearity, wide dynamic range and low distortion.
1.5
GENERAL DESCRIPTION
PLL system clock generation
• Integrated low jitter PLL for use in applications in which
there is digital audio data present but the system cannot
provide an audio related system clock. This mode is
called audio mode.
• The PLL can generate 256 × 48 kHz and 384 × 48 kHz
from a 27 MHz input clock. This mode is called video
mode.
4
ORDERING INFORMATION
TYPE
NUMBER
UDA1334ATS
2000 Jul 31
PACKAGE
NAME
DESCRIPTION
VERSION
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
3
Philips Semiconductors
Product specification
Low power audio DAC with PLL
5
UDA1334ATS
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
DAC analog supply voltage
VDDD
digital supply voltage
IDDA
DAC analog supply current
IDDD
digital supply current
Tamb
ambient temperature
2.4
3.0
3.6
V
2.4
3.0
3.6
V
audio mode
−
3.5
−
mA
video mode
−
3.5
−
mA
audio mode
−
2.5
−
mA
video mode
−
4.5
−
mA
−40
−
+85
°C
Digital-to-analog converter (VDDA = VDDD = 3.0 V)
Vo(rms)
output voltage (RMS value)
at 0 dB (FS) digital input;
note 1
−
900
−
mV
(THD+N)/S
total harmonic distortion-plus-noise to fs = 44.1 kHz; at 0 dB
signal ratio
fs = 44.1 kHz; at −60 dB;
A-weighted
−
−90
−
dB
−
−40
−
dB
fs = 96 kHz; at 0 dB
−
−85
−
dB
fs = 96 kHz; at −60 dB;
A-weighted
−
−38
−
dB
fs = 44.1 kHz; code = 0;
A-weighted
−
100
−
dB
fs = 96 kHz; code = 0;
A-weighted
−
98
−
dB
−
100
−
dB
audio mode
−
18
−
mW
video mode
−
24
−
mW
S/N
αCS
signal-to-noise ratio
channel separation
Power dissipation (at fs = 44.1 kHz)
P
power dissipation
Note
1. The output voltage of the DAC scales proportionally to the power supply voltage.
2000 Jul 31
4
Philips Semiconductors
Product specification
Low power audio DAC with PLL
6
UDA1334ATS
BLOCK DIAGRAM
VSSD
VDDD
handbook, full pagewidth
4
BCK
WS
DATAI
1
2
3
5
DIGITAL INTERFACE
MUTE
DEEM/CLKOUT
10
PLL
DE-EMPHASIS
UDA1334ATS
SYSCLK/PLL1
PLL0
6
7
8
11
INTERPOLATION FILTER
9
SFOR1
SFOR0
NOISE SHAPER
VOUTL
DAC
14
DAC
13
15
VDDA
VSSA
Fig.1 Block diagram.
2000 Jul 31
5
16
12
Vref(DAC)
VOUTR
MGL973
Philips Semiconductors
Product specification
Low power audio DAC with PLL
7
UDA1334ATS
PINNING
SYMBOL
PIN
PAD TYPE
DESCRIPTION
BCK
1
5 V tolerant digital input pad
bit clock input
WS
2
5 V tolerant digital input pad
word select input
DATAI
3
5 V tolerant digital input pad
serial data input
VDDD
4
digital supply pad
digital supply voltage
VSSD
5
digital ground pad
digital ground
SYSCLK/PLL1
6
5 V tolerant digital input pad
system clock input in video mode/PLL
mode control 1 input in audio mode
SFOR1
7
5 V tolerant digital input pad
serial format select 1 input
MUTE
8
5 V tolerant digital input pad
mute control input
DEEM/CLKOUT
9
5 V tolerant digital input/output pad
de-emphasis control input in audio
mode/clock output in video mode
PLL0
10
3-level input pad; note 1
PLL mode control 0 input
SFOR0
11
digital input pad; note 1
serial format select 0 input
Vref(DAC)
12
analog pad
DAC reference voltage
VDDA
13
analog supply pad
DAC analog supply voltage
VOUTL
14
analog output pad
DAC output left
VSSA
15
analog ground pad
DAC analog ground
VOUTR
16
analog output pad
DAC output right
Note
1. Because of test issues these pads are not 5 V tolerant and both pads should be at power supply voltage level or at
a maximum of 0.5 V above that level.
handbook, halfpage
BCK 1
16 VOUTR
WS 2
15 VSSA
DATAI 3
VDDD 4
14 VOUTL
UDA1334ATS
VSSD 5
13 VDDA
12 Vref(DAC)
SYSCLK/PLL1 6
11 SFOR0
SFOR1 7
10 PLL0
MUTE 8
9
DEEM/CLKOUT
MGL972
Fig.2 Pin configuration.
2000 Jul 31
6
Philips Semiconductors
Product specification
Low power audio DAC with PLL
8
UDA1334ATS
Table 2
FUNCTIONAL DESCRIPTION
8.1
System clock
PLL0
The UDA1334ATS incorporates a PLL capable of
generating the system clock. The UDA1334ATS can
operate in 2 modes:
• It operates as an asynchronous DAC, which means the
device regenerates the internal clocks using a PLL from
the incoming WS signal. This mode is called audio
mode.
8.2
Interpolation filter characteristics
CONDITION
VALUE (dB)
Pass-band ripple
0fs to 0.45fs
±0.02
>0.55fs
−50
0fs to 0.45fs
>114
Noise shaper
The 5th-order noise shaper operates at 64fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter Stream DAC (FSDAC).
Sampling frequency range in audio mode
SELECTION
VIDEO MODE
In video mode, the master clock is a 27 MHz external clock
(as is available in video environment). A clock-out signal is
generated at pin DEEM/CLKOUT. The output frequency
can be selected using pin PLL0. The output frequency is
either 12.228 MHz (256 × 48 kHz) with pin PLL0 being at
MID level or 18.432 MHz (384 × 48 kHz) with pin PLL0
being HIGH, as given in Table 2.
2000 Jul 31
Interpolation filter
ITEM
8.3
In audio mode, pin SYSCLK/PLL1 is used to set the
sampling frequency range as given in Table 1.
8.1.2
audio mode
Dynamic range
Audio mode is enabled by setting pin PLL0 to LOW.
De-emphasis can be activated via pin DEEM/CLKOUT
according to Table 5.
fs = 50 to 100 kHz
LOW
Stop band
AUDIO MODE
HIGH
18.432 MHz clock; note 2
Table 3
2. For LSB-justified formats it is important to have a WS
signal with a duty factor of 50%.
fs = 16 to 50 kHz
HIGH
The interpolation digital filter interpolates from 1fs to 64fs
by cascading FIR filters (see Table 3).
1. The WS edge MUST fall on the negative edge of the
BCK at all times for proper operation of the digital I/O
data interface
LOW
12.228 MHz clock; note 1
2. The supported sampling frequencies are:
96, 48 and 24 kHz; 72 and 36 kHz or 32 kHz.
Remarks:
SYSCLK/PLL1
MID
1. The supported sampling frequencies are:
96, 48 and 24 kHz or 64, 32 and 16 kHz.
In video mode, the digital audio input is slave, which
means that the system must generate the BCK and
WS signals from the output clock available at pin CLKOUT
of the UDA1334ATS. The digital audio signals should be
frequency locked to the CLKOUT signal.
Table 1
SELECTION
Notes
• It generates the internal clocks from a 27 MHz clock
input, based on 32, 48 and 96 kHz sampling
frequencies. This mode is called video mode.
8.1.1
Clock output selection in video mode
7
Philips Semiconductors
Product specification
Low power audio DAC with PLL
8.4
UDA1334ATS
Filter stream DAC
8.5
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. No post filter is needed due to
the inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
Power-on reset
The UDA1334ATS has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin Vref(DAC) and
ground. The reset time should be at least 1 µs for
Vref(DAC) < 1.25 V. When VDDA is switched off, the device
will be reset again for Vref(DAC) < 0.75 V.
During the reset time the system clock should be running.
The output voltage of the FSDAC scales proportionally to
the power supply voltage.
3.0
VDDD
handbook, halfpage
(V)
1.5
0
handbook, halfpage
3.0 V
t
VDDA 13
3.0
VDDA
50 kΩ
Vref(DAC)
C1 >
10 µF
(V)
RESET
CIRCUIT
12
1.5
50 kΩ
0
UDA1334ATS
t
MGT015
3.0
Vref(DAC)
(V)
1.5
1.25
0.75
0
>1 µs
t
MGL984
Fig.3 Power-on reset circuit.
2000 Jul 31
Fig.4 Power-on reset timing.
8
Philips Semiconductors
Product specification
Low power audio DAC with PLL
8.6
UDA1334ATS
Feature settings
8.6.1
8.6.2
DE-EMPHASIS CONTROL
This function is only available in audio mode. In that case,
pin DEEM/CLKOUT can be used to activate the digital
de-emphasis for 44.1 kHz as given in Table 5.
DIGITAL INTERFACE FORMAT SELECT
The digital audio interface formats (see Fig.5) can be
selected via pins SFOR1 and SFOR0 as shown in
Table 4.
Table 5
For the digital audio interface holds that the
BCK frequency can be maximum 64 times WS frequency.
DEEM/CLKOUT
The WS signal must change at the negative edge of the
BCK signal for all digital audio formats.
Table 4
De-emphasis control (audio mode)
8.6.3
Data format selection
FUNCTION
LOW
de-emphasis off
HIGH
de-emphasis on
MUTE CONTROL
The output signal can be soft muted by setting pin MUTE
to HIGH as given in Table 6.
SFOR1
SFOR0
LOW
LOW
I2S-bus input
LOW
HIGH
LSB-justified 16 bits input
HIGH
LOW
LSB-justified 20 bits input
MUTE
HIGH
HIGH
LSB-justified 24 bits input
LOW
mute off
HIGH
mute on
2000 Jul 31
INPUT FORMAT
Table 6
9
Mute control
FUNCTION
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2
>=8
3
2
3
MSB
B2
1
>=8
DATA
MSB
B2
MSB
I2S-BUS FORMAT
WS
LEFT
RIGHT
16
15
1
16
B15 LSB
MSB
2
15
2
1
BCK
DATA
MSB
B2
B2
B15 LSB
Philips Semiconductors
1
BCK
Low power audio DAC with PLL
handbook, full pagewidth
2000 Jul 31
RIGHT
LEFT
WS
LSB-JUSTIFIED FORMAT 16 BITS
10
WS
LEFT
20
RIGHT
19
18
17
16
15
1
20
B19 LSB
MSB
2
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B2
B3
B4
B5
B6
B19 LSB
LSB-JUSTIFIED FORMAT 20 BITS
WS
LEFT
24
23
22
21
20
RIGHT
19
18
17
16
15
2
1
24
B23 LSB
MSB
23
22
21
20
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MGS752
Product specification
Fig.5 Digital audio formats.
UDA1334ATS
LSB-JUSTIFIED FORMAT 24 BITS
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−
4.0
V
maximum crystal
temperature
−
150
°C
Tstg
storage temperature
−65
+125
°C
Tamb
ambient temperature
−40
+85
°C
Ves
electrostatic handling voltage human body model; note 2
−2000
+2000
V
−250
+250
V
Isc(DAC)
short-circuit current of DAC
output short-circuited to VSSA
−
450
mA
output short-circuited to VDDA
−
300
mA
VDD
supply voltage
Txtal(max)
note 1
machine model; note 2
note 3
Notes
1. All supply connections must be made to the same power supply.
2. ESD behaviour is tested according to JEDEC II standard.
3. Short-circuit test at Tamb = 0 °C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
11 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
in free air
VALUE
UNIT
145
K/W
12 QUALITY SPECIFICATION
In accordance with “SNW-FQ-611-E”.
13 DC CHARACTERISTICS
VDDD = VDDA = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD); unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
DAC analog supply voltage
note 1
2.4
3.0
3.6
V
VDDD
digital supply voltage
note 1
2.4
3.0
3.6
V
IDDA
DAC analog supply current
IDDD
2000 Jul 31
digital supply current
audio mode
−
3.5
−
mA
video mode
−
3.5
−
mA
audio mode
−
2.5
−
mA
video mode
−
4.5
−
mA
11
Philips Semiconductors
Product specification
Low power audio DAC with PLL
SYMBOL
PARAMETER
UDA1334ATS
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital input pins: TTL compatible
VIH
HIGH-level input voltage
2.0
−
5.0
V
VIL
LOW-level input voltage
−0.5
−
+0.8
V
ILI
input leakage current
−
−
1
µA
Ci
input capacitance
−
−
10
pF
3-level input: pin PLL0
VIH
HIGH-level input voltage
0.9VDDD
−
VDDD + 0.5
V
VIM
MID-level input voltage
0.4VDDD
−
0.6VDDD
V
VIL
LOW-level input voltage
−0.5
−
+0.5
V
Digital output pins
VOH
HIGH-level output voltage
IOH = −2 mA
0.85VDDD −
−
V
VOL
LOW-level output voltage
IOL = 2 mA
−
−
0.4
V
Vref(DAC)
reference voltage
with respect to VSSA
0.45VDD
0.5VDD 0.55VDD
Ro(ref)
output resistance on
pin Vref(DAC)
−
25
−
kΩ
Io(max)
maximum output current
−
1.6
−
mA
RL
load resistance
3
−
−
kΩ
CL
load capacitance
−
−
50
pF
DAC
(THD + N)/S < 0.1%;
RL = 5 kΩ
note 2
V
Notes
1. All supply connections must be made to the same external power supply unit.
2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
14 AC CHARACTERISTICS
14.1 Analog
VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
DAC
Vo(rms)
output voltage (RMS value)
∆Vo
(THD + N)/S
at 0 dB (FS) digital input; note 1
900
mV
unbalance between channels
0.1
dB
total harmonic
fs = 44.1 kHz; at 0 dB
distortion-plus-noise to signal fs = 44.1 kHz; at −60 dB; A-weighted
ratio
fs = 96 kHz; at 0 dB
−90
dB
−40
dB
−85
dB
−38
dB
fs = 96 kHz; at −60 dB; A-weighted
2000 Jul 31
12
Philips Semiconductors
Product specification
Low power audio DAC with PLL
SYMBOL
UDA1334ATS
PARAMETER
S/N
signal-to-noise ratio
αCS
channel separation
PSRR
power supply rejection ratio
CONDITIONS
TYP.
UNIT
fs = 44.1 kHz; code = 0; A-weighted
100
dB
fs = 96 kHz; code = 0; A-weighted
98
dB
100
dB
60
dB
fripple = 1 kHz; Vripple = 30 mV (p-p)
Note
1. The output voltage of the DAC scales proportionally to the analog power supply voltage.
14.2 Timing
VDDD = VDDA = 2.4 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified; note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Output clock timing in video mode (see Fig.6)
Tsys
tCWL
tCWH
output clock cycle
output clock LOW time
output clock HIGH time
fo = 12.228 MHz
−
81.38
−
ns
fo = 18.432 MHz
−
54.25
−
ns
fo = 12.228 MHz
0.3Tsys
−
0.7Tsys
ns
fo = 18.432 MHz
0.4Tsys
−
0.6Tsys
ns
fo = 12.228 MHz
0.3Tsys
−
0.7Tsys
ns
fo = 18.432 MHz
0.4Tsys
−
0.6Tsys
ns
Serial input data timing (see Fig.7)
fBCK
bit clock frequency
−
−
64fs
Hz
tBCKH
bit clock HIGH time
50
−
−
ns
tBCKL
bit clock LOW time
50
−
−
ns
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
tsu(DATAI)
set-up time data input
20
−
−
ns
th(DATAI)
hold time data input
0
−
−
ns
tsu(WS)
set-up time word select
20
−
−
ns
th(WS)
hold time word select
10
−
−
ns
Note
1. The typical value of the timing is specified for a sampling frequency of 44.1 kHz.
2000 Jul 31
13
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
t CWH
handbook, full pagewidth
MGR984
t CWL
Tsys
Fig.6 Output clock timing.
handbook, full pagewidth
WS
th(WS)
tBCKH
tr
tsu(WS)
tf
BCK
tsu(DATAI)
tBCKL
Tcy(BCK)
th(DATAI)
DATAI
MGL880
Fig.7 Serial interface timing.
2000 Jul 31
14
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
15 APPLICATION INFORMATION
analog
supply voltage
handbook, full pagewidth
R7
1Ω
C9
SYSCLK/PLL1
digital
supply voltage
47 µF
(16 V)
47 µF
(16 V)
C10
C6
100 nF
(63 V)
VSSA
100 nF
(63 V)
15
VDDA
13
R6
1Ω
C5
VSSD
5
VDDD
4
6
14
BCK
WS
DATAI
SFOR1
SFOR0
MUTE
DEEM/CLKOUT
PLL0
VOUTL C3
47 µF
(16 V)
1
2
R3
R1
220 kΩ
C1
3
7
11
UDA1334ATS
16
8
9
VOUTR C4
47 µF
(16 V)
12
left
output
100 Ω
10 nF
(63 V)
R4
right
output
100 Ω
R2
220 kΩ
C2
10 nF
(63 V)
Vref(DAC)
C8
100 nF
(63 V)
10
C7
47 µF
(16 V)
MGL971
In audio mode, the system does not need to supply a system clock.
Fig.8 Audio mode application diagram.
2000 Jul 31
15
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
analog
supply voltage
R7
1Ω
C9
27 MHz
clock
R5
SYSCLK/PLL1
47 Ω
digital
supply voltage
47 µF
(16 V)
47 µF
(16 V)
C10
C6
100 nF
(63 V)
VSSA
100 nF
(63 V)
15
R6
1Ω
C5
VDDA
VSSD
13
5
VDDD
4
6
14
BCK
WS
DATAI
I2S-bus
(master)
SFOR1
SFOR0
VOUTL C3
47 µF
(16 V)
1
2
MUTE
audio clock
PLL0
R1
220 kΩ
C1
3
7
11
UDA1334ATS
16
VOUTR C4
47 µF
(16 V)
MPEG
DECODER
DEEM/CLKOUT
R3
8
9
12
left
output
100 Ω
10 nF
(63 V)
R4
right
output
100 Ω
R2
220 kΩ
C2
10 nF
(63 V)
Vref(DAC)
C8
100 nF
(63 V)
10
C7
47 µF
(16 V)
handbook, full pagewidth
MGL974
In video mode, a clock output signal is generated by the UDA1334ATS which is master for the audio signals in the system; the digital audio interface is
slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock.
Fig.9 Video mode application diagram.
2000 Jul 31
16
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
16 PACKAGE OUTLINE
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
D
SOT369-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.5
0.15
0.00
1.4
1.2
0.25
0.32
0.20
0.25
0.13
5.30
5.10
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.45
0.65
0.45
0.2
0.13
0.1
0.48
0.18
10
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT369-1
2000 Jul 31
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
99-12-27
MO-152
17
o
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
If wave soldering is used the following conditions must be
observed for optimal results:
17 SOLDERING
17.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
17.2
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
17.3
17.4
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2000 Jul 31
Manual soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
18
Philips Semiconductors
Product specification
Low power audio DAC with PLL
17.5
UDA1334ATS
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Jul 31
19
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
18 DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
19 DEFINITIONS
20 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 Jul 31
20
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
NOTES
2000 Jul 31
21
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
NOTES
2000 Jul 31
22
Philips Semiconductors
Product specification
Low power audio DAC with PLL
UDA1334ATS
NOTES
2000 Jul 31
23
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SCA 70
© Philips Electronics N.V. 2000
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Printed in The Netherlands
753503/25/02/pp24
Date of release: 2000
Jul 31
Document order number:
9397 750 07238