AD ADT7476A

dBCool™ Remote Thermal
Controller and Voltage Monitor
ADT7476A
FEATURES
GENERAL DESCRIPTION
Monitors up to five voltages
Improved TACH and PWM performance
Controls and monitors up to four fans
High and low frequency fan drive signal
One on-chip and two remote temperature sensors
Extended temperature measurement range up to 191°C
Automatic fan speed control mode controls system
cooling based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel® Pentium® 4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
5 V support on all TACH and PWM channels
Meets SMBus 2.0 electrical specifications
The ADT7476A dBCOOL controller is a thermal monitor
and multiple PWM fan controller for noise-sensitive or powersensitive applications requiring active system cooling. The
ADT7476A can drive a fan using either a low or high frequency
drive signal and can monitor the temperature of up to two
remote sensor diodes plus its own internal temperature. The
part also measures and controls the speed of up to four fans, so
the fans operate at the lowest possible speed for minimum
acoustic noise.
The automatic fan speed control loop optimizes fan speed
for a given temperature. The effectiveness of the system’s
thermal solution can be monitored using the THERM input.
The ADT7476A also provides critical thermal protection to
the system using the bidirectional THERM pin as an output
to prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
ADDR
ADDREN SELECT SCL SDA SMBALERT
VID5/GPIO5
VID4/GPIO4
VID3/GPIO3
VID2/GPIO2
VID1/GPIO1
VID0/GPIO0
GPIO6
PWM1
PWM2
PWM3
ADT7476A
SMBus
ADDRESS
SELECTION
VID/GPIO
REGISTER
SERIAL BUS
INTERFACE
ADDRESS
POINTER
REGISTER
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
TACH1
TACH2
TACH3
TACH4
AUTOMATIC
FAN SPEED
CONTROL
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
FAN
SPEED
COUNTER
PERFORMANCE
MONITORING
THERMAL
PROTECTION
THERM
VCC
VCC TO ADT7476A
ACOUSTIC
ENHANCEMENT
CONTROL
D1+
INTERRUPT
STATUS
REGISTERS
D1–
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
D2+
D2–
+5VIN
+12VIN
+2.5VIN
10-BIT
ADC
BAND GAP
REFERENCE
VCCP
VALUE AND
LIMIT
REGISTERS
05742-001
BAND GAP
TEMP. SENSOR
LIMIT
COMPARATORS
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADT7476A
TABLE OF CONTENTS
Features .............................................................................................. 1
Factors Affecting Diode Accuracy........................................... 20
General Description ......................................................................... 1
Additional ADC Functions for Temperature Measurement 21
Functional Block Diagram .............................................................. 1
Limits, Status Registers, and Interrupts....................................... 23
Revision History ............................................................................... 2
Limit Values ................................................................................ 23
Specifications..................................................................................... 3
Status Registers ........................................................................... 24
Absolute Maximum Ratings............................................................ 5
THERM Timer ........................................................................... 26
Thermal Characteristics .............................................................. 5
Fan Drive Using PWM Control ............................................... 29
ESD Caution.................................................................................. 5
Laying Out 3-Wire Fans ............................................................ 31
Pin Configuration and Function Descriptions............................. 6
Programming TRANGE.................................................................. 34
Typical Performance Characteristics ............................................. 8
Programming the Automatic Fan Speed Control Loop ............ 35
Product Description....................................................................... 10
Manual Fan Control Overview................................................. 35
Feature Comparisons Between ADT7476A and ADT7468.. 10
THERM Operation in Manual Mode...................................... 35
Recommended Implementation............................................... 10
Automatic Fan Control Overview............................................ 35
Serial Bus Interface..................................................................... 11
Step 1—Hardware Configuration ............................................ 37
Write Operations ........................................................................ 14
Step 2—Configuring the Mux .................................................. 40
Read Operations ......................................................................... 14
Step 3—TMIN Settings for Thermal Calibration Channels .... 42
SMBus Timeout .......................................................................... 15
Step 4—PWMMIN for Each PWM (Fan) Output .................... 43
Virus Protection.......................................................................... 15
Step 5—PWMMAX for PWM (Fan) Outputs............................ 43
Voltage Measurement Input...................................................... 15
Step 6—TRANGE for Temperature Channels.............................. 44
Analog-to-Digital Converter .................................................... 15
Step 7—TTHERM for Temperature Channels ............................. 46
Input Circuitry............................................................................ 15
Voltage Measurement Registers................................................ 16
Voltage Limit Registers .............................................................. 16
Extended Resolution Registers ................................................. 16
Additional ADC Functions for Voltage Measurements ........ 16
VID Code Monitoring ............................................................... 18
VID Code Input Threshold Voltage......................................... 18
VID Code Change Detect Function ........................................ 18
Programming the GPIOs........................................................... 18
Step 8—THYST for Temperature Channels................................ 48
Fan Presence Detect................................................................... 49
Fan Sync....................................................................................... 50
Standby Mode ............................................................................. 50
XNOR Tree Test Mode .............................................................. 50
Power-On Default ...................................................................... 50
Register Tables ................................................................................ 51
Outline Dimensions ....................................................................... 71
Ordering Guide .......................................................................... 71
Temperature Measurement Method ........................................ 18
REVISION HISTORY
1/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 72
ADT7476A
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. 1
Table 1.
Parameter
POWER SUPPLY
Supply Voltage
Supply Current, ICC
TEMP-TO-DIGITAL CONVERTER
Local Sensor Accuracy
Min
Typ
Max
Unit
Test Conditions/Comments
3.0
3.3
1.5
3.6
3
V
mA
Interface inactive, ADC active
±0.5
±1.5
±2.5
°C
°C
°C
°C
°C
°C
μA
μΑ
0°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 125°C
%
%
LSB
%/V
ms
ms
ms
ms
ms
kΩ
kΩ
For 12 V channel
For all other channels
8 bits
Averaging enabled
Averaging enabled
Averaging enabled
Averaging enabled
Averaging disabled
For VCCP channel
For all other channels
%
%
0°C ≤ TA ≤ 70°C
−40°C ≤ TA ≤ +120°C
RPM
RPM
RPM
RPM
Fan count = 0xBFFF
Fan count = 0x3FFF
Fan count = 0x0438
Fan count = 0x021C
0.1
8.0
0.4
20
mA
V
μA
IOUT = −8.0 mA
VOUT = VCC
0.1
0.4
1.0
V
μA
IOUT = −4.0 mA
VOUT = VCC
0.4
V
V
mV
Resolution
Remote Diode Sensor Accuracy
0.25
±0.5
0.25
180
11
ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error (TUE)
±1.5
±2.5
Resolution
Remote Sensor Source Current
Differential Nonlinearity (DNL)
Power Supply Sensitivity
Conversion Time (Voltage Input)
Conversion Time (Local Temperature)
Conversion Time (Remote Temperature)
Total Monitoring Cycle Time
Total Monitoring Cycle Time
Input Resistance
70
70
±0.1
11
12
38
145
19
120
114
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
±6
±10
65,535
Full-Scale Count
Nominal Input RPM
OPEN-DRAIN DIGITAL OUTPUTS, PWM1 TO PWM3, XTO
Current Sink, IOL
Output Low Voltage, VOL
High Level Output Current, IOH
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
SMBus DIGITAL INPUTS (SCL, SDA) 2
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
±2
±1.5
±1
109
329
5,000
10,000
2.0
500
Rev. 0 | Page 3 of 72
0°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 125°C
High level
Low level
ADT7476A
Parameter
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
Min
Typ
Max
Unit
Test Conditions/Comments
5.5
V
V
Maximum input voltage
2.0
Input Low Voltage, VIL
0.8
V
V
V p-p
−0.3
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Detect Clock Low Timeout, tTIMEOUT
0.5
0.75 × VCC
0.4
±1
±1
5
Minimum input voltage
V
V
μA
μA
pF
VIN = VCC
VIN = 0
See Figure 2
10
400
50
4.7
4.7
4.0
kHz
ns
μs
μs
μs
ns
μs
ns
ms
50
1,000
300
250
15
35
Can be optionally disabled
1
All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and probably represent a parametric norm. Logic inputs
accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge,
and VIH = 2.0 V for a rising edge.
2
SMBus timing specifications are guaranteed by design and are not production tested.
tLOW
tR
tF
tHD; STA
SCL
tHIGH
tHD; DAT
tSU; STA
tSU; STO
tSU; DAT
SDA
tBUF
P
S
S
Figure 2. Serial Bus Timing Diagram
Rev. 0 | Page 4 of 72
P
05742-002
tHD; STA
ADT7476A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Positive Supply Voltage (VCC)
Maximum Voltage on +12 VIN Pin
Maximum Voltage on +5 VIN Pin
Maximum Voltage on All Open-Drain Outputs
Max Voltage on TACH/PWM Pins
Voltage on Remaining Input or Output Pins
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Lead Temperature, Soldering
IR Reflow Peak Temperature
Pb-Free Peak Temperature
Lead Temperature (Soldering, 10 sec)
ESD Rating
Rating
3.6 V
16 V
6.25 V
3.6 V
+5.5 V
−0.3 V to +4.2 V
±5 mA
±20 mA
150°C
−65°C to +150°C
220°C
260°C
300°C
1500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
24-lead QSOP
θJA
122
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 72
θJC
31.25
Unit
°C/W
ADT7476A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SDA
1
24
SCL
2
23
VCCP
GND
3
22
+2.5VIN/THERM
VCC
4
21
+12VIN/VID5
VID0/GPIO0
5
20
+5VIN
VID1/GPIO1
6
19
VID4/GPIO4
VID2/GPIO2
7
VID3/GPIO3
8
TACH3
ADT7476A
TOP VIEW
(Not to Scale)
18
D1+
17
D1–
D2+
9
16
PWM2/SMBALERT 10
15
D2–
TACH1 11
14
TACH4/THERM/SMBALERT/GPIO6/ADDR SELECT
TACH2 12
13
PWM3/ADDREN
05742-003
PWM1/XTO
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
SDA
SCL
GND
VCC
5
VID0/
GPIO0
VID1/
GPIO1
VID2/
GPIO2
VID3/
GPIO3
TACH3
PWM2/
6
7
8
9
10
SMBALERT
11
12
13
TACH1
TACH2
PWM3
ADDREN
14
TACH4/
THERM/
SMBALERT/
15
16
17
18
GPIO6/
ADDR SELECT
D2–
D2+
D1–
D1+
Description
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
Ground Pin.
Power Supply. Powered by 3.3 V standby, if monitoring in low power states is required. VCC is also monitored
through this pin.
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
General-Purpose Open Drain Digital I/O.
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
General-Purpose Open Drain Digital I/O.
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
General-Purpose Open Drain Digital I/O.
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
General-Purpose Open Drain Digital I/O.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control Fan 2
speed. Can be configured as a high or low frequency drive.
Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-oflimit conditions.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
Digital I/O (Open Drain). Pulse width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 kΩ
typical pull-up. Can be configured as a high or low frequency drive.
If pulled low on power-up, the ADT7476A enters address select mode, and the state of Pin 14 (ADDR SELECT)
determines the ADT7476A’s slave address.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
Alternatively, the pin can be reconfigured as a bidirectional THERM pin. Times and monitors assertions on the
THERM input. For example, it can be connected to the PROCHOT output of Intel’s Pentium 4 processor or to the
output of a trip point temperature sensor. Can be used as an output to signal overtemperature conditions.
Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-oflimit conditions.
General-Purpose Open Drain Digital I/O.
If in address select mode, the logic state of this pin defines the SMBus device address.
Cathode Connection to Second Thermal Diode.
Anode Connection to Second Thermal Diode.
Cathode Connection to First Thermal Diode.
Anode Connection to First Thermal Diode.
Rev. 0 | Page 6 of 72
ADT7476A
Pin No.
19
20
21
22
23
24
Mnemonic
VID4/
GPIO4
+5VIN
+12VIN/
VID5
+2.5VIN/
THERM
VCCP
PWM1/
XTO
Description
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
General-Purpose Open Drain Digital I/O.
Analog Input. Monitors 5 V power supply.
Analog Input. Monitors 12 V power supply.
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
Analog Input. Monitors 2.5 V supply, typically a chipset voltage.
Alternatively, this pin can be reconfigured as a bidirectional/omnidirectional THERM pin. Can be used to time
and monitor assertions on the THERM input. For example, can be connected to the PROCHOT output of Intel’s
Pentium 4 processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
Analog Input. Monitors processor core voltage (0 V to 3 V).
Digital Output (Open Drain). Pulse width modulated output to control the speed of Fan 1. Requires 10 kΩ
typical pull-up.
Also functions as the output from the XOR tree in XOR test mode.
Rev. 0 | Page 7 of 72
ADT7476A
TYPICAL PERFORMANCE CHARACTERISTICS
70
0
60
TEMPERATURE ERROR (°C)
–20
–30
–40
–50
0
2
4
6
8
10
12
14
16
18
20
40
30
100mV
20
60mV
40mV
10
0
05742-004
–60
50
05742-008
TEMPERATURE ERROR (°C)
–10
–10
0
22
100M
200M
300M
400M
500M
600M
NOISE FREQUENCY (Hz)
CAPACITANCE (nF)
Figure 4. Temperature Error vs. Capacitance Between D+ and D−
Figure 7. Remote Temperature Error vs. Differential-Mode Noise Frequency
1.20
30
1.18
20
1.14
10
1.12
D+ TO GND
0
IDD (mA)
D+ TO VCC
–10
1.10
1.08
1.06
–20
1.04
1.02
05742-006
–30
–40
0
20
40
80
60
05742-009
TEMPERATURE ERROR (°C)
1.16
1.00
0.98
3.0
100
3.1
3.2
LEAKAGE RESISTANCE (MΩ)
3.4
3.5
3.6
500M
600M
Figure 8. Normal IDD vs. Power Supply
Figure 5. Remote Temperature Error vs. PCB Resistance
30
15
25
10
100mV
TEMPERATURE ERROR (°C)
20
15
60mV
10
5
5
100mV
0
250mV
–5
–10
05742-007
0
40mV
–5
0
100M
200M
300M
400M
500M
05742-010
TEMPERATURE ERROR (°C)
3.3
VDD (V)
–15
0
600M
100M
200M
300M
400M
FREQUENCY (Hz)
NOISE FREQUENCY (Hz)
Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency
Figure 9. Internal Temperature Error vs. Power Supply Noise Frequency
Rev. 0 | Page 8 of 72
ADT7476A
6
3.0
2.5
4
TEMPERATURE ERROR (°C)
2
0
–2
100mV
–4
–6
–8
1.5
1.0
0.5
0
–0.5
–12
0
100M
200M
300M
400M
500M
–1.5
–2.0
600M
–40
Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency
3.0
2.5
2.0
1.5
1.0
0.5
0
05742-012
–0.5
–1.0
–1.5
–20
0
20
40
60
–20
0
20
40
60
85
105
125
OIL BATH TEMPERATURE (°C)
FREQUENCY (Hz)
–40
05742-013
–10
TEMPERATURE ERROR (°C)
2.0
–1.0
05742-011
TEMPERATURE ERROR (°C)
250mV
85
105
125
OIL BATH TEMPERATURE (°C)
Figure 11. Internal Temperature Error vs. ADT7476A Temperature
Rev. 0 | Page 9 of 72
Figure 12. Remote Temperature Error vs. ADT7476A Temperature
ADT7476A
PRODUCT DESCRIPTION
The ADT7476A is a complete thermal monitor and multiple fan
controller for any system requiring thermal monitoring and
cooling. The device communicates with the system via a serial
system management bus. The serial bus controller has a serial
data line for reading and writing addresses and data (Pin 1),
and an input line for the serial clock (Pin 2). All control and
programming functions for the ADT7476A are performed over
the serial bus. In addition, a pin can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
FEATURE COMPARISONS BETWEEN ADT7476A
AND ADT7468
•
Dynamic TMIN , dynamic operating point, and associated
registers are no longer available in the ADT7476A. The
following related registers are gone:
o
Calibration Control 1 (0x36)
o
Calibration Control 2 (0x37)
o
Operating Point (0x33, 0x34, and 0x35)
•
The ADT7476A offers increased temperature accuracy on
all temperature channels.
•
The ADT7476A defaults to twos complement temperature
measurement mode.
•
Some pins have swapped/added functions.
•
The power-up routine for the ADT7476A is simplified.
•
The ADT7476A has a higher maximum input voltage
TACH/PWM spec, supporting a wider range of fans.
•
VCORE_LOW_ENABLE has been reallocated to Bit 7 of
Configuration Register 1 (0x40).
RECOMMENDED IMPLEMENTATION
Configuring the ADT7476A as shown in Figure 13 allows the
system designer to use the following features:
•
Two PWM outputs for fan control of up to three fans (the
front and rear chassis fans are connected in parallel).
Previously (in the ADT7468), TRANGE defined the slope of
the automatic fan control algorithm. TRANGE now defines a
true temperature range (in the ADT7476A).
•
Three TACH fan speed measurement inputs.
•
VCC measured internally through Pin 4.
•
Acoustic filtering is now assigned to temperature zones,
not to fans. Available smoothing times have been increased
for better acoustic performance.
•
CPU temperature measured using Remote 1 temperature
channel.
•
•
Temperature measurements are now made with two
switching currents instead of three. SRC is not available in
the ADT7476A.
Remote temperature zone measured through Remote 2
temperature channel.
•
Local temperature zone measured through the internal
temperature channel.
•
High frequency PWM can now be enabled/disabled on
each PWM output individually.
•
•
THERM can now be enabled/disabled on each temperature
channel individually.
Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as an
overtemperature THERM output. It can alternatively be
programmed as an SMBALERT system interrupt output.
•
The ADT7476A does not support full shutdown mode.
•
Rev. 0 | Page 10 of 72
ADT7476A
ADT7476A
FRONT
CHASSIS
FAN
PWM1
TACH2
TACH1
PWM3
REAR
CHASSIS
FAN
TACH3
5(VRM9)/6(VRM10)
VID[0:4]/VID[0:5]
D2+
D2–
THERM
PROCHOT
D1+
AMBIENT
TEMPERATURE
D1–
VCC
SDA
+5VIN
SCL
+12VIN/VID5 SMBALERT
05742-014
GND
Figure 13. ADT7476A Configuration
Table 5. Hardwiring the ADT7476A SMBus Device Address
Pin 14
Low (10 kΩ to GND)
High (10 kΩ pull-up)
Don’t Care
Address
0101100 (0x2C)
0101101 (0x2D)
0101110 (0x2E)
PWM3/ADDREN
14
10kΩ
13
ADDRESS = 0x2E
05742-015
ADDR SELECT
Figure 14. Default SMBus Address = 0x2E
ADT7476A
ADDR SELECT
PWM3/ADDREN
14 10kΩ
13
ADDRESS = 0x2C
05742-016
The device address is sampled on power-up and latched on
the first valid SMBus transaction, more precisely on the low-tohigh transition at the beginning of the eighth SCL pulse, when
the serial bus address byte matches the selected slave address.
The selected slave address is chosen using the ADDREN pin/
ADDR SELECT pin. Any attempted changes in the address
have no effect after this.
Pin 13 State
0
0
1
VCC
ADT7476A
Control of the ADT7476A is carried out using the serial system
management bus (SMBus). The ADT7476A is connected to this
bus as a slave device, under the control of a master controller.
The ADT7476A has a 7-bit serial bus address. When the device
is powered up with Pin 13 (PWM3/ADDREN) high, the
ADT7476A has a default SMBus address of 0101110 or 0x2E.
The read/write bit must be added to get the 8-bit address.
If more than one ADT7476A is to be used in a system, each
ADT7476A is placed in ADDR SELECT mode by strapping
Pin 13 low on power-up. The logic state of Pin 14 then
determines the device’s SMBus address. The logic of these
pins is sampled on power-up.
Figure 15. SMBus Address = 0x2C (Pin 14 = 0)
VCC
ADT7476A
10kΩ
ADDR SELECT
PWM3/ADDREN
14
13
ADDRESS = 0x2D
05742-017
SERIAL BUS INTERFACE
Figure 16. SMBus Address = 0x2D (Pin 14 = 1)
Rev. 0 | Page 11 of 72
ADT7476A
3.
VCC
ADT7476A
10kΩ
ADDR SELECT
PWM3/ADDREN
14
13
NC
DO NOT LEAVE ADDREN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 13
(PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 13
FLOATING COULD CAUSE THE ADT7476A TO POWER UP WITH AN
UNEXPECTED ADDRESS.
Any number of bytes of data can be transferred over the serial
bus in one operation. However, it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation. In the ADT7476A,
write operations contain either one or two bytes, and read
operations contain one byte.
05742-018
NOTE THAT IF THE ADT7476A IS PLACED INTO ADDR SELECT
MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATIVE
FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT
CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO
HANDLE THESE DUAL FUNCTIONS.
Figure 17. Unpredictable SMBus Address if Pin 13 is Unconnected
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices
sharing the same serial bus, for example, if more than one
ADT7476A is used in a system.
The serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition, which is defined as a high-to-low transition on
the serial data line SDA while the serial clock line SCL
remains high. This indicates that an address/data stream
follows. All slave peripherals connected to the serial bus
respond to the start condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first), plus a R/W
bit, which determine the direction of the data transfer, that
is, whether data is written to or read from the slave device.
The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/W bit is a 0, the master writes to
the slave device. If the R/W bit is a 1, the master reads from
the slave device.
2.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device overrides
the acknowledge bit by pulling the data line high during the
low period before the ninth clock pulse. This is known as no
acknowledge. The master then takes the data line low during
the low period before the 10th clock pulse, and then high
during the 10th clock pulse to assert a stop condition.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and
remain stable during the high period. A low-to-high
transition, when the clock is high, can be interpreted
as a stop signal. The number of data bytes transmitted
over the serial bus in a single read or write operation is
limited only by what the master and slave devices
can handle.
To write data to one of the device data registers or read data
from it, the address pointer register must be set so the correct
data register is addressed. Then, data can be written into that
register or read from it. The first byte of a write operation
always contains an address stored in the address pointer
register. If data is to be written to the device, then the write
operation contains a second data byte that is written to the
register selected by the address pointer register.
This write operation is illustrated in Figure 18. The device
address is sent over the bus, and then R/W is set to 0. This is
followed by two data bytes. The first data byte is the address of
the internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
1.
If the ADT7476A’s address pointer register value is
unknown, or not the desired value, then it must first be set
to the correct value before data can be read from the
desired data register. This is done by performing a write to
the ADT7476A as before, but only the data byte containing
the register address is sent, because no data is written to
the register (see Figure 19).
A read operation is then performed consisting of the serial
bus address; R/W bit set to 1, followed by the data byte
read from the data register (see Figure 20.)
2.
Rev. 0 | Page 12 of 72
If the address pointer register is already known to be at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register (see Figure 20).
ADT7476A
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is not
possible to write data to a register without writing to the
address pointer register, because the first data byte of a write is
always written to the address pointer register.
In addition to supporting the send byte and receive byte
protocols, the ADT7476A also supports the read byte protocol.
See Intel’s System Management Bus Specifications Rev. 2 for more
information.
If several read or write operations must be performed in
succession, the master can send a repeat start condition instead
of a stop condition to begin a new operation.
1
9
9
1
SCL
SDA
0
1
0
1
1
A0
A1
D6
D7
R/W
START BY
MASTER
ACK. BY
ADT7476A
FRAME 1
SERIAL BUS ADDRESS BYTE
D4
D5
D2
D3
D1
D0
ACK. BY
ADT7476A
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
D4
D5
D6
D2
D3
D1
D0
ACK. BY STOP BY
ADT7476A MASTER
FRAME 3
DATA BYTE
05742-019
D7
SDA (CONTINUED)
Figure 18. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
9
9
1
SCL
0
1
0
1
1
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7476A
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7476A
FRAME 2
ADDRESS POINTER REGISTER BYTE
STOP BY
MASTER
05742-020
SDA
Figure 19. Writing to the Address Pointer Register Only
1
9
9
1
SCL
START BY
MASTER
0
1
0
1
1
A1
FRAME 1
SERIAL BUS ADDRESS BYTE
A0
R/W
D7
D6
ACK. BY
ADT7476A
D5
D4
D3
D1
FRAME 2
DATA BYTE FROM ADT7476A
Figure 20. Reading Data from a Previously Selected Register
Rev. 0 | Page 13 of 72
D2
D0
NO ACK. BY STOP BY
MASTER
MASTER
05742-021
SDA
ADT7476A
WRITE OPERATIONS
Write Byte
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7476A are discussed below. The following abbreviations
are used in the diagrams:
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1.
The master device asserts a start condition on SDA.
•
S – START
2.
The master sends the 7-bit slave address followed by
the write bit (low).
•
P – STOP
3.
The addressed slave device asserts ACK on SDA.
•
R – READ
4.
The master sends a command code.
•
W – WRITE
5.
The slave asserts ACK on SDA.
•
A – ACKNOWLEDGE
6.
The master sends a data byte.
•
A – NO ACKNOWLEDGE
7.
The slave asserts ACK on SDA.
8.
The master asserts a stop condition on SDA,
and the transaction ends.
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
This operation is illustrated in Figure 22.
1
2
3
SLAVE
S ADDRESS W A
4
5
6
7 8
REGISTER
ADDRESS
A
DATA
A P
05742-023
The ADT7476A uses the following SMBus write protocols.
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by
the write bit (low).
3.
The addressed slave device asserts ACK on SDA.
The ADT7476A uses the following SMBus read protocols.
4.
The master sends a command code.
Receive Byte
5.
The slave asserts ACK on SDA.
6.
The master asserts a stop condition on SDA, and the
transaction ends.
This operation is useful when repeatedly reading a single register.
The register address is set up beforehand. In this operation, the
master device receives a single byte from a slave device, as follows:
Figure 22. Single-Byte Write to a Register
READ OPERATIONS
S
2
3
SLAVE
W A
ADDRESS
4
5 6
REGISTER
ADDRESS
A P
Figure 21. Setting a Register Address for Subsequent Read
If the master is required to read data from the register
immediately after setting up the address, it can assert a
repeat start condition immediately after the final ACK
and carry out a single byte read without asserting an
intermediate stop condition.
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives a data byte.
5.
The master asserts NO ACK on SDA.
6.
The master asserts a stop condition on SDA, and the
transaction ends.
In the ADT7476A, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This operation
is illustrated in Figure 23.
1
2
3
SLAVE
S ADDRESS R A
4
5 6
DATA
A P
05742-024
1
05742-022
For the ADT7476A, the send byte protocol is used to write a
register address to RAM for a subsequent single-byte read
from the same address. This operation is illustrated in Figure 21.
Figure 23. Single-Byte Read from a Register
Rev. 0 | Page 14 of 72
ADT7476A
Alert Response Address
VOLTAGE MEASUREMENT INPUT
Alert response address (ARA) is a feature of SMBus devices,
allowing an interrupting device to identify itself to the host
when multiple devices exist on the same bus.
The ADT7476A has four external voltage measurement
channels. It can also measure its own supply voltage, VCC.
The SMBALERT output can be used as either an interrupt output
or an SMBALERT. One or more outputs can be connected to a
common SMBALERT line connected to the master. If a device’s
SMBALERT line goes low, the following procedure occurs:
Pin 20 to Pin 23 can measure 5 V, 12 V, and 2.5 V supplies,
and the processor core voltage VCCP (0 V to 3 V input). The VCC
supply voltage measurement is carried out through the VCC pin
(Pin 4). The 2.5 V input can be used to monitor a chipset supply
voltage in computer systems.
1.
SMBALERT is pulled low.
ANALOG-TO-DIGITAL CONVERTER
2.
The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of this device is now known and can
be interrogated per usual.
4.
If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accordance with normal SMBus arbitration.
5.
Once the ADT7476A responds to the alert response address,
the master must read the status registers, and SMBALERT
is cleared only if the error condition goes away.
All analog inputs are multiplexed into the on-chip, successiveapproximation, analog-to-digital converter, which has a
resolution of 10 bits. The basic input range is 0 V to 2.25 V, but
the inputs have built-in attenuators to allow measurement of
2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP
without any external components. To allow the tolerance of
these supply voltages, the ADC produces an output of ¾ full
scale (768 dec or 300 hex) for the nominal input voltage, giving
it adequate headroom to cope with overvoltages.
INPUT CIRCUITRY
The internal structure for the analog inputs is shown in
Figure 24. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first-order lowpass filter that gives input immunity to high frequency noise.
12VIN
120kΩ
SMBus TIMEOUT
The ADT7476A includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7476A assumes the bus
is locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so if
necessary, it can be disabled.
Configuration Register 1 (0x40)
5VIN
3.3VIN
2.5VIN
[6] TODIS = 0, SMBus timeout enabled (default).
[6] TODIS = 1, SMBus timeout disabled.
VCCP
20kΩ
30pF
47kΩ
30pF
71kΩ
30pF
94kΩ
30pF
93kΩ
68kΩ
45kΩ
17.5kΩ
To prevent rogue programs or viruses from accessing critical
ADT7476A register settings, the lock bit can be set. Setting Bit 1 of
Configuration Register 1 (0x40) sets the lock bit and locks critical
registers. In this mode, certain registers can no longer be written to
until the ADT7476A is powered down and powered up again. For
more information on which registers are locked, see Table 18.
Rev. 0 | Page 15 of 72
35pF
05742-025
52.5kΩ
VIRUS PROTECTION
MUX
Figure 24. Structure of Analog Inputs
ADT7476A
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
VOLTAGE MEASUREMENT REGISTERS
Register 0x20, 2.5 V Reading = 0x00 default
Register 0x21, VCCP Reading = 0x00 default
A number of other functions are available on the ADT7476A to
offer the system designer increased flexibility.
Register 0x22, VCC Reading = 0x00 default
Turn-Off Averaging
Register 0x23, 5 V Reading = 0x00 default
For each voltage/temperature measurement read from a value
register, 16 readings have been made internally and the results
averaged before being placed into the value register. When faster
conversions are needed, setting Bit 4 of Configuration Register 2
(0x73) turns averaging off. This effectively gives a reading 16
times faster but the reading can be noisier. The default round
robin cycle time takes 146.5 ms.
Register 0x24, 12 V Reading = 0x00 default
VOLTAGE LIMIT REGISTERS
Associated with each voltage measurement channel is a high
and low limit register. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts.
Register 0x44, 2.5 V Low Limit = 0x00 default
Register 0x45, 2.5 V High Limit = 0xFF default
Register 0x46, VCCP Low Limit = 0x00 default
Table 6. Conversion Time with Averaging Disabled
Channel
Voltage Channels
Remote Temperature 1
Remote Temperature 2
Local Temperature
Measurement Time (ms)
0.7
7
7
1.3
When Bit 7 of Configuration Register 6 (0x10) is set, the default
round robin cycle time increases to 240 ms.
Register 0x47, VCCP High Limit = 0xFF default
Register 0x48, VCC Low Limit = 0x00 default
Bypass All Voltage Input Attenuators
Register 0x49, VCC High Limit = 0xFF default
Setting Bit 5 of Configuration Register 2 (0x73) removes the
attenuation circuitry from the 2.5 V, VCCP, VCC, 5 V, and 12 V
inputs. This allows the user to directly connect external sensors
or rescale the analog voltage measurement inputs for other
applications. The input range of the ADC without the
attenuators is 0 V to 2.25 V.
Register 0x4A, 5 V Low Limit = 0x00 default
Register 0x4B, 5 V High Limit = 0xFF default
Register 0x4C, 12 V Low Limit = 0x00 default
Register 0x4D, 12 V High Limit = 0xFF default
Table 9 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 0.7 ms and averages 16 conversions to reduce noise;
a measurement takes nominally 11 ms.
EXTENDED RESOLUTION REGISTERS
Voltage measurements can be made with higher accuracy using
the extended resolution registers (0x76 and 0x77). Whenever
the extended resolution registers are read, the corresponding
data in the voltage measurement registers (0x20 to 0x24) is
locked until their data is read. That is, if extended resolution is
required, then the extended resolution register must be read
first, immediately followed by the appropriate voltage
measurement register.
Bypass Individual Voltage Input Attenuators
Bits [7:4] of Configuration Register 4 (0x7D) can be used
to bypass individual voltage channel attenuators.
Table 7. Bypassing Individual Voltage Input Attenuators
Configuration Register 4 (0x7D)
Bit
Channel Attenuated
4
Bypass 2.5 V attenuator
5
Bypass VCCP attenuator
6
Bypass 5 V attenuator
7
Bypass 12 V attenuator
Configuration Register 2 (0x73)
[4] = 1, averaging off.
[5] = 1, bypass input attenuators.
[6] = 1, single-channel convert mode.
TACH1 Minimum High Byte (0x55)
[7:5] Selects ADC channel for single-channel convert mode.
Rev. 0 | Page 16 of 72
ADT7476A
Single-Channel ADC Conversion
Table 8. Programming Single-Channel ADC Mode
While single-channel mode is intended as a test mode that can
be used to increase sampling times for a specific channel, and
therefore helps to analyze that channel’s performance in greater
detail, it can also have other applications.
Bits [7:5] Register 0x55
000
001
010
011
100
101
110
111
Setting Bit 6 of Configuration Register 2 (0x73) places the
ADT7476A into single-channel ADC conversion mode. In this
mode, the ADT7476A can only read a single voltage channel.
The selected voltage input is read every 0.7 ms. The appropriate
ADC channel is selected by writing to Bits [7:5] of the TACH1
minimum high byte register (0x55).
1
Channel Selected 1
2.5 V
VCCP
VCC
5V
12 V
Remote 1 temperature
Local temperature
Remote 2 temperature
In the process of configuring single-channel ADC conversion mode, the
TACH1 minimum high byte is also changed, possibly trading off TACH1
minimum high byte functionality with single-channel mode functionality.
Table 9. 10-Bit A/D Output Code vs. VIN
12 VIN
<0.0156
0.0156 to 0.0312
0.0312 to 0.0469
0.0469 to 0.0625
0.0625 to 0.0781
0.0781 to 0.0937
0.0937 to 0.1093
0.1093 to 0.1250
0.1250 to 0.14060
4.0000 to 4.0156
8.0000 to 8.0156
12.0000 to 12.0156
15.8281 to 15.8437
15.8437 to 15.8593
15.8593 to 15.8750
15.8750 to 15.8906
15.8906 to 15.9062
15.9062 to 15.9218
15.9218 to 15.9375
15.9375 to 15.9531
15.9531 to 15.9687
15.9687 to 15.9843
>15.9843
5 VIN
<0.0065
0.0065 to 0.0130
0.0130 to 0.0195
0.0195 to 0.0260
0.0260 to 0.0325
0.0325 to 0.0390
0.0390 to 0.0455
0.0455 to 0.0521
0.0521 to 0.0586
•
•
•
1.6675 to 1.6740
•
•
•
3.3300 to 3.3415
•
•
•
5.0025 to 5.0090
•
•
•
6.5983 to 6.6048
6.6048 to 6.6113
6.6113 to 6.6178
6.6178 to 6.6244
6.6244 to 6.6309
6.6309 to 6.6374
6.6374 to 6.4390
6.6439 to 6.6504
6.6504 to 6.6569
6.6569 to 6.6634
>6.6634
Input Voltage
VCC (3.3 VIN)
<0.0042
0.0042 to 0.0085
0.0085 to 0.0128
0.0128 to 0.0171
0.0171 to 0.0214
0.0214 to 0.0257
0.0257 to 0.0300
0.0300 to 0.0343
0.0343 to 0.0386
2.5 VIN
<0.0032
0.0032 to 0.0065
0.0065 to 0.0097
0.0097 to 0.0130
0.0130 to 0.0162
0.0162 to 0.0195
0.0195 to 0.0227
0.0227 to 0.0260
0.0260 to 0.0292
VCCP
<0.00293
0.0293 to 0.0058
0.0058 to 0.0087
0.0087 to 0.0117
0.0117 to 0.0146
0.0146 to 0.0175
0.0175 to 0.0205
0.0205 to 0.0234
0.0234 to 0.0263
Decimal
0
1
2
3
4
5
6
7
8
1.1000 to 1.1042
0.8325 to 0.8357
0.7500 to 0.7529
256 (¼ scale)
01000000 00
2.2000 to 2.2042
1.6650 to 1.6682
1.5000 to 1.5029
512 (½ scale)
10000000 00
3.3000 to 3.3042
2.4975 to 2.5007
2.2500 to 2.2529
768 (¾ scale)
11000000 00
4.3527 to 4.3570
4.3570 to 4.3613
4.3613 to 4.3656
4.3656 to 4.3699
4.3699 to 4.3742
4.3742 to 4.3785
4.3785 to 4.3828
4.3828 to 4.3871
4.3871 to 4.3914
4.3914 to 4.3957
>4.3957
3.2942 to 3.2974
3.2974 to 3.3007
3.3007 to 3.3039
3.3039 to 3.3072
3.3072 to 3.3104
3.3104 to 3.3137
3.3137 to 3.3169
3.3169 to 3.3202
3.3202 to 3.3234
3.3234 to 3.3267
>3.3267
2.9677 to 2.9707
2.9707 to 2.9736
2.9736 to 2.9765
2.9765 to 2.9794
2.9794 to 2.9824
2.9824 to 2.9853
2.9853 to 2.9882
2.9882 to 2.9912
2.9912 to 2.9941
2.9941 to 2.9970
>2.9970
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
11111101 01
11111101 10
11111101 11
11111110 00
11111110 01
11111110 10
11111110 11
11111111 00
11111111 01
11111111 10
11111111 11
Rev. 0 | Page 17 of 72
A/D Output
Binary (10 Bits)
00000000 00
00000000 01
00000000 10
00000000 11
00000001 00
00000001 01
00000001 10
00000001 11
00000010 00
ADT7476A
VID CODE MONITORING
The ADT7476A has five dedicated voltage ID (VID code)
inputs. These are digital inputs that can be read back through
the VID/GPIO register (0x43) to determine the processor
voltage required or the system being used. Five VID code inputs
support VRM9.x solutions. In addition, Pin 21 (12 V input) can
be reconfigured as a sixth VID input to satisfy future VRM
requirements.
VID/GPIO Register (0x43)
[0] = VID0, reflects logic state of Pin 5.
[1] = VID1, reflects logic state of Pin 6.
[2] = VID2, reflects logic state of Pin 7.
the logic state of Pin 21. Bit 0 of Interrupt Status Register 2
(0x42) reflects VID code changes.
VID CODE CHANGE DETECT FUNCTION
The ADT7476A has a VID code change detect function. When
Pin 21 is configured as the VID5 input, VID code changes are
detected and reported back by the ADT7476A. Bit 0 of Interrupt
Status Register 2 (0x42) is the 12 V/VC bit and denotes a VID
change when set. The VID code change bit is set when the logic
states on the VID inputs are different than they were 11 μs
previously. The change of VID code is used to generate an
SMBALERT interrupt. If an SMBALERT interrupt is not
required, Bit 0 of Interrupt Mask Register 2 (0x75), when set,
prevents SMBALERTs from occurring on VID code changes.
Interrupt Status Register 2 (0x42)
[3] = VID3, reflects logic state of Pin 8.
[4] = VID4, reflects logic state of Pin 19.
[0] 12V/VC = 0, if Pin 21 is configured as VID5, Logic 0
denotes no change in VID code within the last 11 μs.
[5] = VID5, reconfigurable 12 V input. This bit reads 0 when
Pin 21 is configured as the 12 V input. This bit reflects the logic
state of Pin 21 when the pin is configured as VID5.
[0] 12V/VC = 1, if Pin 21 is configured as VID5, Logic 1 means
that a change has occurred on the VID code inputs within the
last 11 μs. An SMBALERT is generated, if this function is enabled.
VID CODE INPUT THRESHOLD VOLTAGE
PROGRAMMING THE GPIOS
The switching threshold for the VID code inputs is approximately
1 V. To enable future compatibility, it is possible to reduce the
VID code input threshold to 0.6 V. Bit 6 (THLD) of the VID/GPIO
register (0x43) controls the VID input threshold voltage.
The ADT7476A follows an upgrade path from the ADM1027 to
the ADT7476A. In order to maintain consistency between versions,
it is necessary to omit references to GPIO5. As a result, there are
six GPIOs as follows: GPIO0, GPIO1, GPIO2, GPIO3, GPIO4,
and GPIO6.
VID/GPIO Register (0x43)
[6] THLD = 0, VID switching threshold = 1 V,
VOL < 0.8 V, VIH > 1.7 V, VMAX = 3.3 V.
[6] THLD = 1, VID switching threshold = 0.6 V,
VOL < 0.4 V, VIH > 0.8 V, VMAX = 3.3 V.
Reconfiguring Pin 21 as VID5 Input
Pin 21 can be reconfigured as a sixth VID code input (VID5)
for VRM10 compatible systems. Because the pin is configured
as VID5, it is not possible to monitor a 12 V supply.
Bit 7 of the VID/GPIO register (0x43) determines the function
of Pin 21. System or BIOS software can read the state of Bit 7 to
determine whether the system is designed to monitor 12 V or a
sixth VID input.
VID/GPIO Register (0x43)
[7] VIDSEL = 0, Pin 21 functions as a 12 V measurement input.
Software can read this bit to determine that there are five VID
inputs being monitored. Bit 5 of VID/GPIO Register (0x43)
always reads back 0. Bit 0 of Interrupt Status Register 2 (0x42)
reflects 12 V out-of-limit measurements.
[7] VIDSEL = 1, Pin 21 functions as the sixth VID code input
(VID5). Software can read this bit to determine that there are
six VID inputs being monitored. Bit 5 of Register 0x43 reflects
Setting Bit 4 of Configuration Register 5 (0x7C) to 1 enables
GPIO functionality. This turns all pins configured as VID
inputs into general-purpose outputs. Writing to the corresponding
VID bit in the VID/GPIO register (0x43) sets the polarity
for the corresponding GPIO. GPIO6 can be programmed
independently as, for example, an input or output, using
Bits [3:2] of Configuration Register 5 (0x7C).
TEMPERATURE MEASUREMENT METHOD
Local Temperature Measurement
The ADT7476A contains an on-chip band gap temperature
sensor whose output is digitized by the on-chip, 10-bit ADC.
The 8-bit MSB temperature data is stored in the temperature
registers (Addresses 0x25, 0x26, and 0x27). Because both
positive and negative temperatures can be measured, the
temperature data is stored in Offset 64 format or twos
complement format, as shown in Table 10 and Table 11.
Theoretically, the temperature sensor and ADC can measure
temperatures from −63°C to +127°C (or −61°C to +191°C in the
extended temperature range) with a resolution of 0.25°C.
However, this exceeds the operating temperature range of the
device, so local temperature measurements outside the
ADT7476A operating temperature range are not possible.
Rev. 0 | Page 18 of 72
ADT7476A
This is given by
Table 10. Twos Complement Temperature Data Format
Temperature
–128°C
–50°C
–25°C
–10°C
0°C
+10.25°C
+25.5°C
+50.75°C
+75°C
+100°C
+125°C
+127°C
1
Digital Output (10-Bit)
1000 0000 00 (diode fault)
1100 1110 00
1110 0111 00
1111 0110 00
0000 0000 00
0000 1010 01
0001 1001 10
0011 0010 11
0100 1011 00
0110 0100 00
0111 1101 00
0111 1111 00
ΔVBE = KT/q × 1n(N)
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
Figure 25 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows
the external sensor as a substrate transistor, which is provided
on some microprocessors for temperature monitoring. It could
also be a discrete transistor such as a 2N3904/2N3906.
VDD
CPU
Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (0x77) with 0.25°C resolution.
I
Table 11. Extended Range, Temperature Data Format
Temperature
–64°C
–1°C
0°C
+1°C
+10°C
+25°C
+50°C
+75°C
+100°C
+125°C
+191°C
1
REMOTE
SENSING
TRANSISTOR
Digital Output (10-Bit)1
0000 0000 00 (diode fault)
0011 1111 00
0100 0000 00
0100 0001 00
0100 1010 00
0101 1001 00
0111 0010 00
1000 1001 00
1010 0100 00
1011 1101 00
1111 1111 00
THERMDA
D+
THERMDC
D–
N×I
IBIAS
VOUT+
TO ADC
BIAS
DIODE
VOUT–
LOW-PASS FILTER
fC = 65kHz
05742-026
1
Figure 25. Signal Conditioning for Remote Diode Temperature Sensors
If a discrete transistor is used, the collector is not grounded and
is linked to the base. If a PNP transistor is used, the base is
connected to the D– input and the emitter to the D+ input. If an
NPN transistor is used, the emitter is connected to the D– input
and the base to the D+ input. Figure 26 and Figure 27 show how
to connect the ADT7476A to an NPN or PNP transistor for
temperature measurement. To prevent ground noise from
interfering with the measurement, the more negative terminal
of the sensor is not referenced to ground, but is biased above
ground by an internal diode at the D– input.
Bold numbers denote 2 LSB of measurement in Extended Resolution
Register 2 (0x77) with 0.25°C resolution.
ADT7476A
Remote Temperature Measurement
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, the absolute
value of VBE varies from device to device, and individual
calibration is required to null this out. As a result, this
technique is unsuitable for mass production. The technique
used in the ADT7476A is to measure the change in VBE when
the device is operated at two different currents.
D+
D–
05742-027
2N3904
NPN
Figure 26. Measuring Temperature Using an NPN Transistor
ADT7476A
D+
2N3906
PNP
D–
05742-028
The ADT7476A can measure the temperature of two remote
diode sensors or diode-connected transistors connected to
Pin 17 and Pin 18, or Pin 15 and Pin 16.
Figure 27. Measuring Temperature Using a PNP Transistor
Rev. 0 | Page 19 of 72
ADT7476A
To measure ΔVBE, the sensor switches between operating
currents of I and N x I. The resulting waveform passes through
a 65 kHz low-pass filter to remove noise and through a chopperstabilized amplifier. The amplifier performs the amplification
and rectification of the waveform to produce a dc voltage
proportional to ΔVBE. This voltage is measured by the ADC to
give a temperature output in 10-bit, twos complement format.
To further reduce the effects of noise, digital filtering is performed
by averaging the results of 16 measurement cycles.
A remote temperature measurement takes nominally 38 ms.
The results of remote temperature measurements are stored in
10-bit, twos complement format, as illustrated in Table 10. The
extra resolution for the temperature measurements is held in
the Extended Resolution Register 2 (0x77). This gives
temperature readings with a resolution of 0.25°C.
Noise Filtering
For temperature sensors operating in noisy environments,
previous practice placed a capacitor across the D+ pin and
the D− pin to help combat the effects of noise. However,
large capacitances affect the accuracy of the temperature
measurement, leading to a recommended maximum capacitor
value of 1000 pF.
To factor this in, the user can write the ΔT value to the
offset register. The ADT7476A then automatically adds it
to or subtracts it from the temperature measurement.
•
Some CPU manufacturers specify the high and low current
levels of the substrate transistors. The high current level of
the ADT7476A, IHIGH, is 180 μA, and the low level current,
ILOW, is 11 μA. If the ADT7476A current levels do not match
the current levels specified by the CPU manufacturer, it
could be necessary to remove an offset. The CPU’s data sheet
advises whether this offset needs to be removed and how to
calculate it. This offset can be programmed to the offset
register. It is important to note that if more than one offset
must be considered, then the algebraic sum of these offsets
must be programmed to the offset register.
If a discrete transistor is used with the ADT7476A, the best
accuracy is obtained by choosing devices according to the
following criteria:
•
Base-emitter voltage greater than 0.25 V at 11 μA, at
the highest operating temperature.
•
Base-emitter voltage less than 0.95 V at 180 μA,
at the lowest operating temperature.
This capacitor reduces the noise but does not eliminate it, which
makes using the sensor difficult in a very noisy environment. In
most cases, a capacitor is not required because differential
inputs by their very nature have a high immunity to noise.
•
Base resistance less than 100 Ω.
•
Small variation in the current gain, hFE, (approximately 50
to 150) that indicates tight control of VBE characteristics.
FACTORS AFFECTING DIODE ACCURACY
Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23
packages, are suitable devices to use.
Remote Sensing Diode
The ADT7476A is designed to work with substrate transistors
built into processors or with discrete transistors. Substrate
transistors are generally PNP types with the collector connected
to the substrate. Discrete types can be either PNP or NPN
transistors connected as a diode (base-shorted to the collector).
If an NPN transistor is used, the collector and base are
connected to D+ and the emitter to D−. If a PNP transistor is
used, the collector and base are connected to D− and the
emitter is connected to D+.
To reduce the error due to variations in both substrate and
discrete transistors, a number of factors should be taken into
consideration:
•
The ideality factor, nf, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
ADT7476A is trimmed for an nf value of 1.008. Use the
following equation to calculate the error introduced at a
temperature T (°C), when using a transistor whose nf
does not equal 1.008 (see the processor’s data sheet for
the nf values):
ΔT = (nf − 1.008) × (273.15 K + T)
Nulling Out Temperature Errors
As CPUs run faster, it is more difficult to avoid high frequency
clocks when routing the D+/D– traces around a system board.
Even when recommended layout guidelines are followed, some
temperature errors can still be attributable to noise coupled
onto the D+/D– lines. Constant high frequency noise usually
attenuates, or increases, temperature measurements by a linear,
constant value.
The ADT7476A has temperature offset registers (0x70 and
0x72) for the Remote 1 and Remote 2 temperature channels. By
doing a one-time calibration of the system, the user can determine
the offset caused by system board noise and null it out using the
offset registers. The offset registers automatically add a twos
complement 8-bit reading to every temperature measurement.
Changing Bit 1 of Configuration Register 5 (0x7C) changes the
resolution and therefore, the range of the temperature offset as
either having a −63°C to +127°C range with a resolution of 1°C
or having a −63°C to +64°C range with a resolution of 0.5°C.
This temperature offset can be used to compensate for linear
temperature errors introduced by noise.
Rev. 0 | Page 20 of 72
ADT7476A
Temperature Offset Registers
Reading Temperature from the ADT7476A
Register 0x70, Remote 1 Temperature Offset = 0x00 (0°C default)
It is important to note that temperature can be read from the
ADT7476A as an 8-bit value (with 1°C resolution) or as a 10-bit
value (with 0.25°C resolution). If only 1°C resolution is required,
the temperature readings can be read back at any time and in no
particular order.
Register 0x71, Local Temperature Offset = 0x00 (0°C default)
Register 0x72, Remote 2 Temperature Offset = 0x00 (0°C default)
ADT7463/ADT7476A Backwards Compatible Mode
By setting Bit 0 of Configuration Register 5 (0x7C), all temperature measurements are stored in the zone temperature reading
registers (0x25, 0x26, and 0x27) in twos complement in the
−63°C to +127°C range. The temperature limits must be
reprogrammed in twos complement.
If a twos complement temperature below −63°C is entered, the
temperature is clamped to −63°C. In this mode, the diode fault
condition remains −128°C = 1000 0000, while in the extended
temperature range (−63°C to +191°C), the fault condition is
represented by −64°C = 0000 0000.
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. Extended Resolution Register 2
(0x77) should be read first. This causes all temperature reading
registers to be frozen until all temperature reading registers have
been read from. This prevents an MSB reading from being
updated while its two LSBs are being read and vice versa.
ADDITIONAL ADC FUNCTIONS FOR
TEMPERATURE MEASUREMENT
A number of other functions are available on the ADT7476A to
offer the system designer increased flexibility.
Temperature Reading Registers
Turn-Off Averaging
Register 0x25, Remote 1 Temperature
For each temperature measurement read from a value register,
16 readings have actually been made internally, and the results
averaged, before being placed into the value register. Sometimes
it is necessary to take a very fast measurement. Setting Bit 4 of
Configuration Register 2 (0x73) turns averaging off. The default
round robin cycle time takes 146.5 ms.
Register 0x26, Local Temperature
Register 0x27, Remote 2 Temperature
Register 0x77, Extended Resolution 2 = 0x00 default
Table 12. Conversion Time with Averaging Disabled
[7:6] TDM2, Remote 2 temperature LSBs.
Channel
Voltage Channels
Remote Temperature 1
Remote Temperature 2
Local Temperature
[5:4] LTMP, Local temperature LSBs.
[3:2] TDM1, Remote 1 temperature LSBs.
Temperature Limit Registers
Associated with each temperature measurement channel are high
and low limit registers. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts (depending on
the way the interrupt mask register is programmed and assuming
that SMBALERT is set as an output on the appropriate pin).
Register 0x4E, Remote 1 Temperature Low Limit = 0x81 default
Register 0x4F, Remote 1 Temperature High Limit = 0x7F default
Register 0x50, Local Temperature Low Limit = 0x81 default
Register 0x51, Local Temperature High Limit = 0x7F default
Register 0x52, Remote 2 Temperature Low Limit = 0x81 default
Register 0x53, Remote 2 Temperature High Limit = 0x7F default
Measurement Time (ms)
0.7
7
7
1.3
When Bit 7 of Configuration Register 6 (0x10) is set, the default
round robin cycle time increases to 240 ms.
Table 13. Conversion Time with Averaging Enabled
Channel
Voltage Channels
Remote Temperature
Local Temperature
Measurement Time (ms)
11
39
12
Single-Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (0x73) places the
ADT7476A into single-channel ADC conversion mode. In this
mode, the ADT7476A can be made to read a single temperature
channel only. The appropriate ADC channel is selected by writing
to Bits [7:5] of the TACH1 minimum high byte register (0x55).
Table 14. Programming Single Channel ADC Mode for
Temperatures
Bits [7:5] Reg. 0x55
101
110
111
Rev. 0 | Page 21 of 72
Channel Selected
Remote 1 temperature
Local temperature
Remote 2 temperature
ADT7476A
Configuration Register 2 (0x73)
THERM LIMIT
[4] = 1, averaging off.
[6] = 1, single-channel convert mode.
HYSTERESIS (°C)
TEMPERATURE
TACH1 Minimum High Byte (0x55)
FANS
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Register 0x6A to Register 0x6C are the THERM
temperature limits. When a temperature exceeds its THERM
temperature limit, all PWM outputs run at the maximum
PWM duty cycle (Register 0x38, Register 0x39, and Register
0x3A). This effectively runs the fans at the fastest allowed speed.
The fans run at this speed until the temperature drops below
THERM minus hysteresis. This can be disabled by setting Bit 2,
the boost bit, in Configuration Register 3 (0x78). The hysteresis
value for the THERM temperature limit is the value programmed
into the hysteresis registers (0x6D and 0x6E). The default
hysteresis value is 4°C.
100%
05742-029
[7:5] selects ADC channel for single-channel convert mode.
Figure 28. THERM Temperature Limit Operation
THERM can be disabled on specific temperature channels using
Bits [7:5] of Configuration Register 5 (0x7C). THERM can also
be disabled by:
•
Writing −64°C to the appropriate THERM temperature
limit in Offset 64 mode.
•
Writing −128°C to the appropriate THERM temperature
limit in twos complement mode.
Rev. 0 | Page 22 of 72
ADT7476A
LIMITS, STATUS REGISTERS, AND INTERRUPTS
LIMIT VALUES
16-Bit Limits
Associated with each measurement channel on the ADT7476A
are high and low limits. These can form the basis of system
status monitoring; a status bit can be set for any out-of-limit
condition and is detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag out-of-limit
conditions to a processor or microcontroller.
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Because fans running under speed or stalled are normally the
only conditions of interest, only high limits exist for fan TACHs.
Because the fan TACH period is actually being measured,
exceeding the limit indicates a slow or stalled fan.
8-Bit Limits
Fan Limit Registers
The following is a list of 8-bit limits on the ADT7476A.
Register 0x54, TACH1 Minimum Low Byte = 0xFF default
Voltage Limit Registers
Register 0x55, TACH1 Minimum High Byte = 0xFF default
Register 0x44, 2.5 V Low Limit = 0x00 default
Register 0x56, TACH2 Minimum Low Byte = 0xFF default
Register 0x45, 2.5 V High Limit = 0xFF default
Register 0x57, TACH2 Minimum High Byte = 0xFF default
Register 0x46, VCCP Low Limit = 0x00 default
Register 0x58, TACH3 Minimum Low Byte = 0xFF default
Register 0x47, VCCP High Limit = 0xFF default
Register 0x59, TACH3 Minimum High Byte = 0xFF default
Register 0x48, VCC Low Limit = 0x00 default
Register 0x5A, TACH4 Minimum Low Byte = 0xFF default
Register 0x49, VCC High Limit = 0xFF default
Register 0x5B, TACH4 Minimum High Byte = 0xFF default
Register 0x4A, 5 V Low Limit = 0x00 default
Out-of-Limit Comparisons
Once all limits have been programmed, the ADT7476A can be
enabled for monitoring. The ADT7476A measures all voltage
and temperature measurements in round robin format and sets
the appropriate status bit for out-of-limit conditions. TACH
measurements are not part of this round robin cycle. Comparisons are done differently depending on whether the measured
value is being compared to a high or low limit.
Register 0x4B, 5 V High Limit = 0xFF default
Register 0x4C, 12 V Low Limit = 0x00 default
Register 0x4D, 12 V High Limit = 0xFF default
Temperature Limit Registers
Register 0x4E, Remote 1 Temperature Low Limit = 0x81 default
High Limit: > Comparison Performed
Register 0x4F, Remote 1 Temperature High Limit = 0x7F default
Low Limit: ≤ Comparison Performed
Register 0x6A, Remote 1 THERM Limit = 0x64 default
Register 0x51, Local Temperature High Limit = 0x7F default
Voltage and temperature channels use a window comparator
for error detecting and, therefore, have high and low limits.
Fan speed measurements use only a low limit. This fan limit is
needed only in manual fan control mode.
Register 0x6B, Local THERM Limit = 0x64 default
Analog Monitoring Cycle Time
Register 0x50, Local Temperature Low Limit = 0x81 default
Register 0x52, Remote 2 Temperature Low Limit = 0x81 default
Register 0x53, Remote 2 Temperature High Limit = 0x7F default
Register 0x6C, Remote 2 THERM Limit = 0x64 default
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0) of Configuration Register 1 (0x40). The ADC
measures each analog input in turn, and, as each measurement
is completed, the result is automatically stored in the appropriate
value register. This round robin monitoring cycle continues unless
disabled by writing a 0 to Bit 0 of Configuration Register 1.
THERM Timer Limit Register
Register 0x7A, THERM Timer Limit = 0x00 default.
As the ADC is normally left to free-run in this manner, the
time taken to monitor all the analog inputs is normally not of
interest, because the most recently measured value of any input
can be read out at any time.
Rev. 0 | Page 23 of 72
ADT7476A
For applications where the monitoring cycle time is important,
it can easily be calculated.
The total number of channels measured is
•
Four dedicated supply voltage inputs
•
Supply voltage (VCC pin)
•
Local temperature
•
Two remote temperatures
Interrupt Status Register 1 (0x41)
Bit 7 (OOL) = 1, denotes a bit in Interrupt Status Register 2 is
set and Interrupt Status Register 2 should be read.
Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has
been exceeded.
Bit 5 (LT) = 1, Local temperature high or low limit has been
exceeded.
As mentioned previously, the ADC performs round robin
conversions and takes 11 ms for each voltage measurement,
12 ms for a local temperature reading, and 39 ms for each
remote temperature reading. The total monitoring cycle time
for averaged voltage and temperature monitoring is, therefore,
nominally
Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has
been exceeded.
Bit 3 (5 V) = 1, 5 V high or low limit has been exceeded.
Bit 2 (VCC) = 1, VCC high or low limit has been exceeded.
Bit 1 (VCCP) = 1, VCCP high or low limit has been exceeded.
Bit 0 (2.5 V) = 1, 2.5 V high or low limit has been exceeded. If
the 2.5 V input is configured as THERM, this bit represents the
status of THERM.
(5 × 11) + 12 + (2 × 39) =145 ms
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
Interrupt Status Register 2 (0x42)
STATUS REGISTERS
Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.
The results of limit comparisons are stored in Interrupt Status
Register 1 and Interrupt Status Register 2. The status register bit
for each channel reflects the status of the last measurement and
limit comparison on that channel. If a measurement is within
limits, the corresponding status register bit is cleared to 0. If the
measurement is out-of-limits, the corresponding status register
bit is set to 1.
The state of the various measurement channels can be polled by
reading the status registers over the serial bus. In Bit 7 (OOL) of
Interrupt Status Register 1 (0x41), 1 means an out-of-limit event
has been flagged in Interrupt Status Register 2. This means the
user also needs to read Interrupt Status Register 2. Alternatively,
Pin 10 or Pin 14 can be configured as an SMBALERT output.
This hard interrupt automatically notifies the system supervisor
of an out-of-limit condition. Reading the status registers clears
the appropriate status bit as long as the error condition that
caused the interrupt has cleared. Status register bits are sticky.
Whenever a status bit is set, indicating an out-of-limit
condition, it remains set even if the event that caused it has
gone away (until read).
The only way to clear the status bit is to read the status register
after the event has gone away. Interrupt mask registers (0x74
and 0x75) allow individual interrupt sources to be masked from
causing an SMBALERT. However, if one of these masked
interrupt sources goes out of limit, its associated status bit is set
in the status registers.
Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs.
Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum
speed. Alternatively, indicates that the THERM limit has been
exceeded, if the THERM function is used. Alternatively,
indicates the status of GPIO6.
Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below
minimum speed.
Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below
minimum speed.
Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below
minimum speed.
Bit 1 (OVT) = 1, indicates a THERM overtemperature limit has
been exceeded.
Bit 0 (12V/VC) = 1, indicates a 12 V high or low limit has been
exceeded. If the VID code change function is used, this bit
indicates a change in VID code on the VID0 to VID4 inputs.
SMBALERT Interrupt Behavior
The ADT7476A can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status
bits behave when writing interrupt handler software.
Rev. 0 | Page 24 of 72
ADT7476A
Masking Interrupt Sources
HIGH LIMIT
Interrupt Mask Register 1 (0x74) and Interrupt Mask Register 2
(0x75) allow individual interrupt sources to be masked to
prevent SMBALERT interrupts. Note: Masking an interrupt
source prevents only the SMBALERT output from being
asserted; the appropriate status bit is set normally.
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
STICKY
STATUS BIT
05742-030
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
HIGH LIMIT
Figure 29. SMBALERT and Status Bit Behavior
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
STICKY
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
Note that:
•
•
05742-031
Figure 29 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. The status bits are
referred to as sticky because they remain set until read by
software. This ensures that an out-of-limit event cannot be
missed if the software is periodically polling the device.
Figure 30. How Masking the Interrupt Source Affects SMBALERT Output
The SMBALERT output remains low for the entire
duration that a reading is out-of-limit and until the
status register has been read. This has implications on
how software handles the interrupt.
Interrupt Mask Register 1 (0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Interrupt Status Register 2.
THERM overtemperature events are not sticky. They reset
immediately after the overtemperature condition ceases.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing interrupts,
it is recommend to handle the SMBALERT interrupt as follows:
1.
Detect the SMBALERT assertion.
2.
Enter the interrupt handler.
3.
Read the status registers to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (0x74 and 0x75).
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 30.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 3 (5 V) = 1, masks SMBALERT for 5 V channel.
Bit 2 (VCC) = 1, masks SMBALERT for VCC channel.
Bit 1 (VCCP) = 1, masks SMBALERT for VCCP channel.
Bit 0 (2.5V) = 1, masks SMBALERT for 2.5VIN/THERM.
Interrupt Mask Register 2 (0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure.
If the TACH4 pin is being used as the THERM input, this bit masks
SMBALERT for a THERM event. If the TACH4 pin is being used
as GPIO6, setting this bit masks interrupts related to GPIO6.
Rev. 0 | Page 25 of 72
ADT7476A
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
When the THERM pin is driven low externally, the user can
also set up the ADT7476A to run the fans at 100%. The fans run
at 100% for the duration of time that the THERM pin is pulled low.
This is done by setting the BOOST bit (Bit 2) in Configuration
Register 3 (0x78) to 1. This works only if the fan is already running,
for example, in manual mode, when the current duty cycle is above
0x00, or in automatic mode when the temperature is above TMIN.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM temperature limits).
If the temperature is below TMIN or if the duty cycle in manual
mode is set to 0x00, pulling the THERM low externally has no
effect. See Figure 31 for more information.
Bit 0 (12V/VC) = 1, masks SMBALERT for 12 V channel or
for a VID code change, depending on the function used.
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default.
Pin 10 or Pin 14 can be reconfigured as an SMBALERT
output to signal out-of-limit conditions.
TMIN
Table 15. Configuring Pin 10 as SMBALERT Output
THERM
Bit Setting
[1] Pin 10 = SMBALERT
[0] Pin 10 = PWM2
Assigning THERM Functionality to a Pin
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS BELOW TMIN.
Pin 14 on the ADT7476A has four possible functions:
SMBALERT, THERM, GPIO6, and TACH4. The user
chooses the required functionality by setting Bit 0 and Bit 1
of Configuration Register 4 (0x7D).
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS ABOVE TMIN AND FANS
ARE ALREADY RUNNING.
Figure 31. Asserting THERM Low as an Input
in Automatic Fan Speed Control Mode
If THERM is enabled on Bit 1, Configuration Register 3 (0x78):
•
Pin 22 becomes THERM.
•
If Pin 14 is configured as THERM on Bit 0 and Bit 1 of Configuration Register 4 (0x7D), THERM is enabled on this pin.
THERM TIMER
If THERM is not enabled:
•
Pin 22 becomes a 2.5 V measurement input.
•
If Pin 14 is configured as THERM, then THERM is
disabled on this pin.
Bit 1
0
1
0
1
The ADT7476A has an internal timer to measure THERM
assertion time. For example, the THERM input can be
connected to the PROCHOT output of a Pentium 4 CPU to
measure system performance. The THERM input can also be
connected to the output of a trip-point temperature sensor.
The timer is started on the assertion of the ADT7476A’s THERM
input and stopped when THERM is de-asserted. The timer counts
THERM times cumulatively; that is, the timer resumes counting
on the next THERM assertion. The THERM timer continues to
accumulate THERM assertion times until the timer is read
(where it is cleared), or until it reaches full scale. If the counter
reaches full scale, it stops at that reading until cleared.
Table 16. Configuring Pin 14
Bit 0
0
0
1
1
05742-032
Register
Configuration Register 3 (0x78)
Function
TACH4
THERM
SMBALERT
GPIO6
THERM as an Input
When THERM is configured as an input, the user can time
assertions on the THERM pin. This can be useful for connecting
to the PROCHOT output of a CPU to gauge system performance.
The 8-bit THERM timer status register (0x79) is designed so
that Bit 0 is set to 1 on the first THERM assertion. Once the
cumulative THERM assertion time has exceeded 45.52 ms, Bit 1
of the THERM timer is set and Bit 0 now becomes the LSB of
the timer with a resolution of 22.76 ms (see Figure 32).
Rev. 0 | Page 26 of 72
ADT7476A
THERM
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 0 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED
≤ 22.76ms
2.
Bit 0 of the THERM timer is set to 1, because a THERM
assertion is occurring.
3.
The THERM timer increments from zero.
4.
If the THERM timer limit register (0x7A) = 0x00, the F4P
bit is set.
THERM
Generating SMBALERT Interrupts from THERM Timer
Events
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
TIMER
(REG. 0x79)
The ADT7476A can generate SMBALERTs when a programmable
THERM timer limit has been exceeded. This allows the system
designer to ignore brief, infrequent THERM assertions, while
capturing longer THERM timer events. Register 0x7A is the
THERM timer limit register. This 8-bit register allows a limit
from 0 sec (first THERM assertion) to 5.825 sec to be set before
an SMBALERT is generated. The THERM timer value is
compared with the contents of the THERM timer limit register.
If the THERM timer value exceeds the THERM timer limit
value, then the F4P bit (Bit 5) of Interrupt Status Register 2 is
set and an SMBALERT is generated.
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
THERM ASSERTED
≥ 45.52ms
THERM
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 1 0 1
7 6 5 4 3 2 1 0 THERM ASSERTED ≥ 113.8ms
(91.04ms + 22.76ms)
05742-033
ACCUMULATE THERM LOW
ASSERTION TIMES
Figure 32. Understanding the THERM Timer
When using the THERM timer, be aware of the following:
Note: Depending on which pins are configured as a THERM
timer, setting the F4P bit (Bit 5) of Mask Register 2 (0x75) or Bit 0
of Mask Register 1 (0x74) masks out SMBALERT; although the
F4P bit of Interrupt Status Register 2 is still set if the THERM
timer limit is exceeded.
After a THERM timer read (0x79)
1.
The contents of the timer are cleared on read.
2.
The F4P bit (Bit 5) of Interrupt Status Register 2 needs to
be cleared (assuming that the THERM timer limit has
been exceeded).
Figure 33 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (0x7A) causes an SMBALERT to be
generated on the first THERM assertion. A THERM timer limit
value of 0x01 generates an SMBALERT once cumulative
THERM assertions exceed 45.52 ms.
If the THERM timer is read during a THERM assertion, the
following occurs:
The contents of the timer are cleared.
THERM LIMIT
(REG. 0x7A)
2.914s
1.457s
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
2.914s
1.457s
728.32ms
364.16ms THERM TIMER
(REG. 0x79)
182.08ms
91.04ms
45.52ms
22.76ms
0 1 2 3 4 5 6 7
7 6 5 4 3 2 1 0
THERM
THERM TIMER CLEARED ON READ
COMPARATOR
IN
OUT
F4P BIT (BIT 5)
STATUS REGISTER 2
SMBALERT
LATCH
RESET
CLEARED
ON READ
1 = MASK
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
Figure 33. Functional Block Diagram of THERM Monitoring Circuitry
Rev. 0 | Page 27 of 72
05742-034
1.
ADT7476A
Alternatively, OS- or BIOS-level software can timestamp when
the system is powered on. If an SMBALERT is generated due
to the THERM timer limit being exceeded, another timestamp
can be taken. The difference in time can be calculated for a
fixed THERM timer limit time. For example, if it takes one
week for a THERM timer limit of 2.914 sec to be exceeded,
and the next time it takes only 1 hour, then a serious
degradation in system performance has occurred.
Configuring the Relevant THERM Behavior
Configure the desired pin as the THERM timer input.
Setting Bit 1 (THERM timer enable) of Configuration
Register 3 (0x78) enables the THERM timer monitoring
functionality. This is disabled on Pin 14 and Pin 22 by default.
Setting Bit 0 and Bit 1 (PIN14FUNC) of Configuration
Register 4 (0x7D) enables THERM timer output functionality
on Pin 22 (Bit 1 of Configuration Register 3, THERM,
must also be set). Pin 14 can also be used as TACH4.
2.
Select the desired fan behavior for THERM timer events.
Assuming the fans are running, setting Bit 2 (BOOST bit)
of Configuration Register 3 (0x78) causes all fans to run at
100% duty cycle whenever THERM is asserted. This allows
fail-safe system cooling. If this bit is 0, the fans run at their
current settings and are not affected by THERM events. If
the fans are not already running when THERM is asserted,
then the fans do not run to full speed.
3.
Select whether THERM timer events should generate
SMBALERT interrupts.
Setting Bit 5 (F4P) of Mask Register 2 (0x75) or Bit 0 of
Mask Register 1 (0x74), depending on which pins are
configured as a THERM timer, masks SMBALERTs when
the THERM timer limit value is exceeded. This bit should be
cleared if SMBALERTs based on THERM events are required.
4.
Select a suitable THERM limit value.
This value determines whether an SMBALERT is generated
on the first THERM assertion, or if only a cumulative
THERM assertion time limit is exceeded. A value of 0x00
causes an SMBALERT to be generated on the first THERM
assertion.
5.
Configuring the THERM Pin as an Output
In addition to monitoring THERM as an input, the ADT7476A
can optionally drive THERM low as an output. When PROCHOT
is bidirectional, THERM can be used to throttle the processor by
asserting PROCHOT. The user can preprogram system-critical
thermal limits. If the temperature exceeds a thermal limit by
0.25°C, THERM asserts low. If the temperature is still above the
thermal limit on the next monitoring cycle, THERM stays low.
THERM remains asserted low until the temperature is equal to
or below the thermal limit. Because the temperature for that
channel is measured only once for every monitoring cycle, after
THERM asserts, it is guaranteed to remain low for at least one
monitoring cycle.
The THERM pin can be configured to assert low, if the
Remote 1, local, or Remote 2 THERM temperature limits are
exceeded by 0.25°C. The THERM temperature limit registers
are at Register 0x6A, Register 0x6B, and Register 0x6C,
respectively. Setting Bits [5:7] of Configuration Register 5 (0x7C)
enables the THERM output feature for the Remote 1, local, and
Remote 2 temperature channels, respectively. Figure 34 shows
how the THERM pin asserts low as an output in the event of a
critical overtemperature.
THERM LIMIT
0.25°C
THERM LIMIT
TEMP
Select a THERM monitoring time.
THERM
This value specifies how often OS- or BIOS-level software
checks the THERM timer. For example, BIOS can read the
THERM timer once an hour to determine the cumulative
THERM assertion time. If, for example, the total THERM
assertion time is <22.76 ms in Hour 1, >182.08 ms in Hour 2,
and >5.825 s in Hour 3, system performance is degrading
significantly because THERM is asserting more frequently
on an hourly basis.
MONITORING
CYCLE
05742-035
1.
Figure 34. Asserting THERM as an Output, Based on Tripping THERM Limits
An alternative method of disabling THERM is to program the
THERM temperature limit to –63°C or less in Offset 64 mode,
or −128°C or less in twos complement mode; that is, for
THERM temperature limit values less than –63°C or –128°C,
respectively, THERM is disabled.
Rev. 0 | Page 28 of 72
ADT7476A
Enabling and Disabling THERM on individual Channels
THERM can be enabled/disabled for individual or combinations of temperature channels using Bits [7:5] of Configuration
Register 5 (0x7C).
THERM Hysteresis
Setting Bit 0 of Configuration Register 7 (0x11) disables
THERM hysteresis.
If THERM hysteresis is enabled and THERM is disabled (Bit 2 of
Configuration Register 4, 0x7D), the THERM pin does not assert
low when a THERM event occurs. If THERM hysteresis is disabled
and THERM is disabled (Bit 2 of Configuration Register 4, 0x7D)
and assuming the appropriate pin is configured as THERM), the
THERM pin asserts low when a THERM event occurs.
Typical notebook fans draw a nominal 170 mA, so SOT devices
can be used where board space is a concern. In desktops, fans
typically draw 250 mA to 300 mA each. If you drive several fans
in parallel from a single PWM output or drive larger server
fans, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET should
have a gate voltage drive, VGS < 3.3 V, for direct interfacing to
the PWM output pin. The MOSFET should also have a low on
resistance to ensure that there is not a significant voltage drop
across the FET, which would reduce the voltage applied across
the fan and, therefore, the maximum operating speed of the fan.
Figure 35 shows how to drive a 3-wire fan using PWM control.
12V
12V
10kΩ
TACH
If THERM and THERM hysteresis are both enabled, the
THERM output asserts as expected.
10kΩ
4.7kΩ
ADT7476A
THERM Operation in Manual Mode
12V
FAN
TACH
1N4148
3.3V
10kΩ
Q1
NDT3055L
05742-036
In manual mode, THERM events do not cause fans to go to full
speed, unless Bit 3 of Configuration Register 6 (0x10) is set to 1.
PWM
Figure 35. Driving a 3-Wire Fan Using an N-Channel MOSFET
Bit 2 in Configuration Register 4 (0x7D) can be set to disable
THERM events from affecting the fans.
FAN DRIVE USING PWM CONTROL
The ADT7476A uses pulse-width modulation (PWM) to
control fan speed. This relies on varying the duty cycle (or
on/off ratio) of a square wave applied to the fan to vary the fan
speed. The external circuitry required to drive a fan using
PWM control is extremely simple. For 4-wire fans, the PWM
drive might need only a pull-up resistor. In many cases, the
4-wire fan PWM input has a built-in, pull-up resistor.
The ADT7476A PWM frequency can be set to a selection of
low frequencies or a single high PWM frequency. The low
frequency options are used for 3-wire fans, while the high
frequency option is usually used with 4-wire fans.
Figure 35 uses a 10 kΩ pull-up resistor for the TACH signal.
This assumes that the TACH signal is an open-collector from
the fan. In all cases, the TACH signal from the fan must be kept
below 5.5 V maximum to prevent damaging the ADT7476A.
Figure 36 shows a fan drive circuit using an NPN transistor
such as a general-purpose MMBT2222. While these devices are
inexpensive, they tend to have much lower current handling
capabilities and higher on resistance than MOSFETs. When
choosing a transistor, care should be taken to ensure that it
meets the fan’s current requirements. Ensure that the base
resistor is chosen so that the transistor is saturated when the fan
is powered on.
Because the fan drive circuitry in 4-wire fans is not switched on
or off, as with previous PWM driven/powered fans, the internal
drive circuit is always on and uses the PWM input as a signal
instead of a power supply. This enables the internal fan drive
circuit to perform better than 3-wire fans, especially for high
frequency applications.
For 3-wire fans, a single N-channel MOSFET is the only drive
device required. The specifications of the MOSFET depend on
the maximum current required by the fan being driven and
the input capacitance of the FET. Because a 10 kΩ (or greater)
resistor must be used as a PWM pull-up, an FET with large
input capacitance can cause the PWM output to become
distorted and adversely affect the fan control range. This is a
requirement only when using high frequency PWM mode.
12V
12V
10kΩ
TACH
10kΩ
4.7kΩ
ADT7476A
TACH
12V
FAN
1N4148
3.3V
470Ω
PWM
Q1
MMBT2222
Figure 36. Driving a 3-Wire Fan Using an NPN Transistor
Rev. 0 | Page 29 of 72
05742-037
Additionally, Bit 3 of Configuration Register 4 (0x7D) can be
used to select the PWM speed on a THERM event (100% or
maximum PWM).
ADT7476A
Figure 37 shows a typical drive circuit for 4-wire fans.
Because the MOSFET can handle up to 3.5 A, users can
connect another fan directly in parallel with the first. Care
should be taken in designing drive circuits with transistors
and FETs to ensure that the PWM outputs are not required
to source current, and that they sink less than the 5 mA
maximum current specified on the data sheet.
12V 12V
12V, 4-WIRE FAN
10kΩ
4.7kΩ
TACH
TACH
PWM
Driving up to Three Fans from PWM3
3.3V
TACH measurements for fans are synchronized to particular
PWM channels; for example, TACH1 is synchronized to
PWM1. TACH3 and TACH4 are both synchronized to PWM3,
so PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the
PWM3 output. This allows PWM3 to drive two or three fans.
In this case, the drive circuitry looks the same, as shown in
Figure 38 and Figure 39. The SYNC bit in Register 0x62 enables
this function.
05742-038
2kΩ
PWM
Figure 37. Driving a 4-Wire Fan
Driving Two Fans from PWM3
The ADT7476A has four TACH inputs available for fan speed
measurement, but only three PWM drive outputs. If a fourth
fan is being used in the system, it should be driven from the
PWM3 output in parallel with the third fan.
Synchronization is not required in high frequency mode when
used with 4-wire fans.
Figure 38 shows how to drive two fans in parallel using low
cost NPN transistors. Figure 39 shows the equivalent circuit
using a MOSFET.
(SYNC) Enhance Acoustics Register 1 (0x62)
[4] SYNC = 1, synchronizes TACH2, TACH3, and TACH4
to PWM3.
.
12V
ADT7476A
3.3V
3.3V
TACH3
1kΩ
PWM3
3.3V
Q1
MMBT3904
2.2kΩ
10kΩ
TACH4
3.3V
Q2
MMBT2222
05742-039
10kΩ
Q3
MMBT2222
Figure 38. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors
3.3V
10kΩ
TYPICAL
TACH4
+V
3.3V
+V
3.3V
ADT7476A
10kΩ
TYPICAL
TACH
TACH3
5V OR
12V FAN
1N4148
3.3V
TACH
5V OR
12V FAN
3.3V
10kΩ
TYPICAL
PWM3
Q1
NDT3055L
05742-040
ADT7476A
VCC
10kΩ
1N4148
TACH
Figure 39. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET
Rev. 0 | Page 30 of 72
ADT7476A
VCC
12V
Figure 40 shows how to lay out a common circuit arrangement
for 3-wire fans.
PULL-UP
4.7kΩ
TYPICAL
12V OR 5V
TACH
OUTPUT
TACH
ZD1*
R1
1N4148
ADT7476A
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC
3.3V OR 5V
R2
FAN SPEED
COUNTER
05742-043
LAYING OUT 3-WIRE FANS
Figure 42. Fan with TACH Pull-Up to Voltage > 5.5V, (for Example, 12 V)
Clamped with Zener Diode
R4
PWM
If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a
totem-pole output, a series resistor can be added to limit the
Zener current, as shown in Figure 43.
Figure 40. Planning for 3-Wire Fans on a PCB
VCC
5V OR 12V
TACH Inputs
Pin 9, Pin 11, Pin 12, and Pin 14 (when configured as TACH
inputs) are high impedance inputs intended for fan speed
measurement.
Signal conditioning in the ADT7476A accommodates the slow
rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 5.5 V, even though VCC is
3.3 V. In the event that these inputs are supplied from fan
outputs that exceed 0 V to 5.5 V, either resistive attenuation
of the fan signal or diode clamping must be included to keep
inputs within an acceptable range.
Figure 41 to Figure 44 show circuits for most common fan
TACH outputs.
VCC
TACH
OUTPUT
ZD1
ZENER*
FAN SPEED
COUNTER
ADT7476A
Figure 43. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,
Clamped with Zener Diode and Resistor
Alternatively, a resistive attenuator can be used, as shown
in Figure 44. R1 and R2 should be chosen such that
The fan inputs have an input resistance of nominally 160 kΩ to
ground, which should be taken into account when calculating
resistor values.
VCC
12V
FAN SPEED
COUNTER
ADT7476A
TACH
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC
05742-042
TACH
R1
10kΩ
With a pull-up voltage of 12 V and pull-up resistor less than
1 kΩ, suitable values for R1 and R2 are 100 kΩ and 40 kΩ,
respectively. This gives a high input voltage of 3.42 V.
12V
TACH
OUTPUT
PULL-UP TYP
<1kΩ OR
TOTEM POLE
2 V < VPULL-UP × R2 / (RPULL-UP + R1 + R2) < 5.5 V
If the fan TACH output has a resistive pull-up to VCC, it can be
connected directly to the fan input, as shown in Figure 41.
PULL-UP
4.7kΩ
TYP
FAN
05742-044
R3
<1kΩ
R1*
Figure 41. Fan with TACH Pull-Up to VCC
If the fan output has a resistive pull-up to 12 V, or other voltage
greater than 5.5 V, the fan output can be clamped with a Zener
diode, as shown in Figure 42. The Zener diode voltage should
be chosen so that it is greater than VIH of the TACH input but
less than 5.5 V, allowing for the voltage tolerance of the Zener.
A value between 5 V and 5.5 V is suitable.
TACH
OUTPUT
TACH
R2*
*SEE TEXT
FAN SPEED
COUNTER
ADT7476A
05742-045
Q1
MMBT2222
05742-041
TACH
Figure 44. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,
Attenuated with R1/R2
Rev. 0 | Page 31 of 72
ADT7476A
The fan counter does not count the fan TACH output pulses
directly because the fan speed could be less than 1000 RPM,
and it takes several seconds to accumulate a reasonably large
and accurate count. Instead, the period of the fan revolution is
measured by gating an on-chip 90 kHz oscillator into the input
of a 16-bit counter for N periods of the fan TACH output
(Figure 45), so the accumulated count is actually proportional
to the fan tachometer period and inversely proportional to the
fan speed.
N, the number of pulses counted, is determined by the settings
of TACH pulses per revolution register (0x7B). This register
contains two bits for each fan, allowing one, two (default), three,
or four TACH pulses to be counted.
CLOCK
High Limit: > Comparison Performed
Because the actual fan TACH period is being measured, falling
below a fan TACH limit by 1 sets the appropriate status bit and
can be used to generate an SMBALERT.
Measuring fan TACH has the following caveat: When the
ADT7476A starts up, TACH measurements are locked. In
effect, an internal read of the low byte has been made for each
TACH input. The net result of this is that all TACH readings are
locked until the high byte is read from the corresponding
TACH registers. All TACH-related interrupts are also ignored
until the appropriate high byte is read.
Once the corresponding high byte has been read, TACH
measurements are unlocked and interrupts are processed
as normal.
PWM
TACH
Because the device is essentially measuring the fan TACH period,
the higher the count value, the slower the fan is actually running.
A 16-bit fan tachometer reading of 0xFFFF indicates that either
the fan has stalled or is running very slowly (<100 RPM).
1
Fan TACH Limit Registers
3
4
05742-046
2
The fan TACH limit registers are 16-bit values consisting of
two bytes.
Figure 45. Fan Speed Measurement
Register 0x54, TACH1 Minimum Low Byte = 0xFF default
Fan TachometerReading Registers
The fan tachometer readings are 16-bit values consisting of
a 2-byte read from the ADT7476A.
Register 0x55, TACH1 Minimum High Byte = 0xFF default
Register 0x28, TACH1 Low Byte = 0x00 default
Register 0x57, TACH2 Minimum High Byte = 0xFF default
Register 0x29, TACH1 High Byte = 0x00 default
Register 0x58, TACH3 Minimum Low Byte = 0xFF default
Register 0x2A, TACH2 Low Byte = 0x00 default
Register 0x59, TACH3 Minimum High Byte = 0xFF default
Register 0x2B, TACH2 High Byte = 0x00 default
Register 0x5A, TACH4 Minimum Low Byte = 0xFF default
Register 0x2C, TACH3 Low Byte = 0x00 default
Register 0x5B, TACH4 Minimum High Byte = 0xFF default
Register 0x2D, TACH3 High Byte = 0x00 default
Fan Speed Measurement Rate
Register 0x2E, TACH4 Low Byte = 0x00 default
The fan TACH readings are normally updated once every second.
Register 0x2F, TACH4 High Byte = 0x00 default
When set, the FAST bit (Bit 3) of Configuration Register 3 (0x78)
updates the fan TACH readings every 250 ms.
Register 0x56, TACH2 Minimum Low Byte = 0xFF default
Reading Fan Speed from the ADT7476A
The measurement of fan speeds involves a 2-register read
for each measurement. The low byte should be read first.
This causes the high byte to be frozen until both high and
low byte registers have been read, preventing erroneous
TACH readings. The fan tachometer reading registers report
back the number of 11.11 μs period clocks (90 kHz oscillator)
gated to the fan speed counter from the rising edge of the first
fan TACH pulse to the rising edge of the third fan TACH pulse
(assuming two pulses per revolution are being counted).
DC Bits
If any of the fans are not being driven by a PWM channel but
are powered directly from 5 V or 12 V, their associated dc bit
in Configuration Register 3 should be set. This allows TACH
readings to be taken on a continuous basis for fans connected
directly to a dc source. Once high frequency mode is enabled in
4-wire fans, the dc bits do not need to be set because this is
automatically done internally.
Rev. 0 | Page 32 of 72
ADT7476A
Calculating Fan Speed
Assuming a fan with two pulses per revolution, and with the
ADT7476A programmed to measure two pulses per revolution,
fan speed is calculated by
Fan Speed (RPM) = (90,000 × 60)/Fan TACH Reading
where Fan TACH Reading is the 16-bit fan tachometer reading.
Example:
TACH1 High Byte (0x29) = 0x17
inertia and is quieter on spin-up than fans that are programmed
to spin up for a given time.
Fan Startup Timeout
To prevent the generation of false interrupts as a fan spins up
(because it is below running speed), the ADT7476A includes a
fan startup timeout function. During this time, the ADT7476A
looks for two TACH pulses. If two TACH pulses are not
detected, an interrupt is generated.
Fan startup timeout can be disabled by setting Bit 5 (FSPDIS) of
Configuration Register 1 (0x40).
TACH1 Low Byte (0x28) = 0xFF
PWM1, PWM2, PWM3 Configuration (0x5C, 0x5D, 0x5E)
What is Fan 1 speed in RPM?
[2:0] SPIN, startup timeout for PWM1 = 0x5C, PWM2 = 0x5D,
and PWM3 = 0x5E.
Fan 1 TACH Reading = 0x17FF = 6143 (decimal)
RPM = (f × 60)/Fan 1 TACH Reading
000 = No startup timeout
RPM = (90,000 × 60)/6143
001 = 100 ms
Fan Speed = 879 RPM
010 = 250 ms default
TACH Pulses per Revolution
Different fan models can output either one, two, three, or four
TACH pulses per revolution. Once the number of fan TACH
pulses has been determined, it can be programmed into the
TACH Pulses per Revolution Register (0x7B) for each fan.
Alternatively, this register can be used to determine the number
of pulses per revolution output by a given fan. By plotting fan
speed measurements at 100% speed with different pulses per
revolution settings, the smoothest graph with the lowest
ripple determines the correct pulses per revolution value.
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
Disabling Fan Startup Timeout
[3:2] Fan 2 default = 2 pulses per revolution.
Although fan startup makes fan spin-ups much quieter than
fixed-time spin-ups, the option exists to use fixed spin-up
times. Setting Bit 5 (FSPDIS) to 1 in Configuration Register 1
(0x40) disables the spin-up for two TACH pulses. Instead, the
fan spins up for the fixed time as selected in Register 0x5C to
Register 0x5E.
[5:4] Fan 3 default = 2 pulses per revolution.
PWM Logic State
[7:6] Fan 4 default = 2 pulses per revolution.
The PWM outputs can be programmed high for 100% duty
cycle (noninverted) or low for 100% duty cycle (inverted).
Fan Pulses per Revolution Register
[1:0] Fan 1 default = 2 pulses per revolution.
00 = 1 pulse per revolution.
PWM1 Configuration (0x5C)
01 = 2 pulses per revolution.
[4] INV.
10 = 3 pulses per revolution.
0 = Logic high for 100% PWM duty cycle
11 = 4 pulses per revolution.
1 = Logic low for 100% PWM duty cycle
Fan Spin-Up
PWM2 Configuration (0x5D)
The ADT7476A has a unique fan spin-up function. It spins the
fan at 100% PWM duty cycle until two TACH pulses are detected
on the TACH input. Once two TACH pulses have been detected,
the PWM duty cycle goes to the expected running value, for
example, 33%. Fans have different spin-up characteristics and
take different times to overcome inertia. The advantage of the
ADT7476A is that it runs the fans just fast enough to overcome
[4] INV.
0 = Logic high for 100% PWM duty cycle
1 = Logic low for 100% PWM duty cycle
Rev. 0 | Page 33 of 72
ADT7476A
PWM3 Configuration (0x5E)
PWM Configuration Registers (0x5C to 0x5E)
[4] INV.
[7:5] BHVR.
0 = Logic high for 100% PWM duty cycle
111 = manual mode
1 = Logic low for 100% PWM duty cycle
Once under manual control, each PWM output can be manually
updated by writing to Register 0x30 to Register 0x32 (PWM
current duty cycle registers).
Low Frequency Mode PWM Drive Frequency
The PWM drive frequency can be adjusted for the application.
Register 0x5F to Register 0x61 configure the PWM frequency
for PWM1 to PWM3, respectively.
PWM1, PWM 2, PWM3 Frequency Registers (0x5F to 0x61)
[2:0] FREQ
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers that allow
the PWM duty cycle for each output to be set anywhere from
0% to 100% in steps of 0.39%. The value to be programmed into
the PWMMIN register is given by
000 = 11.0 Hz
Value (decimal) = PWMMIN/0.39
001 = 14.7 Hz
Example 1: For a PWM duty cycle of 50%,
010 = 22.1 Hz
Value (decimal) = 50/0.39 = 128 (decimal)
011 = 29.4 Hz
Value = 128 (decimal) or 0x80 (hex)
100 = 35.3 Hz (default)
Example 2: For a PWM duty cycle of 33%,
101 = 44.1 Hz
110 = 58.8 Hz
Value (decimal) = 33/0.39 = 85 (decimal)
111 = 88.2 Hz
Value = 85 (decimal) or 0x54 (hex)
High Frequency Mode PWM Drive
PWM Current Duty Cycle Registers
Setting Bit 3 of Register 0x5F, Register 0x60, and Register 0x61
enables high frequency mode for Fan1, Fan 2, and Fan 3
respectively.
Register 0x30 PWM1 Current Duty Cycle = 0xFF (100% default)
In high frequency mode, the PWM drive frequency is always
22.5 kHz. When high frequency mode is enabled, the dc bits are
automatically asserted internally and do not need to be changed.
Fan Speed Control
The ADT7476A controls fan speed using automatic and manual
modes:
•
In automatic fan speed control mode, fan speed is
automatically varied with temperature and without CPU
intervention once initial parameters are set up. The
advantage is that if the system hangs, the user is guaranteed
that the system is protected from overheating.
•
In manual fan speed control mode, the ADT7476A allows
the duty cycle of any PWM output to be adjusted manually.
This can be useful if the user wants to change fan speed in
software or adjust PWM duty cycle output for test purposes.
Bits [7:5] of Register 0x5C to Register 0x5E (PWM Configuration) control the behavior of each PWM output.
Register 0x31 PWM2 Current Duty Cycle = 0xFF (100% default)
Register 0x32 PWM3 Current Duty Cycle = 0xFF (100% default)
By reading the PWMx current duty cycle registers, the user can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode.
PROGRAMMING TRANGE
TRANGE defines the distance between TMIN and 100% PWM.
For the ADT7467, ADT7468 and ADT7473, TRANGE is effectively
a slope. For the ADT7475 andADT7476A, TRANGE is no longer a
slope, but defines the temperature region where the PWM
output linearly ramps from PWMMIN to 100% PWM.
PWM = 100%
PWMMIN
TRANGE
PWM = 0%
TMIN
Figure 46. TRANGE
Rev. 0 | Page 34 of 72
05742-047
PWMMAX
ADT7476A
PROGRAMMING THE AUTOMATIC FAN SPEED CONTROL LOOP
To understand the automatic fan speed control loop more
efficiently, it is recommended to use the ADT7476A evaluation
board and software while reading this section.
This section provides the system designer with an understanding
of the automatic fan control loop and provides step-by-step
guidance on effectively evaluating and selecting critical system
parameters. To optimize the system characteristics, the designer
needs to give some thought to system configuration, including
the number of fans, where they are located, and what temperatures are being measured in the particular system.
The mechanical or thermal engineer who is tasked with the
system thermal characterization should also be involved at
the beginning of the system development process.
MANUAL FAN CONTROL OVERVIEW
In unusual circumstances, it can be necessary to manually
control the speed of the fans. Because the ADT7476A has an
SMBus interface, a system can read back all necessary voltage,
fan speed, and temperature information, and use this information
to control the speed of the fans by writing to the PWM current
duty cycle register (0x30, 0x31, and 0x32) of the appropriate
fan. Bits [7:5] of the PWMx configuration registers (0x5C,
0x5D, 0x5E) are used to set fans up for manual control.
THERM OPERATION IN MANUAL MODE
In manual mode, if the temperature increases above the programmed THERM temperature limit, the fans automatically
speed up to maximum PWM or100% PWM, whichever way
the appropriate fan channel is configured.
AUTOMATIC FAN CONTROL OVERVIEW
The ADT7476A can automatically control the speed of fans
based on the measured temperature. This is done independently
of CPU intervention once initial parameters are set up.
The ADT7476A has a local temperature sensor and two remote
temperature channels that can be connected to a CPU on-chip
thermal diode (available on Intel Pentium class and other
CPUs). These three temperature channels can be used as the
basis for automatic fan speed control to drive fans using pulsewidth modulation (PWM).
Automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature.
Reducing fan speed can also decrease system current consumption.
The automatic fan speed control mode is very flexible due to the
number of programmable parameters, including TMIN and
TRANGE. The TMIN and TRANGE values for a temperature channel
and, therefore, for a given fan, are critical, because they define
the thermal characteristics of the system. The thermal validation
of the system is one of the most important steps in the design
process, so these values should be selected carefully.
Figure 47 gives a top-level overview of the automatic fan control
circuitry on the ADT7476A. From a systems-level perspective,
up to three system temperatures can be monitored and used to
control three PWM outputs. The three PWM outputs can be
used to control up to four fans. The ADT7476A allows the
speed of four fans to be monitored. Each temperature channel
has a thermal calibration block, allowing the designer to
individually configure the thermal characteristics of each
temperature channel. For example, designers can decide to run
the CPU fan when CPU temperature increases above 60°C and
a chassis fan when the local temperature increases above 45°C.
At this stage, the designer has not assigned these thermal
calibration settings to a particular fan drive (PWM) channel.
The right side of Figure 47 shows fan-specific controls. The
designer has individual control over parameters such as
minimum PWM duty cycle, fan speed failure thresholds, and
even ramp control of the PWM outputs. Automatic fan control,
then, ultimately allows graceful fan speed changes that are less
perceptible to the system user.
Rev. 0 | Page 35 of 72
ADT7476A
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
REMOTE 1
TEMP
TMIN
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
TMIN
TRANGE
PWM
GENERATOR
THERMAL CALIBRATION
100%
TMIN
TRANGE
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM2
TACH2
PWM
CONFIG
PWM
GENERATOR
REMOTE 2
TEMP
TACH1
TACHOMETER 2
MEASUREMENT
0%
PWM
MIN
PWM1
PWM
CONFIG
MUX
LOCAL
TEMP
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
Figure 47. Automatic Fan Control Block Diagram
Rev. 0 | Page 36 of 72
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM3
TACH3
05742-048
THERMAL CALIBRATION
ADT7476A
STEP 1—HARDWARE CONFIGURATION
During system design, the motherboard sensing and control
capabilities should be addressed early in the design stages.
Decisions about how these capabilities are used should involve the
system thermal/mechanical engineer. Ask the following questions:
How many fans are supported in system, three or four?
This influences the choice of whether to use the
TACH4 pin or to reconfigure it for the THERM function.
3.
Is the CPU fan to be controlled using the ADT7476A, or
will the CPU fan run at full speed 100% of the time?
What ADT7476A functionality is used?
•
PWM2 or SMBALERT?
•
TACH4 fan speed measurement or overtemperature
THERM function?
If run at 100%, this frees up a PWM output, but the system
is louder.
•
2.5 V voltage monitoring or overtemperature THERM
function?
•
12 V voltage monitoring or VID5 input?
4.
Where will the ADT7476A be physically located in the
system?
This influences the assignment of the temperature measurement channels to particular system thermal zones. For
example, locating the ADT7476A close to the VRM
controller circuitry allows the VRM temperature to be
monitored using the local temperature channel.
The ADT7476A offers multifunctional pins that can be
reconfigured to suit different system requirements and
physical layouts. These multifunction pins are software
programmable.
THERMAL CALIBRATION
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 1 =
AMBIENT TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
TRANGE
0%
TACH1
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM2
TACH2
PWM
CONFIG
PWM
GENERATOR
TMIN
PWM1
PWM
CONFIG
PWM
GENERATOR
MUX
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
REMOTE 2 =
CPU TEMP
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
FRONT CHASSIS
PWM3
TACH3
REAR CHASSIS
Figure 48. Hardware Configuration Example
Rev. 0 | Page 37 of 72
05742-049
1.
2.
ADT7476A
Recommended Implementation 1
Configuring the ADT7476A as shown in Figure 49 provides the
system designer with the following features:
•
•
•
5 V measurement input.
•
VRM temperature using local temperature sensor.
Six VID inputs (VID0, VID1, VID2, VID3, VID4, and
VID6) for VRM10 support.
•
CPU temperature measured using the Remote 1
temperature channel.
Two PWM outputs for fan control of up to three fans.
The front and rear chassis fans are connected in parallel.
•
Ambient temperature measured through the Remote 2
temperature channel.
•
If not using VID5, it can be reconfigured as the 12 V
monitoring input.
•
Three TACH fan speed measurement inputs.
•
VCC measured internally through Pin 4.
•
CPU core voltage measurement (VCORE).
•
•
2.5 V measurement input used to monitor CPU current
(connected to VCOMP output of ADP316x VRM controller).
This is used to determine CPU power consumption.
Bidirectional THERM pin allows the monitoring of
PROCHOT output from an Intel P4 processor, for example,
or can be used as an overtemperature THERM output.
•
SMBALERT system interrupt output.
ADT7476A
FRONT
CHASSIS
FAN
TACH2
PWM1
TACH1
CPU FAN
PWM3
REAR
CHASSIS
FAN
5(VRM9)/6(VRM10)
VID[0:4]/VID[0:5]
TACH3
D2+
D2–
THERM
PROCHOT
CPU
D1+
D1–
VCC
SDA
+5VIN
SCL
+12VIN/VID5
SMBALERT
GND
Figure 49. Recommended Implementation 1
Rev. 0 | Page 38 of 72
ICH
05742-050
AMBIENT
TEMPERATURE
ADT7476A
Recommended Implementation 2
Configuring the ADT7476A as shown in Figure 50 provides the
system designer with the following features:
•
5 V measurement input.
•
VRM temperature using local temperature sensor.
Six VID inputs (VID0, VID1, VID2, VID3, VID4, and
VID6) for VRM10 support.
•
CPU temperature measured using the Remote 1
temperature channel.
Three PWM outputs for fan control of up to three fans.
All three fans can be individually controlled.
•
Ambient temperature measured through the Remote 2
temperature channel.
•
If not using VID5, it can be reconfigured as the 12 V
monitoring input.
•
Bidirectional THERM pin allows the monitoring of
PROCHOT output/input from an Intel P4 processor,
for example, or can be used as an overtemperature
THERM output.
•
Three TACH fan speed measurement inputs.
•
VCC measured internally through Pin 4.
•
CPU core voltage measurement (VCORE).
•
2.5 V measurement input used to monitor CPU current
(connected to VCOMP output of ADP316x VRM controller).
This is used to determine CPU power consumption.
FRONT
CHASSIS
FAN
ADT7476A
TACH2
PWM1
PWM2
TACH1
CPU FAN
PWM3
REAR
CHASSIS
FAN
5(VRM9)/6(VRM10)
VID[0:4]/VID[0:5]
TACH3
D2+
D2–
THERM
PROCHOT
AMBIENT
TEMPERATURE
CPU
D1+
D1–
SDA
VCC
SCL
+5VIN
ICH
+12VIN/VID5
GND
Figure 50. Recommended Implementation 2
Rev. 0 | Page 39 of 72
05742-051
•
•
ADT7476A
STEP 2—CONFIGURING THE MUX
After the system hardware configuration is determined, the fans
can be assigned to particular temperature channels. Not only
can fans be assigned to individual channels, but the behavior
of the fans is also configurable. For example, fans can be run under
automatic fan control, manually (under software control), or at
the fastest speed calculated by multiple temperature channels. The
mux is the bridge between temperature measurement channels
and the three PWM outputs.
101 = Fastest speed calculated by local and Remote 2
temperature controls PWMx
110 = Fastest speed calculated by all three temperature
channels controls PWMx
The fastest speed calculated options pertain to controlling
one PWM output based on multiple temperature channels.
The thermal characteristics of the three temperature zones
can be set to drive a single fan. An example would be the fan
turning on when Remote 1 temperature exceeds 60°C or if
the local temperature exceeds 45°C.
Bits [7:5] (BHVR) of Register 0x5C, Register 0x5D, and
Register 0x5E (PWM configuration registers) control the behavior
of the fans connected to the PWM1, PWM2, and PWM3 outputs.
The values selected for these bits determine how the mux connects
a temperature measurement channel to a PWM output.
Other Mux Options
[7:5] (BHVR), Register 0x5C, Register 0x5D, Register 0x5E.
Automatic Fan Control Mux Options
011 = PWMx runs full speed
[7:5] (BHVR), Register 0x5C, Register 0x5D, Register 0x5E.
100 = PWMx disabled (default)
000 = Remote 1 temperature controls PWMx
111 = Manual mode. PWMx is running under software
control. In this mode, PWM current duty cycle registers
(0x30 to 0x32) are writable and control the PWM outputs.
001 = Local temperature controls PWMx
010 = Remote 2 temperature controls PWMx
MUX
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 1 =
AMBIENT TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
TMIN
TRANGE
TACH1
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM2
TACH2
PWM
CONFIG
PWM
GENERATOR
0%
PWM1
PWM
CONFIG
PWM
GENERATOR
MUX
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
REMOTE 2 =
CPU TEMP
FRONT CHASSIS
PWM3
TACH3
REAR CHASSIS
Figure 51. Assigning Temperature Channels to Fan Channels
Rev. 0 | Page 40 of 72
05742-052
THERMAL CALIBRATION
ADT7476A
Mux Configuration Example
Example Mux Settings
This is an example of how to configure the mux in a system
using the ADT7476A to control three fans. The CPU fan sink
is controlled by PWM1, the front chassis fan is controlled by
PWM2, and the rear chassis fan is controlled by PWM3. The
mux is configured for the following fan control behavior:
[7:5] (BHVR), PWM1 Configuration Register (0x5C).
•
101 = Fastest speed calculated by local and Remote 2
temperature controls PWM1
[7:5] (BHVR), PWM2 Configuration Register (0x5D).
000 = Remote 1 temperature controls PWM2
PWM1 (CPU fan sink) is controlled by the fastest speed
calculated by the local (VRM temperature) and Remote 2
(processor) temperature. In this case, the CPU fan sink is
also being used to cool the VRM.
[7:5] (BHVR), PWM3 Configuration Register (0x5E).
•
PWM2 (front chassis fan) is controlled by the Remote 1
temperature (ambient).
These settings configure the mux, as shown in Figure 52.
•
PWM3 (rear chassis fan) is controlled by the Remote 1
temperature (ambient).
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
0%
MUX
100%
PWM
MIN
TACHOMETER 1
MEASUREMENT
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TRANGE
0%
TACH1
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM2
TACH2
PWM
CONFIG
PWM
GENERATOR
TMIN
PWM1
PWM
CONFIG
PWM
GENERATOR
TMIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
FRONT CHASSIS
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 52. Mux Configuration Example
Rev. 0 | Page 41 of 72
05742-053
THERMAL CALIBRATION
000 = Remote 1 temperature controls PWM3
ADT7476A
STEP 3—TMIN SETTINGS FOR THERMAL
CALIBRATION CHANNELS
TMIN Registers
TMIN is the temperature at which the fans start to turn on under
automatic fan control. The speed at which the fan runs at TMIN
is programmed later. The TMIN values chosen are temperature
channel specific, for example, 25°C for ambient channel, 30°C
for VRM temperature, and 40°C for processor temperature.
Register 0x68, Local Temperature TMIN = 0x5A (90°C)
Register 0x67, Remote 1 Temperature TMIN = 0x5A (90°C)
Register 0x69, Remote 2 Temperature TMIN = 0x5A (90°C)
Enhance Acoustics Register 1 (0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when
temperature is below TMIN – THYST.
TMIN is an 8-bit value, either twos complement or Offset 64,
which can be programmed in 1°C increments. A TMIN register
is associated with each temperature measurement channel:
Remote 1, local, and Remote 2 temperature. Once the TMIN
value is exceeded, the fan turns on and runs at the minimum
PWM duty cycle. The fan turns off once the temperature has
dropped below TMIN − THYST.
Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle
below TMIN – THYST.
Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when
temperature is below TMIN – THYST.
Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle
below TMIN – THYST.
To overcome fan inertia, the fan is spun up until two valid TACH
rising edges are counted. See the Fan Startup Timeout section
for more details. In some cases, primarily for psycho-acoustic
reasons, it is desirable that the fan never switch off below TMIN.
Setting Bits [7:5] of Enhance Acoustics Register 1 (0x62) keeps
the fans running at the PWM minimum duty cycle if the
temperature should fall below TMIN.
Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when
temperature is below TMIN – THYST.
Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle
below TMIN – THYST.
PWM DUTYCYCLE
100%
0%
TMIN
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
TRANGE
0%
TACH1
CPU FAN SINK
PWM
CONFIG
PWM
GENERATOR
0%
100%
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM2
TACH2
PWM
CONFIG
PWM
GENERATOR
TMIN
PWM1
0%
MUX
TMIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
FRONT CHASSIS
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 53. Understanding the TMIN Parameter
Rev. 0 | Page 42 of 72
05742-054
THERMAL CALIBRATION
ADT7476A
STEP 4—PWMMIN FOR EACH PWM (FAN) OUTPUT
PWMMIN is the minimum PWM duty cycle at which each fan
in the system runs. It is also the start speed for each fan under
automatic fan control once the temperature rises above TMIN.
For maximum system acoustic benefit, PWMMIN should be as
low as possible. Depending on the fan used, the PWMMIN setting is usually in the 20% to 33% duty cycle range. This value
can be found through fan validation.
The value to be programmed into the PWMMIN register is
given by
Value (decimal) = PWMMIN/0.39
Example 1: For a minimum PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Example 2: For a minimum PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
PWM DUTY CYCLE
100%
Value = 85 (decimal)l or 54 (hex)
PWM Minimum Duty Cycle Registers
Register 0x64, PWM1 Minimum Duty Cycle = 0x80 (50% default)
Register 0x65, PWM2 Minimum Duty Cycle = 0x80 (50% default)
PWMMIN
Register 0x66, PWM3 Minimum Duty Cycle = 0x80 (50% default)
TMIN
TEMPERATURE
05742-055
0%
Note on Fan Speed and PWM Duty Cycle
Figure 54. PWMMIN Determines Minimum PWM Duty Cycle
More than one PWM output can be controlled from a single
temperature measurement channel. For example, Remote 1
temperature can control PWM1 and PWM2 outputs. If two
different fans are used on PWM1 and PWM2, the fan
characteristics can be set up differently. As a result, Fan 1 driven
by PWM1 can have a different PWMMIN value than that of Fan 2
connected to PWM2. Figure 55 illustrates this as PWM1MIN
(front fan), which is turned on at a minimum duty cycle of 20%,
while PWM2MIN (rear fan) turns on at a minimum of 40% duty
cycle. Note: Both fans turn on at exactly the same temperature,
defined by TMIN.
PWM DUTY CYCLE
100%
M2
PW
PW
PWM2MIN
M1
The PWM duty cycle does not directly correlate to fan speed in
RPM. Running a fan at 33% PWM duty cycle does not equate to
running the fan at 33% speed. Driving a fan at 33% PWM duty
cycle actually runs the fan at closer to 50% of its full speed. This
is because fan speed in %RPM generally relates to the square
root of PWM duty cycle. Given a PWM square wave as the
drive signal, fan speed in RPM approximates to
% Fan Speed = PWM Duty Cycle × 10
STEP 5—PWMMAX FOR PWM (FAN) OUTPUTS
PWMMAX is the maximum duty cycle that each fan in the system
runs at under the automatic fan speed control loop. For maximum system acoustic benefit, PWMMAX should be as low as
possible but should be capable of maintaining the processor
temperature limit at an acceptable level. If the THERM
temperature limit is exceeded, the fans are still boosted to
100% for fail-safe cooling.
There is a PWMMAX limit for each fan channel. The default
value of this register is 0xFF and has no effect unless it is
programmed.
PWM1MIN
100%
Figure 55. Operating Two Different Fans from a Single Temperature Channel
Programming the PWM Minimum Duty Cycle Registers
The PWM minimum duty cycle registers are 8-bit registers that
allow the minimum PWM duty cycle for each output to be
configured anywhere from 0% to 100%. This allows the
minimum PWM duty cycle to be set in steps of 0.39%.
PWMMAX
PWMMIN
0%
TMIN
TEMPERATURE
Figure 56. PWMMAX Determines Maximum PWM Duty Cycle
Below the THERM Temperature Limit
Rev. 0 | Page 43 of 72
05742-057
TEMPERATURE
PWM DUTY CYCLE
TMIN
05742-056
0%
ADT7476A
Programming the PWM Maximum Duty Cycle Registers
The PWM maximum duty cycle registers are 8-bit registers that
allow the maximum PWM duty cycle for each output to be
configured anywhere from 0% to 100%. This allows the
maximum PWM duty cycle to be set in steps of 0.39%.
The TRANGE is determined by the following procedure:
1.
Determine the maximum operating temperature for that
channel (for example, 70°C).
2.
Determine experimentally the fan speed (PWM duty cycle
value) that does not exceed the temperature at the worstcase operating points. For example, 70°C is reached when
the fans are running at 50% PWM duty cycle.
3.
Determine the slope of the required control loop to meet
these requirements.
4.
Using the ADT7476A evaluation software, you can
graphically program and visualize this functionality.
The value to be programmed into the PWM maximum duty
cycle register is given by
Value (decimal) = PWMMAX/0.39
Example 1: For a maximum PWM duty cycle of 50%,
Value (decimal) – 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Example 2: For a minimum PWM duty cycle of 75%,
As PWMMIN is changed, the automatic fan control slope changes.
Value (decimal) = 75/0.39 = 85 (decimal)
100%
PWM DUTY CYCLE
Value = 192 (decimal) or C0 (hex)
PWM Maximum Duty Cycle Registers
Register 0x38, PWM1 Maximum Duty Cycle = 0xFF
(100% default)
Register 0x39, PWM2 Maximum Duty Cycle = 0xFF
(100% default)
50%
33%
Register 0x3A, PWM3 Maximum Duty Cycle = 0xFF
(100% default)
30°C
TMIN
STEP 6—TRANGE FOR TEMPERATURE CHANNELS
Figure 58. Adjusting PWMMIN Changes the Automatic Fan Control Slope.
As TRANGE is changed, the slope changes. As TRANGE gets smaller,
the fans reach 100% speed with a smaller temperature change.
100%
PWM DUTY CYCLE
TRANGE is the range of temperature over which automatic fan
control occurs once the programmed TMIN temperature has
been exceeded. TRANGE is the temperature range between PWMMIN
and 100% PWM where the fan speed changes linearly. Otherwise
stated, it is the line drawn between the TMIN/PWMMIN and the
(TMIN + TRANGE)/PWM100% intersection points.
TRANGE
100%
10%
0%
0%
TMIN
TEMPERATURE
30°C
40°C
45°C
54°C
TMIN
Figure 59. Increasing TRANGE Changes the AFC slope
Figure 57. TRANGE Parameter Affects Cooling Slope
Rev. 0 | Page 44 of 72
05742-060
TMIN–HYST
PWMMIN
05742-058
PWM DUTY CYCLE
05742-059
0%
ADT7476A
Decreasing the speed the PWM output changes by programming
the smoothing on the appropriate temperature channels
(Register 0x62 and Register 0x63) changes how fast the fan
speed increases/decreases in the event of a temperature spike.
The PWM duty cycle increases slowly until the PWM duty cycle
reaches the appropriate duty cycle as defined by the AFC curve.
MAX
PWM
Figure 61 shows PWM duty cycle vs. temperature for each
TRANGE setting. The lower graph shows how each TRANGE setting
affects fan speed vs. temperature. As can be seen from the
graph, the effect on fan speed is nonlinear.
10%
TRANGE
TMIN–HYST
05742-061
0%
100
Figure 60. Changing PWM Max Does Not Change the AFC Slope
2°C
2.5°C
90
Selecting TRANGE
Table 17. Selecting a TRANGE Value
1
TRANGE (°C)
2
2.5
3.33
4
5
6.67
8
10
13.33
16
20
26.67
32 (default)
40
53.33
80
PWM DUTY CYCLE (%)
The TRANGE value can be selected for each temperature channel:
Remote 1, local, and Remote 2 temperature. Bits [7:4] (TRANGE)
of Register 0x5F to Register 0x61 define the TRANGE value for
each temperature channel.
4°C
5°C
70
6.67°C
60
8°C
10°C
50
13.3°C
16°C
40
20°C
30
26.6°C
32°C
20
40°C
10
0
0
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
(A)
100
2°C
2.5°C
90
3.33°C
80
FAN SPEED (% OF MAX)
Bits [7:4]1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
3.33°C
80
4°C
5°C
70
6.67°C
8°C
60
10°C
50
13.3°C
16°C
40
20°C
30
26.6°C
32°C
20
40°C
10
0
0
Register 0x5F configures Remote 1 TRANGE; Register 0x60 configures local
TRANGE; Register 0x61 configures Remote 2 TRANGE.
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
05742-062
PWM DUTY CYCLE
100%
(B)
Actual Changes in PWM Output (Advanced Acoustics
Settings)
Figure 61. TRANGE vs. Actual Fan Speed (Not PWM Drive) Profile
While the automatic fan control algorithm describes the general
response of the PWM output, it is also necessary to note that the
enhance acoustics registers (0x62 and 0x63) can be used to
set/clamp the maximum rate of change of PWM output for a
given temperature zone. This means that if TRANGE is programmed
with an AFC slope that is quite steep, a relatively small change
in temperature could cause a large change in PWM output and
possibly an audible change in fan speed, which can be noticeable/
bothersome to end users.
The graphs in Figure 61 assume that the fan starts from 0% PWM
duty cycle. Clearly, the minimum PWM duty cycle, PWMMIN,
needs to be factored in to see how the loop actually performs in
the system. Figure 62 shows how TRANGE is affected when the
PWMMIN value is set to 20%. It can be seen that the fan actually
runs at about 45% fan speed when the temperature exceeds TMIN.
Rev. 0 | Page 45 of 72
ADT7476A
90
3.33°C
4°C
80
80
5°C
70
PWM DUTY CYCLE (%)
6.67°C
8°C
60
10°C
50
13.3°C
16°C
40
20°C
30
26.6°C
32°C
20
70
CPU TEMPERATURE
60
50
AMBIENT TEMPERATURE
40
30
20
40°C
10
10
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
0
0
10
20
(A)
100
50
60
70
80
90
100
80
90
100
VRM TEMPERATURE
2.5°C
90
3.33°C
80
80
FAN SPEED (% MAX RPM)
4°C
5°C
70
6.67°C
60
8°C
10°C
50
13.3°C
40
16°C
20°C
30
26.6°C
32°C
20
70
CPU TEMPERATURE
60
AMBIENT TEMPERATURE
50
40
30
20
40°C
10
10
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
05742-063
FAN SPEED (% OF MAX)
40
100
2°C
90
0
0
30
TEMPERATURE ABOVE TMIN
0
0
10
20
30
40
50
60
70
TEMPERATURE ABOVE TMIN
(B)
Figure 62. TRANGE and % Fan Speed Slopes with PWMMIN = 20%
Figure 63. TRANGE and % Fan Speed Slopes for VRM, Ambient, and
CPU Temperature Channels
Example: Determining TRANGE for Each Temperature
Channel
STEP 7—TTHERM FOR TEMPERATURE CHANNELS
The following example shows how the different TMIN and TRANGE
settings can be applied to three different thermal zones. In this
example, the following TRANGE values apply:
TTHERM is the absolute maximum temperature allowed on a
TRANGE = 80°C for ambient temperature
TRANGE = 53.33°C for CPU temperature
TRANGE = 40°C for VRM temperature
05742-064
PWM DUTY CYCLE (%)
VRM TEMPERATURE
2.5°C
90
0
0
100
2°C
100
temperature channel. Above this temperature, a component
such as the CPU or VRM can operate beyond its safe operating
limit. When the temperature measured exceeds TTHERM, all fans
are driven at 100% PWM duty cycle (full speed) to provide
critical system cooling.
This example uses the mux configuration described in Step 2—
Configuring the Mux with the ADT7476A connected as shown
in Figure 52. Both CPU temperature and VRM temperature
drive the CPU fan connected to PWM1. Ambient temperature
drives the front chassis fan and rear chassis fan connected to
PWM2 and PWM3. The front chassis fan is configured to
run at PWMMIN = 20%. The rear chassis fan is configured to
run at PWMMIN = 30%. The CPU fan is configured to run at
PWMMIN = 10%.
Note: The control range for 4-wire fans is much wider than that
of 3-wire fans. In many cases, 4-wire fans can start with a PWM
drive of as little as 20% or less. In extreme cases, some 3-wire
fans cannot run unless a PWM drive of 60% or more is applied.
The fans remain running at 100% until the temperature drops
below TTHERM minus hysteresis, where hysteresis is the number
programmed into the hysteresis registers (0x6D and 0x6E). The
default hysteresis value is 4°C.
The TTHERM limit should be considered the maximum worst-case
operating temperature of the system. Because exceeding any
TTHERM limit runs all fans at 100%, it has very negative acoustic
effects. Ultimately, this limit should be set up as a fail-safe, and
users should ensure that it is not exceeded under normal system
operating conditions.
Rev. 0 | Page 46 of 72
ADT7476A
Note: TTHERM limits are nonmaskable and affect the fan speed no
Hysteresis Registers
matter how automatic fan control settings are configured. This
allows some flexibility, because a TRANGE value can be selected
based on its slope, while a hard limit (such as 70°C), can be
programmed as TMAX (the temperature at which the fan reaches
full speed) by setting TTHERM to that limit (for example, 70°C).
Register 0x6D, Remote 1, Local Temperature Hysteresis
[7:4], Remote 1 temperature hysteresis (4°C default).
[3:0], Local temperature hysteresis (4°C default).
Register 0x6E, Remote 2 Temperature Hysteresis
THERM Limit Registers
[7:4], Remote 2 temperature hysteresis (4°C default).
Register 0x6A, Remote 1 THERM Limit = 0x64 (100°C default)
Because each hysteresis setting is four bits, hysteresis values
are programmable from 1°C to 15°C. It is not recommended to
program hysteresis values to 0°C, because this disables
hysteresis. In effect, this causes the fans to cycle (during a
THERM event) between normal speed and 100% speed, or,
while operating close to TMIN, between normal speed and off,
creating unsettling acoustic noise.
Register 0x6B, Local THERM Limit = 0x64 (100°C default)
Register 0x6C, Remote 2 THERM Limit = 0x64 (100°C default)
THERM Hysteresis
THERM hysteresis on a particular channel is configured via the
hysteresis settings (Register 0x6D and Register 0x6E). For
example, setting hysteresis on the Remote 1 channel also sets
the hysteresis on Remote 1 THERM.
TRANGE
PWM DUTYCYCLE
100%
0%
TTHERM
THERMAL CALIBRATION
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
TRANGE
0%
TACH1
CPU FAN SINK
PWM
CONFIG
PWM
GENERATOR
0%
100%
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM2
TACH2
PWM
CONFIG
PWM
GENERATOR
TMIN
PWM1
0%
MUX
TMIN
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
FRONT CHASSIS
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 64. How TTHERM Relates to Automatic Fan Control
Rev. 0 | Page 47 of 72
05742-065
TMIN
ADT7476A
STEP 8—THYST FOR TEMPERATURE CHANNELS
The THYST setting applies not only to the temperature hysteresis
for fan on/off, but the same setting is used for the TTHERM hysteresis
THYST is the amount of extra cooling a fan provides after the
temperature measured has dropped back below TMIN before
the fan turns off. The premise for temperature hysteresis (THYST)
is that without it, the fan would merely chatter, or cycle on
and off regularly, whenever the temperature hovers around
the TMIN setting.
value, described in Step 6—TRANGE for Temperature Channels.
Therefore, programming Register 0x6D and Register 0x6E sets
the hysteresis for both fan on/off and the THERM function.
In some applications, it is required that fans not turn off below TMIN
but remain running at PWMMIN. Bits [7:5] of Enhance Acoustics
Register 1 (0x62) allow the fans to be turned off or to be kept
spinning below TMIN. If the fans are always on, the THYST value
has no effect on the fan when the temperature drops below TMIN.
The THYST value chosen determines the amount of time needed
for the system to cool down or heat up as the fan is turning on
and off. Values of hysteresis are programmable in the range 1°C
to 15°C. Larger values of THYST prevent the fans from chattering
on and off. The THYST default value is set at 4°C.
THERM Hysteresis
Any hysteresis programmed via Register 0x6D and Register 0x6E
also applies hysteresis on the appropriate THERM channel.
TRANGE
PWM DUTYCYCLE
100%
0%
TTHERM
THERMAL CALIBRATION
PWM
MIN
100%
PWM
CONFIG
PWM
GENERATOR
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
TACHOMETER 1
MEASUREMENT
TRANGE
0%
TACH1
CPU FAN SINK
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 2
MEASUREMENT
PWM2
TACH2
PWM
CONFIG
PWM
GENERATOR
TMIN
PWM1
PWM
CONFIG
PWM
GENERATOR
MUX
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
FRONT CHASSIS
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 65. The THYST Value Applies to Fan On/Off Hysteresis and THERM Hysteresis
Rev. 0 | Page 48 of 72
05742-066
TMIN
ADT7476A
100 = 4.7 sec
101 = 3.1 sec
110 = 1.6 sec
111 = 0.8 sec
Enhance Acoustics Register 1 (0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle
below TMIN − THYST.
Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle
below TMIN − THYST.
Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle
below TMIN − THYST.
Configuration Register 6 (0x10)
[0] SLOW = 1, slows the ramp rate for PWM changes associated
with the Remote 1 temperature channel by a factor of 4.
[1] SLOW = 1, slows the ramp rate for PWM changes associated
with the local temperature channel by a factor of 4.
[2] SLOW = 1, slows the ramp rate for PWM changes associated
with the Remote 2 temperature channel by a factor of 4.
[7] ExtraSlow = 1, slows the ramp rate for all fans by a factor
of 39.2%.
The following sections list the ramp-up times when the
SLOW bit is set for each temperature monitoring channel.
[6:4] ACOU2 selects the ramp rate for PWM outputs associated
with the Remote Temperature 2 input.
000 = 37.5 sec
001 = 18.8 sec
010 = 12.5 sec
011 = 7.5 sec
100 = 4.7 sec
101 = 3.1 sec
110 = 1.6 sec
111 = 0.8 sec
When Bit 7 of Configuration Register 6 (0x10) = 1, the above
ramp rates change to the values below.
000 = 52.2 sec
001 = 26.1 sec
010 = 17.4 sec
011 = 10.4 sec
100 = 6.5 sec
101 = 4.4 sec
110 = 2.2 sec
111 = 1.1 sec
Setting the appropriate slow bit [2:0] of Configuration
Register 6 (0x10) slows the ramp rate further by a factor of 4.
FAN PRESENCE DETECT
Enhance Acoustics Register 1 (0x62)
[2:0] ACOU selects the ramp rate for PWM outputs associated
with the Remote Temperature 1 input.
000 = 37.5 sec
001 = 18.8 sec
010 = 12.5 sec
011 = 7.5 sec
100 = 4.7 sec
101 = 3.1 sec
110 = 1.6 sec
111 = 0.8 sec
This feature is used to determine if a 4-wire fan is directly
connected to a PWM output. This feature does not work for
3-wire fans. To detect whether a 4-wire fan is connected directly
to a PWM output, the following must be performed in this order:
1.
Drive the appropriate PWM outputs to 100% duty cycle.
2.
Set Bit 0 of Configuration Register 2 (0x73).
3.
Wait 5 ms.
4.
Program fans to run at a different speed if necessary.
5.
Read the state of Bits [3:1] of Configuration Register 2
(0x73). The state of these bits reflects whether a 4-wire fan
is directly connected to the PWM output.
Enhance Acoustics Register 2 (0x63)
[2:0] ACOU3 selects the ramp rate for PWM outputs associated
with the local temperature channel.
000 = 37.5 sec
001 = 18.8 sec
010 = 12.5 sec
011 = 7.5 sec
As the detection time only takes 5 ms, programming the
PWM outputs to 100% and then back to its normal speed is
not noticeable in most cases.
Rev. 0 | Page 49 of 72
ADT7476A
How Fan Presence Detect Works
XNOR TREE TEST MODE
4-wire fans typically have an internal pull up to 4.75 V ±10%,
which typically sources 5 mA. While the detection cycle is on,
an internal current sink is turned on, which sinks current from
the fan’s internal pull-up. By driving some of the current from
the fan’s internal pull-up (~100 μA) the logic buffer switches to
a defined logic state. If this state is high, a fan is present; if the
state is low, no fan is present.
The ADT7476A includes an XNOR tree test mode. This mode
is useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XNOR tree, it is
possible to detect opens, or shorts, on the system board.
Note: The PWM input voltage should be clamped to 3.3 V. This
ensures the PWM output is not pulled to a voltage higher than
the maximum allowable voltage on that pin (5.5 V).
Figure 66 shows the signals that are exercised in the XNOR tree
test mode.
The XNOR tree test is invoked by setting Bit 0 (XEN) of the
XNOR Tree Test Enable Register (0x6F).
VID0
VID1
FAN SYNC
When two ADT7476As are used in a system, it is possible to
synchronize them so that one PWM channel from each device
can be effectively OR’ed together to create a PWM output that
reflects the maximum speed of the two OR’ed PWMs. This
OR’ed PWM can in turn be used to drive a chassis fan. See
the Analog Devices website (www.analog.com) for information
on the Fan SYNC function.
VID2
VID3
VID4
TACH1
STANDBY MODE
TACH2
The ADT7476A has been specifically designed to respond to
the STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states.
When monitoring THERM, the THERM timer should be
disabled during these states.
TACH3
TACH4
When the VCCP voltage drops below the VCCP low limit, the
following occurs:
PWM3
1.
Status Bit 1 (VCCP) in Interrupt Status Register 1 is set.
2.
SMBALERT is generated, if enabled.
3.
THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
PWM1/XTO
05742-067
PWM2
Figure 66. XNOR Tree Test
POWER-ON DEFAULT
Once the core voltage, VCCP, goes above the VCCP low limit,
everything is re-enabled and the system resumes normal operation.
When the ADT7476A is powered up, monitoring is off by
default and the PWM outputs go to 100%. All necessary
registers then need to be configured via the SMBus for the
appropriate functions to operate.
Rev. 0 | Page 50 of 72
ADT7476A
REGISTER TABLES
Table 18. ADT7476A Registers
Address
0x10
R/W
R/W
Description
Configuration
Register 6
Bit 7
ExtraSlow
Bit 6
VCCP
Low
Bit 5
MasterEn
Bit 4
SlaveEn
0x11
R/W
RES
RES
RES
0x20
R
9
8
0x21
R
9
0x22
R
0x23
R
0x24
R
0x25
R
0x26
R
0x27
R
0x28
R
0x29
R
0x2A
R
0x2B
R
0x2C
R
0x2D
R
0x2E
R
0x2F
R
0x30
R/W
0x31
R/W
0x32
R/W
0x38
R/W
0x39
R/W
0x3A
R/W
0x3D
R
0x3E
R
0x3F
R
Configuration
Register 7
2.5 V
Measurement
VCCP
Measurement
VCC
Measurement
5V
Measurement
12 V
Measurement
Remote 1
Temperature
Local
Temperature
Remote 2
Temperature
TACH1 Low
Byte
TACH1 High
Byte
TACH2 Low
Byte
TACH2 High
Byte
TACH3 Low
Byte
TACH3 High
Byte
TACH4 Low
Byte
TACH4 High
Byte
PWM1 Current
Duty Cycle
PWM2 Current
Duty Cycle
PWM3 Current
Duty Cycle
PWM1 Max
Duty Cycle
PWM2 Max
Duty Cycle
PWM3 Max
Duty Cycle
Device ID
Register
Company ID
Number
Revision ID
0x40
R/W
0x41
R
0x42
R
0x43
0x44
0x45
0x46
0x47
0x48
R/W
R/W
R/W
R/W
R/W
R/W
Configuration
Register 1
Interrupt Status
Register 1
Interrupt Status
Register 2
VID/GPIO
2.5 V Low Limit
2.5 V High Limit
VCCP Low Limit
VCCP High Limit
VCC Low Limit
Bit 2
SlowFan
Remote 1
Bit 1
SlowFan
Local
Bit 0
SlowFan
Remote 1
Default
0x00
Lockable?
Yes
RES
Bit 3
THERM in
Manual
RES
RES
RES
DisTHERMHys
0x00
Yes
7
6
5
4
3
2
0x00
8
7
6
5
4
3
2
0x00
9
8
7
6
5
4
3
2
0x00
9
8
7
6
5
4
3
2
0x00
9
8
7
6
5
4
3
2
0x00
9
8
7
6
5
4
3
2
0x80
9
8
7
6
5
4
3
2
0x80
9
8
7
6
5
4
3
2
0x80
7
6
5
4
3
2
1
0
0x00
15
14
13
12
11
10
9
8
0x00
7
6
5
4
3
2
1
0
0x00
15
14
13
12
11
10
9
8
0x00
7
6
5
4
3
2
1
0
0x00
15
14
13
12
11
10
9
8
0x00
7
6
5
4
3
2
1
0
0x00
15
14
13
12
11
10
9
8
0x00
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
Yes
7
6
5
4
3
2
1
0
0xFF
Yes
7
6
5
4
3
2
1
0
0xFF
Yes
7
6
5
4
3
2
1
0
0x76
7
6
5
4
3
2
1
0
0x41
7
6
5
4
3
2
1
0
0x6B
RES
TODIS
FSPDIS
Vx1
FSPD
RDY
LOCK
STRT
0x04
OOL
R2T
LT
R1T
5V
VCC
VCCP
2.5 V/THERM
0x00
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
12 V/VC
0x00
VIDSEL
7
7
7
7
7
THLD
6
6
6
6
6
VID 5
5
5
5
5
5
VID4/GPIO4
4
4
4
4
4
VID3/GPIO3
3
3
3
3
3
VID2/GPIO2
2
2
2
2
2
VID1/GPIO1
1
1
1
1
1
VID 0/GPIO 0
0
0
0
0
0
0x1F
0x00
0xFF
0x00
0xFF
0x00
Rev. 0 | Page 51 of 72
Yes
ADT7476A
Address
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x4F
R/W
0x50
R/W
0x51
R/W
0x52
R/W
0x53
R/W
0x54
R/W
0x55
R/W
0x56
R/W
0x57
R/W
0x58
R/W
0x59
R/W
0x5A
R/W
0x5B
R/W
0x5C
R/W
0x5D
R/W
0x5E
R/W
0x5F
R/W
0x60
R/W
0x61
R/W
0x62
R/W
0x63
R/W
0x64
R/W
0x65
R/W
0x66
R/W
0x67
R/W
Description
VCC High Limit
5 V Low Limit
5 V High Limit
12 V Low Limit
12 V High Limit
Remote 1 Temp
Low Limit
Remote 1 Temp
High Limit
Local Temp
Low Limit
Local Temp
High Limit
Remote 2 Temp
Low Limit
Remote 2 Temp
High Limit
TACH1
Minimum Low
Byte
TACH1
Minimum High
Byte
TACH2
Minimum Low
Byte
TACH2
Minimum High
Byte
TACH3
Minimum Low
Byte
TACH3
Minimum High
Byte
TACH4
Minimum Low
Byte
TACH4
Minimum High
Byte
PWM1
Configuration
PWM2
Configuration
PWM3
Configuration
Remote 1
TRANGE/PWM1
Frequency
Local
TRANGE/PWM2
Frequency
Remote 2
TRANGE/PWM3
Frequency
Enhance
Acoustics
Register 1
Enhance
Acoustics
Register 2
PWM1 Min
Duty Cycle
PWM2 Min
Duty Cycle
PWM3 Min
Duty Cycle
Remote 1
Temp TMIN
Bit 7
7
7
7
7
7
7
Bit 6
6
6
6
6
6
6
Bit 5
5
5
5
5
5
5
Bit 4
4
4
4
4
4
4
Bit 3
3
3
3
3
3
3
Bit 2
2
2
2
2
2
2
Bit 1
1
1
1
1
1
1
Bit 0
0
0
0
0
0
0
Default
0xFF
0x00
0xFF
0x00
0xFF
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
BHVR
BHVR
BHVR
INV
RES
SPIN
SPIN
SPIN
0x62
Yes
BHVR
BHVR
BHVR
INV
RES
SPIN
SPIN
SPIN
0x62
Yes
BHVR
BHVR
BHVR
INV
RES
SPIN
SPIN
SPIN
0x62
Yes
RANGE
RANGE
RANGE
RANGE
HF/LF
FREQ
FREQ
FREQ
0XC4
Yes
RANGE
RANGE
RANGE
RANGE
HF/LF
FREQ
FREQ
FREQ
0XC4
Yes
RANGE
RANGE
RANGE
RANGE
HF/LF
FREQ
FREQ
FREQ
0XC4
Yes
MIN3
MIN2
MIN1
SYNC
EN1
ACOU
ACOU
ACOU
0X00
Yes
EN2
ACOU2
ACOU2
ACOU2
EN3
ACOU3
ACOU3
ACOU3
0X00
Yes
7
6
5
4
3
2
1
0
0X80
Yes
7
6
5
4
3
2
1
0
0X80
Yes
7
6
5
4
3
2
1
0
0X80
Yes
7
6
5
4
3
2
1
0
0X5A
Yes
Rev. 0 | Page 52 of 72
Lockable?
ADT7476A
Address
0x68
R/W
R/W
Description
Local Temp
TMIN
Remote 2
Temp TMIN
Remote 1
THERM Limit
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0X5A
Lockable?
Yes
0x69
R/W
7
6
5
4
3
2
1
0
0X5A
Yes
0x6A
R/W
7
6
5
4
3
2
1
0
0X64
Yes
0x6B
R/W
Local THERM
Limit
Remote 2
THERM Limit
7
6
5
4
3
2
1
0
0X64
Yes
0x6C
R/W
7
6
5
4
3
2
1
0
0X64
Yes
0x6D
R/W
Remote 1 and
Local Temp/
TMIN Hysteresis
Remote 2
Temp/TMIN
Hysteresis
XNOR Tree Test
Enable
Remote 1
Temperature
Offset
Local
Temperature
Offset
Remote 2
Temperature
Offset
Configuration
Register 2
Interrupt Mask
Register 1
Interrupt Mask
Register 2
Extended
Resolution
Register 1
Extended
Resolution
Register 2
Configuration
Register 3
HYSR1
HYSR1
HYSR1
HYSR1
HYSL
HYSL
HYSL
HYSL
0X44
Yes
0x6E
R/W
HYSR2
HYSR2
HYSR2
HYRS
RES
RES
RES
RES
0X40
Yes
0x6F
R/W
RES
RES
RES
RES
RES
RES
RES
XEN
0X00
Yes
0x70
R/W
7
6
5
4
3
2
1
0
0X00
Yes
0x71
R/W
7
6
5
4
3
2
1
0
0X00
Yes
0x72
R/W
7
6
5
4
3
2
1
0
0X00
Yes
0x73
R/W
RES
CONV
ATTN
AVG
Fan3Detect
Fan2Detect
Fan1Detect
FanPresenceDT
0X00
Yes
0x74
R/W
OOL
R2T
LT
R1T
5V
VCC
VCCP
2.5 V/THERM
0X00
0x75
R/W
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
12 V/VC
0X00
0x76
R/W
5V
5V
VCC
VCC
VCCP
VCCP
2.5 V
2.5 V
0X00
0x77
R/W
TDM2
TDM2
LTMP
LTMP
TDM1
TDM1
12 V
12 V
0X00
0x78
R/W
DC4
DC3
DC2
DC1
FAST
BOOST
ALERT
0x00
THERM Timer
Status
THERM Timer
Limit
TACH Pulses
per Revolution
Configuration
Register 5
TMR
TMR
TMR
TMR
TMR
TMR
THERM
/2.5V
TMR
0x79
R
ASRT/TMRO
0x00
0x7A
R/W
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
0x00
0x7B
R/W
FAN4
FAN4
FAN3
FAN3
FAN2
FAN2
FAN1
FAN1
0x55
0x7C
R/W
R2 THERM
(O/P Only)
GPIO6P
GPIO6D
TempOffset
2sC
0x01
Yes
Configuration
Register 4
BpAtt
12 V
R1
THERM
(O/P
Only)
BpAtt
VCCP
VID/ GPIO
R/W
Local
THERM
(O/P
Only)
BpAtt
5V
0x7D
BpAtt 2.5 V
MaxSpeed
on THERM
PIN14FUNC
PIN14FUNC
0x00
Yes
R
R
Test 1
Test 2
THERM
Disable
Do not write to these registers
Do not write to these registers
0x7E
0x7F
0x00
0x00
Yes
Yes
Rev. 0 | Page 53 of 72
Yes
ADT7476A
Table 19. Register 0x10—Configuration Register 6 (Power-On Default = 0x00) 1, 2
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
Mnemonic
SlowFan
Remote 1
SlowFan
Local
SlowFan
Remote 2
THERM in
Manual
SlaveEn
MasterEn
VCCPLow
R/W
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
When this bit is set, Fan 1 smoothing times are multiplied ×4 for Remote 1 temperature channel
(as defined in Register 0x62).
When this bit is set, Fan 2 smoothing times are multiplied ×4 for local temperature channel (as defined
in Register 0x63).
When this bit is set, Fan 3 smoothing times are multiplied ×4 for Remote 2 temperature channel
(as defined in Register 0x63).
When this bit is set, THERM is enabled in manual mode1.
Setting this bit configures the ADT7476A as a slave for use in fan sync mode.
Setting this bit configures the ADT7476A as a master for use in fan sync mode.
VCCPLow = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP) drops below
its VCCP low limit value (Register 0x46), the following occurs:
• Status Bit 1 in Interrupt Status Register 1 is set.
• SMBALERT is generated, if enabled.
• PROCHOT monitoring is disabled.
• Everything is re-enabled once VCCP increases above the VCCP low limit.
When VCCP increases above the low limit:
• PROCHOT monitoring is enabled.
[7]
1
2
ExtraSlow
Read/Write
• Fans return to their programmed state after a spin-up cycle.
When this bit is set, all fan smoothing times are increased by a further 39.2%
A THERM event always overrides any fan setting (even when fans are disabled).
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 20. Register 0x11—Configuration Register 7 (Power-On Default = 0x00) 1
Bit
[0]
[7:1]
1
Mnemonic
DisTHERMHys
Reserved
R/W
Read/Write
N/A
Description
Setting this bit to 1 disables THERM hysteresis.
Reserved. Do not write to these bits.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 21. Voltage Reading Registers (Power-On Default = 0x00)1
Register Address
0x20
0x21
0x22
0x23
0x24
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Description
Reflects the voltage measurement at the 2.5 V input on Pin 22 (8 MSBs of reading).
Reflects the voltage measurement2 at the VCCP input on Pin 23 (8 MSBs of reading).
Reflects the voltage measurement3 at the VCC input on Pin 4 (8 MSBs of reading).
Reflects the voltage measurement at the 5 V input on Pin 20 (8 MSBs of reading).
Reflects the voltage measurement at the 12 V input on Pin 21 (8 MSBs of reading).
1
If the extended resolution bits of these readings are also being read, the extended resolution registers (0x76, 0x77) must be read first. Once the extended resolution
registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.
If VCCPLow (Bit 7 of 0x40) is set, VCCP can control the sleep state of the ADT7476A.
3
VCC (Pin 4) is the supply voltage for the ADT7476A.
2
Rev. 0 | Page 54 of 72
ADT7476A
Table 22. Temperature Reading Registers (Power-On Default = 0x80)1, 2, 3
Register Address
0x25
R/W
Read-only
Description
Remote 1 temperature reading3, 4 (8 MSBs of reading).
0x26
0x27
Read-only
Read-only
Local temperature reading (8 MSBs of reading).
Remote 2 temperature reading3, 4 (8 MSBs of reading).
1
If the extended resolution bits of these readings are also being read, the extended resolution registers (0x76, 0x77) must be read first. Once the extended resolution
registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.
2
These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C).
3
In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel.
4
In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel.
Table 23. Fan Tachometer Reading Registers (Power-On Default = 0x00)1
Register Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
1
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Description
TACH1 low byte.
TACH1 high byte.
TACH2 low byte.
TACH2 high byte.
TACH3 low byte.
TACH3 high byte.
TACH4 low byte.
TACH4 high byte.
These registers count the number of 11.11 μs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).
The number of TACH pulses used to count can be changed using the TACH Pulses per Revolution Register (0x7B). This allows the fan speed to be accurately measured.
Because a valid fan tachometer reading requires that two bytes be read, the low byte must be read first. Both the low and high bytes are then frozen
until read. At power-on, these registers contain 0x0000 until the first valid fan TACH measurement is read into these registers. This prevents false interrupts from
occurring while the fans are spinning up.
A count of 0xFFFF indicates that a fan is one of the following: stalled or blocked (object jamming the fan), failed (internal circuitry destroyed), or not populated. (The
ADT7476A expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should be set to 0xFFFF.)
Alternate function, for example, TACH4 reconfigured as THERM pin.
Table 24. PWM Current Duty Cycle Registers (Power-On Default = 0xFF)1
Register Address
0x30
0x31
0x32
1
R/W
Read/Write
Read/Write
Read/Write
Description
PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7476A reports the PWM duty cycles
back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers
report back 0x00. In manual mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table 25. PWM Maximum Duty Cycle (Power-On Default = 0xFF)1, 2
Register Address
0x38
0x39
0x3A
1
2
R/W2
Read/Write
Read/Write
Read/Write
Description
Maximum duty cycle for PWM1 output, default = 100% (0xFF.)
Maximum duty cycle for PWM2 output, default = 100% (0xFF).
Maximum duty cycle for PWM3 output, default = 100% (0xFF).
These registers set the maximum PWM duty cycle of the PWM output.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Rev. 0 | Page 55 of 72
ADT7476A
Table 26. Register 0x40—Configuration Register 1 (Power-On Default = 0x04)
Bit
[0]
Name
STRT1,2
R/W
Read/Write
[1]
LOCK
Write once
[2]
RDY
Read-only
[3]
FSPD
Read/Write
[4]
Vx1
Read/Write
[5]
FSPDIS
Read/Write
[6]
TODIS
Read/Write
[7]
Reserved
N/A
Description
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control is based on the default power-up limit settings.
Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the
default settings are enabled. This bit does not become locked once Bit 1 (LOCK bit) has been set.
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become
read-only and cannot be modified until the ADT7476A is powered down and powered up again. This
prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable.)
This bit is set to 1 by the ADT7476A to indicate that the device is fully powered-up and ready to begin
system monitoring.
When set to 1, this bit runs all fans at max speed as programmed in the max PWM current duty cycle
registers (0x30 to 0x32). Power-on default = 0. This bit is not locked at any time.
BIOS should set this bit to a 1 when the ADT7476A is configured to measure current from an ADOPT®
VRM controller and to measure the CPU’s core voltage. This bit allows monitoring software to display
CPU watts usage. (Lockable.)
Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan
spin-up timeout selected.
When this bit is set to 1, the SMBus timeout feature is enabled.
In this state, if at any point during an SMBus transaction involving the ADT7476A activity ceases for
more than 35 ms, the ADT7476A assumes the bus is locked and releases the bus. This allows the
ADT7476A to be used with SMBus controllers that cannot handle SMBus timeouts. (Lockable.)
Reserved. Do not write to this bit.
1
Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after lock bit is set.
2
When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection.
Table 27. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00)
Bit
[0]
Name
2.5 V/
THERM
R/W
Read-only
[1]
VCCP
Read-only
[2]
VCC
Read-only
[3]
5V
Read-only
[4]
R1T
Read-only
[5]
LT
Read-only
[6]
R2T
Read-only
[7]
OOL
Read-only
Description
2.5 V = 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided. If Pin 22 is configured as THERM, this bit is
asserted when the timer limit has been exceeded.
VCCP = 1 indicates that the VCCP high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
VCC = 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
A 1 indicates that the 5 V high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided.
R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
OOL = 1 indicates that an out-of-limit event has been latched in Interrupt Status Register 2. This bit is a
logical OR of all status bits in Interrupt Status Register 2. Software can test this bit in isolation to
determine whether any of the voltage, temperature, or fan speed readings represented by Interrupt
Status Register 2 are out-of-limit, which eliminates the need to read Interrupt Status Register 2 during
every interrupt or polling cycle.
Rev. 0 | Page 56 of 72
ADT7476A
Table 28. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00)
Bit
[0]
Name
12 V/VC
R/W
Read-only
[1]
OVT
Read-only
[2]
FAN1
Read-only
[3]
FAN2
Read-only
[4]
FAN3
Read-only
[5]
F4P
Read-only
Read/write
Read-only
[6]
[7]
D1
D2
Read-only
Read-only
Description
A 1 indicates that the 12 V high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided. If Pin 21 is configured as VID5, this bit is the VID change bit.
This bit is set when the levels on VID0 to VID5 are different than they were 11 μs previously. This pin can be
used to generate an SMBALERT whenever the VID code changes.
OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a
read of the status register when the temperature drops below THERM − THYST.
FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when
the PWM1 output is off.
FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when
the PWM2 output is off.
FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when
the PWM3 output is off.
When Pin 14 is programmed as a TACH4 input, F4P = 1 indicates that Fan 4 has dropped below minimum
speed or has stalled. This bit is not set when the PWM3 output is off.
When Pin 14 is programmed as the GPIO6 output, writing to this bit determines the logic output of GPIO6.
When GPIO6 is programmed as an input, this bit reflects the value read by GPIO6.
If Pin 14 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM
assertion time exceeds the limit programmed in the THERM timer limit register (0x7A).
D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table 29. Register 0x43—VID/GPIO Register (Power-On Default = 0x1F )
Bit
[4:0]
Name
VID[4:0]/
GPIO[4:0]
R/W
Read/Write
[5]
[6]
VID5
THLD
Read/Write
Read/Write
[7]
VIDSEL
Read/Write
Description
The VID[4:0] inputs from the CPU indicate the expected processor core voltage. On power-up, these bits
reflect the state of the VID pins, even if monitoring is not enabled. When Bit 4 of Configuration Register 5
(0x7C) = 1, these bits become general-purpose outputs. The state of these bits then reflects the state of
the appropriate GPIO pin.
Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, the VID5 bit always reads back 0 (power-on default).
Selects the input switching threshold for the VID inputs.
THLD = 0 selects a threshold of 1 V (VOL < 0.8 V, VIH > 1.7 V).
THLD = 1 lowers the switching threshold to 0.6 V (VOL < 0.4 V, VIH > 0.8 V).
VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default).
Table 30. Voltage Limit Registers1
Register Address
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
1
2
R/W
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description2
2.5 V low limit.
2.5 V high limit.
VCCP low limit.
VCCP high limit.
VCC low limit.
VCC high limit.
5 V low limit.
5 V high limit.
12 V low limit.
12 V high limit.
Power-On Default
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
Setting the Configuration Register 1 lock bit has no effect on these registers.
High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value is equal to or below its low
limit (≤ comparison).
Rev. 0 | Page 57 of 72
ADT7476A
Table 31. Temperature Limit Registers1
Register Address
0x4E
R/W
Read/Write
Description2
Remote 1 temperature low limit.
Power-On Default
0x81
0x4F
0x50
0x51
0x52
0x53
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Remote 1 temperature high limit.
Local temperature low limit.
Local temperature high limit.
Remote 2 temperature low limit.
Remote 2 temperature high limit.
0x7F
0x81
0x7F
0x81
0x7F
1
Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock
bit has no effect on these registers.
2
High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value is equal to or below its low
limit (≤ comparison).
Table 32. Fan TACH Limit Registers1
Register Address
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
1
R/W
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
TACH1 minimum low byte.
TACH1 minimum high byte/single-channel ADC channel select.
TACH2 minimum low byte.
TACH2 minimum high byte.
TACH3 minimum low byte.
TACH3 minimum high byte.
TACH4 minimum low byte.
TACH4 minimum high byte.
Power-On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2
to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
Table 33. Register 0x55—TACH1 Minimum High Byte (Power-On Default = 0xFF)
Bits
[4:0]
Name
Reserved
R/W
Read-only
[7:5]
SCADC
Read/Write
Description
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits are reserved.
Otherwise, these bits represent Bits [4:0] of the TACH1 minimum high byte.
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits are used to
select the only channel from which the ADC will take measurements. Otherwise, these bits represent Bits
[7:5] of the TACH1 minimum high byte.
Rev. 0 | Page 58 of 72
ADT7476A
Table 34. PWM Configuration Registers
Register Address
0x5C
0x5D
0x5E
Bit
[2:0]
Name
SPIN
R/W1
Read/Write
Read/Write
Read/Write
R/W
Read/Write
[3]
[4]
RES
INV
N/A
Read/Write
[7:5]
BHVR
Read/Write
1
Description
Power-On Default
PWM1 configuration.
0x62
PWM2 configuration.
0x62
PWM3 configuration.
0x62
Description
These bits control the startup timeout for PWMx. The PWM output stays high until
two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal
during the fan TACH measurement directly after the fan startup timeout period, the
TACH measurement reads 0xFFFF and Interrupt Status Register 2 reflects the fan
fault. If the TACH minimum high and low bytes contain 0xFFFF or 0x0000, the
Interrupt Status Register 2 bit is not set, even if the fan has not started.
000 = No startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
Reserved. Do not write to this bit.
This bit inverts the PWM output. The default is 0, which corresponds to a logic high
output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100%
duty cycle corresponds to a logic low output.
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temperature controls PWMx (automatic fan control mode).
001 = Local temperature controls PWMx (automatic fan control mode).
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed (default).
100 = PWMx disabled.
101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx.
110 = Fastest speed calculated by all three temperature channel controls PWMx.
111 = Manual mode. PWM current duty cycle registers (0x30 to 0x32) become writable.
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Rev. 0 | Page 59 of 72
ADT7476A
Table 35. TRANGE/PWM Frequency Registers
Register Address
0x5F
0x60
0x61
Bit
Name
[2:0]
FREQ
R/W1
Read/Write
Read/Write
Read/Write
R/W
Read/Write
[3]
HF/LF
Read/Write
[7:4]
RANGE
Read/Write
Description
Power-On Default
Remote 1 TRANGE/PWM1 frequency.
0xC4
Local TRANGE/PWM2 frequency.
0xC4
Remote 2 TRANGE/PWM3 frequency.
0xC4
Description
These bits control the PWMx frequency (only apply when PWM channel is in low
frequency mode).
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
HF/LF = 1, High frequency PWM mode is enabled for PWMx.
HF/LF = 0, Low frequency PWM mode is enabled for PWMx.
These bits determine the PWM duty cycle vs. the temperature range for automatic fan
control.
0000 = 2°C
0001 = 2.5°C
0010 = 3.33°C
0011 = 4°C
0100 = 5°C
0101 = 6.67°C
0110 = 8°C
0111 = 10°C
1000 = 13.33°C
1001 = 16°C
1010 = 20°C
1011 = 26.67°C
1100 = 32°C (default)
1101 = 40°C
1110 = 53.33°C
1111 = 80°C
1
These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.
Rev. 0 | Page 60 of 72
ADT7476A
Table 36. Register 0x62—Enhance Acoustics Register 1 (Power-On Default = 0x00)
Bit
[2:0]
Name
ACOU2
R/W1
Read/Write
[3]
[4]
EN1
SYNC
Read/Write
Read/Write
[5]
MIN1
Read/Write
[6]
MIN2
Read/Write
[7]
MIN3
Read/Write
1
2
Description
Assuming that PWMx is associated with the Remote 1 temperature channel, these bits define the maximum
rate of change of the PWMx output for Remote 1 temperature-related changes. Instead of the fan speed
jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by
these bits. This feature ultimately enhances the acoustics of the fan.
When Bit 7 of Configuration Register 6 (0x10) is 0
Time Slot Increase
Time for 0% to 100%
000 = 1
37.5 sec
001 = 2
18.8 sec
010 = 3
12.5 sec
011 = 4
7.5 sec
100 = 8
4.7 sec
101 = 12
3.1 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
Time Slot Increase
Time for 0% to 100%
000 = 1
52.2 sec
001 = 2
26.1 sec
010 = 3
17.4 sec
011 = 4
10.4 sec
100 = 8
6.5 sec
101 = 12
4.4 sec
110 = 24
2.2 sec
111 = 48
1.1 sec
When this bit is 1, smoothing is enabled on Remote 1 temperature channel.
SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to
three fans to be driven from PWM3 output and their speeds to be measured.
SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output.
When the ADT7476A is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle)
or at PWM1 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value.
0 = 0% duty cycle below TMIN – hysteresis.
1 = PWM1 minimum duty cycle below TMIN – hysteresis.
When the ADT7476A is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty
cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value.
0 = 0% duty cycle below TMIN – hysteresis.
1 = PWM 2 minimum duty cycle below TMIN – hysteresis.
When the ADT7476A is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty
cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value.
0 = 0% duty cycle below TMIN – hysteresis.
1 = PWM3 minimum duty cycle below TMIN – hysteresis.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Setting the relevant bit of Configuration Register 6, (0x10, [2:0]), further decreases these ramp rates by a factor of 4.
Rev. 0 | Page 61 of 72
ADT7476A
Table 37. Register 0x63—Enhance Acoustics Register 2 (Power-On Default = 0x00)
Bit
[2:0]
Name
ACOU3
R/W1
Read/Write
[3]
[6:4]
EN3
ACOU2
Read/Write
Read/Write
[7]
EN2
Read/Write
1
Description
Assuming that PWMx is associated with the local temperature channel, these bits define the maximum
rate of change of the PWMx output for local temperature-related changes. Instead of the fan speed
jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by
these bits. This feature ultimately enhances the acoustics of the fan.
When Bit 7 of Configuration Register 6 (0x10) is 0
Time Slot Increase
Time for 0% to 100%
000 = 1
37.5 sec
001 = 2
18.8 sec
010 = 3
12.5 sec
011 = 4
7.5 sec
100 = 8
4.7 sec
101 = 12
3.1 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
Time Slot Increase
Time for 0% to 100%
000 = 1
52.2 sec
001 = 2
26.1 sec
010 = 3
17.4 sec
011 = 4
10.4 sec
100 = 8
6.5 sec
101 = 12
4.4 sec
110 = 24
2.2 sec
111 = 48
1.1 sec
When this bit is 1, smoothing is enabled on the local temperature channel.
Assuming that PWMx is associated with the Remote 2 temperature channel, these bits define the
maximum rate of change of the PWMx output for Remote 2 temperature related changes. Instead of
the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate
determined by these bits. This feature ultimately enhances the acoustics of the fan.
When Bit 7 of Configuration Register 6 (0x10) is 0
Time Slot Increase
Time for 0% to 100%
000 = 1
37.5 sec
001 = 2
18.8 sec
010 = 3
12.5 sec
011 = 4
7.5 sec
100 = 8
4.7 sec
101 = 12
3.1 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When Bit 7 of Configuration Register 6 (0x10) is 1
Time Slot Increase
Time for 0% to 100%
000 = 1
52.2 sec
001 = 2
26.1 sec
010 = 3
17.4 sec
011 = 4
10.4 sec
100 = 8
6.5 sec
101 = 12
4.4 sec
110 = 24
2.2 sec
111 = 48
1.1 sec
When this bit is 1, smoothing is enabled on the Remote 2 temperature channel.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Rev. 0 | Page 62 of 72
ADT7476A
Table 38. PWM Minimum Duty Cycle Registers
Register Address
0x64
0x65
0x66
Bit
Name
[7:0]
PWM duty cycle
R/W1
Read/Write
Read/Write
Read/Write
R/W1
Read/Write
Description
PWM1 minimum duty cycle.
PWM2 minimum duty cycle.
PWM3 minimum duty cycle.
Description
These bits define the PWMMIN duty cycle for PWMx.
0x00 = 0% duty cycle (fan off ).
0x40 = 25% duty cycle.
0x80 = 50% duty cycle.
0xFF = 100% duty cycle (fan full speed).
Power-On Default
0x80 (50% duty cycle)
0x80 (50% duty cycle)
0x80 (50% duty cycle)
1
These registers become read-only when the ADT7476A is in automatic fan control mode.
Table 39. TMIN Registers1
R/W2
Read/Write
Read/Write
Read/Write
Register Address
0x67
0x68
0x69
Description
Remote 1 temperature TMIN.
Local temperature TMIN.
Remote 2 temperature TMIN.
Power-On Default
0x5A (90°C)
0x5A (90°C)
0x5A (90°C)
1
These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increases
with temperature according to TRANGE.
2
These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.
Table 40. THERM Limit Registers1
Register Address
0x6A
R/W2
Read/Write
Description
Remote 1 THERM limit.
Power-On Default
0x64 (100°C)
0x6B
Read/Write
Local THERM limit.
0x64 (100°C)
0x6C
Read/Write
Remote 2 THERM limit.
0x64 (100°C)
If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the
system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is
disabled. The PWM output remains at 100% until the temperature drops below THERM limit − hysteresis. If the THERM pin is programmed as an output, exceeding
these limits by 0.25°C can cause the THERM pin to assert low as an output.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
1
Table 41. Temperature/TMIN Hysteresis Registers1
Register Address
0x6D
[3:0]
R/W2
Read/Write
HYSL
[7:4]
HYSR1
0x6E
[7:4]
Read/Write
HYSR2
Description
Remote 1 and local temperature hysteresis.
Local temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the local
temperature AFC control loops.
Remote 1 temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the
Remote 1 temperature AFC control loops.
Remote 2 temperature hysteresis.
Local temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the local
temperature AFC control loops.
1
Power-On Default
0x44
0x40
Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its
TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN – hysteresis. Up to 15°C of hysteresis can be assigned to any temperature
channel. The hysteresis value chosen also applies to that temperature channel if its THERM limit is exceeded. The PWM output being controlled goes to 100% if the
THERM limit is exceeded and remains at 100% until the temperature drops below THERM – hysteresis. For acoustic reasons, it is recommended that the hysteresis
value not be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
Rev. 0 | Page 63 of 72
ADT7476A
Table 42. XNOR Tree Test Enable
Register Address
0x6F
[0]
R/W1
Read/Write
XEN
[7:1]
Reserved
1
Description
XNOR tree test enable register.
If the XEN bit is set to 1, the device enters the XNOR tree test mode.
Clearing the bit removes the device from the XNOR tree test mode.
Unused. Do not write to these bits.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 43. Remote 1 Temperature Offset1
Register Address
0x70
[7:0]
1
R/W1
Read/Write
Read/Write
Description
Remote 1 temperature offset.
Allows a temperature offset to be automatically applied to the Remote
Temperature 1 channel measurement. Bit 1 of Configuration Register 5 (0x7C)
determines the range and resolution of this register.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 44. Local Temperature Offset1
Register Address
0x71
[7:0]
1
R/W1
Read/Write
Read/Write
Description
Local temperature offset.
Allows a temperature offset to be automatically applied to the local
temperature measurement. Bit 1 of Configuration Register 5 (0x7C)
determines the range and resolution of this register.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 45. Remote 2 Temperature Offset1
Register Address
0x72
[7:0]
1
R/W1
Read/Write
Read/Write
Description
Remote 2 temperature offset.
Allows a temperature offset to be automatically applied to the Remote
Temperature 2 channel measurement. Bit 1 of Configuration Register 5 (0x7C)
determines the range and resolution of this register.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Rev. 0 | Page 64 of 72
ADT7476A
Table 46. Register 0x73—Configuration Register 2 (Power-On Default = 0x00)1
Bit
0
Name
FanPresenceDT
R/W1
Read/Write
1
2
3
4
Fan1Detect
Fan2Detect
Fan3Detect
AVG
Read
Read
Read
Read/Write
5
ATTN
Read/Write
6
CONV
Read/Write
7
RES
1
Description
When FanPresenceDT = 1, the state of Bits [3:1] of 0x73 reflects the presence of a
4-wire fan on the appropriate TACH channel.
Fan1Detect = 1 indicates that a 4-wire fan is connected to the TACH 1 input.
Fan2Detect = 1 indicates that a 4-wire fan is connected to the TACH 2 input.
Fan3Detect = 1 indicates that a 4-wire fan is connected to the TACH 3 input.
AVG = 1 indicates that averaging on the temperature and voltage measurements is
turned off. This allows measurements on each channel to be made much faster. (x16).
ATTN = 1 indicates that the ADT7476A removes the attenuators from the +2.5VIN,
VCCP, +5VIN, and +12VIN inputs. These inputs can be used for other functions such as
connecting up external sensors. It is also possible to remove attenuators from
individual channels using Bits [7:4] of Configuration Register 4 (0x7D).
CONV = 1 indicates that the ADT7476A is put into a single-channel ADC conversion
mode. In this mode, the ADT7476A can be made to read continuously from one
input only, for example, Remote 1 temperature. The appropriate ADC channel is
selected by writing to Bits [7:5] of TACH1 minimum high byte register (0x55).
Bits [7:5] Register 0x55
000
2.5 V
001
VCCP
010
VCC (3.3 V)
011
5V
100
12 V
101
Remote 1 temperature
110
Local temperature
111
Remote 2 temperature
This bit is reserved and should not be changed.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 47. Register 0x74—Interrupt Mask Register 1 (Power-On Default [7:0] = 0x00)
Bit
0
1
2
3
4
5
6
7
Name
2.5V/THERM
VCCP
VCC
5V
R1T
LT
R2T
OOL
R/W
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
2.5V/ THERM = 1, masks SMBALERT for out-of-limit conditions on the 2.5 V/ THERM timer channel.
VCCP = 1 masks SMBALERT for out-of-limit conditions on the VCCP channel.
VCC = 1 masks SMBALERT for out-of-limit conditions on the VCC channel.
5 V = 1 masks SMBALERT for out-of-limit conditions on the 5 V channel.
R1T = 1 masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
LT = 1 masks SMBALERT for out-of-limit conditions on the local temperature channel.
R2T = 1 masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
OOL = 0 when one or more alerts are generated in Interrupt Status Register 2, assuming all the
mask bits in the Interrupt Mask Register 2 (0x75) =1, SMBALERT is still asserted.
OOL = 1 when one or more alerts are generated in Interrupt Status Register 2, assuming all the
mask bits in the Interrupt Mask Register 2 (0x75) =1, SMBALERT is not asserted.
Rev. 0 | Page 65 of 72
ADT7476A
Table 48. Register 0x75—Interrupt Mask Register 2 (Power-On Default [7:0] = 0x00)
Bit
0
Name
12 V/VC
R/W
Read/Write
1
2
3
4
5
OVT
FAN1
FAN2
FAN3
F4P
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
6
7
D1
D2
Read/Write
Read/Write
Description
When Pin 21 is configured as a 12 V input, 12 V/VC = 1 masks SMBALERT for out-of-limit conditions
on the 12 V channel. When Pin 21 is programmed as VID5, this bit masks an SMBALERT, if the VID5
VID code bit changes.
OVT = 1 masks SMBALERT for overtemperature THERM conditions.
FAN1 = 1 masks SMBALERT for a Fan 1 fault.
FAN2 = 1 masks SMBALERT for a Fan 2 fault.
FAN3 = 1 masks SMBALERT for a Fan 3 fault.
If Pin 14 is configured as TACH4, F4P = 1 masks SMBALERT for a Fan 4 fault.
If Pin 14 is configured as THERM, F4P = 1 masks SMBALERT for an exceeded THERM timer limit.
If Pin 14 is configured as GPIO, F4P = 1 masks SMBALERT when GPIO is an input and GPIO is asserted.
D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel.
D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel.
Table 49. Register 0x76—Extended Resolution Register 11 (Power-On Default [7:0] = 0x00)
Bit
[1:0]
[3:2]
[5:4]
[7:6]
1
Name
2.5 V
VCCP
VCC
5V
R/W
Read-only
Read-only
Read-only
Read-only
Description
2.5 V LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement.
VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement.
VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement.
5 V LSBs. Holds the 2 LSBs of the 10-bit 5 V measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 50. Register 0x77—Extended Resolution Register 21 (Power-On Default [7:0] = 0x00)
Bit
[1:0]
[3:2]
[5:4]
[7:6]
1
Name
12 V
TDM1
LTMP
TDM2
R/W
Read-only
Read-only
Read-only
Read-only
Description
12 V LSBs. Holds the 2 LSBs of the 10-bit 12 V measurement.
Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement.
Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.
Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Rev. 0 | Page 66 of 72
ADT7476A
Table 51. Register 0x78—Configuration Register 3 (Power-On Default = 0x00)
Bit
[0]
Name
ALERT
R/W1
Read/Write
[1]
THERM/
2.5 V
Read/Write
[2]
BOOST
Read/Write
[3]
FAST
Read/Write
[4]
DC1
Read/Write
[5]
DC2
Read/Write
[6]
DC3
Read/Write
[7]
DC4
Read/Write
1
Description
ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate
out-of-limit error conditions.
ALERT = 0, Pin 10 (PWM2/SMBALERT) is configured as the PWM2 output.
THERM = 1 enables THERM functionality on Pin 22 and Pin 14, if Pin 14 is configured as THERM,
determined by Bits 0 and 1 (PIN14FUNC) of Configuration Register 4. When THERM is asserted, if
the fans are running and the boost bit is set, then the fans run at full speed. Alternatively, THERM
can be programmed so that a timer is triggered to time how long THERM has been asserted.
THERM = 0 enables 2.5 V measurement on Pin 22 and disables THERM. If bits [5:7] of Configuration
Register 5 are set, THERM is bidirectional. If they are 0, THERM is a timer input only.
Pin14FUNC
THERM/2.5 V
Pin 22
Pin 14
00
01
10
11
00
01
10
11
0
0
0
0
1
1
1
1
+2.5VIN
+2.5VIN
+2.5VIN
+2.5VIN
THERM
+2.5VIN
THERM
THERM
TACH4
THERM
SMBALERT
GPIO6
TACH4
THERM
SMBALERT
GPIO6
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum
programmed duty cycle for fail-safe cooling.
FAST = 1 enables fast TACH measurements on all channels. This increases the TACH measurement
rate from once per second to once every 250 ms (4 ×).
DC1 = 1 enables TACH measurements to be continuously made on TACH1. Fans must be driven by
dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors.
DC2 = 1 enables TACH measurements to be continuously made on TACH2. Fans must be driven by
dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors.
DC3 = 1 enables TACH measurements to be continuously made on TACH3. Setting this bit prevents
pulse stretching because it is not required for dc-driven motors.
DC4 = 1 enables TACH measurements to be continuously made on TACH4. Setting this bit prevents
pulse stretching because it is not required for dc-driven motors.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 52. Register 0x79—THERM Timer Status Register (Power-On Default = 0x00)
Bit
[7:1]
Name
TMR
R/W
Read-only
[0]
ASRT/TMRO
Read-only
Description
Times how long THERM input is asserted. These seven bits read zero until the THERM assertion
time exceeds 45.52 ms.
This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM
assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This
allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of
22.76 ms.
Table 53. Register 0x7A—THERM Timer Limit Register (Power-On Default = 0x00)
Bit
[7:0]
Name
LIMT
R/W
Read/Write
Description
Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit
limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 sec to be
programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register 2
(0x42) is set. If the limit value is 0x00, an interrupt is generated immediately on the assertion of the
THERM input.
Rev. 0 | Page 67 of 72
ADT7476A
Table 54. Register 0x7B—TACH Pulses per Revolution Register (Power-On Default = 0x55)
Bit
[1:0]
Name
FAN1
R/W
Read/Write
[3:2]
FAN2
Read/Write
[5:4]
FAN3
Read/Write
[7:6]
FAN4
Read/Write
Description
Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Rev. 0 | Page 68 of 72
ADT7476A
Table 55. Register 0x7C—Configuration Register 5 (Power-On Default = 0x01)
Bit
[0]
Name
2sC
R/W1
Read/Write
[1]
TempOffset
Read/Write
[2]
GPIO6D
Read/Write
[3]
GPIO6P
Read/Write
[4]
VID/GPIO
Read/Write
[5]
R1 THERM
Read/Write
[6]
Local
THERM
Read/Write
[7]
R2 THERM
Read/Write
Description
2sC = 1 sets the temperature range to the twos complement temperature range.
2sC = 0 changes the temperature range to the Offset 64 temperature range. When this bit is changed,
the ADT7476A interprets all relevant temperature register values as defined by this bit.
TempOffset = 0 sets offset range to −63°C to +64°C with 0.5°C resolution.
TempOffset = 1 sets offset range to −63°C to +127°C with 1°C resolution.
These settings apply to Remote 1, Local, and Remote2 temperature offset registers (0x70, 0x71, and 0x72).
GPIO6 direction. When GPIO6 function is enabled, this determines whether GPIO6 is an input (0) or
an output (1).
GPIO6 polarity. When the GPIO6 function is enabled and is programmed as an output, this bit
determines whether the GPIO6 is active low (0) or high (1).
VID/GPIO = 0 enables VID functionality on Pin 5, Pin 6, Pin 7, Pin 8, and Pin 19.
VID/GPIO = 1 enables GPIO functionality on Pin 5, Pin 6, Pin 7, Pin 8, and Pin 19.
R1 THERM = 1 enables THERM temperature limit functionality for Remote 1 temperature channel;
that is, THERM is bidirectional. R1 THERM = 0 indicates THERM is a timer input only.
THERM can also be disabled on any channel by:
Writing −64˚C to the appropriate THERM temperature limit in Offset 64 mode.
Writing −128˚C to the appropriate THERM temperature limit in twos complement mode.
Local THERM = 1 enables THERM temperature limit functionality for local temperature channel;
that is, THERM is bidirectional. Local THERM = 0 indicates THERM is a timer input only.
THERM can also be disabled on any channel by:
Writing −64°C to the appropriate THERM temperature limit in Offset 64 mode.
Writing −128°C to the appropriate THERM temperature limit in twos complement mode.
R2 THERM = 1 enables THERM temperature limit functionality for Remote 2 temperature channel;
that is, THERM is bidirectional. R2 THERM = 0 indicates THERM is a timer input only.
THERM can also be disabled on any channel by:
Writing −64°C to the appropriate THERM temperature limit in Offset 64 mode.
Writing −128°C to the appropriate THERM temperature limit in twos complement mode.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Rev. 0 | Page 69 of 72
ADT7476A
Table 56. Register 0x7D—Configuration Register 4 (Power-On Default = 0x00)
Bit
[1:0]
Name
PIN14FUNC
R/W1
Read/Write
[2]
THERM
Disable
Read/Write
[3]
MaxSpeed
on THERM
Read/Write
[4]
BpAtt 2.5 V
Read/Write
[5]
BpAtt VCCP
Read/Write
[6]
BpAtt 5 V
Read/Write
[7]
BpAtt 12 V
Read/Write
1
Description
These bits set the functionality of Pin 14:
00 = TACH4 (default)
01 = THERM
10 = SMBALERT
11 = GPIO
THERM Disable = 0 enables THERM overtemperature output assuming THERM is correctly configured
(Register 0x78, Register 0x7C, and Register 0x7D).
THERM Disable = 1 disables THERM overtemperature output on all channels.
THERM can also be disabled on any channel by:
Writing −64°C to the appropriate THERM temperature limit in Offset 64 mode.
Writing −128°C to the appropriate THERM temperature limit in twos complement mode.
MaxSpeed on THERM = 0 indicates that fans go to full speed when THERM temperature limit is exceeded.
MaxSpeed on THERM = 1 indicates that fans go to max speed (0x38, 0x39, 0x3A) when THERM
temperature limit is exceeded.
Bypass 2.5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.25 V (0xFF).
Bypass VCCP attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.25 V (0xFF).
Bypass 5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.25 V (0xFF).
Bypass 12 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.25 V (0xFF).
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 57. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00)
Bit
[7:0]
Name
Reserved
R/W
Read-only
Description
Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not
be written to under normal operation.
Table 58. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00)
Bit
[7:0]
Name
Reserved
R/W
Read-only
Description
Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not
be written to under normal operation.
Rev. 0 | Page 70 of 72
ADT7476A
OUTLINE DIMENSIONS
0.345
0.341
0.337
24
13
0.158
0.154
0.150
1
12
0.244
0.236
0.228
PIN 1
0.069
0.053
0.065
0.049
0.010
0.004
0.025
BSC
COPLANARITY
0.004
0.012
0.008
SEATING
PLANE
0.010
0.006
8°
0°
0.050
0.016
COMPLIANT TO JEDEC STANDARDS MO-137AE
Figure 67. 24-Lead Shrink Small Outline Package [QSOP]
(RQ-24)
Dimensions shown in inches
ORDERING GUIDE
Model
ADT7476AARQZ 1
ADT7476AARQZ-REEL1
ADT7476AARQZ-REEL71
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
24-Lead Shrink Small Outline Package [QSOP]
24-Lead Shrink Small Outline Package [QSOP]
24-Lead Shrink Small Outline Package [QSOP]
Z = Pb-free part.
Rev. 0 | Page 71 of 72
Package Option
RQ-24
RQ-24
RQ-24
ADT7476A
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05742-0-1/06(0)
Rev. 0 | Page 72 of 72