AD ADT7470ARQ-REEL

Preliminary Technical Data
Temperature Sensor Hub and Fan Controller
ADT7470
FEATURES
GENERAL DESCRIPTION
Monitors up to 10 remote temperature sensors
Monitors and controls speed of up to 4 fans independently
PWM outputs drive each fan under software control
FULL_SPEED input allows fans to be blasted 100% by
external hardware
SMBALERT interrupt signals failures to system controller
Tristate ADDR pin allows up to 3 devices on a single bus
Temperature decoder interprets TMP05/TMP06 temperature
sensors and communicates values over I2C bus
Limit comparison of all monitored values
Supports fast I2C standard (400 kHz max)
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Footprint compatible with ADT7460
The ADT7470 controller is a multichannel temperature sensor
and PWM fan controller and fan speed monitor for noisesensitive systems requiring active system cooling. It is designed
to interface directly to an I2C bus and control/monitor the fans
using a service processor. The aim is to quickly develop systems
that are modular and can easily be expanded depending on the
system’s cooling requirements. The device can monitor up to ten
temperature sensors. It can also monitor and control the speed
of four fans so that they operate at the lowest possible speed for
minimum acoustic noise. A FULL_SPEED input is provided to
allow the fans to be “blasted” to 100% via external hardware
control, under extreme thermal conditions or on system startup.
An SMBALERT interrupt communicates error conditions such
as fan underspeed, fan failure to the system service processor.
Individual error conditions can then be read from status registers
over the I2C bus. In the event of a fan failure condition, any or
all PWM outputs can be programmed to automatically adjust to
100% to provide failsafe cooling.
APPLICATIONS
Servers
Networking and telecommunications equipment
Desktops
FUNCTIONAL BLOCK DIAGRAM
SDA SCL SMBALERT
ADDR
ADT7470
FULL_SPEED
PWM1
PWM2
PWM3
SMBus
ADDRESS
SELECTION
PWM
REGISTERS
AND
CONTROLLERS
SERIAL BUS
INTERFACE
AUTOMATIC
FAN SPEED
CONTROL
ADDRESS
POINTER
REGISTER
PWM
CONFIG
REGISTERS
PWM4
INTERRUPT
MASKING
TACH1
TMP_START
TMP_IN
FAN SPEED
COUNTERS
INTERRUPT
STATUS
REGISTERS
TEMPERATURE
DECODER
LIMIT
COMPARATORS
VALUE AND
LIMIT
REGISTERS
04684-0-001
TACH2
TACH3
TACH4
Figure 1.
Protected by Patent Numbers US6,188,189, US6,169,442, US6,097,239, US5,982,221, US5,867,012. Other patents pending.
Rev. PrA
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© 2004 Analog Devices, Inc. All rights reserved.
ADT7470
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
16-Bit Limits ............................................................................... 13
Absolute Maximum Ratings............................................................ 5
Out-of-Limit Comparisons....................................................... 14
Thermal Characteristics .............................................................. 5
Monitoring Cycle Time ............................................................. 15
ESD Caution.................................................................................. 5
Status Registers ........................................................................... 15
Pin Configuration and Function Descriptions............................. 6
SMBALERT Interrupt Behavior ............................................... 16
Functional Description .................................................................... 7
Handling SMBALERT Interrupts............................................. 16
General Description..................................................................... 7
Masking Interrupt Sources........................................................ 17
Fan Speed Measurement.............................................................. 7
Enabling the SMBALERT Interrupt Output........................... 17
ADT7470 Address Selection ....................................................... 7
Fan Drive Using PWM Control.................................................... 18
Internal Registers of the ADT7470 ............................................ 7
Fan Speed Measurement................................................................ 19
2
SMBus/I C Communications Interface ..................................... 7
Tach Inputs.................................................................................. 19
ADT7470 Write Operations ...................................................... 10
Fan Speed Measurement ........................................................... 19
ADT7470 Read Operations....................................................... 11
Manual Fan Speed Control ........................................................... 22
SMBus Timeout .......................................................................... 11
PWM Logic State........................................................................ 22
Temperature Measurement Using TMP05/TMP06 ................... 12
Manual Fan Speed Control ....................................................... 22
Measuring Temperature ............................................................ 12
Automatic Fan Speed Control .................................................. 22
TMP05/TMP06 Decoder........................................................... 12
ADT7470 Registers ........................................................................ 23
Interrupt Functionality and Status Registers .............................. 13
Outline Dimensions ....................................................................... 38
Limit Values................................................................................. 13
Ordering Guide .......................................................................... 38
8-Bit Limits.................................................................................. 13
REVISION HISTORY
Revision 0: Initial Version
Rev. PrA | Page 2 of 40
Preliminary Technical Data
ADT7470
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY1
Supply Voltage
Supply Current, ICC
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
Full-Scale Count
Nominal Input RPM
Min
Typ
Max
Unit
3.0
3.3
1.4
5.5
2.5
V
mA
±3
65,535
%
109
329
5000
10000
45
Internal Clock Frequency
OPEN-DRAIN DIGITAL OUTPUTS,PWM1–PWM4, SMBALERT
Current Sink, IOL
Output Low Voltage, VOL
High Level Output Current, IOH
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS, FULL_SPEED)
Input High Voltage, VIH
RPM
RPM
RPM
RPM
kHz
0.1
mA
V
µA
IOUT = –8.0 mA, VCC = 3.3 V
VOUT = VCC
0.1
0.4
1
V
µA
IOUT = –4.0 mA, VCC = 3.3 V
VOUT = VCC
0.4
V
V
mV
2.0
500
2.0
5.5
0.8
–0.3
1
Fan count = 0xBFFF
Fan count = 0x3FFF
Fan count = 0x0438
Fan count = 0x021C
8.0
0.4
1
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Detect Clock Low Timeout, tTIMEOUT
Test Conditions/Comments
0.5
–5
5
20
400
50
1.3
600
600
1.3
0.6
300
300
100
300
25
64
V
V
V
V
V p-p
Maximum input voltage
Minimum input voltage
µA
µA
pF
VIN = VCC
VIN = 0
kHz
ns
µs
ns
ns
µs
µs
ns
ns
ns
ns
ms
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
Can be optionally disabled
VDD should never be floated in presence of SCL/SDA activity. Charge injection can be sufficient to induce approximately 0.6 V on VDD.
Rev. PrA | Page 3 of 40
ADT7470
Preliminary Technical Data
Note the following about the specifications for the ADT7470:
•
All voltages are measured with respect to GND, unless otherwise specified.
•
Typical values are at TA = 25°C and represent most likely parametric norm.
•
Logic inputs accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V.
•
VDD should never be floated in presence of SCL/SDA activity. Charge injection can be sufficient to induce approximately 0.6 V on
VDD.
•
Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
tR
tF
tHD;STA
tLOW
SCL
tHIGH
tHD;DAT
tSU;STA
tSU;DAT
tSU;STO
SDA
tBUF
P
S
S
Figure 2. Diagram for Serial Bus Timing
Rev. PrA | Page 4 of 40
P
04684-0-002
tHD;STA
Preliminary Technical Data
ADT7470
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Positive Supply Voltage (VCC)
Voltage on Any Tach or PWM pin
Voltage on Any Input or Output Pin
Input Current at any Pin
Package Input Current
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Lead Temperature, Soldering
Vapor Phase, 60 sec
Infrared, 15 sec
ESD Rating
Rating
6.5 V
–0.3 V to 6.5 V
–0.3 V to VCC + 0.3 V
±5 mA
±20 mA
150°C
–65°C to +150°C
215°C
200°C
2000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
16-Lead QSOP Package:
θJA = 105°C/Watt, θJC = 39°C/Watt
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 5 of 40
ADT7470
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCL 1
16
SDA
GND 2
15
PWM1
14
SMBALERT
VCC 3
PWM2 5
ADT7470
FULL_SPEED/TMP_START
TOP VIEW
(Not to Scale) 12 TMP_IN
13
TACH1 6
11
ADDR
TACH2 7
10
PWM4
PWM3 8
9
TACH4
04684-0-003
TACH3
4
Figure 3. RQ-16
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
SCL
GND
VCC
TACH3
PWM2
6
7
8
TACH1
TACH2
PWM3
9
10
TACH4
PWM4
11
12
ADDR
TMP_IN
13
FULL_SPEED
13
TMP_START
14
SMBALERT
15
PWM1
16
SDA
Description
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
Ground pin for the ADT7470.
Power Supply Pin. Can be powered by 3.3 V standby if operation in low power states is required.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
Digital I/O (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control Fan 2 speed.
Can be configured as GPIO by setting Bit 0x7F[2] = 1.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
Digital I/O (Open Drain). Pulse width modulated output to control Fan 3 speed. Requires 10 kΩ typical pull-up.
Can be configured as GPIO by setting Bit 0x7F[1] = 1
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
Digital I/O (Open Drain). Pulse width modulated output to control Fan 4 speed. Requires 10 kΩ typical pull-up.
Can be configured as GPIO by setting Bit 0x7F[0] = 1.
Tristate Input. Used to set SMBus device address.
Digital Input (Open Drain). PWM input to PWM processing engine that interprets daisy chained output from
multiple TMP05 temperature sensors. Readings from individual TMP05 temperature sensors are available by
reading the temperature reading registers over the SMBus.
Digital Input—Active Low (Open Drain). This inputl blasts the fans to 100% when the pin is pulled low
externally.
Digital Output (Open Drain). This pin can be used as an output to start daisy-chained temperature
measurements from TMP05 or TMP06 temperature sensors.
Digital Output—Active Low (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to
signal out-of-limit conditions such as fan failures.
Digital I/O (Open Drain). Pulse width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up.
Can be configured as GPIO by setting Bit 0x7F[3] = 1.
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.
Rev. PrA | Page 6 of 40
Preliminary Technical Data
ADT7470
FUNCTIONAL DESCRIPTION
Status Registers
GENERAL DESCRIPTION
The ADT7470 is a multichannel PWM fan controller and
monitor for any system requiring monitoring and cooling. The
device communicates with the system via a serial system
management bus. The device has a single address line for
address selection (Pin 11), a serial data line for reading and
writing addresses and data (Pin 16), and an input line for the
serial clock (Pin 1). All control and programming functions of
the ADT7470 are performed over the serial bus that supports
both SMBus and fast I2C specifications. In addition, an
SMBALERT interrupt output is provided to indicate out-oflimit conditions.
FAN SPEED MEASUREMENT
When the ADT7470 monitoring sequence is started, it cycles
through each fan tach input to measure fan speed. Measured
values from these inputs are stored in value registers. These can
be read out over the serial bus, or can be compared with
programmed limits stored in the limit registers. The results of
out of limit comparisons are stored in the status registers, which
can be read over the serial bus to flag out of limit conditions. If
fan speeds drop below preset levels or a fan stalls, an interrupt is
generated and the fans can automatically blast to 100%.
Likewise, the ADT7470 has the ability to flag fan overspeed
conditions using fan tach max registers.
ADT7470 ADDRESS SELECTION
Pin 11 is the address selection pin, ADDR. If Pin 11 is pulled
low on power-up, the ADT7470 defaults to Slave Address 0x58
(left-justified) or 0x2C (right-justified). If Pin 11 is floating on
power-up, then the ADT7470 defaults to SMBus slave Address
0x5A (left-justified) or 0x2D (right-justified). By pulling the pin
high on power-up, the SMBus slave address is 0x5C (leftjustified) or 0x2E (right-justified).
INTERNAL REGISTERS OF THE ADT7470
A brief description of the ADT7470’s principal internal registers
is given in the following sections. More detailed information on
the function of each register is found in the register map in
Table 21.
Configuration Registers
These registers provide control and configuration of the
ADT7470, including alternate pinout functionality such as a fan
blast input (FULL_SPEED) or daisy-chained TMP05 measurement (start) output.
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADT7470, the first byte
of data is always a register address, which is written to the
address pointer register.
These registers provide status of each limit comparison and are
used to signal out-of-limit conditions on the fan speed channels,
or temperature channels if monitored using the PWM_IN
feature. If Pin 14 (SMBALERT) is used in the system, then this
pin asserts low whenever a status bit gets set, signaling an outof-limit condition.
Interrupt Mask Registers
Allows each interrupt status event to be individually masked
from driving the SMBALERT output as required. This is useful
where fan tach inputs is unused and left floating, or if temperature
inputs from TMP05s are ignored from an interrupt perspective.
Masking interrupt status bits prevents the SMBALERT output
from being driven although the status bits still reflect out-oflimit conditions. This can prevent a service processor from being
continually tied up in an interrupt service routine, should a
value remain outside limits for a relatively long duration.
Value and Limit Registers
The results of fan speed measurements are stored in these
registers, along with their limit values. The limit values store the
slowest speed that the fans are expected to run at, or the limit
value can determine what a fan failure is expected to be, in
terms of running speed in case the fan doesn’t completely stall.
If TMP05s and TMP06s are daisy-chained in through the
PWM_IN pin, then the measured temperatures are stored in
temperature value registers.
TMIN Registers
Programs the starting temperature for each fan under automatic
fan speed control. The ADT7470 has limited automatic fan
speed control capability where only one mode of operation is
supported. If TMP05s are daisy-chained in, the fastest speed
calculated, determined by the measured temperature, TMIN and a
fixed slope of 20°C can drive each fan. Fan on/off hysteresis is
set at 4°C so that the fans turn off 4°C below the temperature at
which they turn. This prevents fan chatter in the system.
SMBus/I2C COMMUNICATIONS INTERFACE
Serial Bus Interface
Control of the ADT7470 is carried out using the serial system
management bus (SMBus). This interface is fully compatible
with SMBus 2.0 electrical specifications and meets 400 pF bus
capacitance requirements. The device also supports fast I2C
(400 kHz max). The ADT7470 is connected to the bus as a slave
device, under the control of a master controller or service
processor.
The ADT7470 has a 7-bit serial bus address. When the device is
powered up with Pin 11 (ADDR) high, the ADT7470 has an
SMBus address of 0101111 or 0x5E (left-justified). Because the
address is 7 bits, it can be left or right justified; this determines
whether the address reads as 0x5x or 0x2x. Pin 11 can be left
Rev. PrA | Page 7 of 40
ADT7470
Preliminary Technical Data
floating or tied low for other addressing options as shown in
Table 4.
Table 4. ADT7470 Address Select Mode
Pin 11 State (ADDR)
High (10 kΩ to VCC)
Low (10 kΩ to GND)
Floating (no pull-up)
Address
0101111 (0x5E left-justified or
0x2F right-justified)
0101100 (0x58 left-justified or
0x2C right-justified)
0101110 (0x5C left-justified or
0x2E right-justified)
1
16
2
15
3
14
ADT7470
6
11
7
10
8
9
1.
VCC
13
12
5
The serial bus protocol operates as follows:
ADDR
10kΩ
TYP.
Figure 4. SMBus Address = 0x5E or 0x2F (Pin 11 = 1)
1
16
2
15
3
14
2.
Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, as a low to high transition when
the clock is high may be interpreted as a stop signal. The
number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
3.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device overrides
the acknowledge bit by pulling the data line high during
the low period before the 9th clock pulse. This is known as
No Acknowledge. The master then takes the data line low
during the low period before the 10th clock pulse, then
high during the 10th clock pulse to assert a stop condition.
13
4
ADT7470
12
6
11
7
10
8
9
ADDR
10kΩ
TYP.
04684-0-005
5
Figure 5. SMBus Address = 0x58 or 0x2C (Pin 11 = 0)
1
16
2
15
3
14
ADT7470
13
5
12
6
11
7
10
8
9
ADDR
04684-0-006
4
Figure 6. SMBus Address = 0x5C or 0x2E (Pin 11 = Floating)
The master initiates data transfer by establishing a start
condition, defined as a high to low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
start condition, and shift in the next 8 bits, consisting of a
7-bit address (MSB first) and a R/W bit, which determines
the direction of the data transfer, i.e., whether data is
written to or read from the slave device.
The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/W bit is a 0, then the master writes
to the slave device. If the R/W bit is a 1, the master reads
from the slave device.
04684-0-004
4
The device address is sampled and latched on the first valid
SMBus transaction, so any additional attempted addressing
changes have no immediate effect. The facility to make
hardwired changes to the SMBus slave address allows the user
to avoid conflicts with other devices sharing the same serial bus,
for example, if more than one ADT7470 is used in a system.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and subsequently cannot be changed without
starting a new operation.
Rev. PrA | Page 8 of 40
Preliminary Technical Data
ADT7470
1
9
1
9
SCL
0
SDA
1
0
1
1
A1
A0
D7
R/W
START BY
MASTER
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7470
ACK. BY
ADT7470
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7470
STOP BY
MASTER
FRAME 3
DATA
BYTE
04684-0-007
SDA (CONTINUED)
Figure 7. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
9
1
1
9
SCL
0
1
0
1
1
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7470
START BY
MASTER
ACK. BY
ADT7470
FRAME 1
SERIAL BUS ADDRESS
BYTE
STOP BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
04684-0-008
SDA
Figure 8. Writing to the Address Pointer Register Only
1
9
1
9
SCL
0
1
0
1
1
A1
START BY
MASTER
A0
R/W
D7
D6
D5
D4
D3
D2
ACK. BY
ADT7470
D1
D0
NO ACK.
STOP BY
BY MASTER MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
DATA BYTE FROM
ADT7470
04684-0-009
SDA
Figure 9. Reading Data from a Previously Selected Register
In the case of the ADT7470, write operations contain either one
or two bytes, and read operations contain one byte, and perform
the following functions.
To write data to one of the device data registers or read data
from it, the address pointer register must be set so that the
correct data register is addressed, then data can be written into
that register or read from it. The first byte of a write operation
always contains an address that is stored in the address pointer
register. If data is to be written to the device, then the write
operation contains a second data byte that is written to the
register selected by the address pointer register.
This is illustrated in Figure 7. The device address is sent over the
bus followed by R/W set to 0. This is followed by two data bytes.
The first data byte is the address of the internal data register to
be written to, which is stored in the address pointer register. The
second data byte is the data to be written to the internal data
register.
When reading data from a register there are two possibilities:
•
Rev. PrA | Page 9 of 40
If the ADT7470 address pointer register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7470
ADT7470
Preliminary Technical Data
A read operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data byte read
from the data register. This is shown in Figure 9.
If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, so Figure 8 can be omitted.
Notes:
•
•
•
•
Although it is possible to read a data byte from a data
register without first writing to the address pointer register
if the address pointer register is already at the correct value,
it is not possible to write data to a register without writing
to the address pointer register, because the first data byte of
a write is always written to the address pointer register.
In Figure 7 to Figure 9, the serial bus address is shown as
the default value 01011(A1)(A0), where A1 and A0 are set
by the address select mode function previously defined.
In addition to supporting the send byte and receive byte
protocols, the ADT7470 also supports the read byte
protocol. See System Management Bus specifications
Rev. 2.0 for more information.
If it is required to perform several read or write operations
in succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
ADT7470 WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7470 are discussed in the following sections. The following
abbreviations are used in the diagrams:
S—Start
P—Stop
R—Read
W—Write
A—Acknowledge
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
5.
The slave asserts ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7470, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This is illustrated in Figure 10.
1
2
S
SLAVE
ADDRESS
W
3
4
5
6
A
REGISTER
ADDRESS
A
P
Figure 10. Setting a Register Address for Subsequent Read
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
5.
The slave asserts ACK on SDA.
6.
The master sends a data byte.
7.
The slave asserts ACK on SDA.
8.
The master asserts a stop condition on SDA to end the
transaction.
This is illustrated in Figure 11.
A—No Acknowledge
1
2
S
SLAVE
ADDRESS
The ADT7470 uses the following SMBus write protocols:
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
Rev. PrA | Page 10 of 40
W
3
4
5
6
7
8
A
REGISTER
ADDRESS
A
DATA
A
P
Figure 11. Single-Byte Write to a Register
04684-0-011
•
1.
04684-0-010
as before, but only the data byte containing the register
address is sent, as data is not to be written to the register.
This is shown in Figure 8.
Preliminary Technical Data
ADT7470
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
occurs:
ADT7470 READ OPERATIONS
The ADT7470 uses the following SMBus read protocols:
Receive Byte
This is useful when repeatedly reading a single register. The
register address needs to have been set up previously. In this
operation, the master device receives a single byte from a slave
device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives a data byte.
5.
The master asserts NO ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
In the ADT7470, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
2
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
SMBALERT is pulled low.
2.
Master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known, and it can
be interrogated in the usual way.
4.
If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority, in
accordance with normal SMBus arbitration.
5.
Once the ADT7470 has responded to the alert response
address, the master must read the status registers, and the
SMBALERT is cleared only if the error condition has gone
away.
SMBus TIMEOUT
The ADT7470 includes an SMBus timeout feature. If there is no
SMBus activity for 35 ms, the ADT7470 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
04684-0-012
1
1.
Figure 12. Single-Byte Write from a Register
Alert Response Address
Table 5. Configuration Register 1—Register 0x40
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
Bit Address and Value
<3> TODIS = 0
<3> TODIS = 1
The SMBALERT output can be used as an interrupt output or
can be used as an SMBALERT. One or more outputs can be
.
Rev. PrA | Page 11 of 40
Description
SMBus Timeout Enabled (default).
SMBus Timeout Disabled.
ADT7470
Preliminary Technical Data
TEMPERATURE MEASUREMENT USING TMP05/TMP06
MEASURING TEMPERATURE
For more information, refer to the TMP05/TMP06 data sheets.
TMP05 generates a PWM output proportional to temperature,
which can be easily interfaced to most micros or CPUs.
The following table lists the temperature reading registers on
the ADT7470.
TMP05/TMP06 DECODER
Table 6. Temperature Reading Registers
Reading
Temperature 1 Reading
Temperature 2 Reading
Temperature 3 Reading
Temperature 4 Reading
Temperature 5 Reading
Temperature 6 Reading
Temperature 7 Reading
Temperature 8 Reading
Temperature 9 Reading
Temperature 10 Reading
SCL
1
16 SDA
GND
2
15 PWM1
VCC
3
14 SMBALERT
TACH3
4
PWM2
ADT7470
13 FULL_SPEED/TMP_START
TOP VIEW
5 (Not to Scale) 12 TMP_IN
TACH1
6
11 ADDR
TACH2
7
10 PWM4
PWM3
8
9
TACH4
The ADT7470 includes a PWM processing engine to decode the
daisy-chained PWM output from multiple TMP05s/TMP06s
and passes each decoded temperature value to temperature
value registers. This allows the ADT7470 to do high/low limit
comparisons of temperature and to automatically control fan
speed based on measured temperature. The PWM processing
engine contains all necessary logic to initiate start conversions
on the first daisy-chained TMP05/TMP06 and synchronize with
each temperature value as it is fed back to the device through
the daisy chain. The start function is multiplexed on to the same
pin that can be used to blast the fans to full speed. The start
conversion for TMP05/TMP06 temperature measurement is
fully transparent to the user and doesn’t require any software
intervention to function.
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
CONV/IN
TMP05/
TMP06
NO. 1
OUT
CONV/IN
TMP05/
TMP06
NO. 2
OUT
CONV/IN
TMP05/
TMP06
NO. 3
OUT
CONV/IN
TMP05/
TMP06
n
Figure 13. Interfacing the ADT7470 to Multiple Daisy-Chained TMP05/TMP06 Temperature Sensors
Rev. PrA | Page 12 of 40
OUT
04684-0-013
Register
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
8-bit temperature values are reported in the preceding registers
only if the PWM_IN function is used and if TMP05s/TMP06s
are daisy-chained according to their respective data sheets and
connected as shown in Figure 13. Note that this device does
NOT have any temperature measurement capability when used
as a standalone device, without TMP05s/TMP06s connected.
Preliminary Technical Data
ADT7470
INTERRUPT FUNCTIONALITY AND STATUS REGISTERS
LIMIT VALUES
16-BIT LIMITS
Associated with each measurement channel on the ADT7470
are high and low limits. These can form the basis of system
status monitoring: a status bit can be set for any out-of-limit
condition and be detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to automatically flag a
service processor or microcontroller of out-of-limit conditions
as they occur.
The fan tach measurements are 16-bit results. The fan tach
limits are also 16-bits; consisting of 2 bytes; a high byte and low
byte. On the ADT7470 it is possible to set both high and low
speed fan limits for overspeed and underspeed or stall conditions.
Be aware that since fan tach period is actually being measured,
exceeding the limit by 1 indicates a slow or stalled fan. Likewise,
exceeding the high speed limit by 1 generates an overspeed
condition.
8-BIT LIMITS
Table 8. Fan Underspeed Limit Registers
The following table lists the 8-bit limits on the ADT7470.
Table 7. Temperature Limit Registers (8-Bit Limits)
Register Address
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
Description
Temperature 1 Low Limit
Temperature 1 High Limit
Temperature 2 Low Limit
Temperature 2 High Limit
Temperature 3 Low Limit
Temperature 3 High Limit
Temperature 4 Low Limit
Temperature 4 High Limit
Temperature 5 Low Limit
Temperature 5 High Limit
Temperature 6 Low Limit
Temperature 6 High Limit
Temperature 7 Low Limit
Temperature 7 High Limit
Temperature 8 Low Limit
Temperature 8 High Limit
Temperature 9 Low Limit
Temperature 9 High Limit
Temperature 10 Low Limit
Temperature 10 High Limit
Default
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
Register Address
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
Description
Tach 1 Min Low Byte
Tach 1 Min High Byte
Tach 2 Min Low Byte
Tach 2 Min High Byte
Tach 3 Min Low Byte
Tach 3 Min High Byte
Tach 4 Min Low Byte
Tach 4 Min High Byte
Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Table 9. Fan Overspeed Limit Registers
Register Address
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
Rev. PrA | Page 13 of 40
Description
Tach 1 Max Low Byte
Tach 1 Max High Byte
Tach 2 Max Low Byte
Tach 2 Max High Byte
Tach 3 Max Low Byte
Tach 3 Max High Byte
Tach 4 Max Low Byte
Tach 4 Max High Byte
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADT7470
Preliminary Technical Data
OUT-OF-LIMIT COMPARISONS
Once all limits have been programmed, the ADT7470 can be
enabled monitoring. The ADT7470 measures all parameters in
round-robin format and set the appropriate status bit for out-oflimit conditions. Comparisons are done differently depending
on whether the measured value is being compared to a high or
low limit.
High Limit: > Comparison Performed
Low Limit: ≤ Comparison Performed
NO INT
NO INT
TEMP >
LOW LIMIT
04684-0-014
TEMP =
HIGH LIMIT
INT
LOW LIMIT
HIGH LIMIT
04684-0-015
INT
Figure 15. Temperature = Low Limit—INT Occurs
TEMP >
HIGH LIMIT
Figure 17. Temperature > High Limit—INT Occurs
Rev. PrA | Page 14 of 40
04684-0-017
Figure 16. Temperature = High Limit—No INT
Figure 14. Temperature > Low Limit—No INT
TEMP =
LOW LIMIT
04684-0-016
HIGH LIMIT
LOW LIMIT
Preliminary Technical Data
ADT7470
The monitoring cycle begins when a one is written to the start
bit (Bit 0) of Configuration Register 1 (Register 0x40). Each fan
tach input is monitored in turn, and as each measurement is
completed, the result is automatically stored in the appropriate
value register. Multiple temperature channels can also be monitored by clocking in temperatures by using the PWM_IN pin.
The temperature measurement function is addressed in hardware
and requires no software intervention. The monitoring cycle
continues unless disabled by writing a 0 to Bit 0 of Configuration
Register 1.
The rate of temperature measurement updates depends on the
nominal conversion rate of the TMP05/TMP06 temperature
sensor (approximately 120 ms) and on the number of TMP05s
daisy-chained together. The total monitoring cycle time is the
temperature conversion time multiplied by the number of
temperature channels being monitored.
Fan tach measurements are taken in parallel and are not
synchronized with the temperature measurements in any way.
STATUS REGISTERS
The results of limit comparisons are stored in Status Registers 1
and 2. The status register bit for each channel reflects the status
of the last measurement and limit comparison on that channel.
If a measurement is within limits, the corresponding status
register bit is cleared to 0. If the measurement is out-of-limits,
the corresponding status register bit is set to 1.
The state of the various measurement channels may be polled
by reading the status registers over the serial bus. Bit 7 (OOL) of
Status Register 1 (Register 0x41) when 1 means that an out-oflimit event has been flagged in Status Register 2. This means
that you need to read Status Register 2 only when the OOL bit is
set. Alternatively, Pin 11 operates as an SMBALERT output and
can be connected back to the system service processor. This
automatically notifies the system supervisor of an out-of-limit
condition. Reading the status registers clears the appropriate
status bit as long as the error condition that caused the interrupt
has cleared. Status register bits are “sticky.” Whenever a status bit
is set, indicating an out-of-limit condition, it remains set even if
the event that caused it has gone away (until read). The only way
to clear the status bit is to read the status register when the event
has gone away. Interrupt status mask registers (Registers 0x72
and 0x73) allow individual interrupt sources to be masked from
causing an SMBALERT. However, if one of these masked
interrupt sources goes out-of-limit, its associated status bit is
still set in the interrupt status registers. This allows the device to
be periodically polled to determine if an error condition has
subsided, without unnecessarily tying up precious system
resources handling interrupt service routines. The issue is that
the device could potentially interrupt the system every monitoring cycle (< 1 sec) as long as a measurement parameter remains
out-of-limit. Masking eliminates unwanted system interrupts.
OOL = 1 DENOTES A PARAMETER
MONITORED THROUGH STATUS REG 2
IS OUT-OF-LIMIT
04684-0-018
MONITORING CYCLE TIME
Figure 18. Interrupt Status Register 1
Table 10. Interrupt Status Register 1 (Register 0x41)
Bit No. and Value
Bit 7 (OOL) = 1,
Bit 6 (R7T) = 1
Bit 5 (R6T) = 1
Bit 4 (R5T) = 1
Bit 3 (R4T) = 1
Bit 2 (R3T) = 1
Bit 1 (R2T) = 1
Bit 0 (R1T) = 1
Description
Denotes a bit in Status Register 2 is set and Status Register 2 should now be read.
TMP05 Temperature 7 high or low limit has been exceeded.
TMP05 Temperature 6 high or low limit has been exceeded.
TMP05 Temperature 5 high or low limit has been exceeded.
TMP05 Temperature 4 high or low limit has been exceeded.
TMP05 Temperature 3 high or low limit has been exceeded.
TMP05 Temperature 2 high or low limit has been exceeded.
TMP05 Temperature 1 high or low limit has been exceeded.
Rev. PrA | Page 15 of 40
Preliminary Technical Data
F4P = 1, FAN4 OR PROCHOT
TIMER IS OUT-OF-LIMIT
04684-0-019
ADT7470
Figure 19. Interrupt Status Register 2
Table 11. Interrupt Status Register 2 (Register 0x42)
Bit No. and Value
Bit 7 (Fan 4) = 1
Bit 6 (Fan 3) = 1
Bit 5 (Fan 2) = 1
Bit 4 (Fan 1) = 1
Bit 3 (NORM) = 1
Bit 2 (R10T) = 1
Bit 1 (R9T) = 1
Bit 0 (R8T) = 1
Description
Indicates that Fan 4 has dropped below minimum speed or is above maximum speed.
Indicates that Fan 3 has dropped below minimum speed or is above maximum speed.
Indicates that Fan 2 has dropped below minimum speed or is above maximum speed.
Indicates that Fan 1 has dropped below minimum speed or is above maximum speed.
Indicates that the temperatures are below TMIN and that the fans are supposed to be off.
TMP05 Temperature 10 high or low limit has been exceeded.
TMP05 Temperature 9 high or low limit has been exceeded.
TMP05 Temperature 8 high or low limit has been exceeded.
SMBALERT INTERRUPT BEHAVIOR
HANDLING SMBALERT INTERRUPTS
The ADT7470 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status bits
behave when writing interrupt handler software.
To prevent the system from being tied up servicing interrupts, it
is recommend to handle the SMBALERT interrupt as follows:
HIGH LIMIT
HIGH LIMIT
TEMPERATURE
"STICKY"
STATUS
BIT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
04684-0-020
"STICKY"
STATUS
BIT
CLEARED ON READ
(TEMP BELOW LIMIT)
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
Figure 20. SMBALERT and Status Bit Behavior
Figure 20 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides AND the status register are read. The status bits are
referred to as sticky since they remain set until read by software.
This ensures that an out-of-limit event cannot be missed if
software is polling the device periodically. Note that the
SMBALERT output remains low for the entire duration that a
reading is out-of-limit and until the status register has been
read. This has implications on how software handles the
interrupt.
04684-0-021
TEMPERATURE
Figure 21. How Masking the Interrupt Source Affects SMBALERT Output
1.
Detect the SMBALERT assertion.
2.
Enter the interrupt handler.
3.
Read the status registers to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Registers 0x72 and 0x73).
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 21.
Rev. PrA | Page 16 of 40
Preliminary Technical Data
ADT7470
MASKING INTERRUPT SOURCES
ENABLING THE SMBALERT INTERRUPT OUTPUT
Interrupt Mask Registers 1 and 2 are located at Addresses 0x72
and 0x73. These allow individual interrupt sources to be masked
out to prevent unwanted SMBALERT interrupts. Note that
masking an interrupt source only prevents the SMBALERT
output from being asserted; the appropriate status bit is still set
as usual. This is useful if the system polls the monitoring
devices periodically to determine whether or not out-of-limit
conditions have subsided, without tying up time-critical system
resources.
The SMBALERT interrupt output is a dedicated function that is
provided on Pin 14 to signal out-of-limit conditions to a host or
system processor. Because this is a dedicated function, it is
important that limit registers get programmed before monitoring
gets enabled, to prevent spurious interrupts occurring on the
SMBALERT pin. Although the SMBALERT output cannot be
specifically disabled, interrupt sources can be masked to prevent
SMBALERT assertions. Monitoring is enabled when Bit 0
(STRT) of Configuration Register 1 (Register 0x40) is set to 1.
Table 12. Interrupt Mask Register 1 (Register 0x72)
Bit No. and Value
Bit 7 (OOL) = 1
Bit 6 (R7T) = 1
Bit 5 (R6T) = 1
Bit 4 (R5T) = 1
Bit 3 (R4T) = 1
Bit 2 (R3T) = 1
Bit 1 (R2T) = 1
Bit 0 (R1T) = 1
Description
Masks SMBALERT for any alert condition flagged in Status Register 2.
Masks SMBALERT for TMP05 Temperature 7.
Masks SMBALERT for TMP05 Temperature 6.
Masks SMBALERT for TMP05 Temperature 5.
Masks SMBALERT for TMP05 Temperature 4.
Masks SMBALERT for TMP05 Temperature 3.
Masks SMBALERT for TMP05 Temperature 2.
Masks SMBALERT for TMP05 Temperature 1.
Table 13. Interrupt Mask Register 2 (Register 0x73)
Bit No. and Value
Bit 7 (Fan 4) = 1
Bit 6 (Fan 3) = 1
Bit 5 (Fan 2) = 1
Bit 4 (Fan 1) = 1
Bit 3 (NORM) = 1
Bit 2 (R10T) = 1
Bit 1 (R9T) = 1
Bit 0 (R8T) = 1
Description
Masks SMBALERT for Fan 4 overspeed/ underspeed conditions.
Masks SMBALERT for Fan 3 overspeed/ underspeed conditions.
Masks SMBALERT for Fan 2 overspeed/ underspeed conditions.
Masks SMBALERT for Fan 1 overspeed/ underspeed conditions.
Masks SMBALERT for temperatures below TMIN.
Masks SMBALERT for TMP05 Temperature 10.
Masks SMBALERT for TMP05 Temperature 9.
Masks SMBALERT for TMP05 Temperature 8.
Rev. PrA | Page 17 of 40
ADT7470
Preliminary Technical Data
FAN DRIVE USING PWM CONTROL
meets the fan’s current requirements. This is the only major
difference between a MOSFET and NPN transistor fan driver
circuit.
When using transistors, ensure that the base resistor is chosen
such that the transistor is fully saturated when the fan is
powered on. Otherwise, there are power inefficiencies in the
implementation.
12V
12V
10kΩ
12V
FAN
TACH/AIN
10kΩ
4.7kΩ
TACH
1N4148
3.3V
ADT7470
470Ω
Q1
MMBT2222
PWM
04684-0-023
The ADT7470 uses pulse width modulation (PWM) to control
fan speed. This relies on varying the duty cycle (or on/off ratio)
of a square wave applied to the fan, to vary the fan speed. Two
main control schemes are used: low frequency and high
frequency PWM. For low frequency, low-side drive, the external
circuitry required to drive a fan using PWM control is extremely
simple. A single NMOS FET is the only drive device required.
The specifications of the MOSFET depends on the maximum
current required by the fan being driven. Typical notebook fans
draw a nominal 170 mA, therefore SOT devices can be used
where board space is a concern. In desktops, fans can typically
draw 250 mA to 300 mA each. If the user need to drive several
fans in parallel from a single PWM output, or drive larger server
fans, the MOSFET needs to handle the higher current requirements. The only other stipulation is that the MOSFET should
have a gate voltage drive, VGS < 3.3 V for direct interfacing to
the PWM_OUT pin of the TSM devices. VGS of the chosen
MOSFET can be greater than 3.3 V as long as the pull-up on its
gate is tied to 5 V. The MOSFET should also have a low onresistance to ensure that there is not significant voltage drop
across the FET. This would reduce the voltage applied across the
fan and therefore the maximum operating speed of the fan.
Figure 23. Driving a 3-Wire Fan Using an NPN Transistor
Figure 22 shows how a 3-wire fan can be driven using low
frequency PWM control where the control method is low-side,
low frequency switching.
12V
V
10kΩ
12V
12V
10kΩ
1N4148
TACH
TACH
10kΩ
4.7kΩ
12V
TACH/AIN
10kΩ
4.7kΩ
ADT7470
TACH
FAN
GND
1N4148
ADT7470
10kΩ
3.3V
PWM
PWM_IN
04684-0-024
10kΩ
Q1
NDT3055L
Figure 24. Driving a 4-Wire Fan
04684-0-022
PWM
3.3V
High Frequency vs. Low Frequency
Figure 22. Driving a 3-Wire Fan Using an N-Channel MOSFET
Figure 22 shows the ideal interface when interfacing a tach
signal from a 12 V fan (or greater voltage) to a 5 V (or less) logic
device. In all cases, the tach signal from the fan must be kept
below 5 V maximum to prevent damage to the ADT7470. The
three resistors in Figure 22 ensure that the tach voltage is kept
within safe levels for typical desktop and notebook systems.
Figure 23 shows a fan drive circuit using an NPN transistor such
as a general-purpose MMBT2222. While these devices are
inexpensive, they tend to have much lower current handling
capabilities and higher on resistance than MOSFETs. When
choosing a transistor, care should be taken in ensuring that it
One of the important features of fan controllers is the PWM
drive frequency. Today, most fans are driven asynchronously at
low frequency (30 Hz to 100 Hz).Going forward, the devices
drive fans at >20 kHz. These controllers are meant to drive
4-wire fans with PWM control built-in internal to the fan. Note
that the ADT7470 supports high frequency PWM (>20 kHz) as
well as 1.4 kHz and other low frequency PWM. This allows the
user to drive 3-wire or 4-wire fans.
Rev. PrA | Page 18 of 40
Preliminary Technical Data
ADT7470
FAN SPEED MEASUREMENT
TACH INPUTS
R1 and R2 should be chosen such that
Signal conditioning in the ADT7470 accommodates the slow
rise and fall times typical of fan tachometer outputs. The
maximum input signal range is 0 V to 5 V, even where VCC is less
than 5 V. In the event that these inputs are supplied from fan
outputs that exceed 0 V to 5 V, either resistive attenuation of the
fan signal or diode clamping must be included to keep inputs
within an acceptable range. Figure 25 to Figure 28 show circuits
for most common fan tach outputs.
2 V < VPULL-UP × R2/(RPULL-UP + R1 + R2) < 5 V
The fan inputs have an input resistance of nominally 160 kΩ to
ground, so this should be taken into account when calculating
resistor values.
With a pull-up voltage of 12 V and pull-up resistor less than
1 kΩ, suitable values for R1 and R2 would be 100 kΩ and 47 kΩ.
This gives a high input voltage of 3.83 V.
VCC
12V
If the fan tach output has a resistive pull-up to VCC then it can
be connected directly to the fan input, as shown in Figure 25.
12V
PULLUP
TYP. <1kΩ
OR TOTEM-POLE
VCC
PULLUP
4.7kΩ
TYP.
FAN SPEED
COUNTER
04684-0-025
TACH
R1
10kΩ
TACH
FAN SPEED
COUNTER
ZD1
ZENER*
*CHOOSE ZD1 VOLTAGE APPROX. 0.8 × VCC
ADT7470
TACH
OUTPUT
ADT7470
TACH
O/P
04684-0-027
Pins 6, 7, 4, and 9 are open-drain tach inputs intended for fan
speed measurement.
Figure 27. Fan with Strong Tach.
Pull-up to >VCC or totem-pole output, clamped with zener and resistor.
VCC
12V
Figure 25. Fan with Tach Pull-Up to +VCC
TACH
OUTPUT
TACH
OUTPUT
ADT7470
TACH
*CHOOSE ZD1 VOLTAGE APPROX. 0.8 × VCC
R2*
*SEE TEXT
FAN SPEED MEASUREMENT
FAN SPEED
COUNTER
ZD1*
ZENER
FAN SPEED
COUNTER
Figure 28. Fan with Strong Tach.
Pull-up to > VCC or totem-pole output, attenuated with R1/R2.
04684-0-026
PULLUP
4.7kΩ
TYP.
TACH
R1*
VCC
12V
ADT7470
<1kΩ
04684-0-028
If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 5 V) then the fan output can be clamped with a
Zener diode, as shown in Figure 26. The Zener diode voltage
should be chosen so that it is greater than VIH of the tach input
but less than 5 V, allowing for the voltage tolerance of the Zener.
A value of between 3 V and 5 V is suitable.
Figure 26. Fan with Tach.
Pull-up to voltage >5 V, for example., 12 V clamped with Zener diode.
If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 5 V), then the fan output can be clamped with a
Zener diode, as shown in Figure 26. The Zener diode voltage
should be chosen so that it is greater than VIH of the tach input
but less than 5 V, allowing for the voltage tolerance of the Zener.
A value of between 3 V and 5 V is suitable. If the fan has a
strong pull-up (less than 1 kΩ) to 12 V, or a totem-pole output,
then a series resistor can be added to limit the Zener current, as
shown in Figure 27. Alternatively, a resistive attenuator may be
used, as shown in Figure 28.
The fan counter does not count the fan tach output pulses
directly, because the fan speed may be less than 1000 RPM and
it would take several seconds to accumulate a reasonably large
and accurate count. Instead, the period of the fan revolution is
measured by gating an on-chip 90 kHz oscillator into the input
of a 16-bit counter for N periods of the fan tach output, as shown
in Figure 29, so the accumulated count is actually proportional
to the fan tachometer period and inversely proportional to the
fan speed.
N, the number of pulses counted is determined by the settings
of Register 0x43 (fan pulses per revolution register). This register
contains two bits for each fan, allowing 1, 2 (default), 3, or 4 tach
pulses to be counted.
Rev. PrA | Page 19 of 40
ADT7470
Preliminary Technical Data
Fan Tach Limit Registers
CLOCK
The fan tach limit registers are 16-bit values consisting of two
bytes. Minimum limits determine fan underspeed limits while
maximum limits determine fan overspeed settings.
PWM
Table 15. Fan Tach Limit Registers
TACH
1
2
04684-0-029
3
4
Figure 29. Fan Speed Measurement
Fan Speed Measurement Registers
The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7470.
Table 14. Fan Speed Measurement Registers
Register Address
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
Description
Tach 1 Low Byte
Tach 1 High Byte
Tach 2 Low Byte
Tach 2 High Byte
Tach 3 Low Byte
Tach 3 High Byte
Tach 4 Low Byte
Tach 4 High Byte
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Register Address
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
Description
Tach 1 Min Low Byte
Tach 1 Min High Byte
Tach 2 Min Low Byte
Tach 2 Min High Byte
Tach 3 Min Low Byte
Tach 3 Min High Byte
Tach 4 Min Low Byte
Tach 4 Min High Byte
Tach 1 Max Low Byte
Tach 1 Max High Byte
Tach 2 Max Low Byte
Tach 2 Max High Byte
Tach 3 Max Low Byte
Tach 3 Max High Byte
Tach 4 Max Low Byte
Tach 4 Max High Byte
Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Fan Speed Measurement Rate
The fan tach readings are normally updated once every second.
Calculating Fan Speed
Reading Fan Speed from the ADT7470
If fan speeds are being measured, this involves a 2-register read
for each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers have been read from. This prevents erroneous tach
readings.
The fan tachometer reading registers report back the number of
11.11 ms period clocks (90 kHz oscillator) gated to the fan
speed counter, from the rising edge of the first fan tach pulse to
the rising edge of the third fan tach pulse (assuming 2 pulses
per revolution is being counted). Since the device is essentially
measuring the fan tach period, the higher the count value, the
slower the fan is actually running. A 16-bit fan tachometer
reading of 0xFFFF indicates either that the fan has stalled or is
running very slowly (<100 RPM).
High Limit: Comparison Performed
Assuming a fan with 2 pulses/revolution (and 2 pulses/rev being
measured) fan speed is calculated by
Fan Speed (RPM) = (90,000 × 60)/ Fan Tach Reading
where Fan Tach Reading is the 16-bit fan tachometer reading.
For example:
Tach 1 High Byte (Reg 0x2B) = 0x17
Tach 1 Low Byte (Reg 0x2A) = 0xFF
What is Fan 1 speed in RPM?
Fan 1 tach reading = 0x17FF = 6143 decimal.
RPM = (f × 60)/Fan 1 tach reading
RPM = (90000 × 60)/6143
Fan Speed = 879 RPM
Because the actual fan tach period is being measured, exceeding
a fan tach limit by 1 sets the appropriate status bit and can be
used to generate an SMBALERT.
Rev. PrA | Page 20 of 40
Preliminary Technical Data
ADT7470
Fan Pulses per Revolution
Different fan models can output either 1, 2, 3, or 4 tach pulses
per revolution. Once the number of fan tach pulses has been
determined, it can be programmed in to the fan pulses per
revolution register (Register 0x43) for each fan. Alternatively,
this register can be used to determine the number or pulses/
revolution output by a given fan. By plotting fan speed
measurements at 100% speed with different pulses/rev setting,
the smoothest graph with the lowest ripple determines the
correct pulses/rev value.
Fan Spin Up
The ADT7470 has a unique fan spin-up function. Fans are 100%
on if there is no interaction with the ADT7470.It incorporates a
2 second bus alive/dead detection feature. If no bus activity is
seen and the ADT7470 is not specifically written to within 2
seconds, then the PWM outputs auto drive 100%. This is useful
where a system lock-up occurs before software has a chance to
configure the basic system devices. This is intended as a bus
communication failsafe feature. Where normal communication
occurs, the fans are given “grace time” to spin up, before the
PWM auto throttles back to some normal speed. For example,
under normal conditions the ADT7470 spins the fan at 100%
PWM duty cycle until 2 tach pulses are detected on the tach
input. Once 2 pulses are detected, the PWM duty cycle goes to
the expected running value, for example, 33%. The advantage of
this is that fans with different spin-up characteristics that take
different times to overcome inertia still spin up and not generate
excess acoustic noise. The ADT7470 just runs the fans fast
enough to overcome inertia and is quieter on spin-up than fans
programmed to spin-up for a fixed spin-up time.
Fan Start Up Timeout
To prevent false interrupts being generated as a fan spins up
(because it is below running speed), the ADT7470 includes a
fan start-up timeout function. This is the time limit allowed for
2 tach pulses to be detected on spin-up. The fan start-up timeout
is fixed at 2 seconds, and if no tach pulses occur within 2 seconds
of the start of spin-up, a fan fault is detected and flagged in the
interrupt status registers.
Table 16. PWM1/PWM2 Configuration (Register 0x68)
Bit No.
<0>
<1>
<2>
<3>
<4>
Mnenonic
FAIL2
FAIL1
OVT2
OVT1
INV2
<5>
INV1
<6>
BHVR2
<7>
BHVR1
Description
Setting this bit to 1 causes all fans to spin 100% if Fan 2 fails.
Setting this bit to 1 causes all fans to spin 100% if Fan 1 fails.
Setting this bit to 1 causes Fan 2 to spin 100% if any overtemperature condition occurs.
Setting this bit to 1 causes Fan 1 to spin 100% if any overtemperature condition occurs.
Setting this bit to 1 inverts the PWM2 out put.
Default = 0 drives a logic high for 100% duty cycle.
Setting this bit to 1 inverts the PWM1 out put.
Default = 0 drives a logic high for 100% duty cycle.
This bit determines fan behavior for PWM2 output.
0 = Manual mode (PWM2 duty cycle controlled in software).
1 = Fastest speed calculated by all temperatures control PWM2 (automatic fan control mode).
This bit determines fan behavior for PWM1 output.
0 = Manual mode (PWM1 duty cycle controlled in software).
1 = Fastest speed calculated by all temperatures control PWM1 (automatic fan control mode).
Table 17. PWM3/PMW4 Configuration (Register 0x69)
Bit
<0>
<1>
<2>
<3>
<4>
Mnemonic
FAIL4
FAIL3
OVT4
OVT3
INV4
<5>
INV3
<6>
BHVR4
<7>
BHVR3
Description
Setting this bit to 1 causes all fans to spin 100% if Fan 4 fails.
Setting this bit to 1 causes all fans to spin 100% if Fan 3 fails.
Setting this bit to 1 causes Fan 4 to spin 100% if any overtemperature condition occurs.
Setting this bit to 1 causes Fan 3 to spin 100% if any overtemperature condition occurs.
Setting this bit to 1 inverts the PWM4 output.
Default = 0 drives a logic high for 100% duty cycle.
Setting this bit to 1 inverts the PWM3 output.
Default = 0 drives a logic high for 100% duty cycle.
This bit determines fan behavior for PWM4 output.
0 = Manual mode (PWM4 duty cycle controlled in software).
1 = Fastest speed calculated by all temperatures control PWM4 (automatic fan control mode).
This bit determines fan behavior for PWM3 output.
0 = Manual mode (PWM3 duty cycle controlled in software).
1 = Fastest speed calculated by all temperatures control PWM3 (automatic fan control mode).
Rev. PrA | Page 21 of 40
ADT7470
Preliminary Technical Data
FAN SPEED CONTROL
PWM LOGIC STATE
Example 1: For a PWM Duty Cycle of 50%
The PWM outputs can be programmed to be high for 100%
duty cycle (non-inverted) or low for 100% duty cycle (inverted).
Table 18. PWM1/PWM2 Configuration (Register 0x68)
Bit
<5>
Mnemonic
INV1
<4>
INV2
Description
0 = Logic high for 100% PWM1 duty cycle.
1 = Logic low for 100% PWM1 duty cycle.
0 = Logic high for 100% PWM2 duty cycle.
1 = Logic low for 100% PWM2 duty cycle.
Table 19. PWM3/PWM4 Configuration (Register 69H)
Bit
<5>
Mnemonic
INV3
<4>
INV4
Description
0 = Logic high for 100% PWM3 duty cycle.
1 = Logic low for 100% PWM3 duty cycle.
0 = Logic high for 100% PWM4 duty cycle.
1 = Logic low for 100% PWM4 duty cycle.
Value (decimal) = 50/0.39 = 128 decimal
Value = 128 decimal or 80 hex.
Example 2: For a PWM Duty Cycle of 33%
Value (decimal) = 33/0.39 = 85 decimal
Value = 85 decimal or 54 hex.
Table 20. PWM Duty Cycle Registers
Register Address
0x32
0x33
0x34
0x35
Description
PWM1 Duty Cycle
PWM2 Duty Cycle
PWM3 Duty Cycle
PWM4 Duty Cycle
Default
0xFF (100%)
0xFF (100%)
0xFF (100%)
0xFF (100%)
By reading the PWMx current duty cycle registers you can keep
track of the current duty cycle on each PWM output, even when
the fans are running in automatic fan speed control mode.
PWM Drive Frequency
The PWM drive frequency is variable on the ADT7470. The
PWM drive frequency is a high frequency signal greater than
20 kHz. This is most suitable for use with 4-wire fans. It is also
possible to use low frequency PWM drive, such as 1.4 kHz.
The ADT7470 allows the duty cycle of any PWM output to be
manually adjusted. This can be useful if users want to change
fan speed in software or want to adjust PWM duty cycle output
for test purposes. The PWM current duty cycle registers
(Register 0x32 to 0x35) can be written with 8-bit values in
manual fan speed control mode to manually adjust the speeds
of the cooling fans.
PWM Configuration (Register 0X68, 0X69)
These registers control the behavior of the fans under certain
conditions as well as define whether the fans are being used in
manual or automatic fan speed control mode.
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100%. This allows PWM duty cycle to be set in steps
of 0.39%.
The value to be programmed into the PWMMIN register is
given by
VARY PWM DUTY
CYCLE WITH 8-BIT
RESOLUTION
04684-0-030
MANUAL FAN SPEED CONTROL
Figure 30. Control PWM Duty Cycle Manually with a Resolution of 0.39%
AUTOMATIC FAN SPEED CONTROL
In automatic fan speed control mode, fan speed automatically
varies with temperature and without CPU intervention, once
initial parameters are set up. The advantage of this is that when
a system hangs, the user is guaranteed that the system is protected
from overheating. The automatic fan speed control incorporates
a feature called dynamic TMIN calibration. This feature reduces
the design effort required to program the automatic fan speed
control loop. For more information and how to program the
automatic fan speed control loop and dynamic TMIN calibration,
see Application Note AN-613, Programming the Automatic Fan
Speed Control Loop.
Value (decimal) = PWMMIN/0.39
Rev. PrA | Page 22 of 40
Preliminary Technical Data
ADT7470
ADT7470 REGISTERS
Table 21. ADT7470 Register Map
Address
0x20
R/W
R
0x21
R
0x22
R
0x23
R
0x24
R
0x25
R
0x26
R
0x27
R
0x28
R
0x29
R
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
R
R
R
R
R
R
R
R
R/W
0x33
R/W
0x34
R/W
0x35
R/W
0x36
R
0x37
0x38
R/W
R/W
0x39
R/W
0x3A
R/W
0x3B
R/W
0x3C
0x3D
0x3E
R/W
R
R
0x3F
0x40
R
R/W
0x41
R
Description
Temperature 1
Reading
Temperature 2
Reading
Temperature 3
Reading
Temperature 4
Reading
Temperature 5
Reading
Temperature 6
Reading
Temperature 7
Reading
Temperature 8
Reading
Temperature 9
Reading
Temperature 10
Reading
Tach 1 Low Byte
Tach 1 High Byte
Tach 2 Low Byte
Tach 2 High Byte
Tach 3 Low Byte
Tach 3 High Byte
Tach 4 Low Byte
Tach 4 High Byte
PWM1 Current Duty
Cycle
PWM2 Current Duty
Cycle
PWM3 Current Duty
Cycle
PWM4 Current Duty
Cycle
Fans Not Present
Register
ADI Test register 1
PWM1 Max Duty
Cycle
PWM2 Max Duty
Cycle
PWM3 Max Duty
Cycle
PWM4 Max Duty
Cycle
ADI Test register 2
Device ID Register
Company ID
Number
Revision Number
Configuration
Register 1
Interrupt Status
Register 1
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
7
15
7
15
7
15
7
15
7
6
14
6
14
6
14
6
14
6
5
13
5
13
5
13
5
13
5
4
12
4
12
4
12
4
12
4
3
11
3
11
3
11
3
11
3
2
10
2
10
2
10
2
10
2
1
9
1
9
1
9
1
9
1
0
8
0
8
0
8
0
8
0
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
Fan 4
Fan 3
Fan 2
Fan 1
0x00
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0x00
0xFF
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
0x00
0x70
0x41
VER
T05_S
TB
OOL
VER
HF_LF
VER
FST_TC
H
R6T
VER
LOCK
STP
TODIS
STP
FSPD
STP
TEST
STP
STRT
0x00
0x01
R5T
R4T
R3T
R2T
R1T
0xXX
R7T
Rev. PrA | Page 23 of 40
Lockable
y
y
ADT7470
Address
0x42
R/W
R
0x43
R/W
0x44
R/W
0x45
R/W
0x46
R/W
0x47
R/W
0x48
R/W
0x49
R/W
0x4A
R/W
0x4B
R/W
0x4C
R/W
0x4D
R/W
0x4E
R/W
0x4F
R/W
0x50
R/W
0x51
R/W
0x52
R/W
0x53
R/W
0x54
R/W
0x55
R/W
0x56
R/W
0x57
R/W
0x58
R/W
0x59
R/W
0x5A
R/W
0x5B
R/W
0x5C
R/W
0x5D
R/W
0x5E
R/W
0x5F
R/W
Preliminary Technical Data
Description
Interrupt Status
Register 2
Fan Pulses per
Revolution
Temperature 1 Low
Limit
Temperature 1
High Limit
Temperature 2 Low
Limit
Temperature 2
High Limit
Temperature 3 Low
Limit
Temperature 3
High Limit
Temperature 4 Low
Limit
Temperature 4
High Limit
Temperature 5 Low
Limit
Temperature 5
High Limit
Temperature 6 Low
Limit
Temperature 6
High Limit
Temperature 7 Low
Limit
Temperature 7
High Limit
Temperature 8 Low
Limit
Temperature 8
High Limit
Temperature 9 Low
Limit
Temperature 9
High Limit
Temperature 10
Low Limit
Temperature 10
High Limit
Tach 1 Min Low
Byte
Tach 1 Min High
Byte
Tach 2 Min Low
Byte
Tach 2 Min High
Byte
Tach 3 Min Low
Byte
Tach 3 Min High
Byte
Tach 4 Min Low
Byte
Tach 4 Min High
Byte
Bit 7
Fan 4
Bit 6
Fan 3
Bit 5
Fan 2
Bit 4
Fan 1
Bit 3
NORM
Bit 2
R10T
Bit 1
R9T
Bit 0
R8T
Default
0xXX
Fan 4
Fan 4
Fan 3
Fan 3
Fan 2
Fan 2
Fan 1
Fan 1
0x55
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0x81
7
6
5
4
3
2
1
0
0x7F
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
Rev. PrA | Page 24 of 40
Lockable
Preliminary Technical Data
Address
0x60
R/W
R/W
0x61
R/W
0x62
R/W
0x63
R/W
0x64
R/W
0x65
R/W
0x66
R/W
0x67
R/W
0x68
R/W
0x69
R/W
0x6A
R/W
0x6B
R/W
0x6C
R/W
0x6D
R/W
0x6E
0x6F
0x70
0x71
0x72
R/W
R/W
R/W
R/W
R/W
0x73
R/W
0x74
R/W
0x75
0x76
0x77
0x78
R/W
R/W
R/W
R
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Tach 1 Max Low
Byte
Tach 1 Max High
Byte
Tach 2 Max Low
Byte
Tach 2 Max High
Byte
Tach 3 Max Low
Byte
Tach 3 Max High
Byte
Tach 4 Max Low
Byte
Tach 4 Max High
Byte
PWM1/2 Config
Register
PWM3/4 Config
Register
PWM1 Min Duty
Cycle
PWM2 Min Duty
Cycle
PWM3 Min Duty
Cycle
PWM4 Min Duty
Cycle
Temperature 1 TMIN
Temperature 2 TMIN
Temperature 3 TMIN
Temperature 4 TMIN
Interrupt Mask 1
Register
Interrupt Mask 2
Register
Configuration
Register 2
Enhance Acoustics 1
Enhance Acoustics 2
ADI Test Register 3
Max TMP05
Temperature
TMP05 Coef Option 1
TMP05 Coef Option 2
TMP05 Coef Option 3
TMP05 Zone Select 1
TMP05 Zone Select 2
TMP05 Coef Select 1
TMP05 Coef Select 2
GPIO Config
GPIO Status
ADT7470
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0x00
15
14
13
12
11
10
9
8
0x00
7
6
5
4
3
2
1
0
0x00
15
14
13
12
11
10
9
8
0x00
7
6
5
4
3
2
1
0
0x00
15
14
13
12
11
10
9
8
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
BHVR
BHVR
INV1
INV2
OVT1
OVT2
FAIL1
FAIL2
0x00
y
BHVR
BHVR
INV3
INV4
OVT3
OVT4
FAIL3
FAIL4
0x00
y
7
6
5
4
3
2
1
0
0x80
y
7
6
5
4
3
2
1
0
0x80
y
7
6
5
4
3
2
1
0
0x80
y
7
6
5
4
3
2
1
0
0x80
y
7
7
7
7
OOL
6
6
6
6
R7T
5
5
5
5
R6T
4
4
4
4
R5T
3
3
3
3
R4T
2
2
2
2
R3T
1
1
1
1
R2T
0
0
0
0
R1T
0x5A
0x5A
0x5A
0x5A
0x00
3
Fan 4
Fan 3
Fan 2
Fan 1
NORM
R10T
R9T
R8T
0x00
SHDN
FREQ
FREQ
FREQ
T4_dis
T3_dis
T2_dis
T1_dis
0x00
EN1
EN3
7
7
ACOU1
ACOU3
6
6
ACOU1
ACOU3
5
5
ACOU1
ACOU3
4
4
EN2
EN4
3
3
ACOU2
ACOU4
2
2
ACOU2
ACOU4
1
1
ACOU2
ACOU4
0
0
0x00
0x00
0x00
0x00
7
7
7
7
7
7
7
7
GPIO4
6
6
6
6
6
6
6
6
GPIO3
5
5
5
5
5
5
5
5
GPIO2
4
4
4
4
4
4
4
4
GPIO1
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Rev. PrA | Page 25 of 40
Lockable
y
y
ADT7470
Preliminary Technical Data
Table 22. Register 0x20 to Register 0x29. Temperature Reading Registers (Power-On Default = 0x00)
Register Address
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Description
Temperature 1 Reading (from TMP05 sensor)
Temperature 2 Reading (from TMP05 sensor)
Temperature 3 Reading (from TMP05 sensor)
Temperature 4 Reading (from TMP05 sensor)
Temperature 5 Reading (from TMP05 sensor)
Temperature 6 Reading (from TMP05 sensor)
Temperature 7 Reading (from TMP05 sensor)
Temperature 8 Reading (from TMP05 sensor)
Temperature 9 Reading (from TMP05 sensor)
Temperature 10 Reading (from TMP05 sensor)
Readings from daisy-chained TMP05s are processed and loaded into the temperature reading registers.
Table 23. Register 0x2A to Register 0x31. Fan Tach Reading Registers (Power-On Default = 0x00)
Register Address
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Description
Tach 1 Low Byte (8 MSBs of reading)
Tach 1 High Byte (8 LSBs of reading)
Tach 2 High Byte (8 MSBs of reading)
Tach 2 Low Byte (8 LSBs of reading)
Tach 3 High Byte (8 MSBs of reading)
Tach 3 Low Byte (8 LSBs of reading)
Tach 4 High Byte (8 MSBs of reading)
Tach 4 Low Byte (8 LSBs of reading)
The fan tach reading registers count the number of 11.11 µs periods (based on an internal 90 kHz clock) that occur between a number of
consecutive fan tach pulses (default = 2). The number of tach pulses used to count can be changed using the fan pulses per revolution
register (Register 0x43). This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two
bytes are read, the low byte MUST be read first. Both the low and high bytes are then frozen until read. At power-on, these registers
contain 0x0000 until such time as the first valid fan tach measurement is read in to these registers. This prevents false interrupts from
occurring while the fans are spinning up.
A count of 0xFFFF indicates that a fan is
•
Stalled or blocked (object jamming the fan).
•
Failed (internal circuitry destroyed).
•
Not populated (the ADT7470 expects to see a fan connected to each tach. If a fan is not connected to that tach, its tach minimum
high and low byte should be set to 0xFFFF).
Table 24. Register 0x32 to Register 0x35. Current PWM Duty Cycle Registers (Power-On Default = 0xFF)
Register Address
0x32
0x33
0x34
0x35
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
PWM1 Current Duty Cycle (0% to 100% duty cycle = 0x00 to 0xFF)
PWM2 Current Duty Cycle (0% to 100% duty cycle = 0x00 to 0xFF)
PWM3 Current Duty Cycle (0% to 100% duty cycle = 0x00 to 0xFF)
PWM4 Current Duty Cycle (0% to 100% duty cycle = 0x00 to 0xFF)
The current PWM duty cycle registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed
control mode, the ADT7470 reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to
temperature in sutomatic fan speed control mode. During fan startup, these registers report back 0x00. In software mode, the PWM duty
cycle outputs can be set to any duty cycle value by writing to these registers.
Rev. PrA | Page 26 of 40
Preliminary Technical Data
ADT7470
Table 25. Register 0x36. Fans Not Present Register (Power-On Default = 0x00)
Register Address
0x36
Read/Write
Read
<0> Fan 1
<1> Fan 2
<2> Fan 3
<3> Fan 4
<4:7> Reserved
Read
Read
Read
Read
Read
Description
Fans Not Present Register.
The TEST bit in the Configuration Register (Register 0x40) invokes a fan freewheeling test to
determine how many fans are connected to the part. The results of the fan test are reflected
in the fans not present register.
A 1 indicates that Fan 1 is not present.
A 1 indicates that Fan 2 is not present.
A 1 indicates that Fan 3 is not present.
A 1 indicates that Fan 4 is not present.
Unused.
Table 26. Register 0x3D. Device ID Register (Power-On Default = 0x70)
Register Address
0x3D
Read/Write
Read/Write
Description
Device ID.
The device ID register contains the ADT7470 device ID value as a means of identifying the part over the bus.
Table 27. Register 0x3E. Company ID Register (Power-On Default = 0x41)
Register Address
0x3E
Read/Write
Read/Write
Description
Company ID.
The company ID register contains the “0x41”, the manufacturer ID number representative of Analog Devices product.
Table 28. Register 0x3F. Revision Register (Power-On Default = xxH)
Register Address
0x3F
Read/Write
Read/Write
Description
Revision Register
The revision register contains the stepping number and version of the product.
Table 29. Register 0x40. Configuration Register 1 (Power-On Default = 0x00)
Bit Name
<0> STRT
Read/Write
Read/Write
<1> TEST
Read/Write
<2> FSPD
<3> TODIS
<4> LOCK
Read/Write
Read/Write
Write Once
<5> FST_TCH
<6> HF_LF
Read/Write
Read/Write
<7> T05_STB
Read/Write
Description
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control based on the default power-up limit settings. Note that
the limit values programmed are preserved even if a Logic 0 is written to this bit and the default settings
are enabled.
Logic 1 invokes a fan free-wheeling test by running all four PWM outputs at 100% for x seconds and
monitors the fans using the tach inputs. If any of the fans are not present, then the individual fan bits in
the fans not present register is set.
Writing a 1 drives the PWM outputs to 100% for software control.
Writing a 1 enables SMBus timeout.
Once this bit is set, all lockable registers become read-only and cannot be modified until the ADT7470 is
powered down and powered up again.
Enable Fast Tach.
This bit switches between high frequency and low frequency fan drive.
0 = Default = High Frequency Fan Drive (1.4 kHz or 22.5 kHz - see Configuration Register 2, Register 0x74,
Bits <6:4>) in Table 41.
1 = Low Frequency FanDrive (frequency determined by Configuration Register 2, Register 0x74, Bits <6:4>)
in Table 41.
Select configuration for Pin 13.
0 = Default = full_speedb input.
1 = TMP05 start pulse output.
Rev. PrA | Page 27 of 40
ADT7470
Preliminary Technical Data
Table 30. Register 0x41. Interrupt Status Register 1 (Power On Default = 00H)
Bit Name
<0> R1T
Read/Write
Read-only
<1> R2T
Read-only
<2> R3T
Read-only
<3> R4T
Read-only
<4> R5T
Read-only
<5> R6T
Read-only
<6> R7T
Read-only
<7> OOL
Read-only
Description
A 1 indicates that the Remote 1 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that the Remote 2 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that the Remote 3 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that the Remote 4 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that the Remote 5 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that the Remote 6 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that the Remote 7 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that an out-of-limit event has been latched in Status Register 2. This bit is a logical OR of all
status bits in Status Register 2. Software can test this bit in isolation to determine whether any of the
temperature or fan speed readings represented by Status Register 2 are out-of-limit. This saves the need
to read Status Register 2 every interrupt or polling cycle.
Table 31. Register 0x42. Interrupt Status Register 2 (Power-On Default = 0x00)
Bit Name
<0> R8T
Read/Write
Read-only
<1> R9T
Read-only
<2> R10T
Read-only
<3> NORM
Read-only
<4> Fan 1
Read-only
<5> Fan 2
Read-only
<6> Fan 3
Read-only
<7> Fan 4
Read-only
Description
A 1 indicates that the Remote 8 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that the Remote 9 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that the Remote 10 temperature high or low limit has been exceeded.
This bit is cleared on a read of the status register only if the error condition has subsided.
A 1 indicates that the measured temperatures are normal (below TMIN) and that the fans are supposed to
be off.
A 1 indicates that Fan 1 has gone above max speed, dropped below min speed, or has stalled.
This bit is not set when the PWM 1 output is off.
A 1 indicates that Fan 2 has gone above max speed, dropped below min speed, or has stalled.
This bit is not set when the PWM 2 output is off.
A 1 indicates that Fan 3 has gone above max speed, dropped below min speed, or has stalled.
This bit is not set when the PWM 3 output is off.
A 1 indicates that Fan 4 has gone above max speed, dropped below min speed, or has stalled.
This bit is not set when the PWM 4 output is off.
Rev. PrA | Page 28 of 40
Preliminary Technical Data
ADT7470
Table 32. Register 0x43. Fan Pulses Per Revolution Register (Power On Default = 0x55)
Bit Name
<1:0> Fan 1
Read/Write
Read/Write
<3:2> Fan 2
Read/Write
<5:4> Fan 3
Read/Write
<7:6> Fan 4
Read/Write
Description
Sets the number of pulses to be counted when measuring Fan 1 speed.
Can be used to determine fan’s pulses per revolution number for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets the number of pulses to be counted when measuring Fan 2 speed.
Can be used to determine fan’s pulses per revolution number for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets the number of pulses to be counted when measuring Fan 3 speed.
Can be used to determine fan’s pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets the number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan’s
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Table 33. Register 0x44 to Register 0x57. Temperature Limit Registers
Register Address
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
Temperature 1 Low Limit
Temperature 1 High Limit
Temperature 2 Low Limit
Temperature 2 High Limit
Temperature 3 Low Limit
Temperature 3 High Limit
Temperature 4 Low Limit
Temperature 4 High Limit
Temperature 5 Low Limit
Temperature 5 High Limit
Temperature 6 Low Limit
Temperature 6 High Limit
Temperature 7 Low Limit
Temperature 7 High Limit
Temperature 8 Low Limit
Temperature 8 High Limit
Temperature 9 Low Limit
Temperature 9 High Limit
Temperature 10 Low Limit
Temperature 10 High Limit
Power-On Default
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
0x81
0x7F
Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status registers.
High Limits: An interrupt is generated when a value exceeds its high limit ( > comparison).
Low Limits: An interrupt is generated when a value is equal to or below its low limit (≤ comparison).
Rev. PrA | Page 29 of 40
ADT7470
Preliminary Technical Data
Table 34. Register 0x58 to Register 0x67. Fan Tachometer Limit Registers
Register Address
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
Tach 1 Min Low Byte
Tach 1 Min High Byte
Tach 2 Min Low Byte
Tach 2 Min High Byte
Tach 3 Min Low Byte
Tach 3 Min High Byte
Tach 4 Min Low Byte
Tach 4 Min High Byte
Tach 1 Max Low Byte
Tach 1 Max High Byte
Tach 2 Max Low Byte
Tach 2 Max High Byte
Tach 3 Max Low Byte
Tach 3 Max High Byte
Tach 4 Max Low Byte
Tach 4 Max High Byte
Power-On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Exceeding any of the tach min limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is
set in Interrupt Status Register 2 to indicate the fan failure.
Exceeding any of the tach max limit registers by 1 indicates that the fan is too fast. The appropriate status bit is set in Interrupt Status
Register 2 to indicate the fan failure.
Table 35. Register 0x68. PWM1/PWM2 Configuration Register
Register Address
0x68
Read/Write
Read/Write
Description
PWM1/PMW2 Configuration
Bit Name
<0> FAIL2
<1> FAIL1
<2> OVT2
<3> OVT1
<4> INV2
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
<5> INV1
Read/Write
<6> BHVR2
Read/Write
<7> BHVR1
Read/Write
Description
Setting this bit to 1 causes all fans to spin 100% if Fan 2 fails.
Setting this bit to 1 causes all fans to spin 100% if Fan 1 fails.
Setting this bit to 1 causes Fan 2 to spin 100% if any overtemperature condition occurs.
Setting this bit to 1 causes Fan 1 to spin 100% if any overtemperature condition occurs.
Setting this bit to 1 inverts the PWM2 output (100% = logic low).
Default = 0 drives the PWM2 output logic high for 100% duty cycle.
Setting this bit to 1 inverts the PWM1 output (100% = logic low).
Default = 0 drives the PWM1 output logic high for 100% duty cycle.
This bit assigns fan behavior for PWM2 output.
0 = Manual fan control mode (PWM duty cycle controlled in software).
1 = Fastest speed calculated by all temperatures control PWM2 (automatic fan control
mode).
This bit assigns fan behavior for PWM1 output.
0 = Manual fan control mode (PWM duty cycle controlled in software).
1 = Fastest speed calculated by all temperatures control PWM1 (automatic fan control
mode).
Rev. PrA | Page 30 of 40
Power-On Default
0x00
Preliminary Technical Data
ADT7470
Table 36. Register 0x69. PWM3/PWM4 Configuration Register
Register Address
0x69
Read/Write
Read/Write
Description
PWM3/PMW4 Configuration
Power-On Default
0x00
Bit Name
<0> FAIL4
<1> FAIL3
<2> OVT4
<3> OVT3
<4> INV4
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
<5> INV3
Read/Write
<6> BHVR4
Read/Write
<7> BHVR3
Read/Write
Description
Setting this bit to 1 causes all fans to spin 100% if Fan 4 fails.
Setting this bit to 1 causes all fans to spin 100% if Fan 3 fails.
Setting this bit to 1 causes Fan 4 to spin 100% if any overtemperature condition occurs.
Setting this bit to 1 causes Fan 3 to spin 100% if any overtemperature condition occurs.
Setting this bit to 1 inverts the PWM4 output (100% = logic low).
Default = 0 drives the PWM4 output logic high for 100% duty cycle.
Setting this bit to 1 inverts the PWM3 output (100% = logic low).
Default = 0 drives the PWM3 output logic high for 100% duty cycle.
This bit assigns fan behavior for PWM4 output.
0 = Manual fan control mode (PWM duty cycle controlled in software).
1 = Fastest speed calculated by all temperatures control PWM4 (automatic fan control
mode).
This bit assigns fan behavior for PWM3 output.
0 = Manual fan control mode (PWM duty cycle controlled in software).
1 = Fastest speed calculated by all temperatures control PWM3 (automatic fan control
mode).
Table 37. Register 0x6A to Register 0x6D. PWMMIN Duty Cycle Registers
Register Address
0x6A
0x6B
0x6C
0x6D
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
PWM1 Min Duty Cycle
PWM2 Min Duty Cycle
PWM3 Min Duty Cycle
PWM4 Min Duty Cycle
Bit Name
<7:0> PWM Duty Cycle
Read/Write
Read/Write
Description
These bits define the PWMMIN duty cycle for PWMx.
0x00 = 0% duty cycle (fan off)
0x40 = 25% duty cycle
0x80 = 50% duty cycle
0xFF = 100% duty cycle (fan full-speed)
Power-On Default
0x80 (50% duty cycle)
0x80 (50% duty cycle)
0x80 (50% duty cycle)
0x80 (50% duty cycle)
Registers 0x6A to 0x6D become read-only when the ADT7470 is in automatic fan control mode.
Table 38. Register 0x6E to Register 0x71. TMIN Registers
Register Address
0x6E
0x6F
0x70
0x71
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
Temperature 1 TMIN
Temperature 2 TMIN
Temperature 3 TMIN
Temperature 4 TMIN
Power-On Default
0x5A (90°C)
0x5A (90°C)
0x5A (90°C)
0x5A (90°C)
These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan run at
minimum speed and increase with temperature according to TMIN + TRANGE.
Rev. PrA | Page 31 of 40
ADT7470
Preliminary Technical Data
Table 39. Register 0x72. Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00)
Bit Name
<6> R7T
Read/Write
Read/Write
<7> OOL
Read/Write
<0> R7T
Read/Write
<1> R6T
Read/Write
<2> R5T
Read/Write
<3> R4T
Read/Write
<4> R3T
Read/Write
<5> R2T
Read/Write
<6> R1T
Read/Write
Description
A 1 masks the Temperature 7 value from generating an interrupt on the SMBALERT
output. The R7T bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the OOL bit from generating an interrupt on the SMBALERT output. The OOL
bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 7 value from generating an interrupt on the SMBALERT
output. The R1T bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 6 value from generating an interrupt on the SMBALERT
output. The R2T bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 5 value from generating an interrupt on the SMBALERT
output. The R3T bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 4 value from generating an interrupt on the SMBALERT
output. The R4T bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 3 value from generating an interrupt on the SMBALERT
output. The R5T bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 2 value from generating an interrupt on the SMBALERT
output. The R6T bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 1 value from generating an interrupt on the SMBALERT
output. The R7T bit is set as normal in the status register for out-of-limit conditions.
Table 40. Register 0x73. Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00)
Bit Name
<7> Fan 4
Read/Write
Read/Write
<6> Fan 3
Read/Write
<5> Fan 2
Read/Write
<4> Fan 1
Read/Write
<3> NORM
Read/Write
<2> R10T
Read/Write
<1> R9T
Read/Write
<0> R8T
Read/Write
Description
A 1 masks the Fan 4 value from generating an interrupt on the SMBALERT output.
The Fan 4 bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Fan 3 value from generating an interrupt on the SMBALERT output.
The Fan 3 bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Fan 2 value from generating an interrupt on the SMBALERT output.
The Fan 2 bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Fan 1 value from generating an interrupt on the SMBALERT output.
The Fan 1 bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the NORM bit from generating an interrupt on the SMBALERT output.
The NORM bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 10 value from generating an interrupt on the SMBALERT
output. The R10T bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 9 value from generating an interrupt on the SMBALERT
output. The R9T bit is set as normal in the status register for out-of-limit conditions.
A 1 masks the Temperature 8 value from generating an interrupt on the SMBALERT
output. The R8T bit is set as normal in the status register for out-of-limit conditions.
Rev. PrA | Page 32 of 40
Preliminary Technical Data
ADT7470
Table 41. Register 0x74. Configuration Register 2 (Power-On Default = 0x00)
Bit Name
<7> SHDN
<6:4> FREQ
Read/Write
Read/Write
Read/Write
<3> T4_dis
<2> T3_dis
<1> T2_dis
<0> T1_dis
Read/Write
Read/Write
Read/Write
Read/Write
Description
Shutdown/low current mode.
These bits control PWM1–4 frequency when the fan drive is configured as a low
frequency drive.
Register 0x74<6:4>
Register 0x40<6> = 1
Register 0x40<6> = 0
000
11.0 Hz
1.4 kHz
001
14.7 Hz
22.5 kHz
010
22.1 Hz
22.5 kHz
011
29.4 Hz
22.5 kHz
100
35.3 Hz
22.5 kHz
101
44.1 Hz
22.5 kHz
110
58.8 Hz
22.5 kHz
111
88.2 Hz
22.5 kHz
Writing a 1 disables Tach 4 pulses.
Writing a 1 disables Tach 3 pulses.
Writing a 1 disables Tach 2 pulses.
Writing a 1 disables Tach 1 pulses.
Table 42. Register 0x75. Enhance Acoustics 1 (Power-On Default = 0x00)
Bit Name
<7> EN1
<6:4> ACOU1
Read/Write
Read/Write
Read/Write
<3> EN2
<2:0> ACOU2
Read/Write
Read/Write
Description
When this bit is 1, acoustic enhancement is enabled on PWM1 output.
These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping
instantaneously to its newly calculated speed, PWM1 ramps gracefully at the rate determined by these bits. This effects the acoustics of the fans being driven by the PWM1 output.
Time Slot
Increase Time for 33% to 100%
000 = 1
35 s
001 = 2
17.6 s
010 = 3
11.8 s
011 = 5
7s
100 = 8
4.4 s
101 = 12
3s
110 = 24
1.6 s
111 = 48
0.8 s
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping
instantaneously to its newly calculated speed, PWM2 ramps gracefully at the rate determined by these bits. This effects the acoustics of the fans being driven by the PWM2 output.
Time Slot
Increase Time for 33% to 100%
000 = 1
35 s
001 = 2 17
6s
010 = 3
11.8 s
011 = 5
7s
100 = 8
4.4 s
101 = 12
3s
110 = 24
1.6 s
111 = 48
0.8 s
Rev. PrA | Page 33 of 40
ADT7470
Preliminary Technical Data
Table 43. Register 0x76. Enhance Acoustics 2 (Power-On Default = 0x00)
Bit Name
<7> EN3
<6:4> ACOU3
Read/Write
Read/Write
Read/Write
<3> EN4
<2:0> ACOU4
Read/Write
Read/Write
Description
When this bit is 1, acoustic enhancement is enabled on PWM3 output.
These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping
instantaneously to its newly calculated speed, PWM3 ramps gracefully at the rate
determined by these bits. This effects the acoustics of the fans being driven by the
PWM3 output.
Time Slot
Increase Time for 33% to 100%
000 = 1
35 s
001 = 2
17.6 s
010 = 3
11.8 s
011 = 5
7s
100 = 8
4.4 s
101 = 12
3s
110 = 24
1.6 s
111 = 48
0.8 s
When this bit is 1, acoustic enhancement is enabled on PWM4 output.
These bits select the ramp rate applied to the PWM4 output. Instead of PWM4 jumping
instantaneously to its newly calculated speed, PWM4 ramps gracefully at the rate
determined by these bits. This effects the acoustics of the fans being driven by the
PWM4 output.
Time Slot
Increase Time for 33% to 100%
000 = 1
35 s
001 = 2
17.6 s
010 = 3
11.8 s
011 = 5
7s
100 = 8
4.4 s
101 = 12
3s
110 = 24
1.6 s
111 = 48
0.8 s
Table 44. Register 0x78. Max TMP05 Temperature (Power-On Default = 0x00)
Bit Name
<7:0> TMP05_MAX
Read/Write
Read
Description
This is a read-only register that indicates the maximum of all TMP05 temperatures.
Table 45. Register 0x79. TMP05 COEF Option 1 (Power-On Default = 0x00)
Bit Name
<7:0> TMP05_GAIN<9:2>
Read/Write
Read/Write
Description
This register contains Bits 9–2 of the optional TMP05 gain coefficient.
Table 46. Register 0x7A. TMP05 COEF Option 2 (Power-On Default = 0x00)
Bit Name
<7:6> TMP05_GAIN<1:0>
<5:0> TMP05_OFFS<8:3>
Read/Write
Read/Write
Read/Write
Description
These bits contain Bits 1–0 of the optional TMP05 gain coefficient.
These bits contain Bits 8–3 of the optional TMP05 offset coefficient. See also Register
0x7B in the next table.
Rev. PrA | Page 34 of 40
Preliminary Technical Data
ADT7470
Table 47. Register 0x7B. TMP05 COEF Option 3 (Power-On Default = 0x00)
Bit Name
<7:5> TMP05_OFFS
<2:0> AFC_Spin_Up
Read/Write
Read/Write
Read/Write
Description
These bits contain Bits 2–0 of the optional TMP05 offset coefficient.
These bits control the AFC fan spin-up .
Programming
Setting
000
No Start Up (Default)
001
100 msec
010
250 msec
011
400 msec
100
667 msec
101
1 sec
110
2 sec
111
4 sec
Table 48. Register 0x7C. TMP05 Zone Select 1 (Power-On Default = 0x00)
Bit Name
<7:4> zone_fan1<3:0>
Read/Write
Read/Write
<3:0> zone_fan2<3:0>
Read/Write
Description
These bits determine which temperature zone controls Fan 1.
zone_fan1<3:0>
Description
0000
Max_temperature from Register 0x78 controls Fan 1.
0001
Temperature 1 from Register 0x20 controls Fan 1.
0010
Temperature 2 from Register 0x21 controls Fan 1.
0011
Temperature 3 from Register 0x22 controls Fan 1.
0100
Temperature 4 from Register 0x23 controls Fan 1.
0101
Temperature 5 from Register 0x24 controls Fan 1.
0110
Temperature 6 from Register 0x25 controls Fan 1.
0111
Temperature 7 from Register 0x26 controls Fan 1.
1000
Temperature 8 from Register 0x27 controls Fan 1.
1001
Temperature 9 from Register 0x28 controls Fan 1.
1010
Temperature 10 from Register 0x29 controls Fan 1.
These bits determine which temperature zone controls Fan 2.
zone_fan2<3:0>
Description
0000
max_temperature from Register 0x78 controls Fan 2.
0001
Temperature 1 from Register 0x20 controls Fan 2.
0010
Temperature 2 from Register 0x21 controls Fan 2.
0011
Temperature 3 from Register 0x22 controls Fan 2.
0100
Temperature 4 from Register 0x23 controls Fan 2.
0101
Temperature 5 from Register 0x24 controls Fan 2.
0110
Temperature 6 from Register 0x25 controls Fan 2.
0111
Temperature 7 from Register 0x26 controls Fan 2.
1000
Temperature 8 from Register 0x27 controls Fan 2.
1001
Temperature 9 from Register 0x28 controls Fan 2.
1010
Temperature 10 from Register 0x29 controls Fan 2.
Rev. PrA | Page 35 of 40
ADT7470
Preliminary Technical Data
Table 49. Register 0x7D. TMP05 Zone Select 2 (Power-On Default = 0x00)
Bit Name
Read/Write
Description
<7:4> zone_fan3<3:0>
Read/Write
<3:0> zone_fan4<3:0>
Read/Write
These bits determine which temperature zone controls Fan 3.
zone_fan3<3:0>
Description
0000
max_temperature from Register 0x78 controls Fan 3.
0001
Temperature 1 from Register 0x20 controls Fan 3.
0010
Temperature 2 from Register 0x21 controls Fan 3.
0011
Temperature 3 from Register 0x22 controls Fan 3.
0100
Temperature 4 from Register 0x23 controls Fan 3.
0101
Temperature 5 from Register 0x24 controls Fan 3.
0110
Temperature 6 from Register 0x25 controls Fan 3.
0111
Temperature 7 from Register 0x26 controls Fan 3.
1000
Temperature 8 from Register 0x27 controls Fan 3.
1001
Temperature 9 from Register 0x28 controls Fan 3.
1010
Temperature 10 from Register 0x29 controls Fan 3.
These bits determine which temperature zone controls Fan 4.
zone_fan4<3:0>
Description
0000
max_temperature from Register 0x78 controls Fan 4.
0001
Temperature 1 from Register 0x20 controls Fan 4.
0010
Temperature 2 from Register 0x21 controls Fan 4.
0011
Temperature 3 from Register 0x22 controls Fan 4.
0100
Temperature 4 from Register 0x23 controls Fan 4.
0101
Temperature 5 from Register 0x24 controls Fan 4.
0110
Temperature 6 from Register 0x25 controls Fan 4.
0111
Temperature 7 from Register 0x26 controls Fan 4.
1000
Temperature 8 from Register 0x27 controls Fan 4.
1001
Temperature 9 from Register 0x28 controls Fan 4.
1010
Temperature 10 from Register 0x29 controls Fan 4.
Table 50. Register 0x7E. TMP05 COEF Select 1 (Power-On Default = 0x00)
Bit Name
<7:0> coef_sel<9:2>
Read/Write
Read/Write
Description
These bits determine whether the default TMP05 (coef_sel<x> = 0) coefficients are used,
or whether the optional coefficients (0x79 to 0x7B) are used (coef_sel<x> = 1)
Table 51. Register 0x7F. TMP05 COEF Select 2 (Power-On Default = 0x00)
Bit Name
<7:6> coef_sel<1:0>
Read/Write
Read/Write
<5:4>reserved
<3> GPIO1_en
<2> GPIO2_en
<1> GPIO3_en
<0> GPIO4_en
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
These bits determine whether the default TMP05 (coef_sel<x> = 0) coefficients are used,
or whether the optional coefficients (0x79 to 0x7B) are used (coef_sel<x> = 1).
Reserved. This bit should be set to 0.
PWM1 becomes a GPIO.
PWM2 becomes a GPIO.
PWM3 becomes a GPIO.
PWM4 becomes a GPIO.
Rev. PrA | Page 36 of 40
Preliminary Technical Data
ADT7470
Table 52. Register 0x80. GPIO CONFIG (Power-On Default = 0x00)
Bit Name
<7> GPIO1_d
Read/Write
Read/Write
<6> GPIO1_p
Read/Write
<5> GPIO2_d
Read/Write
<4> GPIO2_p
Read/Write
<3> GPIO3_d
Read/Write
<2> GPIO3_p
Read/Write
<1> GPIO4_d
Read/Write
<0> GPIO4_p
Read/Write
Description
This bit sets the direction of GPIO 1 when the PWM1 pin is configured as GPIO)
1= Output; 0 = Input.
Data for GPIO 1 is set by the LSB of the PWM1 min duty cycle register.
This bit sets the polarity of GPIO 1 when the PWM1 pin is configured as GPIO.
1 = Active High; 0 = Active Low.
This bit sets the direction of GPIO 2 when the PWM2 pin is configured as GPIO.
1= Output; 0 = Input.
Data for GPIO 2 is set by the LSB of the PWM2 min duty cycle register.
This bit sets the polarity of GPIO 2 when the PWM2 pin is configured as GPIO.
1 = Active High; 0 = Active Low
This bit sets the direction of GPIO 3 when the PWM3 pin is configured as GPIO.
1= Output; 0 = Input.
Data for GPIO 3 is set by the LSB of the PWM3 min duty cycle register.
This bit sets the polarity of GPIO 3 when the PWM3 pin is configured as GPIO.
1 = Active High; 0 = Active Low.
This bit sets the direction of GPIO 4 when the PWM4 pin is configured as GPIO.
1= Output; 0 = Input.
Data for GPIO 4 is set by the LSB of the PWM4 min duty cycle register.
This bit sets the polarity of GPIO 4 when the PWM4 pin is configured as GPIO.
1 = Active High; 0 = Active Low.
Table 53. Register 0x81. GPIO Status (Power-On Default = 0x00)
Bit Name
<7:4> GPIO_s
Read/Write
Read/Write
<7> GPIO4_s
<6> GPIO3_s
<5> GPIO2_s
<4> GPIO1_s
<3:0> Reserved
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
These bit indicates the status of the GPIO when the corresponding PWM pin is configured
as GPIO.
When GPIO is configured as an input, these bits are read-only. They are set when the input
is asserted. (Asserted can be high or low depending on the setting of the GPIO poliarity.)
When GPIO is configured as an output, these bits are read/write. Setting these bits asserts
the GPIO output. (Asserted can be high or low depending on the setting of GPIO4
poliarity). See Register 0x36<7:0> (Table 25).
This bit indicates the status of GPIO 4 when the PWM4 pin is configured as GPIO.
This bit indicates the status of GPIO 3 when the PWM3 pin is configured as GPIO.
This bit indicates the status of GPIO 2 when the PWM2 pin is configured as GPIO.
This bit indicates the status of GPIO 1 when the PWM1 pin is configured as GPIO.
Test Bit. For ADI use only.
Rev. PrA | Page 37 of 40
ADT7470
Preliminary Technical Data
OUTLINE DIMENSIONS
0.193
BSC
9
16
0.154
BSC
1
0.236
BSC
8
PIN 1
0.069
0.053
0.065
0.049
0.010
0.025
0.004
BSC
COPLANARITY
0.004
0.012
0.008
SEATING
PLANE
0.010
0.006
8°
0°
0.050
0.016
COMPLIANT TO JEDEC STANDARDS MO-137AB
Figure 31. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADT7470ARQ
ADT7470ARQ-REEL
ADT7470ARQ-REEL7
Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Package Description
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
Rev. PrA | Page 38 of 40
Package Option
RQ-16
RQ-16
RQ-16
Preliminary Technical Data
ADT7470
NOTES
Rev. PrA | Page 39 of 40
ADT7470
Preliminary Technical Data
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04684–0–3/04(PrA)
Rev. PrA | Page 40 of 40